A chip packaging method and system based on energetic ion beam deposition technology

Abstract

The present invention discloses a chip packaging method and system based on energetic ion beam deposition technology, which relates to the field of chip packaging technology and is used to solve the problem that factors such as fluctuations in ion beam energy and uneven ion beam flow rate will affect the stability of the deposition rate. An unstable deposition rate will lead to uneven thickness of the deposition layer, affecting the quality and performance of the packaging layer. The method includes establishing a training model of the regularity of the crystal structure of the deposition surface and the deposition rate based on the regularity of the crystal structure of the deposition surface, and deriving the expected deposition rate; comparing the expected deposition rate with the real-time deposition rate to determine whether the real-time deposition rate needs to be adjusted, further making corresponding adjustments, implementing and monitoring; deriving the expected deposition rate through model training, and comparing it with the real-time deposition rate to determine whether the deposition rate needs to be adjusted. Finally, the stability of the deposition rate is controlled by adjusting the energy and flow of the ion beam.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging technology, and more specifically, to a chip packaging method and system based on energetic ion beam deposition technology. Background Art

[0002] In the existing chip packaging method based on energetic ion beam deposition technology, the deposition rate will fluctuate in different time periods during the actual deposition process, and even increase or decrease suddenly. Factors such as fluctuations in ion beam energy and uneven ion beam flow will affect the stability of the deposition rate. Unstable deposition rate will lead to uneven thickness of the deposited layer, affecting the quality and performance of the packaging layer.

[0003] In view of the above problems, the present invention proposes a solution. Summary of the invention

[0004] In order to overcome the above-mentioned defects of the prior art, an embodiment of the present invention provides a chip packaging method and system based on energetic ion beam deposition technology to solve the problems raised in the above-mentioned background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A chip packaging method and system based on energetic ion beam deposition technology, comprising the following steps:

[0007] Step 1: Collect analytical data for analyzing the crystal structure of the deposition surface, including temperature, pressure, lattice constant, etc., and pre-process them;

[0008] Step 2: Calculate the deposition environment and the crystal structure of the chip. The deposition environment is the environment in which the chip is deposited by an energetic ion beam during the packaging process. The crystal structure of the chip is the arrangement and orderliness of atoms or molecules inside the material.

[0009] Step 3: Comprehensively analyze the deposition environment and the crystal structure of the chip to obtain the regularity of the crystal structure of the deposition surface;

[0010] Step 4: According to the regularity of the crystal structure of the deposition surface, a training model of the regularity of the crystal structure of the deposition surface and the deposition rate is established to deduce the expected deposition rate;

[0011] Step 5: Compare the expected deposition rate with the real-time deposition rate to determine whether the real-time deposition rate needs to be adjusted, make further corresponding adjustments, implement and monitor.

[0012] In a preferred embodiment, in step 1, the analysis data collected for analyzing the crystal structure of the deposition surface is the deposition environment and the crystal structure of the chip, including the temperature and pressure of the deposition process and the lattice constant of the chip.

[0013] In a preferred embodiment, in step 2, the specific process of calculating the deposition environment is as follows:

[0014] Y1: Collect data; use a temperature sensor and a press to measure the temperature and pressure of the deposition process respectively, and collect the measured temperature and pressure at intervals of one unit time; mark the temperature as T and the pressure as P;

[0015] Y2: average value;

[0016] Y3: Normalization processing: normalize the average temperature and average pressure, and perform weighted calculation according to the weight;

[0017] If the calculated result is closer to 1, it is suitable for the deposition process;

[0018] The specific process of calculating the crystal structure of the chip is as follows:

[0019] S1: Sample preparation;

[0020] S2: Perform X-ray diffraction experiments;

[0021] S3: Calculate the lattice constant using the Bragg formula.

[0022] In a preferred embodiment, in step 3, fuzzy rules are used to comprehensively analyze the deposition environment and the crystal structure of the chip, and the regularity of the crystal structure of the deposition surface is further obtained according to the comprehensive analysis results; the specific process is as follows:

[0023] The deposition environment and the crystal structure of the chip are defined as input variables and divided into different fuzzy sets;

[0024] The regularity of the crystal structure of the deposition surface is defined as the output variable and divided into different fuzzy sets;

[0025] Formulate fuzzy rules to describe the effects of deposition environment and chip crystal structure on the regularity of the crystal structure of the deposition surface;

[0026] Fuzzy reasoning is performed according to fuzzy rules to obtain the regularity of the crystal structure of the deposited surface.

[0027] In a preferred embodiment, in step 4, the deposition rate is the speed of the deposition process in the chip package; a mathematical model of the deposition rate is established according to the regularity of the crystal structure of the deposition surface, and a neural network is used to derive the expected deposition rate; the specific process is as follows:

[0028] D1: Collect data; collect sample data of N chips, the sample data includes the regularity of the crystal structure of the deposition surface and the deposition rate of the N chips; the sample data is expressed as (Xi, Ci), where Xi represents the deposition rate of the i-th sample chip, and Ci represents the regularity of the crystal structure of the deposition surface of the i-th sample chip;

[0029] The calculation of the deposition rate specifically includes the following steps:

[0030] D1.1: Collect data; use a thickness gauge to detect the thickness of the chip surface in real time during the deposition process, set the detection time, and record the thickness of the chip surface at every interval of Δt; mark the thickness of the chip surface as F, and Fi represents the thickness of the i-th chip surface recorded;

[0031] D1.2: Calculate the deposition rate; record the thickness of the surface of H chips, and the calculation formula is: Where F i+1 is the thickness of the i+1th chip surface, F i+1 -F i represents the change in chip surface thickness at adjacent time points, ΔF is the average thickness change on the chip surface; then there is the real-time deposition rate

[0032] D2: Data normalization processing: normalizing the deposition rates of these N chips;

[0033] D3: Neural network structure design; for the input layer, the number of input layer nodes is equal to the dimension of the input feature, that is, the dimension of the regularity of the crystal structure of the deposition surface; the number of input layer nodes is 3; the output layer node is 1, indicating the expected deposition rate;

[0034] D4: Data division: divide the data set into training set, validation set and test set;

[0035] D5: Model training; use the gradient descent algorithm to optimize the parameters of the neural network and fit the training set data through the minimum loss function;

[0036] D6: Predict the deposition rate of new sample chips using the trained model.

[0037] In a preferred embodiment, in step 5, after obtaining the expected deposition rate of the new sample chip, the chip is packaged and the real-time deposition rate X is collected during the deposition process. 实时 , and compare it with the expected deposition rate Make a comparison to determine whether the deposition rate needs to be adjusted;

[0038] if When the real-time deposition rate exceeds the threshold, there is no need to adjust the real-time deposition rate; otherwise, the real-time deposition rate needs to be adjusted.

[0039] A chip packaging system based on energetic ion beam deposition technology, used to implement the above-mentioned chip packaging method based on energetic ion beam deposition technology, comprising a data acquisition module, a data analysis module and a data storage module;

[0040] The data acquisition module is used to acquire analysis data of the crystal structure of the deposition surface and send it to the data analysis module;

[0041] The data analysis module determines whether the real-time deposition rate needs to be adjusted according to the analysis data of the crystal structure of the deposition surface;

[0042] The data storage module is used to store all data in the data processing process of the chip packaging system based on the energetic ion beam deposition technology.

[0043] The technical effects and advantages of the chip packaging method and system based on energetic ion beam deposition technology of the present invention are as follows:

[0044] The present invention packages the chip based on the energetic ion beam deposition technology, and obtains the crystal structure of the deposition surface by combining the deposition environment and the crystal structure of the chip. The expected deposition rate is further deduced through model training, and the expected deposition rate is compared with the real-time deposition rate to determine whether the deposition rate needs to be adjusted. Finally, the stability of the deposition rate is controlled by adjusting the energy and flow of the ion beam. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A logic schematic diagram of a chip packaging system based on energetic ion beam deposition technology of the present invention;

[0046] Figure 2 The schematic diagram of a chip packaging method based on energetic ion beam deposition technology of the present invention is shown in FIG. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] The present invention packages the chip based on the energetic ion beam deposition technology, and obtains the crystal structure of the deposition surface by combining the deposition environment and the crystal structure of the chip. The expected deposition rate is further deduced through model training, and the expected deposition rate is compared with the real-time deposition rate to determine whether the deposition rate needs to be adjusted. Finally, the stability of the deposition rate is controlled by adjusting the energy and flow of the ion beam.

[0049] Example 1

[0050] like Figure 1 , Figure 2 As shown, a flow chart of a method for adjusting the deposition rate of the present invention is provided, comprising the following specific steps:

[0051] Step 1: Collect analytical data for analyzing the crystal structure of the deposition surface, including temperature, pressure, lattice constant, etc., and pre-process these analytical data.

[0052] Step 2: Calculate the deposition environment and the crystal structure of the chip based on these analysis data. The deposition environment refers to the environment in which the chip is deposited by an energetic ion beam during the packaging process. The crystal structure of the chip refers to the arrangement and orderliness of atoms or molecules inside the material.

[0053] Step 3: Comprehensively analyze the deposition environment and the crystal structure of the chip to obtain the regularity of the crystal structure of the deposition surface.

[0054] Step 4: According to the regularity of the crystal structure of the deposition surface, a training model of the regularity of the crystal structure of the deposition surface and the deposition rate is established to deduce the expected deposition rate.

[0055] Step 5: Compare the expected deposition rate with the real-time deposition rate to determine whether the real-time deposition rate needs to be adjusted, make further corresponding adjustments, implement and monitor.

[0056] Specifically in step 1, the crystal structure of the deposition surface refers to the crystal structure formed on the surface during the deposition process. When the material is deposited on the surface, due to the restriction and interaction of the surface, the growth mode and structure of the crystal may change, resulting in the crystal structure of the deposition surface being different from the crystal structure inside the material. The analytical data collected for analyzing the crystal structure of the deposition surface are the crystal structure of the deposition environment and the chip, including the temperature, pressure of the deposition process, and the lattice constant of the chip. Appropriate temperature can promote crystal growth and crystallinity. Higher temperature is conducive to the diffusion and surface diffusion of atoms or molecules, and helps to form a more complete and regular lattice structure. However, too high a temperature may increase the thermal stress of the crystal structure, causing crystal defects or grain boundary migration, thereby affecting the stability of the crystal structure. Changes in pressure can affect the diffusion rate and deposition rate of gas molecules, thereby affecting the kinetic process of crystal growth. Higher pressure can increase the diffusion rate of gas molecules and promote crystal growth, but too high pressure may cause bubbles or grain boundary displacement, affecting the integrity of the crystal structure. The lattice constant is one of the basic parameters describing the lattice structure, which contains the distance information between adjacent atoms or ions in the lattice. The size and proportion of the lattice constant reflect the density and arrangement of atoms in the crystal, and the lattice constant reflects the periodicity and geometric structure of the arrangement of atoms or ions in the crystal. Preprocessing these analysis data facilitates subsequent processing.

[0057] Specifically in step 2, the specific process of calculating the deposition environment is as follows:

[0058] Y1: Collect data. Use a temperature sensor and a pressure machine to measure the temperature and pressure of the deposition process respectively, and collect the measured temperature and pressure at intervals of one unit time. Mark the temperature as T and the pressure as P.

[0059] Y2: Take the average value. Assuming that a total of m sets of temperature and pressure are collected, calculate the average temperature and average pressure of the deposition process respectively, specifically Where Ti and Pi are the i-th temperature and the i-th pressure.

[0060] Y3: Normalization. Normalize the average temperature and average pressure to put them on the same level to make weighted calculation easier. Assume T max is the maximum temperature, P max is the maximum value of pressure, then the normalized temperature pressure According to the weighted calculation, E = w T ×T′+w P ×P′; where w T and w Pare weight coefficients of temperature and pressure respectively, and their sum is 1. The weight setting is determined according to the professional knowledge in the relevant field and the specific situation, and is not limited here.

[0061] If the calculated E is closer to 1, it means that the deposition environment is better and suitable for the deposition process; if the value of E is lower, it means that the deposition environment is poor, which may affect the quality and efficiency of deposition.

[0062] The specific process of calculating the crystal structure of the chip is as follows:

[0063] S1: Sample preparation. Prepare chip samples and ensure that their surfaces are smooth and clean. If higher requirements are required, the surface quality can be improved by polishing or other means.

[0064] S2: Perform an X-ray diffraction experiment. First, fix the chip sample on the sample stage of the X-ray diffractometer, then adjust the X-ray instrument and select the appropriate X-ray wavelength and scanning range. Among them, common X-ray sources include tungsten target X-ray (α=0.209) tubes or copper target X-ray tubes (α=1.5418). Set the scanning range and scanning speed, usually selecting a 2θ range between 10 degrees and 90 degrees, and a scanning speed of two degrees per minute. Start the X-ray diffraction experiment, record the diffraction pattern through the detector, and collect the serial numbers of the diffraction peaks.

[0065] S3: Use the Bragg formula to calculate the lattice constant, the specific formula is 2d sinθ=nα, where θ is the diffraction angle, n is the diffraction order, the diffraction order refers to the serial number of the obvious diffraction peak appearing in the diffraction pattern, α is the wavelength of the X-ray, and d is the lattice constant.

[0066] The value of the crystal constant directly affects the crystal structure of the deposition surface. The larger the crystal constant, the looser the crystal structure of the deposition surface becomes. On the contrary, the smaller the crystal constant, the tighter the crystal structure of the deposition surface becomes.

[0067] It should be noted that the crystal structure of the chip can also be evaluated by other indicators, such as crystal plane orientation, crystal symmetry, etc. Using crystal constants to evaluate the crystal structure of the chip is only an example of this implementation and will not be elaborated on here.

[0068] Specifically, in step 3, the regularity of the crystal structure of the deposition surface describes the order and integrity of the crystal structure. Fuzzy rules can be used to comprehensively analyze the deposition environment and the crystal structure of the chip, and the regularity of the crystal structure of the deposition surface can be further obtained based on the comprehensive analysis results. The specific process is as follows:

[0069] First, the deposition environment and the crystal structure of the chip are defined as input variables and divided into different fuzzy sets, such as "Low", "Medium", "High" for the deposition environment, and "Small", "Medium", "Big" for the crystal structure of the chip.

[0070] The regularity of the crystal structure of the deposition surface is defined as the output variable and divided into different fuzzy sets, such as “Irregular”, “Partially regular” and “Completely regular”, which are irregular, partially regular and completely regular for the regularity of the crystal structure of the deposition surface, respectively.

[0071] Formulate fuzzy rules to describe the influence of deposition environment and chip crystal structure on the regularity of deposition surface crystal structure. The definition of rules can be based on the professional knowledge of the industry or obtained through data analysis and experiments. For example, the deposition environment is marked as A, the chip crystal structure is marked as B, and the regularity of deposition surface crystal structure is marked as C. It can be defined as:

[0072] Ru le 1:IF(A is H i gh)AND(B is Big)THEN(C is Comp l ete l yregu l ar)

[0073] Ru le 2:IF(A is Low)AND(B is Small)THEN(C is I rregu l ar) ......

[0074] Fuzzy reasoning is performed according to fuzzy rules to obtain the regularity of the crystal structure of the deposited surface.

[0075] It should be noted that the division of fuzzy sets can be adjusted according to actual conditions. For example, the present embodiment takes three fuzzy sets as an example. In fact, the deposition environment, the crystal structure of the chip, and the regularity of the crystal structure of the deposition surface can be divided into more than three sets, so as to more conveniently obtain the regularity of the crystal structure of the deposition surface.

[0076] For further judgments on whether the deposition environment is low, medium or high and the crystal structure of the chip is small, medium or large, thresholds can be set according to actual conditions. For example, when the comprehensive score of temperature and pressure E≥0.7, the deposition environment is marked as "H i gh"; when the lattice constant d≥0.6, the crystal structure of the chip is marked as "Big", etc., which will not be elaborated here.

[0077] Specifically, in step 4, the deposition rate is the speed of the deposition process in the chip package. A mathematical model of the deposition rate is established based on the regularity of the crystal structure of the deposition surface, and a neural network is used to derive the expected deposition rate. The specific process is as follows:

[0078] D1: Collect data. Collect sample data of N chips, including the regularity of the crystal structure of the deposition surface and the deposition rate of these N chips. Specifically, there are sample data (Xi, Ci), where Xi represents the deposition rate of the i-th sample chip, and Ci represents the regularity of the crystal structure of the deposition surface of the i-th sample chip.

[0079] The calculation of the deposition rate specifically includes the following steps:

[0080] D1.1: Collect data. Use a thickness gauge to detect the thickness of the chip surface in real time during the deposition process. Set the detection time and record the thickness of the chip surface at every interval of Δt. Mark the thickness of the chip surface as F, and Fi represents the thickness of the i-th chip surface recorded.

[0081] D1.2: Calculate the deposition rate. Assuming that the thickness of H chip surfaces is recorded, there is a formula: Where F i+1 is the thickness of the i+1th chip surface, F i+1 -F i represents the change in chip surface thickness at adjacent time points, and ΔF is the average thickness change on the chip surface. Then there is the real-time deposition rate

[0082] It should be noted that when calculating the deposition rate of the sample chip, the stability of various factors in the deposition process of the sample chip should be maximized to make the calculated deposition rate more effective and reasonable, which is convenient for subsequent model training. No further elaboration will be given here.

[0083] D2: Data normalization. The deposition rates of these N chips are normalized using the formula Where Normalized_Score is the normalized value.

[0084] D3: Neural network structure design. For the input layer, the number of input layer nodes is equal to the dimension of the input feature, that is, the dimension of the regularity of the crystal structure of the deposition surface. In this embodiment, the regularity of the crystal structure of the deposition surface includes completely regular, partially regular and irregular, so the number of input layer nodes is 3. For the hidden layer, the number of nodes and layers of the hidden layer can be selected according to actual conditions, which will not be described in detail here. For the output layer, the output layer node is 1, indicating the expected deposition rate. Select a suitable activation function to improve the performance of the neural network. Commonly used activation functions include Sigmoid function and ReLU function. This embodiment takes the Sigmoid function as an example, and the specific formula is Where X is the deposition rate of these N chips. The mean square error (MSE) is a commonly used loss function for regression problems, which is used to measure the difference between the predicted value and the actual value. The specific formula is Where Xi represents the deposition rate, represents the expected deposition rate, is the expected deposition rate of the i-th sample chip.

[0085] D4: Data partitioning. The data set is divided into training set, validation set and test set, usually in a ratio of 7:2:1. It should be noted that the data set partitioning should be random and the deposition rate and the regularity of the crystal structure of the deposition surface should be uniformly distributed.

[0086] D5: Model training. Use the gradient descent algorithm to optimize the parameters of the neural network and fit the training set data through the minimum loss function. The parameter update rule is as follows: β = β - γΔ β MSE; where β represents the parameters of the network, including weights and biases; γ is the learning rate, which is used to control the step size of each parameter update. The larger the learning rate, the faster the parameter update, but it may cause instability and oscillation. The smaller the learning rate, the more stable the parameter update, but it may cause the convergence speed to be too slow; Δ β is the gradient of the loss function with respect to the parameter, which indicates the slope or rate of change of the loss function at the current parameter value. It should be noted that in practice, it is necessary to carefully select an appropriate learning rate to ensure the convergence and stability of the gradient descent algorithm. Specifically, the optimal learning rate can be selected based on the change of the loss function under different learning rates, which will not be elaborated here.

[0087] D6: Apply the trained model to practical problems to predict the deposition rate of new sample chips.

[0088] Specifically, in step 5, after obtaining the expected deposition rate of the new sample chip, the chip is packaged and the real-time deposition rate X is collected during the deposition process. 实时 , and compare it with the expected deposition rate Comparison is made to determine whether the deposition rate needs to be adjusted. The calculation of the real-time deposition rate is consistent with the calculation of the deposition rate of the sample chip. Further, the calculation of the real-time deposition rate does not need to ensure the stability of various factors in the maximum deposition process, and can be based on specific circumstances.

[0089] if When the threshold is reached, it means that the real-time deposition rate fluctuates slightly with the expected deposition rate, and the real-time deposition rate does not need to be adjusted; otherwise, it means that the real-time deposition rate fluctuates greatly with the expected deposition rate, and the real-time deposition rate needs to be adjusted. The threshold can be set according to the professional knowledge in the relevant field and the actual situation, and is not limited here.

[0090] Common methods for adjusting the real-time deposition rate include adjusting the energy and flow rate of the ion beam, adjusting the deposition time, optimizing the distance and angle between the target and the substrate, etc. Among them, adjusting the energy of the ion beam can directly affect the deposition rate. Increasing the energy will increase the intensity of the ion beam bombardment on the target surface, thereby increasing the deposition rate; reducing the energy will slow down the deposition rate. Controlling the flow rate of the ion beam can also directly affect the deposition rate. Increasing the ion beam flow rate will increase the number of ions that hit the target surface, thereby increasing the deposition rate; reducing the flow rate will reduce the rate. The specific adjustment methods will not be described in detail here.

[0091] It should be noted that during the adjustment process, the stability of the deposition process must be ensured to avoid exceeding the material's tolerance range and causing damage or adverse effects.

[0092] The present invention utilizes energetic ion beam deposition technology to package chips, and through comprehensive analysis of the deposition environment and the chip crystal structure, deduces the regularity of the crystal structure of the deposition surface, and establishes a prediction model for the deposition rate. The obtained expected deposition rate is compared with the real-time deposition rate, so as to determine whether the real-time deposition rate needs to be adjusted, and the adjustment is made in time to make the deposition rate more stable, thereby improving the quality and efficiency of chip packaging.

[0093] Example 2

[0094] The present invention also discloses a chip packaging system based on energetic ion beam deposition technology, including a data acquisition module, a data analysis module and a data storage module;

[0095] The data acquisition module is used to acquire analysis data of the crystal structure of the deposition surface and send it to the data analysis module;

[0096] The data analysis module determines whether the real-time deposition rate needs to be adjusted according to the analysis data of the crystal structure of the deposition surface;

[0097] The data storage module is used to store all data in the data processing process of the chip packaging system based on the energetic ion beam deposition technology.

[0098] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0099] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments may be implemented in whole or in part in the form of a computer program product.

[0100] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0101] In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0102] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0103] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip packaging method based on energetic ion beam deposition technology, characterized in that: The steps include: Step 1: Collect analytical data for analyzing the crystal structure of the deposition surface, including temperature, pressure, and lattice constant, and pre-process them; Step 2: Calculate the deposition environment and the crystal structure of the chip. The deposition environment is the environment in which the chip is deposited by an energetic ion beam during the packaging process. The crystal structure of the chip is the arrangement and orderliness of atoms or molecules inside the material. Step 3: Comprehensively analyze the deposition environment and the crystal structure of the chip to obtain the regularity of the crystal structure of the deposition surface; Step 4: According to the regularity of the crystal structure of the deposition surface, a training model of the regularity of the crystal structure of the deposition surface and the deposition rate is established to deduce the expected deposition rate; Step 5: Compare the expected deposition rate with the real-time deposition rate to determine whether the real-time deposition rate needs to be adjusted, make further corresponding adjustments, implement and monitor.

2. The chip packaging method based on energetic ion beam deposition technology according to claim 1, characterized in that: In step 2, the specific process of calculating the deposition environment is as follows: Y1: Collect data; use a temperature sensor and a press to measure the temperature and pressure of the deposition process respectively, and collect the measured temperature and pressure at intervals of one unit time; mark the temperature as T and the pressure as P; Y2: average value; Y3: Normalization processing: normalize the average temperature and average pressure, and perform weighted calculation according to the weight; If the calculated result is closer to 1, it is suitable for the deposition process; The specific process of calculating the crystal structure of the chip is as follows: S1: Sample preparation; S2: Perform X-ray diffraction experiments; S3: Calculate the lattice constant using the Bragg formula.

3. The chip packaging method based on energetic ion beam deposition technology according to claim 2, characterized in that: In step 3, fuzzy rules are used to comprehensively analyze the deposition environment and the crystal structure of the chip, and the regularity of the crystal structure of the deposition surface is further obtained based on the comprehensive analysis results; the specific process is as follows: The deposition environment and the crystal structure of the chip are defined as input variables and divided into different fuzzy sets; The regularity of the crystal structure of the deposition surface is defined as the output variable and divided into different fuzzy sets; Formulate fuzzy rules to describe the effects of deposition environment and chip crystal structure on the regularity of the crystal structure of the deposition surface; Fuzzy reasoning is performed according to fuzzy rules to obtain the regularity of the crystal structure of the deposited surface.

4. The chip packaging method based on energetic ion beam deposition technology according to claim 3, characterized in that: In step 4, the deposition rate is the speed of the deposition process in the chip package; a mathematical model related to the deposition rate is established based on the regularity of the crystal structure of the deposition surface, and a neural network is used to derive the expected deposition rate; the specific process is as follows: D1: Collect data; collect sample data of N chips, the sample data includes the regularity of the crystal structure of the deposition surface and the deposition rate of the N chips; the sample data is expressed as (Xi, Ci), where Xi represents the deposition rate of the i-th sample chip, and Ci represents the regularity of the crystal structure of the deposition surface of the i-th sample chip; The calculation of the deposition rate specifically includes the following steps: D1.1: Collect data; use a thickness gauge to detect the thickness of the chip surface in real time during the deposition process, set the detection time, and record the thickness of the chip surface at every interval of Δt; mark the thickness of the chip surface as F, and Fi represents the thickness of the i-th chip surface recorded; D1.2: Calculate the deposition rate; record the thickness of the surface of H chips, and the calculation formula is: Where F i+1 is the thickness of the i+1th chip surface, F i+1 -F i represents the change in chip surface thickness at adjacent time points, ΔF is the average thickness change on the chip surface; then there is the real-time deposition rate D2: Data normalization processing: normalizing the deposition rates of these N chips; D3: Neural network structure design; for the input layer, the number of input layer nodes is equal to the dimension of the input feature, that is, the dimension of the regularity of the crystal structure of the deposition surface; the number of input layer nodes is 3; the output layer node is 1, indicating the expected deposition rate; D4: Data division: divide the data set into training set, validation set and test set; D5: Model training; use the gradient descent algorithm to optimize the parameters of the neural network and fit the training set data through the minimum loss function; D6: Predict the deposition rate of new sample chips using the trained model.

5. The chip packaging method based on energetic ion beam deposition technology according to claim 3, characterized in that: In step 5, after obtaining the expected deposition rate of the new sample chip, the chip is packaged and the real-time deposition rate X is collected during the deposition process. 实时 , and compare it with the expected deposition rate Make a comparison to determine whether the deposition rate needs to be adjusted; if If the real-time deposition rate is 0, the real-time deposition rate does not need to be adjusted; otherwise, the real-time deposition rate needs to be adjusted.

6. A chip packaging system based on energetic ion beam deposition technology, used to implement a chip packaging method based on energetic ion beam deposition technology as claimed in any one of claims 1 to 5, characterized in that: It includes a data acquisition module, a data analysis module and a data storage module; The data acquisition module is used to acquire analysis data of the crystal structure of the deposition surface and send it to the data analysis module; The data analysis module determines whether the real-time deposition rate needs to be adjusted according to the analysis data of the crystal structure of the deposition surface; The data storage module is used to store all data in the data processing process of the chip packaging system based on the energetic ion beam deposition technology.

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