An internal compensation structure suitable for high-voltage LDO

Abstract

The present invention discloses an internal compensation structure suitable for high-voltage LDOs, designed to improve the LDO's performance when facing rapid changes in load current. The internal compensation structure includes a transient enhancement module, a bias module, and an LDO main loop module. The transient enhancement module is used to provide additional current when the load current changes rapidly; the LDO main loop module is used to maintain the stability of the output voltage and works in conjunction with the bias module; the bias module is used to provide a constant bias voltage or current; and the bias module includes at least: a PMOS transistor M1, a PMOS transistor M2, and a current source V1. The gate-source voltages of the PMOS transistors M1 and M2 are superimposed on the current source V1 to generate a stable internal reference voltage Start_REF, providing a precise voltage reference for the LDO, thereby ensuring high output voltage consistency over a wide input voltage range.

Description

Technical Field

[0001] The present invention belongs to the technical field of power integrated circuits, and in particular relates to an internal compensation structure suitable for high-voltage LDOs. Background Art

[0002] Current low-dropout (LDO) linear regulator (LDO) designs typically adjust the output voltage by controlling the gate voltage of a PMOS transistor. To achieve the required output current, a PMOS transistor is typically used. However, PMOS transistors still suffer from excessive parasitic capacitance. To ensure the dynamic response of the circuit system, ESR compensation is introduced.

[0003] However, the aforementioned ESR compensation scheme has limitations in capacitor selection. Integrating microfarad-level capacitors on-chip results in an excessively large layout area. Using off-chip capacitors can lead to circuit stability issues. Choosing tantalum capacitors with better stability to improve stability increases manufacturing costs on top of the high cost of large capacitors. Furthermore, capacitors can negatively impact the transient response of the power supply system, increasing the overshoot voltage at the output of the LDO module.

[0004] Chinese patent CN116736920A discloses a high-voltage LDO module using an N-type regulator. The module comprises an error amplifier, a buffer, two RC series modules, and an N-type regulator tube MM. The error amplifier receives a feedback voltage signal and a reference voltage signal, amplifies them, and outputs an amplified low-voltage signal. The buffer converts the amplified low-voltage signal into a high-voltage signal, which is then input to the gate of the N-type regulator tube MM. The drain of the N-type regulator tube MM serves as the input of the LDO module, while the source serves as the output. The second end of the feedback resistor RF2 is connected to ground. Two RC series modules are connected in series: one is connected between the output of the error amplifier and ground, and the other is connected in series between the gate and source of the N-type regulator tube NM.

[0005] The above scheme uses an N-type pass transistor, which has high carrier mobility. The error amplifier also uses an NMOS transistor as a differential input pair, reducing the layout area of the high-voltage LDO module. Two series RC models jointly modulate the circuit's poles and zeros, optimizing the circuit's phase margin. However, due to the characteristics of the N-type pass transistor, its drain current and gate voltage have a certain relationship. Maintaining a stable operating point is crucial to prevent output voltage fluctuations caused by changes in drain current. To this end, we propose an internal compensation structure suitable for high-voltage LDOs. Summary of the Invention

[0006] The present invention aims to provide an internal compensation structure for a high-voltage LDO to address the problems raised in the background art. This internal compensation structure maintains output voltage stability when the load current changes rapidly and optimizes the performance of the LDO main loop module.

[0007] In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions: including:

[0008] A transient enhancement module is configured to provide additional current when the load current changes rapidly. The transient enhancement module comprises: a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, and a PMOS transistor M8. The gate of the PMOS transistor M5 is connected to the drain of the PMOS transistor M2, the source of the PMOS transistor M5 is connected to the drain of the PMOS transistor M6, the drain of the PMOS transistor M5 is grounded, the source of the PMOS transistor M6 is connected to the Vin terminal, the gate of the PMOS transistor M6 is respectively connected to the gate of the PMOS transistor M7 and the gate of the PMOS transistor M8, the source of the PMOS transistor M7 is connected to the bias module, the drain of the PMOS transistor M7 is connected to the source of the PMOS transistor M8, and the drain of the PMOS transistor M8 is respectively connected to the drain of the LDO main loop module and the drain of the PMOS transistor M3.

[0009] The LDO main loop module is used to maintain the stability of the output voltage and works in conjunction with the bias module;

[0010] A bias module for providing a constant bias voltage or current; the bias module includes: a current source Vbg, a current source V1, a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, and a PMOS transistor M4, wherein the source of the PMOS transistor M1 is connected to the Vin terminal, the gate is connected to the current source Vbg and is grounded, and the drain is respectively connected to the source of the PMOS transistor M3 and the gate of the PMOS transistor M4; the source of the PMOS transistor M2 is connected to the source of the PMOS transistor M1, the gate is connected to the LDO main loop module, and the drain is respectively connected to the source of the PMOS transistor M4 and the transient enhancement module; the gate of the PMOS transistor M3 is connected to the gate of the PMOS transistor M4, and the drain is connected to the transient enhancement module; the drain of the PMOS transistor M4 is connected to the current source V1 and is grounded;

[0011] A bidirectional voltage level converter is located between the PMOS tube M2 and the LDO main loop module, or between the current source Vbg and the gate of the PMOS tube M1.

[0012] Preferably, the LDO main loop module further includes: a buffer module, a capacitor C1, a capacitor C3, a resistor R1, a resistor R2, a resistor R3, a PMOS tube M9, and a PMOS tube M10. The input end of the buffer module is connected to the drain of the PMOS tube M8, the output end of the buffer module is connected to the gate of the PMOS tube M10, the buffer module is also connected to the drain of the PMOS tube M9, the source of the PMOS tube M9 is connected to the transient enhancement module, one end of the capacitor C1 is connected to the gate of the PMOS tube M9, and the other end of the capacitor C1 is connected to the buffer module. The source of the PMOS tube M10 is connected to the source of the PMOS tube M9, and the drain of the PMOS tube M10 is connected to the Vout terminal and grounded through the resistor R1 and the resistor R2. One end of the capacitor C3 is connected to the Vout terminal, and the other end of the capacitor C3 is grounded. One end of the resistor R3 is connected to the Vout terminal, and the other end of the resistor R3 is grounded.

[0013] Furthermore, the LDO main loop module includes: an electrolytic capacitor C2 and an electrolytic capacitor C4. The electrolytic capacitor C2 is connected between the PMOS transistor M3 and the output voltage Vout, and the electrolytic capacitor C4 is connected between the PMOS transistor M1 and the buffer module. Both the electrolytic capacitor C2 and the electrolytic capacitor C4 are grounded through pull-down resistors to introduce a zero and a pole in the loop gain.

[0014] Furthermore, the internal reference voltage Start_REF in the LDO main loop module is obtained by superimposing the gate-source voltage of the PMOS tube M1 and the gate-source voltage of the PMOS tube M2 on the voltage of the current source V1.

[0015] Preferably, the bidirectional voltage level converter includes at least: an inverter INV1, an inverter INV2, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M1, an NMOS transistor M2, and a transistor Q1. The inverters INV1 and INV2 invert the phases of the transistors and apply the inverted voltages to the gates of the PMOS transistor M11 and the NMOS transistor N1, which are connected between a voltage source VCCB and ground. The drains of the PMOS transistor M11 and the NMOS transistor M1 are connected via a resistor R4. The gates of the PMOS transistor M12 and the NMOS transistor M2 are coupled and coupled to an enable input of the bidirectional voltage level converter. The outputs of the PMOS transistor M12 and the NMOS transistor M2 are coupled to the base of the transistor Q1. The emitter of the transistor Q1 is coupled to a bias line BIAS, and the collector of the transistor Q1 is coupled to ground.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] By introducing a transient enhancement module, it can provide additional current when the load current changes rapidly, thereby significantly improving the transient response performance of the LDO and maintaining the stability of the output voltage in applications where the load current changes drastically. At the same time, the coordinated work of the LDO main loop module and the bias module can further ensure that the output voltage Vout remains stable even when the load current changes rapidly.

[0018] On the other hand, by introducing specific capacitor and resistor combinations into the LDO main loop module, these combinations form zeros and poles in the loop gain, which helps to optimize the frequency response, thereby improving the stability of the system and reducing noise. In addition, a current mirror circuit is formed by PMOS tubes M1, M2, and M4, ensuring that the bias module can provide a constant bias voltage or current to the LDO even when the input voltage Vin changes.

[0019] At the same time, since the gate-source voltage of PMOS tubes M1 and M2 is constant, a stable reference is created by superimposing the voltage provided by the current source V1. Therefore, the voltage of the current source V1 is combined with the constant gate-source voltage of the PMOS tubes M1 and M2 to generate a stable internal reference voltage Start_REF. This setting allows the LDO to operate normally in a wide input voltage range without affecting its performance by using an internal, stable reference voltage, thereby ensuring the consistency of the LDO output voltage even when the input voltage changes.

[0020] Furthermore, the design of the internal reference voltage Start_REF simplifies the LDO calibration process because the characteristics of the current source V1 and the PMOS transistors M1 and M2 can be more easily adjusted during production to obtain the desired reference voltage value. This helps reduce production costs while improving product consistency and yield.

[0021] When the bidirectional voltage level converter is provided between the current source Vbg and the gate of the PMOS transistor M1, on the one hand, in a forward voltage conversion mode, the bidirectional voltage level converter can convert the output voltage of the current source Vbg into a voltage level suitable for the gate of the PMOS transistor M1, thereby allowing the PMOS transistor M1 to operate normally under different power supply voltages, thereby improving the compatibility and flexibility of the system. On the other hand, in a reverse voltage conversion mode, the bidirectional voltage level converter can convert the output voltage of the gate of the PMOS transistor M1 into a voltage level suitable for the current source Vbg, thereby allowing the current source Vbg to operate normally under different power supply voltages, thereby improving the compatibility and flexibility of the system.

[0022] In summary, the present invention effectively improves the performance of the LDO in the face of rapid changes in load current through its unique internal compensation structure, ensures high stability of the output voltage, and enhances the robustness and reliability of the system through optimized design, thus having significant technical effects in the field of high-voltage LDO applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0024] Figure 1 A schematic diagram of an internal compensation structure suitable for high-voltage LDO;

[0025] Figure 2 This is a system block diagram suitable for high-voltage LDO;

[0026] Figure 3 A schematic diagram of a portion of the structure of a bidirectional voltage level converter;

[0027] Figure 4 1 is a simulation diagram of the LDO in one embodiment under two different loads;

[0028] Figure 5 FIG. 4 is a simulation diagram of the LDO under another load in one embodiment. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0030] Reference Figure 1The present invention proposes a technical solution for an internal compensation structure suitable for a high-voltage LDO, comprising: a bias module, a transient enhancement module, and an LDO main loop module. The bias module includes at least: a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, a current source Vbg, and a current source V1. The source of the PMOS transistor M1 is connected to the Vin terminal, the gate of the PMOS transistor M1 is connected to the current source Vbg and is grounded, the drain of the PMOS transistor is respectively connected to the source of the PMOS transistor M3 and the gate of the PMOS transistor M4, the source of the PMOS transistor M2 is connected to the source of the PMOS transistor M1, the gate of the PMOS transistor M2 is connected to the LDO main loop module, the drain of the PMOS transistor M2 is respectively connected to the source of the PMOS transistor M4 and the transient enhancement module, the gate of the PMOS transistor M3 is connected to the gate of the PMOS transistor M4, the drain of the PMOS transistor M3 is connected to the transient enhancement module, and the drain of the PMOS transistor M4 is connected to the current source V1 and is grounded.

[0031] In the above solution, a current mirror circuit can be formed by the PMOS transistor M1, the PMOS transistor M2, and the PMOS transistor M4. Specifically, the PMOS transistor M1 serves as an input transistor, with its source connected to the input voltage Vin and its gate connected to the current source Vbg and grounded, thereby establishing the current passing through the PMOS transistor M1 as a reference current. The PMOS transistor M2 serves as an output transistor, with its source connected to the source of the PMOS transistor M1 and its gate connected to the LDO main loop module.

[0032] At the same time, because the gate and source of PMOS transistor M2 are connected, it operates in diode mode. Its drain will generate a current almost identical to that of PMOS transistor M1. This current is passed through PMOS transistor M4, which acts as a load transistor for the current mirror. Its gate is connected to the gate of PMOS transistor M3, and both gates are connected to the drain of PMOS transistor M1. At this time, the gate-source voltage (Vgs) of PMOS transistor M4 will match the Vgs of PMOS transistor M1, making the current passing through PMOS transistor M4 the same as the current passing through PMOS transistor M1.

[0033] On the other hand, the current source V1 can also be used to provide a constant current to the circuit. , and absorbs the current from the drain of the PMOS tube M4 and grounds it to ensure that the current passing through the PMOS tube M4 will not change due to changes in the load, maintaining the stable replication function of the current mirror.

[0034] In summary, the current bias in this embodiment is set by a constant current source Vbg and is replicated to different parts through current mirrors.

[0035] For example, the current source Vbg provides a constant current At the same time, the drain current of PMOS tube M1 = , and since the gate and drain of the PMOS tube M4 are short-circuited, the PMOS tube M4 will also have an almost identical current. Furthermore, since the gate-source voltage Vgs of the PMOS tube M1 and the PMOS tube M4 are the same, and the above-mentioned PMOS tubes are all working in the saturation region, the drain current of the PMOS tube It can be expressed as:

[0036] in, is the process-related coefficient, The crystal length ratio of the tube, is the gate-source voltage, It is the threshold voltage of the PMOS tube.

[0037] Based on the above, the drain current of the PMOS tube M1 can be expressed as:

[0038]

[0039] The drain current of the PMOS tube M4 can be expressed as:

[0040] And through the above current mirror circuit, it can be concluded that even if the threshold voltage and aspect ratio of PMOS tubes M1 and M4 are different, since their Vgs are equal, the current passing through them will also be equal, that is, At the same time, according to the above-mentioned PMOS tube M1 drain current = , we can get: In one embodiment, it further includes: a bidirectional voltage level converter, which is arranged between the PMOS tube M2 and the LDO main loop module, and can also be arranged between the current source Vbg and the gate of the PMOS tube M1.

[0041] Specifically, when the bidirectional voltage level converter is provided between the PMOS transistor M2 and the LDO main loop module, on the one hand, in the forward voltage conversion mode, the bidirectional voltage level converter can convert the output voltage of the PMOS transistor M2 into a voltage level suitable for the LDO main loop module, thereby allowing the LDO main loop module to operate normally under different power supply voltages. On the other hand, in the reverse voltage conversion mode, the bidirectional voltage level converter can convert the output voltage of the LDO main loop module into a voltage level suitable for the PMOS transistor M2, thereby allowing the PMOS transistor M2 to operate normally under different power supply voltages.

[0042] When the bidirectional voltage level converter is provided between the current source Vbg and the gate of the PMOS transistor M1, on the one hand, in a forward voltage conversion mode, the bidirectional voltage level converter can convert the output voltage of the current source Vbg into a voltage level suitable for the gate of the PMOS transistor M1, thereby allowing the PMOS transistor M1 to operate normally under different power supply voltages, thereby improving the compatibility and flexibility of the system. On the other hand, in a reverse voltage conversion mode, the bidirectional voltage level converter can convert the output voltage of the gate of the PMOS transistor M1 into a voltage level suitable for the current source Vbg, thereby allowing the current source Vbg to operate normally under different power supply voltages, thereby improving the compatibility and flexibility of the system.

[0043] The current mirror circuit formed by PMOS transistors M1, M2, and M4 effectively replicates and distributes a constant current, maintaining circuit stability. The use of current sources Vbg and V1 further helps stabilize the current, ensuring consistent circuit performance under varying load conditions.

[0044] According to the above description, the drain current of the PMOS tube can be expressed as: in, is the hole mobility; Cox is the gate oxide capacitance per unit area; W / L is the aspect ratio of the transistor; is the gate-to-source voltage; is the threshold voltage.

[0045] In addition, for the PMOS transistors M1 and M4, since their Vgs are equal and both operate in the saturation region, the currents passing through them will be equal even if their threshold voltages and width-to-length ratios are different.

[0046] Furthermore, the bidirectional voltage level converter is connected between the PMOS tube M2 and the LDO main loop module, or between the current source Vbg and the gate of the PMOS tube M1, and is in a low-level active state. It at least includes: an inverter INV1, an inverter INV2, a PMOS tube M11, a PMOS tube M12, an NMOS tube M1, an NMOS tube M2, and a transistor Q1.

[0047] Specifically, the enable signal of the bidirectional voltage level converter is inverted by a pair of inverters INV1 and INV2 and applied to the gates of a PMOS transistor P1 and an NMOS transistor N1 connected between a voltage source VCCB and ground. The drains of the PMOS transistor M11 and the NMOS transistor M1 are connected via a resistor R4, and the PMOS P1 is turned on by driving the ENABLE node to a low state. It then provides a pull-up current to the bias line BIAS of the transfer transistor through the resistor R1. The PMOS transistor M12 is coupled to the gate of the NMOS transistor M2 and coupled to the enable input of the bidirectional voltage level converter. The outputs of the PMOS transistor M12 and the NMOS transistor M2 are coupled to the base of the transistor Q1. The emitter of the transistor Q1 is coupled to the bias line BIAS, and the collector is coupled to ground. When the enable signal is low, the base of the transistor Q1 is biased to VCCA via the PMOS transistor M12, which causes the transistor Q1 to turn on. Since the collector of transistor Q1 is grounded and the emitter is coupled to the bias line BIAS, when transistor Q1 is turned on, it injects current from VCCA to the bias line BIAS.

[0048] Wherein, the transistor Q1 is a PNP transistor.

[0049] In one embodiment, the transient enhancement module includes: a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, and a PMOS transistor M8. The gate of the PMOS transistor M5 is connected to the drain of the PMOS transistor M2, the source of the PMOS transistor M5 is connected to the drain of the PMOS transistor M6, the drain of the PMOS transistor M5 is grounded, the source of the PMOS transistor M6 is connected to the Vin terminal, the gate of the PMOS transistor M6 is respectively connected to the gate of the PMOS transistor M7 and the gate of the PMOS transistor M8, the source of the PMOS transistor M7 is connected to the bias module, the drain of the PMOS transistor M7 is connected to the source of the PMOS transistor M8, and the drain of the PMOS transistor M8 is respectively connected to the drain of the LDO main loop module and the drain of the PMOS transistor M3.

[0050] In the above solution, a basic current mirror circuit can be formed by the PMOS transistor M2 and the PMOS transistor M5, wherein the PMOS transistor M2 serves as a reference current source, and the PMOS transistor M5 replicates this current and provides a bias for the PMOS transistor M6. At the same time, the source of the PMOS transistor M6 is connected to the input voltage Vin and is connected to the gates of the PMOS transistors M7 and M8, thereby providing a constant gate drive for the PMOS transistors M7 and M8 to ensure their normal operation.

[0051] On the other hand, by connecting the source of the PMOS transistor M7 to the bias module and the drain to the source of the PMOS transistor M8, the PMOS transistor M7 can adjust its drain current according to the reference voltage provided by the bias module, thereby controlling the source voltage of the PMOS transistor M8. At the same time, the drain of the PMOS transistor M8 is connected to the drain of the LDO main loop module and the PMOS transistor M3. Since the gate of the PMOS transistor M8 is connected to the gate of the PMOS transistor M6, it can quickly respond to the signal from the error amplifier in the LDO main loop module and provide the enhanced current to the LDO main loop module and the PMOS transistor M3 through its drain, thereby improving the response speed and stability of the LDO under transient load changes.

[0052] Among them, the error amplifier in the LDO main loop module should be located between the PMOS tube M8 and the Buffer module in the LDO main loop module, and its specific structure and connection method are prior art for those skilled in the art, and therefore, are not shown in the accompanying drawings.

[0053] The LDO main loop module includes: a buffer module, a capacitor C1, a capacitor C3, a resistor R1, a resistor R2, a resistor R3, a PMOS tube M9 and a PMOS tube M10. The input end of the buffer module is connected to the drain of the PMOS tube M8, the output end of the buffer module is connected to the gate of the PMOS tube M10, the buffer module is also connected to the drain of the PMOS tube M9, and the source of the PMOS tube M9 is connected to the transient enhancement module. One end of the capacitor C1 is connected to the gate of the PMOS tube M9, and the other end of the capacitor C1 is connected to the buffer module. The source of the PMOS tube M10 is connected to the source of the PMOS tube M9, and the drain of the PMOS tube M10 is connected to the Vout terminal and grounded through the resistor R1 and the resistor R2. One end of the capacitor C3 is connected to the Vout terminal, and the other end of the capacitor C3 is grounded. One end of the resistor R3 is connected to the Vout terminal, and the other end of the resistor R3 is grounded.

[0054] In the above solution, the use of the buffer module can provide a stable control signal to PMOS transistor M10, which helps stabilize the output voltage of the LDO. Capacitor C1, connected between the gate of PMOS transistor M9 and the buffer module, acts as a filter, reducing the impact of noise on the loop and improving system stability. Off-chip capacitor C3, with one end connected to the Vout terminal and the other end connected to ground, absorbs current pulses generated by rapid load changes, providing additional filtering, reducing output voltage fluctuations, and helping to improve the transient response of the LDO. Furthermore, grounding the drain of PMOS transistor M10 through resistors R1 and R2 forms a feedback network that works together with the buffer module to precisely control the gate voltage of PMOS transistor M10, thereby achieving fine output voltage regulation.

[0055] On the other hand, the source of PMOS transistor M9 can also be connected to the transient enhancement module, allowing it to directly adjust the source voltage of M9, thereby affecting the gate voltage of M10 and providing the necessary transient enhancement to cope with rapidly changing load demands. In summary, the internal reference voltage Start_REF in the LDO main loop module is applied to the inverting input of the error amplifier. It is compared with the feedback value of the LDO output voltage VOUT applied to the non-inverting input of the error amplifier. The difference between the two is amplified by the op amp to generate an error signal, which controls the gate voltage of PMOS transistor M10, thereby regulating the current through the load and maintaining the stability of the LDO output voltage VOUT.

[0056] The internal reference voltage Start_REFF is obtained by superimposing the voltage of the current source V1 on the gate-source voltage of the PMOS tube M1 and the PMOS tube M2, and is expressed as: Start_REF=V1+Vgs_M1+Vgs_M2

[0057] When the output voltage VOUT increases, the error amplifier detects a decrease in the difference between the feedback voltage at the non-inverting input and the Start_REF at the inverting input. The error amplifier amplifies this difference, generating a corresponding decrease in the error signal, causing the gate voltage of the PMOS transistor M10 to decrease. When the output voltage VOUT decreases, the error amplifier detects a increase in the difference between the feedback voltage at the non-inverting input and the Start_REF at the inverting input. The error amplifier amplifies this difference, generating a corresponding increase in the error signal, causing the gate voltage of the PMOS transistor M10 to increase.

[0058] Because PMOS transistor M10 functions as a source follower in this embodiment, its source voltage (i.e., the LDO output voltage VOUT) changes with changes in the gate voltage. As the gate voltage of PMOS transistor M10 increases, its conductivity decreases, reducing the current flowing from VOUT through M10 to ground. This causes the LDO output voltage to rise, approaching the desired Start_REF level. This regulation is achieved by changing the conductive state of PMOS transistor M10, effectively adjusting a variable resistor to maintain a stable output voltage.

[0059] Furthermore, thanks to the transient enhancement and buffer modules, the system can quickly respond to load changes and ensure that the LDO provides a stable output voltage even with rapid changes in load current. The feedback network, consisting of capacitor C1, external capacitor C3, and resistors R1, R2, and R3, further optimizes loop stability and transient response. Therefore, the entire LDO main loop module forms a negative feedback system. The low-frequency loop gain of this feedback loop is: T(s) = AOL(s)cdotgm⋅β, where AOL(s) is the open-loop gain of the error amplifier and is a function of frequency.

[0060] gm is the transconductance of the PMOS tube M10, which reflects the effect of gate voltage changes on source current.

[0061] β is the feedback factor, which is determined by the feedback network and is typically determined by the ratios of resistors R1, R2, and R3, and the values of capacitors C1 and C3.

[0062] For this feedback loop, there are two main poles worth considering, one located at the drain N1 of the PMOS tube M8, and the other located at the gate N2 of the PMOS tube M10.

[0063] like Figure 2 As shown, for an LDO main loop module in an application scenario with a wide input range and low power consumption, in one embodiment, the LDO main loop module further includes: a combination of a capacitor C2 and a pull-down resistor, and a combination of a capacitor C1 and a pull-down resistor, introducing a zero and a pole in the loop gain, thereby improving the phase margin and enhancing the stability of the system.

[0064] Specifically, capacitor C2 is connected between PMOS transistor M3 and the output voltage Vout, while capacitor C1 is connected between PMOS transistor M1 and the buffer module. Both capacitors are connected to ground via their own resistors. This configuration helps reflect the capacitor impedance at the input of the error amplifier rather than the output, which is known as the "Miller effect."

[0065] In one embodiment, when designing the Miller compensation network, the values of the capacitors and resistors need to be carefully selected to ensure that the loop has sufficient phase margin to remain stable.

[0066] like Figure 3-4 As shown, for example, when resistor R1 = 10kΩ, resistor R2 = 20kΩ, resistor R3 = 30kΩ, capacitor C1 = 1μF, capacitor C2 = 8μF, capacitor C3 = 10μF, the expressions for the resistor string voltage divider ratio B and the output node resistance Roeq are: B = R1 + R2 / R2 Roeq = rop∥(R1 + R2)∥R3

[0067] At the same time, due to the setting of the Buffer module, the resistance of M2 is small, and the pole of M2 is pushed to the high frequency to ignore the pole at N2 and Figure 2 The loop gain expression obtained by breaking the loop is as follows:

[0068] Among them, the capacitor C2 and the capacitor C3 are both larger than the capacitor C4, and from the above expression, it can be seen that there are three poles and a left half plane zero. .

[0069] Furthermore, when IL = 0 (i.e., when the load current is zero), the current flowing through Mp is limited to the portion of the resistor string (resistors R1 and R2), expressed as Vout / (R1+R2), which is typically very small, such as 1 to 3 μA. At this point, the current flowing through resistor R3 can be considered almost zero, reducing power consumption and improving the overall efficiency of the LDO. Furthermore, because resistor R3 is connected in parallel with resistors R1 and R2, and the resistance of R3 is greater than that of R2 and greater than that of R1, the effect of resistor R3 on the loop gain is negligible under light or no-load conditions, thereby reducing the output noise introduced by the resistor's thermal noise. Furthermore, through appropriate pole-zero configuration, the LDO's transient response to load changes can be optimized, enabling it to more quickly restore a stable output voltage.

[0070] For example, because capacitors C2 and C3 are both larger than capacitor C4, only one of the three poles mentioned above is associated with capacitor C4 and is located at a higher frequency, while the other two poles are associated with the larger capacitors C2 and C3 and are located at lower frequencies. Furthermore, a left-half-plane zero exists, which cancels one of the non-dominant poles, thereby improving the system's phase margin and enhancing its stability.

[0071] As IL gradually increases, As the output resistance increases, the output voltage decreases to maintain a stable output voltage. Since ρ is proportional to √IL, and rop is proportional to 1 / IL, the total open-loop gain is proportional to 1 / √IL and decreases as IL increases. The dominant pole at the output is proportional to IL and increases as IL increases. This shifts the dominant pole to higher frequencies, increasing the LDO's bandwidth. The gain-bandwidth product (GBW), or unity-gain bandwidth (ωu), is proportional to √IL and increases as IL increases.

[0072] In summary, the combined effects of the above enable the LDO to remain stable over a wider load current range while providing fast and accurate load regulation.

[0073] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. An internal compensation structure suitable for high-voltage LDO, characterized in that: include: A transient enhancement module is used to provide additional current when the load current changes rapidly; The transient enhancement module includes: a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, and a PMOS transistor M8. The gate of the PMOS transistor M5 is connected to the drain of the PMOS transistor M2, the source of the PMOS transistor M5 is connected to the drain of the PMOS transistor M6, the drain of the PMOS transistor M5 is grounded, the source of the PMOS transistor M6 is connected to the Vin terminal, the gate of the PMOS transistor M6 is respectively connected to the gate of the PMOS transistor M7 and the gate of the PMOS transistor M8, the source of the PMOS transistor M7 is connected to the bias module, the drain of the PMOS transistor M7 is connected to the source of the PMOS transistor M8, and the drain of the PMOS transistor M8 is respectively connected to the LDO main loop module and the drain of the PMOS transistor M3; The LDO main loop module is used to maintain the stability of the output voltage and works in conjunction with the bias module; A bias module for providing a constant bias voltage or current; the bias module includes: a current source Vbg, a current source V1, a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, and a PMOS transistor M4, wherein the source of the PMOS transistor M1 is connected to the Vin terminal, the gate is connected to the current source Vbg and is grounded, and the drain is respectively connected to the source of the PMOS transistor M3 and the gate of the PMOS transistor M4; the source of the PMOS transistor M2 is connected to the source of the PMOS transistor M1, the gate is connected to the LDO main loop module, and the drain is respectively connected to the source of the PMOS transistor M4 and the transient enhancement module; the gate of the PMOS transistor M3 is connected to the gate of the PMOS transistor M4, and the drain is connected to the transient enhancement module; the drain of the PMOS transistor M4 is connected to the current source V1 and is grounded; A bidirectional voltage level converter is located between the PMOS tube M2 and the LDO main loop module, or between the current source Vbg and the gate of the PMOS tube M1.

2. The internal compensation structure suitable for a high-voltage LDO according to claim 1, characterized in that: The LDO main loop module includes: a buffer module, a capacitor C1, a capacitor C3, a resistor R1, a resistor R2, a resistor R3, a PMOS tube M9 and a PMOS tube M10. The input end of the buffer module is connected to the drain of the PMOS tube M8, the output end of the buffer module is connected to the gate of the PMOS tube M10, the buffer module is also connected to the drain of the PMOS tube M9, and the source of the PMOS tube M9 is connected to the transient enhancement module. One end of the capacitor C1 is connected to the gate of the PMOS tube M9, and the other end of the capacitor C1 is connected to the buffer module. The source of the PMOS tube M10 is connected to the source of the PMOS tube M9, and the drain of the PMOS tube M10 is connected to the Vout terminal and grounded through the resistor R1 and the resistor R2. One end of the capacitor C3 is connected to the Vout terminal, and the other end of the capacitor C3 is grounded. One end of the resistor R3 is connected to the Vout terminal, and the other end of the resistor R3 is grounded.

3. The internal compensation structure suitable for high-voltage LDO according to claim 2, characterized in that The LDO main loop module also includes: an electrolytic capacitor C2 and an electrolytic capacitor C4. The electrolytic capacitor C2 is connected between the PMOS tube M3 and the output voltage Vout, and the electrolytic capacitor C4 is connected between the PMOS tube M1 and the buffer module. Both the electrolytic capacitor C2 and the electrolytic capacitor C4 are grounded through pull-down resistors to introduce a zero and a pole in the loop gain.

4. The internal compensation structure suitable for high-voltage LDO according to claim 3, characterized in that The internal reference voltage Start_REF in the LDO main loop module is obtained by superimposing the gate-source voltage of the PMOS tube M1 and the PMOS tube M2 by the current source V1 voltage.

5. The internal compensation structure suitable for a high-voltage LDO according to claim 1, characterized in that: The bidirectional voltage level converter includes at least an inverter INV1, an inverter INV2, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M1, an NMOS transistor M2, and a transistor Q1. The inverters INV1 and INV2 invert the phases of the transistors and apply them to the gates of the PMOS transistor M11 and the NMOS transistor N1, which are connected between a voltage source VCCB and ground. The drains of the PMOS transistor M11 and the NMOS transistor M1 are connected via a resistor R4. The gates of the PMOS transistor M12 and the NMOS transistor M2 are coupled and coupled to an enable input of the bidirectional voltage level converter. The outputs of the PMOS transistor M12 and the NMOS transistor M2 are coupled to the base of the transistor Q1. The emitter of the transistor Q1 is coupled to a bias line BIAS, and the collector of the transistor Q1 is coupled to ground.

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