A cache structure in a self-reconfigurable and self-evolving AI chip and its chip

Abstract

The present invention relates to a cache structure in a self-reconstructing and self-evolving AI chip and the chip thereof, comprising: a cache control unit for splicing image input data sent by a storage controller MC, and for rearranging image output data sent by an output cache unit to obtain rearranged data, and sending the rearranged data to the storage controller MC; an input cache unit for caching the spliced ​​data using a ping-pong cache structure; the input cache unit includes two input cache sub-units; a weight cache unit for caching weight data sent by the storage controller MC, and sending the weight data to a PE array; the PE array is for performing image processing on the spliced ​​data based on the weight data to obtain image output data; an output cache unit for caching the image output data obtained after the PE array processing; the output cache unit includes two output cache sub-units, thereby improving the computing efficiency of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a cache structure in a self-reconfigurable and self-evolving AI chip and a chip thereof. Background Art

[0002] Complex and ever-changing real-world scenarios, rapidly evolving AI algorithms, and rapidly growing target data require AI chips to adapt to the severe challenges of scenario-driven, model evolution, and storage improvement. Facing the urgent need for self-organizing and self-evolving AI chips in complex scenarios, the chip supports model self-evolution through self-reconstruction technology, achieving adaptive deployment and efficient computing of intelligent tasks.

[0003] However, existing AI chips at least have the problem of low computing efficiency due to data access. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a cache structure in a self-reconstructing and self-evolving AI chip and a chip thereof, which alleviates the problem of high memory access-to-computation ratio in AI chips and can flexibly configure the cache structure to adapt to the computing requirements of different algorithms in the face of complex application scenarios.

[0006] (II) Technical solution

[0007] In order to achieve the above object, the main technical solutions adopted by the present invention include:

[0008] In a first aspect, an embodiment of the present invention provides a cache structure in a self-reconfigurable and self-evolving AI chip, including a cache control unit, an input cache unit, a weight cache unit, a PE array, and an output cache unit;

[0009] Among them, a cache control unit, the cache control unit is connected to the input cache unit and the output cache unit respectively, the cache control unit is used to splice the image input data sent by the storage controller MC to obtain the spliced ​​data, and to rearrange the image output data sent by the output cache unit to obtain the rearranged data, and send the rearranged data to the storage controller MC; the input cache unit, the input cache unit is also connected to the PE array, the input cache unit is used to cache the spliced ​​data using a ping-pong cache structure; wherein the input cache unit includes a first input cache sub-unit and a second input cache sub-unit; a weight cache unit, the weight cache unit is connected to the PE array, the weight cache unit is used to cache the weight data sent by the storage controller MC, and send the weight data to the PE array; the PE array, the PE array is also connected to the output cache unit, the PE array is used to perform image processing on the spliced ​​data based on the weight data to obtain image output data; the output cache unit is used to cache the image output data obtained after processing by the PE array; wherein the output cache unit includes a first output cache sub-unit and a second output cache sub-unit.

[0010] Therefore, by means of the above technical solution, the embodiment of the present application provides two output caches for the PE array, significantly reducing data competition and conflicts between different processing units, and realizing localization of data storage and access. In addition, it not only significantly reduces memory access latency, but also enhances the parallel capability of the system through two parallel input and output caches, improves data access efficiency and system response speed, and thus improves the computing efficiency of the chip.

[0011] In addition, compared with existing AI chips, the self-reconstructive and self-evolving AI chip of the present application can utilize self-reconstruction technology to flexibly configure the cache structure, and adopts a local cache method to efficiently utilize the data in the memory for calculations, reduce data access delays and the number of interactions with the storage controller, thereby improving computing efficiency, increasing speed and increasing circuit flexibility.

[0012] Furthermore, the input cache unit adopts a ping-pong cache structure and uses a read-write alternating cache method to further reduce data access time.

[0013] Furthermore, the output buffer adopts a configurable implementation mode, and can independently select the output data form according to the configuration information, thereby enhancing the circuit flexibility.

[0014] In a possible embodiment, the PE array includes multiple columns of PEs; the input cache unit includes a first input cache subunit connected to a first column of PEs in the multiple columns of PEs and a second input cache subunit connected to a last column of PEs in the multiple columns of PEs.

[0015] In a possible embodiment, the first input cache sub-unit and the second input cache sub-unit are both used to control the empty or full state of the ping-pong cache according to a read request signal including a read address sent by the PE array.

[0016] In a possible embodiment, the cache control unit includes a data splicing unit, which is used to perform splicing processing on the image input data sent by the storage controller MC to obtain spliced ​​data, and send the spliced ​​data to the first input cache sub-unit and / or the second input cache sub-unit according to the cache configuration information sent by the master control.

[0017] In a possible embodiment, the weight cache unit includes a weight data forwarding unit and a plurality of first-in-first-out cache units, and each of the plurality of first-in-first-out cache units corresponds to a column of PEs in the plurality of columns of PEs;

[0018] Among them, there are multiple first-in-first-out cache units, and each of the multiple first-in-first-out cache units is used to obtain the weight data sent by the storage controller MC in a synchronous processing manner; the weight data forwarding unit is used to split the weight data to obtain multiple weight sub-data, and based on the cache configuration information sent by the master control, each weight sub-data in the multiple weight sub-data is sent to the corresponding first-in-first-out cache unit; each weight sub-data corresponds to a first-in-first-out cache unit.

[0019] In a possible embodiment, the PE array includes multiple rows of PEs; the output cache unit includes a first output cache subunit connected to a first row of PEs in the multiple rows of PEs and a second output cache subunit connected to a last row of PEs in the multiple rows of PEs.

[0020] In a possible embodiment, the cache control unit includes a data reordering unit, which is used to cache the image output data obtained after the PE array is processed, and control the amount of image output data output to the cache control unit based on the cache configuration information sent by the master control.

[0021] In a possible embodiment, the first output cache sub-unit and the second output cache sub-unit each include a plurality of register Bank units and a Bank arbitration unit;

[0022] Among them, there are multiple register Bank units, each of the multiple register Bank units is used to cache the image output data obtained after PE array processing, and write the image output data to the address corresponding to the storage address according to the storage request signal including the storage address sent by the PE array processing, and according to the cache configuration information sent by the master control, after the image output data written in the address corresponding to the storage address reaches a specified number, send a request output signal to the Bank arbitration unit; the Bank arbitration unit is used to arbitrate the request output signals sent by at least some of the register Bank units in the multiple register Bank units, obtain a first arbitration result, and select the register Bank unit with the highest priority for output according to the first arbitration result.

[0023] In a possible embodiment, each register bank unit includes multiple address polling arbitration units, and each of the multiple address polling arbitration units is used to arbitrate multiple storage request signals when receiving storage request signals sent by multiple PEs in the PE array to the same target storage address, obtain a second arbitration result, and based on the second arbitration result, write the image output data corresponding to the storage request signal with the highest priority to the target storage address.

[0024] In a second aspect, an embodiment of the present invention provides a self-reconfigurable and self-evolving AI chip, comprising multiple cache structures, and each of the multiple cache structures is a cache structure in the self-reconfigurable and self-evolving AI chip as described in any one of the first aspects.

[0025] In order to make the above-mentioned objectives, features and advantages to be achieved by the embodiments of the present application more obvious and understandable, the following specifically cites preferred embodiments and describes them in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A schematic diagram showing a cache structure in a self-reconfigurable and self-evolving AI chip provided in an embodiment of the present application is shown;

[0028] Figure 2 A schematic diagram of a cache control unit provided in an embodiment of the present application is shown;

[0029] Figure 3A schematic diagram of a scalar data rearrangement principle provided by an embodiment of the present application is shown;

[0030] Figure 4 A schematic diagram of a vector data rearrangement principle provided by an embodiment of the present application is shown;

[0031] Figure 5 A schematic diagram of an input cache subunit provided in an embodiment of the present application is shown;

[0032] Figure 6 A schematic diagram of a weight cache unit provided in an embodiment of the present application is shown;

[0033] Figure 7 A schematic diagram of an output cache unit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below through specific implementation modes in conjunction with the accompanying drawings.

[0035] In order to solve the problem of low computing efficiency in the prior art, an embodiment of the present application provides a cache structure in a self-reconstructing and self-evolving AI chip and a chip thereof, including a cache control unit, an input cache unit, a weight cache unit, a processing unit (Processing Element, PE) array and an output cache unit; wherein the cache control unit is connected to the input cache unit and the output cache unit respectively, and the cache control unit is used to splice the image input data sent by the memory controller (MemoryController, MC) to obtain the spliced ​​data, and to rearrange the image output data sent by the output cache unit to obtain the rearranged data, and send the rearranged data to the memory controller MC; the input cache unit is also connected to the PE array, and the input cache unit is used to cache the spliced ​​data using a ping-pong cache structure, wherein the input cache unit includes a first input cache subunit and a second output cache subunit. The input cache subunit; the weight cache unit is connected to the PE array, and the weight cache unit is used to cache the weight data sent by the storage controller MC, and send the weight data to the PE array; the PE array, the PE array is also connected to the output cache unit, and the PE array is used to perform image processing on the spliced ​​data based on the weight data to obtain image output data; the output cache unit is used to cache the image output data obtained after the PE array is processed, and the output cache unit includes a first output cache subunit and a second output cache subunit, thereby providing two output caches for the PE array, significantly reducing data competition and conflicts between different processing units, and realizing localization of data storage and access. In addition, it not only significantly reduces the memory access delay, but also enhances the parallel capability of the system through two parallel input and output caches, and improves data access efficiency and system response speed. In addition, each PE array can also customize the cache management strategy according to its specific computing needs and data access mode through the cache configuration information issued by the master control. In addition, the input cache unit can also be implemented using two alternating register stacks in a ping-pong structure, thereby achieving high-speed data access to suit application scenarios with continuous data streams, and accurately controlling the data update timing through the read address and read enable signals sent by the PE, thereby improving system efficiency and performance.

[0036] In order to better understand the above technical solution, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a clearer and more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0037] First embodiment

[0038] To facilitate understanding of the embodiments of the present application, the cache configuration information mentioned in the present application is first explained as follows:

[0039] "Cache configuration information": It is sent by the master control to the cache control unit, weight cache unit and output cache unit, so that the cache control unit, weight cache unit and output cache unit can perform corresponding operations based on the instructions of the corresponding fields in the cache configuration information.

[0040] And, as shown in Table 1 below, the cache configuration information can be defined as 22 bits and divided into 5 different field intervals, the first 8 bits (i.e., [7:0]) of the field interval are used to indicate whether the PE array is controlled to accept weight data, and the 9th to 12th bits (i.e., [11:8]) of the field interval are used to indicate the number of output data of the second output cache subunit ODB2, and the 13th to 16th bits (i.e., [15:12]) of the field interval are used to indicate the number of output data of the first output cache subunit ODB1, and the 17th to 20th bits (i.e., [19:16]) of the field interval are used to indicate the input cache combination, and the 21st to 22nd bits (i.e., [21:20]) of the field interval are used to indicate the multi-granularity of the control data (i.e., how many bits the data is), for example, it supports three bit widths of int4, int8, and int16.

[0041] Table 1: Cache configuration information instruction structure

[0042]

[0043] Based on the above cache configuration information, the following Figures 1 to 7 The cache structure and working principle of the self-reconfigurable and self-evolving AI chip of the present application are described in detail.

[0044] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram showing a cache structure in a self-reconfigurable and self-evolving AI chip provided in an embodiment of the present application. Figure 1 As shown, the cache structure includes a cache control unit, an input cache unit, a weight cache unit, a PE array and an output cache unit;

[0045] The cache control unit is connected to the input cache unit and the output cache unit respectively, and is used to splice the image input data sent by the storage controller MC to obtain spliced ​​data, and to rearrange the image output data sent by the output cache unit to obtain rearranged data, and send the rearranged data to the storage controller MC;

[0046] The input cache unit is also connected to the PE array, and the input cache unit is used to cache the spliced ​​data using a ping-pong cache structure; wherein the input cache unit includes a first input cache subunit and a second input cache subunit;

[0047] The weight cache unit is connected to the PE array, and is used to cache the weight data sent by the storage controller MC and send the weight data to the PE array;

[0048] The PE array is also connected to the output buffer unit, and the PE array is used to perform image processing on the spliced ​​data based on the weight data to obtain image output data;

[0049] The output cache unit is used to cache the image output data obtained after the PE array is processed; wherein the output cache unit includes a first output cache sub-unit and a second output cache sub-unit.

[0050] It should be noted here that although Figure 1 The PE array unit in the description is described by taking 6×6 PEs as an example, but those skilled in the art should understand that the PE array may also include more or fewer PEs, and the embodiments of the present application are not limited to this.

[0051] In order to facilitate understanding of each unit in the cache structure, a specific embodiment is used to describe it below.

[0052] Alternatively, if Figure 2 As shown, the cache control unit BCU includes a data splicing unit (Data Splicing Unit, DSU) and a data reflow unit (Data Reflow Unit, DRU).

[0053] Among them, the data splicing unit is used to splice multiple image input data continuously sent by the storage controller MC (for example, two image input data continuously sent, etc.) to obtain spliced ​​data, and decode the cache configuration information sent by the master control as shown in Table 1, and according to the field interval from the 17th to the 20th bit in the decoded cache configuration information used to represent the input cache combination, the spliced ​​data is sent to the first input cache sub-unit IDB1 and / or the second input cache sub-unit IDB2 (or a customized input cache combination). There are four cases in total, as shown in Table 2 below.

[0054] Table 2: Different input buffer combinations

[0055]

[0056] And, the data rearrangement unit receives data from the first output buffer subunit ODB1 and / or the second output buffer subunit ODB2, and rearranges the received image output data. In the case where only the lower 16 bits (i.e., bits 0 to 15) of each address of the scalar data are valid, the 16 bits of valid data can be sorted according to Figure 3 The data of the register bank unit in the first output buffer subunit ODB1 is rearranged in the manner of , wherein the address data No. 0 of the register bank unit in the first output buffer subunit ODB1 is used as the low bit of the rearranged data, and the address data No. 0 of the register bank unit in the second output buffer subunit ODB2 is arranged next to the first output buffer subunit ODB1; if the 128 bits (i.e., bits 0 to 127) of each address of the vector data are valid, it is rearranged and output in the same manner as the scalar data, such as Figure 4 As shown, scalar data and vector data are the computing forms that the chip of the present application can support, which are determined by the instructions sent to the PE.

[0057] Furthermore, if Figure 1 As shown, the PE array includes multiple columns of PE; the input cache unit includes a first input cache subunit IDB1 connected to the first column of PE in the multiple columns of PE and a second input cache subunit IDB2 connected to the last column of PE in the multiple columns of PE, and the ping-pong cache structure of the first input cache subunit IDB1 and the second input cache subunit IDB2 is as shown in Figure 5 The first input buffer subunit IDB1 or the second input buffer subunit IDB2 includes an input data selection unit (IDC), an output data selection unit (ODC) and a double buffer storage unit (ie, BUFFER1 and BUFFER2).

[0058] Furthermore, the first input cache subunit and the second input cache subunit can both control the empty and full state of the ping-pong cache according to the read request signal including the read address sent by the PE array, and each ping-pong cache structure (i.e., each BUFFER) can contain multiple addresses (e.g., 32 addresses, etc.), and when there is an empty cache state in the double cache, the ready signal (i.e., the ready signal) sent to the cache control unit is pulled high, so as to receive the data sent by the cache control unit; when the read address signal of the PE array is switched from reading BUFFER1 to BUFFER2, BUFFER2 is not empty at this time, indicating that the data of BUFFER1 has been used up, and the state of BUFFER1 is empty at this time, and new data can be updated to BUFFER1; when the read address signal of the PE array is switched from reading BUFFER2 to BUFFER1, BUFFER1 is not empty at this time, indicating that the data of BUFFER2 has been used up, and the state of BUFFER2 is empty at this time, and new data can be updated to BUFFER2. That is to say, the PE array can read data only when the BUFFER is not empty, otherwise the read address signal and the read request signal will be stored.

[0059] Furthermore, if Figure 6 As shown, the weight cache unit includes a weight forwarding unit (Weight Forwarding Unit, WFU) and multiple first-in-first-out cache units (FIFO Buffer Unit, FBU), and each of the multiple first-in-first-out cache units corresponds to a column of PE in the multiple columns of PE. For example, the weight cache unit includes 6 first-in-first-out cache units, etc.;

[0060] Among them, multiple first-in-first-out cache units are used to obtain weight data sent by the storage controller MC in a synchronous processing manner. For example, when the first-in-first-out cache unit receives the configuration start signal, it sends a ready signal to the storage controller MC, indicating that the weight data can be received. And, when the first-in-first-out cache unit is not full and the handshake signals with MC are valid, the write pointer continues to increase until the first-in-first-out cache unit is full; when the first-in-first-out cache unit is not empty and the ready signal sent by the PE array is valid, the read pointer continues to increase until the first-in-first-out cache unit is empty;

[0061] The weight data forwarding unit splits the weight data to obtain multiple weight sub-data, and based on the cache configuration information sent by the master control, sends each of the multiple weight sub-data to the corresponding first-in-first-out cache unit; each weight sub-data corresponds to a first-in-first-out cache unit. Among them, if the first 8-bit field of the cache configuration information is "1", it means that the corresponding PE column receives the weight data.

[0062] Furthermore, the weight data and the input data are simultaneously sent to the PE array, and the PE array performs calculations based on the weight data and the input data, obtains the image output data, and then outputs it.

[0063] Furthermore, if Figure 7 As shown, the first output buffer sub-unit ODB1 and the second output buffer sub-unit ODB2 each include a plurality of register Bank units (i.e., register Bank1 to register Bankn, where n is a preset positive integer) and a Bank arbitration unit (Bank Polling Arbitration, BPB), and the number of data written in the register Bank can be set according to actual needs. For example, the first output buffer sub-unit ODB1 and the second output buffer sub-unit ODB2 each include 16 register Bank units, and the number of registers in each register Bank unit is 8, and the bit width is 128 bits.

[0064] Furthermore, each of the multiple register Bank units is used to cache the image output data obtained after the PE array is processed, and write the image output data to the address corresponding to the storage address according to the storage request signal including the storage address sent by the PE array processing, and according to the cache configuration information sent by the master control, after the image output data written in the address corresponding to the storage address reaches a specified number, send a request output signal to the Bank arbitration unit.

[0065] Furthermore, each register bank unit includes multiple address polling arbitration units (APBs), each of which is used to arbitrate multiple storage request signals when receiving storage request signals sent by multiple PEs in the PE array to the same target storage address, obtain a second arbitration result, and write the image output data corresponding to the storage request signal with the highest priority to the target storage address based on the second arbitration result, thereby reducing the competition conflict caused by multiple PEs accessing the same target storage address at the same time. At the same time, according to the cache configuration information sent by the master control, when the data of the storage address is written to a specified number, the register bank unit will pull up a pause signal (for example, it can be a wr_en_flag signal), indicating that the register bank unit no longer receives data at this time, and there are 9 configurations of the number of output data received by the first output cache sub-unit ODB1 and the second output cache sub-unit ODB2, as shown in Table 3 below. When a write operation is completed, the register bank unit will send a write end flag signal to the PE unit corresponding to the write request.

[0066] Table 3: Output data length configuration for each output buffer

[0067]

[0068] It should be noted here that the cache structure in the self-reconstructing and self-evolving AI chip of the present application is a neural network algorithm suitable for four application scenarios: earth observation, open-pit mine intelligent driving, public safety detection, and underground multi-source disaster information fusion perception. It uses self-reconstruction technology, adapts to different weight data, and can flexibly configure the cache structure required by different algorithms.

[0069] In summary, with the help of the above technical solutions, the present application can effectively utilize the input data required by the self-reconstructing and self-evolving PE array through the splicing operation of the cache control unit, and the cache structure as a whole adopts a local cache method to temporarily process the data required by the PE array, thereby improving the access speed and reducing the complexity of the circuit design while improving the PE utilization rate. At the same time, by using reconfigurable technology, it is possible to adapt to different algorithm requirements in different application scenarios and configure the corresponding cache structure according to different algorithms. By using this application, the problem that the input feature map in the self-reconstructing and self-evolving AI chip cannot be efficiently utilized can be solved, and the flexibility of the circuit can be improved while reducing the use of resources.

[0070] It should be understood that the cache structure in the above-mentioned self-reconfigurable and self-evolving AI chip is only exemplary, and those skilled in the art may make various modifications based on the above-mentioned method, and the modified scheme also falls within the protection scope of this application.

[0071] Second embodiment

[0072] The present application also provides a self-reconfigurable and self-evolving AI chip, comprising a plurality of cache structures, and each of the plurality of cache structures is a cache structure in the self-reconfigurable and self-evolving AI chip as described in the first embodiment. For details, please refer to the relevant description of the first embodiment, which will not be repeated here.

[0073] It should be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0074] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions.

[0075] It should be noted that the word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention may be implemented by means of hardware comprising a number of different components and by means of a suitably programmed computer. Among the several means listed, several of these means may be embodied by the same hardware. The use of the words first, second, third, etc., is for convenience of expression only and does not indicate any order. These words may be understood as part of the name of the component.

[0076] In addition, it should be noted that, in the description of this specification, the description of the terms "one embodiment", "some embodiments", "embodiment", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0077] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments after knowing the basic creative concept. Therefore, the technical solution should be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0078] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention belong to the scope of the technical solution of the present invention and its equivalent technology, the present invention should also include these modifications and variations.

Claims

1. A cache structure in a self-reconfigurable and self-evolving AI chip, characterized in that: It includes a cache control unit, an input cache unit, a weight cache unit, a PE array and an output cache unit; The cache control unit is connected to the input cache unit and the output cache unit respectively, and is used to splice the image input data sent by the storage controller MC to obtain spliced ​​data, and to rearrange the image output data sent by the output cache unit to obtain rearranged data, and send the rearranged data to the storage controller MC; The input cache unit is also connected to the PE array, and is used to cache the spliced ​​data using a ping-pong cache structure; wherein the input cache unit includes a first input cache subunit and a second input cache subunit; The weight cache unit is connected to the PE array, and is used to cache the weight data sent by the storage controller MC and send the weight data to the PE array; The PE array is also connected to the output buffer unit, and the PE array is used to perform image processing on the spliced ​​data based on the weight data to obtain the image output data; The output cache unit is used to cache the image output data obtained after the PE array is processed; wherein the output cache unit includes a first output cache sub-unit and a second output cache sub-unit; The weight cache unit includes a weight data forwarding unit and a plurality of first-in-first-out cache units, and each of the plurality of first-in-first-out cache units corresponds to a column of PEs in the plurality of columns of PEs in the PE array; Among them, each of the plurality of first-in-first-out cache units is used to obtain the weight data sent by the storage controller MC in a synchronous processing manner; The weight data forwarding unit is used to split the weight data to obtain multiple weight sub-data, and based on the cache configuration information issued by the master control, send each of the multiple weight sub-data to the corresponding first-in-first-out cache unit; each weight sub-data corresponds to a first-in-first-out cache unit.

2. The cache structure according to claim 1, characterized in that: The PE array includes the multiple columns of PEs; the input cache unit includes a first input cache subunit connected to a first column of PEs in the multiple columns of PEs and a second input cache subunit connected to a last column of PEs in the multiple columns of PEs.

3. The cache structure according to claim 2, characterized in that: The first input cache sub-unit and the second input cache sub-unit are both used to control the empty or full state of the ping-pong cache according to a read request signal including a read address sent by the PE array.

4. The cache structure according to claim 3, characterized in that: The cache control unit includes a data splicing unit, which is used to splice the image input data sent by the storage controller MC to obtain spliced ​​data, and send the spliced ​​data to the first input cache sub-unit and / or the second input cache sub-unit according to the cache configuration information sent by the master control.

5. The cache structure according to claim 1, characterized in that: The PE array includes multiple rows of PEs; the output cache unit includes a first output cache subunit connected to a first row of PEs in the multiple rows of PEs and a second output cache subunit connected to a last row of PEs in the multiple rows of PEs.

6. The cache structure according to claim 5, characterized in that: The cache control unit includes a data reordering unit, which is used to cache the image output data obtained after the PE array is processed, and control the amount of image output data output to the cache control unit based on the cache configuration information sent by the master control.

7. The cache structure according to claim 5, characterized in that: The first output cache sub-unit and the second output cache sub-unit each include a plurality of register Bank units and a Bank arbitration unit; Among them, each of the multiple register Bank units is used to cache the image output data obtained after the PE array is processed, and write the image output data to the address corresponding to the storage address according to the storage request signal including the storage address sent by the PE array processing, and send a request output signal to the Bank arbitration unit after the image output data written in the address corresponding to the storage address reaches a specified number according to the cache configuration information sent by the master control; The Bank arbitration unit is used to arbitrate the request output signals sent by at least some of the multiple register Bank units, obtain a first arbitration result, and select the register Bank unit with the highest priority for output based on the first arbitration result.

8. The cache structure according to claim 7, characterized in that: Each of the register Bank units includes multiple address polling arbitration units, and each of the multiple address polling arbitration units is used to arbitrate multiple storage request signals when receiving storage request signals sent by multiple PEs in the PE array to the same target storage address, to obtain a second arbitration result, and based on the second arbitration result, write the image output data corresponding to the storage request signal with the highest priority into the target storage address.

9. A self-reconfigurable and self-evolving AI chip, characterized in that: It comprises a plurality of cache structures, and each of the plurality of cache structures is a cache structure in a self-reconfigurable and self-evolving AI chip as described in any one of claims 1 to 8.

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