A preparation method of a silicon-based embedded light sensing chip 3D integrated packaging structure

Abstract

The application discloses a preparation method of a silicon-based embedded light-sensing chip 3D integrated packaging structure, which comprises the following steps: pressing a light-sensing chip and a substrate together; making holes on the front surface of the light-sensing chip to expose the light-sensing chip Pad and wiring; edge covering of the cutting path of the light-sensing chip, ball planting on the front surface of the light-sensing chip, and cutting to obtain a chip a; fixing the chip a in a silicon groove; forming a dry film on the surface of the chip a, and forming a second metal redistribution layer on the surface; flip chip mounting a chip b, and packaging by a plastic packaging material; forming a TMV through hole and a TMV groove on the surface of the plastic packaging material; fixing a chip c on the chip b; working a third metal redistribution layer on the surface of the plastic packaging material, and ball planting; thinning the silicon wafer to expose the substrate. The application realizes three-layer chip stacking and conduction, realizes high-density 3D packaging, shortens the electrical signal conduction path between chips, accelerates the photoelectric transmission rate, does not affect the photoelectric action area of the light-sensing chip in the packaging process, and avoids pollution of the optical coupling area.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, specifically relating to a method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure. Background Technology

[0002] The optical communication industry is a rapidly developing sector. Utilizing optical fiber as the transmission medium, optical communication converts information into optical signals for transmission, offering advantages such as high transmission speed, long transmission distance, and strong anti-interference capabilities. It is gradually replacing traditional cable communication and becoming a central focus of information society development. The optical sensor chip packaging structure is the core component of the entire optical communication process. In actual packaging, problems such as optical coupling area contamination and poor packaging reliability frequently occur. Therefore, improving packaging reliability and avoiding optical coupling area contamination have become urgent challenges for the industry. Summary of the Invention

[0003] To address the technical problems existing in the prior art, the present invention aims to provide a method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure.

[0004] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows:

[0005] A method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure includes the following steps:

[0006] Step 1: Press the photosensitive chip and the substrate together. The light coupling area of ​​the substrate and the photosensitive chip are not in direct contact, and there is a gap between them to form a cavity structure.

[0007] Step 2: First, make holes on the front side of the photosensitive chip to expose the photosensitive chip pad, and then perform TSV wiring to form the first metal redistribution layer;

[0008] Step 3: Edge the cut of the photosensitive chip, then place a ball on the front of the photosensitive chip, and then cut to obtain chip a;

[0009] Step 4: Provide silicon wafers with silicon trenches;

[0010] Step 5: Fix chip a inside the silicon tank, ensuring that chip a does not contact the sidewall of the silicon tank, leaving a certain gap;

[0011] Step 6: Form a dry film on the surface of chip a and fill the gap between chip a and the silicon trench; form a second metal redistribution layer and metal pads on the surface of the dry film;

[0012] Step 7: Flip mount chip b on the metal pads from Step 6, and then encapsulate it with molding compound.

[0013] Step 8: Form TMV vias on the upper surface of the molding compound, and then fill the TMV vias. The positions of the TMV vias correspond to the metal pads of the second metal redistribution layer, which facilitates subsequent three-dimensional interconnection of signals.

[0014] Step 9: Form a TMV groove on the upper surface of the molding compound to expose chip b;

[0015] Step 10: Fix chip c onto chip b;

[0016] Step 11: Apply a third metal redistribution layer to the surface of the molding compound and form metal pads on the top layer, then add solder balls;

[0017] Step 12: Thin the silicon wafer to expose the substrate, making it easier for the optical coupling area of ​​the photosensitive chip to receive light signals.

[0018] Furthermore, in step one, a permanent bonding adhesive is used to bond the photosensitive chip to the substrate, with the photosensitive chip pad and the optical coupling area of ​​the photosensitive chip facing downwards, and the thickness of the substrate being 300-800μm.

[0019] Furthermore, in step two, the hole shape is either a straight hole structure or an oblique hole structure.

[0020] Furthermore, in step three, solder resist material is used to wrap the cut edges of the photosensitive chip.

[0021] Furthermore, in step four, the shape of the silicon trench is the same as that of chip a, the size of the silicon trench is slightly larger than that of chip a, and the size of the silicon trench is 20-50 μm outward on one side in the horizontal direction and 5-15 μm outward on one side in the vertical direction.

[0022] Furthermore, in step five, chip a is fixed to the bottom of the silicon tank by double-sided adhesive material I, the substrate is placed downwards and the solder ball I is placed upwards to facilitate signal extraction; the number of silicon tanks is the same as the number of chips a, and one chip a is fixed in one silicon tank.

[0023] Furthermore, in step six, multiple openings are formed on the surface of the dry film by coating, exposure, and development. The opening size is 10-20μm, and the opening positions correspond to the solder balls I on the surfaces of chip I and chip II, exposing the solder balls I to facilitate the output of electrical signals. Then, a second metal redistribution layer is formed at the openings through electroplating, resist removal, and etching processes. Finally, a metal pad is formed on the top of the second metal redistribution layer.

[0024] Furthermore, in step eight, TMV through holes are formed on the upper surface of the molding compound using laser drilling technology. The depth-to-diameter ratio of the TMV through holes is greater than 5:1. The TMV through holes are filled by electroplating, and the upper surface of the molding compound is ground smooth using CMP process.

[0025] Furthermore, in step nine, the size of the TMV groove is slightly larger than the chip size. Compared to the chip size, the size of the TMV groove is 10-20 μm larger on one side in the horizontal direction and 5-10 μm larger on one side in the vertical direction.

[0026] Furthermore, chip a includes chip I and chip II, chip b is a logic chip including chip III and chip IV, chip c is a memory chip including chip V and chip VI, chip III is electrically connected to chip I and chip V, and chip IV is electrically connected to chip II and chip VI.

[0027] Furthermore, in step ten, chip V and chip VI are respectively fixed to chip III and chip IV by double-sided adhesive material II and located at the bottom of the TMV groove. The chip pads of chip V and chip VI are placed upward to facilitate signal output.

[0028] This invention also discloses a silicon-based embedded photosensitive chip 3D integrated packaging structure, fabricated using the method described above. The structure includes a photosensitive chip, a logic chip, and a memory chip. The logic chip is stacked on top of the photosensitive chip, and the memory chip is stacked on top of the logic chip. The photosensitive chip 1 includes chip I and chip II, the logic chip includes chip III and chip IV, and the memory chip includes chip V and chip VI. Chips I and II are bonded to a substrate using permanent bonding adhesive. The substrate does not directly contact the optical coupling areas of chips I and II, forming a cavity structure. Chips I and II have holes etched on their front sides for TSV wiring and ball bonding. The etched paths of chips I and II are edge-wrapped with solder resist material. Chip I and Chip II are disposed on a silicon wafer. Dry films are disposed on the surfaces of Chips I and II and in the gaps between Chips I and II and the silicon wafer. A second metal redistribution layer is disposed on the dry films. Chips III and IV are flip-chip mounted on the metal pads of the second metal redistribution layer. Chips III and IV are encapsulated with a molding compound. TMV vias and TMV grooves are formed on the surface of the molding compound. Chips V and VI are fixed to Chips III and IV respectively by double-sided adhesive material II and are located in the TMV grooves. A third metal redistribution layer is disposed on the surface of the molding compound, and metal pads and solder balls are formed on its top layer. Chips III are electrically connected to Chips I and V, and Chips IV are electrically connected to Chips II and VI. By exposing the substrate, the optical coupling area of ​​the photosensitive chip can receive light signals.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] 1) This invention discloses a method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure. The photosensitive chip is embedded in a silicon trench, and then logic chips, memory chips, etc. are stacked on top of it to achieve three-layer chip stacking. The chips in each layer are connected by multi-layer metal lines and TMV vias to achieve high-density 3D packaging. The density of these line layers can shorten the electrical signal transmission path between chips and accelerate the photoelectric transmission rate.

[0031] 2) This invention discloses a method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure. First, the photosensitive chip is buried in a silicon trench, and then the substrate is exposed by chemical mechanical polishing (CMP). This facilitates the light coupling area of ​​the photosensitive chip to receive light signals. The packaging process does not affect the photoelectric action area of ​​the photosensitive chip, avoids contamination of the light coupling area, and solves the problem of light coupling area contamination in the prior art.

[0032] 3) This invention discloses a method for preparing a silicon-based embedded photosensitive chip 3D integrated packaging structure. It does not limit the number of chips, and integrates multiple chips to form a compact 3D integrated packaging structure with a smaller size. Moreover, this invention can thin the chip and increase the telecommunication interconnection and sealing between the chips of each layer, thereby improving the interconnection reliability and assemblability of the package. Attached Figure Description

[0033] Figure 1 This is a structural schematic diagram of step one of the present invention;

[0034] Figure 2 This is a schematic diagram of the structure of step two of the present invention;

[0035] Figure 3 This is a schematic diagram of the structure before cutting in step three of the present invention;

[0036] Figure 4 This is a schematic diagram of the structure after cutting in step three of the present invention; Figure 4 a is a schematic diagram of the structure of chip I101. Figure 4 b is a schematic diagram of the structure of chip II102;

[0037] Figure 5 This is a structural schematic diagram of step four of the present invention;

[0038] Figure 6 This is a structural schematic diagram of step five of the present invention;

[0039] Figure 7 This is a schematic diagram of step six of the present invention;

[0040] Figure 8 This is a structural schematic diagram of step seven of the present invention;

[0041] Figure 9 This is a structural schematic diagram of step eight of the present invention;

[0042] Figure 10 This is a schematic diagram of step nine of the present invention;

[0043] Figure 11 This is a schematic diagram of step ten of the present invention;

[0044] Figure 12 This is a structural schematic diagram of step eleven of the present invention;

[0045] Figure 13 This is a schematic diagram of step twelf of the present invention;

[0046] Among them, 1-photosensitive chip; 101-chip I; 102-chip II; 2-photosensitive chip Pad; 21-optical coupling area; 3-substrate; 4-first metal redistribution layer; 5-solder ball I; 6-solder resist material; 7-silicon trench; 8-silicon wafer; 9-double-sided adhesive material I; 10-second metal redistribution layer; 11-dry film; 12-chip Pad; 13-molding material; 14-TMV via; 15-TMV trench; 16-double-sided adhesive material II; 17-chip pad; 18-third metal redistribution layer; 19-solder ball II. Detailed Implementation

[0047] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0048] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0049] like Figure 1-13 As shown, this invention discloses a method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure, comprising the following steps:

[0050] Step 1: As Figure 1As shown, a permanent bonding adhesive is used to bond the photosensitive chip 1 and the substrate 3 together. The thickness of the substrate 3 is 300-800μm. The photosensitive chip pad 2 and the optical coupling region 21 of the photosensitive chip 1 are placed downwards. The substrate 3 and the optical coupling region 21 are not in direct contact, but are suspended between them, forming a cavity structure. Light shines through the cavity structure onto the optical coupling region 21 of the photosensitive chip 1, and the optical signal is converted into an electrical signal. Without the cavity structure, the optical coupling region 21 would be contaminated, affecting the transmission of the optical signal.

[0051] Step Two: As Figure 2 As shown, holes are first etched on the front side of the photosensitive chip 1, with the hole shape being a straight hole structure or an oblique hole structure, to expose the photosensitive chip Pad 2, and then TSV wiring is performed to form the first metal redistribution layer 4.

[0052] Step 3: As Figure 3 As shown, firstly, solder resist material 6 is used to wrap the cutting edge of the photosensitive chip 1, then solder balls I5 are implanted on the front side of the photosensitive chip 1, and then it is cut to obtain the shape shown. Figure 4 The chip a shown includes chip I 101 and chip II 102;

[0053] Step Four: As Figure 5 As shown, a silicon trench 7 is formed on the surface of silicon wafer 8 by photolithography and silicon etching. The shape of the silicon trench 7 is the same as and compatible with the shape of chip a (chip I 101 and chip II 102). The size of the silicon trench 7 is slightly larger than the size of chip I 101 and chip II 102. Compared with the size of chip I 101 and chip II 102, the size of the silicon trench 7 is 20-50μm outward on one side in the horizontal direction and 5-15μm outward on one side in the vertical direction.

[0054] Step 5: As Figure 6 As shown, chips I101 and II102 are fixed to the bottom of silicon tank 7 using double-sided adhesive material I9. The glass surfaces of chips I101 and II102 are placed downwards, and the solder balls I5 of chips I101 and II102 are placed upwards to facilitate signal output. Chips I101 and II102 do not contact the sidewalls of silicon tank 7, leaving a certain gap. The size of the gap is generally 20-50μm, and the horizontal offset of the chips is <5μm. The double-sided adhesive material I9 is ​​an adhesive film such as DAF film, or a non-conductive film such as NCF film, or other adhesive films with adhesive properties.

[0055] Step Six: As Figure 7As shown, a dry film 11 is formed on the surfaces of chip I 101 and chip II 102 by lamination. The dry film 11 uses a photosensitive material to fill the gap between chip I 101 and chip II 102 and the silicon tank 7. Multiple openings with a size of 10-20 μm are formed on the surface of the dry film 11 by coating, exposure and development. The opening positions correspond to the solder balls I5 on the surfaces of chip I 101 and chip II 102, exposing the solder balls I5 to facilitate the output of electrical signals. Then, a second metal redistribution layer 10 is formed at the openings by electroplating, resist removal and etching processes. Then, a metal pad is formed on the top layer of the second metal redistribution layer 10 using conventional technology. The second metal redistribution layer 10 can be a single layer or a multi-layer circuit.

[0056] Step Seven: As Figure 8 As shown, the chip pads 12 of chips III201 and IV202 are mounted on the surface of metal pads using a flip-chip bonding process, and then encapsulated with molding compound 13. The molding compound 13 can protect chips III201 and IV202, and can also support the wafer in subsequent processes.

[0057] Step 8: As Figure 9 As shown, TMV vias 14 are formed on the surface of the molding compound 13 using laser drilling technology. This process is simple and low-cost, and the depth-to-diameter ratio of the TMV vias 14 is greater than 5:1. The TMV vias 14 are then filled with metals such as titanium, nickel, gold, or copper through electroplating. The upper surface is then smoothed using CMP technology. The positions of the TMV vias 14 correspond to specific pads on the first metal redistribution layer 4, enabling subsequent three-dimensional signal interconnection.

[0058] Step Nine: As Figure 10 As shown, a TMV groove 15 is laser-etched on the upper surface of the molding compound 13. The size of the TMV groove 15 is slightly larger than the chip size. Compared with the chip size, the size of the TMV groove 15 is 10-20 μm outward on one side in the horizontal direction and 5-10 μm outward on one side in the vertical direction.

[0059] Step 10: As Figure 11 As shown, chips V301 and VI302 are fixed to chips III201 and IV202 respectively using double-sided adhesive material II16 and are located at the bottom of TMV groove 15. Chip pads 17 of chips V301 and VI302 are placed upwards to facilitate signal output. Double-sided adhesive material II16 is an adhesive film such as DAF film, or a non-conductive film such as NCF film, or other adhesive films with adhesive properties.

[0060] Step 11: As Figure 12As shown, a third metal redistribution layer 18 is applied to the upper surface of the molding compound 13. The top layer forms a metal pad, and then solder balls II 19 are formed on the surface of the metal pad by ball planting or solder paste printing. The third metal redistribution layer 18 can be a single layer or a multi-layer circuit.

[0061] Step Twelve: As Figure 13 As shown, the product obtained in step eleven is inverted with the silicon side facing up. The silicon wafer 8 is thinned using the CMP process to expose the substrate 3, making it easier for the optical coupling regions 21 of chip I 101 and chip II 102 to receive optical signals, thus completing the overall packaging structure.

[0062] This invention also discloses a silicon-based embedded photosensitive chip 3D integrated packaging structure, comprising a photosensitive chip 1, a logic chip, and a memory chip stacked sequentially. The logic chip is stacked on the photosensitive chip 1, and the memory chip is stacked on the logic chip. The photosensitive chip 1 includes chip I 101 and chip II 102, the logic chip includes chip III 201 and chip IV 202, and the memory chip includes chip V 301 and chip VI 302. Chips I 101 and II 102 are respectively bonded to the substrate 3 using permanent bonding adhesive. Together, the substrate 3 does not directly contact the optical coupling regions 21 of chips I 101 and II 102, forming a cavity structure. Holes are etched on the front sides of chips I 101 and II 102 and TSV wiring is performed to form the first metal redistribution layer 4 and solder balls I 5. The hole shapes are either straight or angled. The etched paths of chips I 101 and II 102 are edged with solder resist material 6. Chips I 101 and II 102 are mounted on the silicon wafer 8, and the surfaces of chips I 101 and II 102 and the chip... Dry films 11 are respectively disposed in the gaps between chip I101 and chip II102 and silicon wafer 8. A second metal redistribution layer 10 is disposed on the dry films 11. Chip pads 12 of chips III201 and IV202 are mounted on the surface of the metal pads of the second metal redistribution layer 10 by flip-chip bonding process. Chip III201 is compatible with chip I101, and chip IV202 is compatible with chip II102. Chips III201 and IV202 are encapsulated with molding compound 13, and a T-shaped ... MV via 14 and TMV groove 15, chip V 301 and chip VI 302 are fixed to chip III 201 and chip IV 202 respectively by double-sided adhesive material II 16 and are located at the bottom of TMV groove 15. A third metal redistribution layer 18 is provided on the upper surface of the molding compound 13 and a metal pad is formed on the top of it. Then, solder balls II 19 are formed on the surface of the metal pad by ball planting or solder paste printing. By exposing the substrate 3, the optical coupling area 21 of chip I 101 and chip II 102 can receive optical signals.

[0063] Example 1

[0064] like Figure 1-13As shown in the figure, this embodiment discloses a method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure, including the following steps:

[0065] Step 1: As Figure 1 As shown, the photosensitive chip 1 and the substrate 3 are bonded together using permanent bonding adhesive. The substrate 3 is made of glass with a thickness of 300μm. The photosensitive chip Pad 2 and the optical coupling region 21 of the photosensitive chip 1 are placed downwards. The substrate 3 and the optical coupling region 21 are not in direct contact, but are suspended between them, forming a cavity structure. Light shines through the cavity structure onto the optical coupling region 21 of the photosensitive chip 1, and the optical signal is converted into an electrical signal.

[0066] Step Two: As Figure 2 As shown, holes are first etched on the front side of the photosensitive chip 1, with the hole shape being an oblique hole structure, to expose the photosensitive chip Pad 2. Then, TSV wiring is performed to form the first metal redistribution layer 4.

[0067] Step 3: As Figure 3 As shown, firstly, solder resist material 6 is used to wrap the cutting edge of the photosensitive chip 1, then solder balls I5 are implanted on the front side of the photosensitive chip 1, and then it is cut to obtain the shape shown. Figure 4 Chip I 101 and chip II 102 are shown; in this embodiment, the solder resist material 6 is photosensitive ink photoresist;

[0068] Step Four: As Figure 5 As shown, a silicon trench 7 is formed on the surface of a silicon wafer 8 using conventional photolithography and silicon etching. The shape of the silicon trench 7 is the same as that of the chip, generally rectangular. The size of the silicon trench 7 is slightly larger than that of the chip. Compared to the chip size, the size of the silicon trench 7 is 20 μm larger on one side in the horizontal direction and 5 μm larger on one side in the vertical direction.

[0069] Step 5: As Figure 6 As shown, chips I101 and II102 are fixed to the bottom of the silicon tank 7 using double-sided adhesive material I9. The glass surfaces of chips I101 and II102 are placed downwards, and the solder balls I5 of chips I101 and II102 are placed upwards to facilitate signal output. Chips I101 and II102 do not contact the sidewalls of the silicon tank 7, leaving a certain gap with a size of 20μm. The horizontal offset of the chips is <5μm. In this embodiment, the double-sided adhesive material I9 is ​​a DAF film.

[0070] Step Six: As Figure 7As shown, a dry film 11 is formed on the surfaces of chip I 101 and chip II 102 by lamination. The dry film 11 uses a commercially available photosensitive material (polymer compound) to fill the gap between chip I 101 and chip II 102 and the silicon tank 7. Multiple openings with a size of 10 μm are formed on the surface of the dry film 11 by coating, exposure and development. The opening positions correspond to the solder balls 5 on the surfaces of chip I 101 and chip II 102, exposing the solder balls 5 to facilitate the output of electrical signals. Then, a second metal redistribution layer 10 is formed at the openings by electroplating, resist removal and etching processes. Finally, a metal pad is formed on the top layer of the second metal redistribution layer 10 using conventional technology. The second metal redistribution layer 10 is a circuit layer.

[0071] Step Seven: As Figure 8 As shown, the chip pads 12 of chips III201 and IV202 are mounted on the surface of metal pads using a flip-chip bonding process, and then encapsulated with molding compound 13 (epoxy resin). The molding compound 13 can protect chips III201 and IV202, and can also support the wafer in subsequent processes.

[0072] Step 8: As Figure 9 As shown, TMV vias 14 are formed on the surface of the molding compound 13 using laser drilling technology. The depth-to-diameter ratio of the TMV vias 14 is greater than 5:1. The TMV vias 14 are then filled with titanium using electroplating. The upper surface is then ground smooth using CMP technology. The positions of the TMV vias 14 correspond to specific pads on the first metal redistribution layer 4, enabling subsequent three-dimensional signal interconnection.

[0073] Step Nine: As Figure 10 As shown, a TMV groove 15 is laser-etched on the upper surface of the molding compound 13. The size of the TMV groove 15 is slightly larger than the chip size. Compared with the chip size, the size of the TMV groove 15 is 10μm outward on one side in the horizontal direction and 5μm outward on one side in the vertical direction.

[0074] Step 10: As Figure 11 As shown, chips V301 and VI302 are fixed to chips III201 and IV202 respectively using double-sided adhesive material II16 and are located at the bottom of TMV groove 15. The chip pads 17 of chips V301 and VI302 are placed upwards to facilitate signal output. It should be noted that chips III201 and V301 are the same size, and the upper and lower layers are as symmetrical as possible. Chips IV202 and VI302 are the same size, and the upper and lower layers are as symmetrical as possible to avoid excessive warping of the chips and molding compound due to mismatch of thermal expansion coefficients. In this embodiment, double-sided adhesive material II16 is DAF film.

[0075] Step 11: As Figure 12 As shown, a third metal redistribution layer 18 is applied to the upper surface of the molding compound 13. The top layer forms a metal pad, and then solder balls II 19 are formed on the surface of the metal pad by ball planting. The third metal redistribution layer 18 is a single circuit layer.

[0076] Step Twelve: As Figure 13 As shown, the product obtained in step eleven is inverted with the silicon side facing up. The silicon wafer 8 is thinned using the CMP process to expose the substrate 3, making it easier for the optical coupling regions 21 of chip I 101 and chip II 102 to receive optical signals, thus completing the overall packaging structure.

[0077] This embodiment also discloses a silicon-based embedded photosensitive chip 3D integrated packaging structure, including a photosensitive chip 1, a logic chip, and a memory chip stacked sequentially. The logic chip is stacked on the photosensitive chip 1, and the memory chip is stacked on the logic chip. The photosensitive chip 1 includes chip I 101 and chip II 102, the logic chip includes chip III 201 and chip IV 202, and the memory chip includes chip V 301 and chip VI 302. Chips I 101 and II 102 are respectively bonded to the substrate 3D using permanent bonding adhesive. The substrate 3 is pressed together, and the optical coupling areas 21 of chips I 101 and II 102 are not in direct contact, forming a cavity structure. Holes are etched on the front sides of chips I 101 and II 102 to form the first metal redistribution layer 4 and solder balls I 5. The holes are angled. The etched paths of chips I 101 and II 102 are edged with solder resist material 6. Chips I 101 and II 102 are mounted on the silicon wafer 8, and the surfaces of chips I 101 and II 102 and the chip... Dry films 11 are respectively disposed in the gaps between chip I101 and chip II102 and silicon wafer 8. A second metal redistribution layer 10 is disposed on the dry films 11. The chip pads 12 of chips III201 and IV202 are mounted on the surface of the metal pads of the second metal redistribution layer 10 by flip-chip bonding process. Chip III201 is compatible with chip I101, and chip IV202 is compatible with chip II102. Chips III201 and IV202 are encapsulated with molding compound 13. TMV vias 14 and TMV grooves 15 are formed. Chips V 301 and VI 302 are fixed to chips III 201 and IV 202 respectively by double-sided adhesive material II 16 and are located at the bottom of TMV grooves 15. A third metal redistribution layer 18 is provided on the upper surface of the molding compound 13 and a metal pad is formed on its top. Then, solder balls II 19 are formed on the surface of the metal pad by ball planting. By exposing the substrate 3, the optical coupling regions 21 of chips I 101 and II 102 can receive optical signals.

[0078] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0079] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure, characterized in that, Includes the following steps: Step 1: Press the photosensitive chip and the substrate together, ensuring that the light coupling area between the substrate and the photosensitive chip is not in contact; Step 2: First, make holes on the front of the photosensitive chip to expose the photosensitive chip pad, and then rewire it; Step 3: Edge the cut of the photosensitive chip, then place a ball on the front of the photosensitive chip, and then cut to obtain chip a; Step 4: Provide silicon wafers with silicon trenches; Step 5: Fix chip a inside the silicon tank, ensuring that chip a does not contact the sidewall of the silicon tank, leaving a certain gap; Step 6: Form a dry film on the surface of chip a and fill the gap between chip a and the silicon trench; form metal pads on the surface of the dry film; Step 7: Flip mount chip b on the metal pads from Step 6, and then encapsulate it with molding compound. Step 8: Form TMV through-holes on the upper surface of the molding compound, and then fill the TMV through-holes; Step 9: Form a TMV groove on the upper surface of the molding compound to expose chip b; Step 10: Fix chip c onto chip b; Step 11: Form metal pads on the surface of the molding compound, then implant the solder balls; Step 12: Thin the silicon wafer to expose the substrate, making it easier for the optical coupling area of ​​the photosensitive chip to receive light signals.

2. The method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure according to claim 1, characterized in that, In step one, a permanent bonding adhesive is used to bond the photosensitive chip to the substrate. The photosensitive chip pad and the optical coupling area of ​​the photosensitive chip are placed downwards. The thickness of the substrate is 300-800μm.

3. The method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure according to claim 1, characterized in that, In step two, the hole shape is either a straight hole structure or an oblique hole structure.

4. The method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure according to claim 1, characterized in that, In step four, the shape of the silicon trench is the same as that of chip a, the size of the silicon trench is slightly larger than that of chip a, and the size of the silicon trench is 20-50μm outward on one side in the horizontal direction and 5-15μm outward on one side in the vertical direction.

5. The method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure according to claim 1, characterized in that, In step five, chip a is fixed to the bottom of the silicon tank using double-sided adhesive material I, with the substrate facing downwards and solder balls I facing upwards to facilitate signal extraction; the number of silicon tanks is the same as the number of chips a, with one chip a fixed in one silicon tank.

6. The method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure according to claim 1, characterized in that, In step six, multiple openings are formed on the surface of the dry film by coating, exposure, and development. Then, a second metal redistribution layer is formed at the openings by electroplating, resist removal, and etching processes. Finally, metal pads are formed on the top of the second metal redistribution layer.

7. The method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure according to claim 1, characterized in that, In step eight, TMV through holes are formed on the upper surface of the molding compound using laser drilling technology. The depth-to-diameter ratio of the TMV through holes is greater than 5:

1. The TMV through holes are filled by electroplating, and the upper surface of the molding compound is ground smooth using CMP process.

8. The method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure according to claim 1, characterized in that, Chip a includes chip I and chip II, chip b is a logic chip including chip III and chip IV, chip c is a memory chip including chip V and chip VI, chip III is electrically connected to chip I and chip V, and chip IV is electrically connected to chip II and chip VI.

9. The method for fabricating a silicon-based embedded photosensitive chip 3D integrated packaging structure according to claim 8, characterized in that, In step ten, chips V and VI are fixed to chips III and IV respectively by double-sided adhesive material II and are located at the bottom of the TMV groove. The chip pads of chips V and VI are placed upward to facilitate signal output.

10. A silicon-based embedded photosensitive chip 3D integrated packaging structure, characterized in that, The silicon-based embedded photosensitive chip 3D integrated packaging structure, fabricated using any one of claims 1-9, comprises a photosensitive chip, a logic chip, and a memory chip. The logic chip is stacked on the photosensitive chip, and the memory chip is stacked on the logic chip. The photosensitive chip includes chip I and chip II, the logic chip includes chip III and chip IV, and the memory chip includes chip V and chip VI. Chips I and II are bonded to a substrate using permanent bonding adhesive. The substrate does not directly contact the photocoupled regions of chips I and II, forming a cavity structure. Chips I and II have holes etched on their front sides for TSV wiring and ball bonding. The etched paths of chips I and II are edge-wrapped with solder resist material. Chips I and II are disposed on a silicon wafer. A dry film is disposed on the surface of chip I and chip II, and in the gap between chip I and chip II and the silicon wafer. A second metal redistribution layer is disposed on the dry film. Chips III and IV are flip-chip mounted on the surface of the metal pads of the second metal redistribution layer. Chips III and IV are wrapped with a molding compound. TMV vias and TMV grooves are formed on the surface of the molding compound. Chips V and VI are fixed to chips III and IV respectively by double-sided adhesive material II and are located in the TMV grooves. A third metal redistribution layer is disposed on the surface of the molding compound, and metal pads and solder balls are formed on its topmost layer. Chip III is electrically connected to chips I and V, and chip IV is electrically connected to chips II and VI. By exposing the substrate, the optical coupling area of ​​the photosensitive chip can easily receive optical signals.

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