Interposer and test method thereof, semiconductor structure

Abstract

The present application provides an interposer and a test method thereof, as well as a semiconductor structure. The interposer includes a test area and a functional area. The interposer includes an insulating layer and a conductive structure located in the test area and the functional area. The insulating layer includes a plurality of insulating film layers; each opening of the insulating layer includes one sub-opening or more than two sub-openings; the test area and the functional area are respectively provided with openings. The conductive structure includes a plurality of conductive parts and a plurality of rewiring layers; a conductive part is provided in each sub-opening; a rewiring layer is provided between any two adjacent insulating film layers; the rewiring layer includes a plurality of wires and a plurality of conductive blocks; a conductive block is provided between two adjacent conductive parts in at least one opening, and each wire is in contact with the conductive parts in at least two corresponding openings; the test area and the functional area are respectively provided with at least one wire and a plurality of conductive blocks; the portion of the conductive structure located in the test area is insulated from the portion located in the functional area; the portion of the conductive structure located in the test area is used to test whether it has a short circuit and an open circuit.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an interposer and a testing method thereof, and a semiconductor structure. Background Art

[0002] In the semiconductor field, interposers can achieve high-density interconnection between chips. Using interposers for chip integration can achieve more complex multi-chip module design, improve system performance and reduce overall size. It is an important technology to improve chip integration and improve integrated circuit performance.

[0003] With the increase in the types and number of chips integrated on the interposer, the wiring density, wiring complexity and the number of conductive vias in the interposer are getting higher and higher, and the difficulty of open circuit and short circuit testing of the interposer is also increasing. The current microscope observation method can no longer meet the testing requirements of the interposer. Summary of the invention

[0004] The embodiments of the present application provide an interposer and a testing method thereof, and a semiconductor structure.

[0005] According to a first aspect of an embodiment of the present application, an interposer is provided. The interposer includes a test area and a functional area; the interposer includes:

[0006] An insulating layer, located in the test area and the functional area; the insulating layer comprises a plurality of insulating film layers stacked in layers; the insulating layer is provided with a plurality of openings, each of the openings comprises a sub-opening or two or more sub-openings arranged along the stacking direction of the insulating film layers, and each of the sub-openings penetrates one of the insulating film layers; some of the openings are located in the test area, and some of the openings are located in the functional area;

[0007] A conductive structure, comprising a plurality of conductive parts and a plurality of rewiring layers; one conductive part is respectively arranged in each of the sub-openings; the rewiring layer is arranged between any two adjacent insulating film layers; each of the rewiring layers comprises a plurality of conductive wires and a plurality of conductive blocks; the conductive block is located between two adjacent conductive parts in the same opening, each of the conductive wires corresponds to at least two of the openings, and contacts with a conductive part located in the corresponding opening; at least one of the conductive wires and a plurality of the conductive blocks are located in the test area, and at least one of the conductive wires and a plurality of the conductive blocks are located in the functional area; the portion of the conductive structure located in the test area is insulated from the portion located in the functional area; the portion of the conductive structure located in the test area is used to test whether there is a short circuit or an open circuit.

[0008] In one embodiment, the insulating layer includes a first surface and a second surface opposite to each other; the insulating layer includes N insulating film layers, where N is a positive integer greater than or equal to 2; the conductive wires of the conductive structure include a plurality of first conductive wires located in the test area; the conductive structure includes a disconnection test structure located in the test area, and the disconnection test structure includes N-1 first sub-test structures and at least one second sub-test structure;

[0009] Each of the first sub-test structures includes a first conductive wire and two first conductive connection parts located on the side of the first conductive wire away from the second surface and in contact with the first conductive wire, and the conductive end of the first conductive connection part away from the second surface is exposed from the insulating layer; each of the first conductive wires corresponds to two of the openings, and each of the first conductive connection parts includes each of the conductive parts located in an opening corresponding to the first conductive wire, and when the opening includes more than two sub-openings, the first conductive connection part also includes a conductive block located between two adjacent conductive parts; the first conductive wires of N-1 first sub-test structures are respectively located in different rewiring layers; each of the second sub-test structures includes a second conductive connection part, and the conductive end of the second conductive connection part away from the second surface and the conductive end away from the first surface are respectively exposed from the insulating layer; the second conductive connection part includes each of the conductive parts located in an opening penetrating the insulating layer and a conductive block located between two adjacent conductive parts.

[0010] In one embodiment, the insulating layer includes a first surface and a second surface relative to each other; the conductive structure includes a short-circuit test structure located in the test area, the short-circuit test structure includes at least two third sub-test structures, each of the third sub-test structures includes a third conductive connection part; each of the third conductive connection parts includes each conductive part located in an opening penetrating the insulating layer and a conductive block located between two adjacent conductive parts; the conductive end of the third conductive connection part away from the second surface and the conductive end away from the first surface are respectively exposed from the insulating layer.

[0011] In one embodiment, the conductive structure includes a parasitic parameter test structure located in the test area; the insulating layer includes a first surface and a second surface opposite to each other; the insulating layer includes N insulating film layers, N is a positive integer greater than or equal to 2; the conductive wires of the conductive structure include a plurality of second conductive wires located in the test area; the parasitic parameter test structure includes N-1 fourth sub-test structures and at least one fifth sub-test structure; each of the fourth sub-test structures includes a second conductive wire and three fourth conductive connection parts located on a side of the second conductive wire away from the second surface and in contact with the second conductive wire, and the three fourth conductive connection parts are arranged in parallel; the second conductive wire corresponds to the three openings, and each of the fourth conductive connection parts includes Including each conductive part located in an opening corresponding to the second conductive wire, when the opening includes more than two sub-openings, the fourth conductive connection part also includes a conductive block located between two adjacent conductive parts; the conductive end of each fourth conductive connection part away from the second surface is exposed from the insulating layer; the second conductive wires of N-1 fourth sub-test structures are respectively located in different rewiring layers; each fifth sub-test structure includes a fifth conductive connection part, and the conductive end of the fifth conductive connection part away from the second surface and the conductive end away from the first surface are respectively exposed from the insulating layer; the fifth conductive connection part includes a conductive part located in an opening passing through the insulating layer and a conductive block located between two adjacent conductive parts.

[0012] In one embodiment, the insulating layer includes a first surface and a second surface relative to each other; the conductive wires of the conductive structure include at least one third conductive wire and an auxiliary conductive wire located in the test area; the parasitic parameter test structure also includes a sixth sub-test structure, the sixth sub-test structure includes one third conductive wire, and two sixth conductive connection parts located on the side of the third conductive wire away from the second surface, the auxiliary conductive wire located between the first surface and the third conductive wire, and two conductive parts located between the auxiliary conductive wire and the third conductive wire; the conductive end of each sixth conductive connection part away from the second surface is exposed from the insulating layer; the third conductive wire is opposite to two openings, and the opening includes at least two sub-openings; the sixth conductive connection part includes each conductive part located in one of the openings corresponding to the third conductive wire and a conductive block located between adjacent conductive parts; an insulating film layer is provided between the auxiliary conductive wire and the third conductive wire, and the two conductive parts located between the auxiliary conductive wire and the third conductive wire are in contact with the third conductive wire and the auxiliary conductive wire respectively; the sizes of each conductive part of the sixth sub-test structure and each conductive part of the fourth sub-test structure are the same.

[0013] In one embodiment, the conductive wire of the conductive structure includes a fourth conductive wire located in the test area; the extension direction of the second conductive wire is different from the extension direction of the fourth conductive wire; the parasitic parameter test structure also includes a seventh sub-test structure, the seventh sub-test structure includes the fourth conductive wire, and two seventh conductive connection parts located on the side of the fourth conductive wire away from the second surface and connected to the conductive wire, the fourth conductive wire corresponds to two openings, each of the seventh conductive connection parts includes a conductive part located in an opening corresponding to the fourth conductive wire, when the opening includes more than two sub-openings, the seventh conductive connection part also includes a conductive block located between two adjacent conductive parts; the conductive end of the seventh conductive connection part away from the second surface exposes the insulating layer.

[0014] In one embodiment, the insulating layer includes a first surface and a second surface relative to each other; the conductive wires of the conductive structure include a plurality of fifth conductive wires located in the test area; the conductive structure includes a signal crosstalk test structure located in the test area; the signal crosstalk test structure includes a plurality of eighth sub-test structures, the eighth sub-test structure includes one fifth conductive wire, and two eighth conductive connection parts located on the side of the fifth conductive wire away from the second surface and connected to the fifth conductive wire, the fifth conductive wire corresponds to two openings; the conductive end of each eighth conductive connection part away from the second surface is exposed from the insulating layer; each eighth conductive connection part includes a conductive part located in an opening corresponding to the fifth conductive wire, and when the opening includes more than two sub-openings, the eighth conductive connection part also includes a conductive block located between two adjacent conductive parts; the extension directions of each of the conductive wires in the signal crosstalk test structure are parallel to each other, and at least two of the fifth conductive wires are located in different rewiring layers.

[0015] According to a second aspect of an embodiment of the present application, a semiconductor structure is provided, which includes a plurality of chips and the above-mentioned intermediate layer; each of the chips is located on a side of the insulating layer away from the second surface, and is respectively electrically connected to a conductive part located in an opening in the functional area.

[0016] According to a third aspect of an embodiment of the present application, a method for testing an interposer is provided, for testing the interposer described above; the testing method comprises:

[0017] Determine whether a portion of the conductive structure located in the test area has a short circuit or an open circuit;

[0018] If a short circuit and / or an open circuit exists in the portion of the conductive structure located in the test area, it is determined that the portion of the conductive structure located in the functional area does not meet the requirements.

[0019] In one embodiment, when the conductive structure includes a short circuit test structure located in the test area, the step of determining whether a part of the conductive structure located in the test area has a short circuit includes:

[0020] For each of the first sub-test structures, determining whether the first sub-test structure has a short circuit; for each of the second sub-test structures, determining whether the second sub-test structure has a short circuit;

[0021] If at least one of the first sub-test structures has a short circuit, it is determined that the portion of the conductive structure located in the test area has a short circuit; if at least one of the second sub-test structures has a short circuit, it is determined that the portion of the conductive structure located in the test area has a short circuit.

[0022] In one embodiment, when the conductive structure includes a short circuit test structure located in the test area, the step of determining whether a short circuit exists in a portion of the conductive structure located in the test area includes:

[0023] Determine whether there is a short circuit between any two of the third sub-test structures;

[0024] If there is a short circuit between two of the third sub-test structures, it is determined that a short circuit exists in a portion of the conductive structure located in the test area.

[0025] In one embodiment, when the conductive structure includes a parasitic parameter test structure located in the test area, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes:

[0026] For each of the fourth sub-test structures, a first parasitic parameter and a second parasitic parameter of the fourth sub-test structure are detected; a third parasitic parameter of the fifth conductive connection portion is detected; the first parasitic parameter is a parasitic parameter between conductive ends of two fourth conductive connection portions located on both sides of the three fourth conductive connection portions, and the second parasitic parameter is a parasitic parameter between conductive ends of two adjacent fourth conductive connection portions of the three fourth conductive connection portions; the third parasitic parameter is a parasitic parameter between two conductive ends of the fifth conductive connection portion; the parasitic parameter includes at least one of a parasitic resistance and a parasitic capacitance;

[0027] For each of the fourth sub-test structures, parasitic parameters of the fourth conductive connection portion and parasitic parameters of the second conductive line per unit length in the fourth sub-test structure are calculated according to the first parasitic parameters and the second parasitic parameters.

[0028] In one embodiment, in one embodiment, the parasitic parameters include parasitic resistance, parasitic capacitance and parasitic impedance; the first parasitic parameter includes a first parasitic impedance, and the second parasitic parameter includes a second parasitic impedance; for each of the fourth sub-test structures, after calculating the parasitic parameters of the fourth conductive connection portion and the parasitic parameters of the second wire per unit length in the fourth sub-test structure according to the first parasitic parameter and the second parasitic parameter, the test method further includes:

[0029] For each of the fourth sub-test structures, the parasitic inductance of the fourth conductive connection portion and the parasitic inductance of the second conductive wire per unit length are calculated based on the first parasitic impedance, the second parasitic impedance, the parasitic resistance and parasitic capacitance of the fourth conductive connection portion, and the parasitic resistance and parasitic capacitance of the second conductive wire per unit length.

[0030] In one embodiment, the first parasitic parameter includes a first parasitic resistance, and the second parasitic parameter includes a second parasitic resistance;

[0031] When the parasitic parameter test structure includes the sixth sub-test structure, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes:

[0032] detecting a third parasitic resistance between two conductive ends of the sixth sub-test structure;

[0033] The parasitic resistance of the conductive end is calculated based on the resistance per unit length of the second conductive wire located in the same rewiring layer as the auxiliary conductive wire, the third parasitic resistance, the parasitic resistance of the fourth conductive connecting part including only one conductive part, the fourth parasitic resistance and the fifth parasitic resistance; the fourth parasitic resistance is the parasitic resistance of the fourth conductive connecting part in the fourth sub-test structure where the second conductive wire located in the same rewiring layer as the third conductive wire is located, and the fifth parasitic resistance is the parasitic resistance per unit length of the second conductive wire located in the same rewiring layer as the third conductive wire, and the parasitic resistance of the conductive end is calculated.

[0034] In one embodiment, when the conductive structure includes a signal crosstalk test structure located in the test area, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes:

[0035] Applying a test signal to the conductive ends of the eighth conductive connection parts away from the second surface in at least two of the eighth sub-test structures at the same time, wherein the test signal is a pulse signal or a sinusoidal signal;

[0036] receiving output signals of each of the eighth sub-test structures;

[0037] For each of the eighth sub-test signals, a difference between parameters of the test signal and the output signal is determined according to the test signal and the output signal of the eighth sub-test structure, wherein the parameter includes at least one of a frequency, an amplitude and a phase difference. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a top view of an interposer provided by an exemplary embodiment of the present application;

[0039] Figure 2 yes Figure 1 The partial cross-sectional view of the portion of the interposer located in the functional area is obtained by cutting along AA;

[0040] Figure 3 yes Figure 1 The partial cross-sectional view of the portion of the interposer located in the test area is obtained by cutting along AA;

[0041] Figure 4 yes Figure 1 The partial cross-sectional view of the portion of the interposer located in the test area is obtained by cutting along AA;

[0042] Figure 5 yes Figure 1 The partial cross-sectional view of the portion of the interposer located in the test area is obtained by cutting along AA;

[0043] Figure 6 yes Figure 1 The partial cross-sectional view of the portion of the interposer located in the test area is obtained by cutting along AA;

[0044] Figure 7 yes Figure 1 The partial cross-sectional view of the portion of the interposer located in the test area is obtained by cutting along AA;

[0045] Figure 8 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application. Specific embodiments

[0046] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The following embodiments and features in the embodiments can be combined with each other without conflict.

[0047] If there are terms involving directional indications or positional relationships in the embodiments of the present application (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationship, movement, etc. between the components in a certain specific posture; if the specific posture changes, the directional indication or positional relationship will also change accordingly. In addition, the terms "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of convenience of description and cannot be understood as indicating or implying relative importance.

[0048] The present application embodiment provides an intermediate layer. Figure 1 As shown, the interposer 100 includes a test area 101 and a functional area 102. Figure 2 and Figure 3 As shown, the interposer includes an insulating layer 10 and a conductive structure.

[0049] The insulating layer 10 is located in the test area 101 and the functional area 102, and includes a first surface 11 and a second surface 12 relative to each other; the insulating layer 10 includes a plurality of stacked insulating film layers 13; the insulating layer 10 is provided with a plurality of openings 131, each of the openings 131 includes a sub-opening or two or more sub-openings 1311 arranged along the stacking direction of the insulating film layer 13, and each of the sub-openings 1311 penetrates one of the insulating film layers 13; some of the openings 131 are located in the test area 101, and some of the openings 131 are located in the functional area 102.

[0050] The conductive structure includes multiple conductive parts 30 and multiple rewiring layers 40; each of the sub-openings 1311 is provided with a conductive part 30; a rewiring layer 40 is provided between any two adjacent insulating film layers 13; each of the rewiring layers 40 includes multiple wires 41 and multiple conductive blocks 42; the conductive blocks 42 are located between two adjacent conductive parts 30 in the same opening 131 and are respectively in contact with the two adjacent conductive parts 30; each of the conductive wires 41 corresponds to at least two of the openings 131, and is in contact with one of the conductive parts 30 located in the corresponding opening 131, specifically, the conductive wire is in contact with the conductive part 30 in the corresponding opening 131 that is closest to it; at least one of the conductive wires 41 and multiple conductive blocks 42 are located in the test area 101, and at least one of the conductive wires 41 and multiple conductive blocks 42 are located in the functional area 102. The portion of the conductive structure located in the test area 101 is insulated from the portion located in the functional area 102 ; the portion of the conductive structure located in the test area 101 is used to test whether there is a short circuit or an open circuit.

[0051] In the semiconductor field, in the process of preparing the interposer, each wire 41 and each conductive block 42 located in the same rewiring layer are formed at the same time, and each sub-opening 131 penetrating the same insulating film layer 13 is formed in the same process step. In the process of preparing the rewiring layer 40, the wire 41 may be broken or the surface of the rewiring layer 40 in contact with the conductive part 30 may be contaminated by non-conductive stains, which will cause the conductive path in the interposer to be broken; in the process of forming the interposer, if the conductive block 42 and the corresponding conductive part 30 are misaligned, it may also cause the conductive path in the interposer to be broken, or the conductive block 42 may contact the non-corresponding conductive part 30 and cause a short circuit. Since the parts of each wire 41 and each conductive block 42 located in the same rewiring layer located in the test area 101 and the functional area 102 are formed at the same time, and the sub-openings 131 penetrating the same insulating film layer 13 in the test area 101 and the functional area 102 are formed at the same time, when the part of the conductive structure located in the test area has a problem of breaking or short circuit, the functional area also has the same problem.

[0052] The interposer provided in the embodiment of the present application can determine whether the portion of the conductive structure located in the test area has short circuit and open circuit problems by testing the portion of the conductive structure located in the test area, and further determine whether the portion of the conductive structure located in the functional area has short circuit and open circuit problems. Since the portion of the conductive structure located in the test area is insulated from the portion located in the functional area, during the process of applying a test electrical signal to the portion of the conductive structure located in the test area for testing, the test electrical signal will not flow to the functional area, thereby preventing the test electrical signal from being too large to cause damage to the portion of the conductive structure located in the functional area.

[0053] The embodiment of the present application also provides a method for testing an interposer layer, which is used to test the interposer layer; the method comprises the following steps:

[0054] Determine whether a portion of the conductive structure located in the test area has a short circuit or an open circuit;

[0055] If a short circuit and / or an open circuit exists in the portion of the conductive structure located in the test area, it is determined that the portion of the conductive structure located in the functional area does not meet the requirements.

[0056] As analyzed above, when it is determined that the portion of the conductive structure located in the test area has at least one of short circuit and open circuit problems, it can be determined that the portion of the conductive structure located in the functional area has the same problem, and therefore it can be determined that the portion of the conductive structure located in the functional area does not meet the requirements.

[0057] In the embodiment of the present application, the portion of the conductive structure located in the test area 101 is only used for testing and is not used to connect to electrical components such as chips; the portion of the conductive structure located in the functional area 102 is used to electrically connect to electrical components, and can achieve signal connectivity and signal extraction between different electrical components.

[0058] In one embodiment, Figure 1 As shown, the test area 101 is located on one side of the functional area 102. In this way, when it is determined that the portion of the conductive structure located in the functional area 102 meets the requirements, it is convenient to cut off the portion of the interposer located in the test area 101, so that only the portion of the interposer located in the functional area 102 is retained, which helps to reduce the size of the semiconductor structure including the interposer.

[0059] In one embodiment, Figure 2 As shown, in the functional area 102, some of the openings 131 extend from the first surface 11 toward the second surface 12, and some of the openings 131 extend from the second surface 12 to the first surface 11; some of the openings 131 penetrate the insulating layer 10, and the openings 131 penetrating the insulating layer 10 means that the openings 131 include sub-openings 1311 penetrating all insulating film layers 13; some of the openings 131 include sub-openings 1311 penetrating part of the insulating film layer 13; when the opening 131 includes multiple sub-openings 1311, the conductive parts 30 in each sub-opening 1311 are electrically connected, specifically, adjacent conductive parts 30 in the same opening 131 can be electrically connected through a conductive block 42 located therebetween.

[0060] In one embodiment, Figures 1 to 3 As shown, the interposer also includes a plurality of first solder balls 50 located on the first surface 11 and a plurality of second solder balls 60 located on the second surface 12, each first solder ball 50 is electrically connected to a conductive part 30, and each second solder ball 60 is electrically connected to a conductive part 30. The first solder ball 50 is used for soldering to electrical components, and the second solder ball 60 can be used for soldering to circuit boards. The conductive end mentioned later is the first solder ball or the second solder ball. In other embodiments, the first surface 11 may not be provided with the first solder ball 50, and the electrical component may be electrically connected to the surface of the conductive part 30 that exposes the insulating layer 10 through a bonding process. The conductive end mentioned later is the surface of the conductive part 30 that exposes the insulating layer 10.

[0061] In one embodiment, in the intermediate layer, except for the insulating film layer 13 which is the farthest from the first surface 11, the thicknesses of the other insulating film layers 13 may be the same, and the lengths and diameters of the openings 131 of the insulating film layers 13 may be the same; the cross-sections and lengths of the conductive blocks 42 may be the same.

[0062] In one embodiment, Figure 3As shown, the insulating layer 10 includes N insulating film layers 13, N is a positive integer greater than or equal to 2; the conductive wire 41 of the conductive structure includes a plurality of first conductive wires 411 located in the test area 101; the conductive structure includes a disconnection test structure 801 located in the test area 101, and the disconnection test structure 801 includes N-1 first sub-test structures 81; each of the first sub-test structures 81 includes a first conductive wire 411 and two first conductive connection parts 811 located on a side of the first conductive wire 411 away from the second surface 12 and in contact with the first conductive wire 411, and the first conductive wire 411 is connected to the conductive wire 411. The conductive end 8111 of the electrical connection part 811 is away from the second surface 12, exposing the insulating layer 10; each of the first conductive wires 411 corresponds to two of the openings 131, and each of the first conductive connection parts 811 includes each of the conductive parts 30 located in an opening 131 corresponding to the first conductive wire 411. When the opening 131 includes more than two sub-openings 1311, the first conductive connection part 811 also includes a conductive block 42 located between two adjacent conductive parts 30; the first conductive wires 411 of N-1 first sub-test structures 81 are respectively located in different rewiring layers 40. Figure 2 In the illustrated embodiment, N is equal to 4, that is, the insulating layer 10 includes four insulating film layers 13 , and the open circuit test structure 801 includes three first sub-test structures 81 .

[0063] In one embodiment, when the conductive structure includes the above-mentioned short circuit test structure, the step of determining whether a short circuit exists in the portion of the conductive structure located in the test area includes the following process: for each of the first sub-test structures, determining whether a short circuit exists in the first sub-test structure; if a short circuit exists in at least one of the first sub-test structures, determining whether a short circuit exists in the portion of the conductive structure located in the test area.

[0064] For each of the first sub-test structures 81, a voltage may be applied to the conductive ends 8111 of the two first conductive connecting portions 811 of the first sub-test structure 81 to test the current passing through the first sub-test structure 81. If the measured current is within the preset range, it is determined that there is no open circuit in the first sub-test structure; if the measured current is not within the preset range and is less than the minimum value of the preset range, it indicates that the resistance of the first sub-test structure is very large, and it is determined that there is an open circuit in the first sub-test structure 81. In some embodiments, the voltage applied to the first sub-test structure may be about 1V, and the maximum and minimum values ​​of the preset range are both in the milliampere level. If the measured current is microampere or less, it indicates that there is an open circuit in the first sub-test structure 81.

[0065] In the present embodiment, since the first conductive wires 411 of the N-1 first sub-test structures 81 are respectively located in different rewiring layers 40, by testing each first sub-test structure 81, it is possible to determine whether there is a short circuit in the conductive wire 41 in the rewiring layer, and it is possible to determine whether there is a short circuit in the first conductive connection portion 811, that is, it is possible to determine whether there is a short circuit between the conductive portions located on the side of each rewiring layer facing the first surface 11 and adjacent to it.

[0066] In one embodiment, Figure 3 As shown, the open circuit test structure 801 includes at least one second sub-test structure 82; each of the second sub-test structures 82 includes a second conductive connection portion 821, and the conductive end 8211 of the second conductive connection portion 821 away from the second surface 12 and the conductive end 8211 away from the first surface respectively expose the insulating layer; the second conductive connection portion 821 includes each of the conductive portions 30 located in an opening 131 passing through the insulating layer 10 and a conductive block 42 located between two adjacent conductive portions 30.

[0067] When the short circuit test structure includes a second sub-test structure, the step of determining whether a short circuit exists in the portion of the conductive structure located in the test area. The step of determining whether a short circuit exists in each of the second sub-test structures. If a short circuit exists in at least one of the second sub-test structures, determining whether a short circuit exists in the portion of the conductive structure located in the test area.

[0068] The current passing through the second sub-test structure can be tested by applying a voltage to the conductive ends 8111 of the two first conductive connecting parts 811 of the second sub-test structure. If the measured current is within the preset range, it is determined that there is no short circuit in the second sub-test structure; if the measured current is not within the preset range, for example, it is less than the minimum value of the preset range, it means that the resistance of the second sub-test structure is very large, and it is determined that there is a short circuit in the second sub-test structure. In some embodiments, the voltage applied to the second sub-test structure can be about 1V, and the maximum and minimum values ​​of the preset range are both in the milliampere level. If the measured current is microamperes or less, it means that there is a short circuit in the first sub-test structure.

[0069] By testing the second sub-test structure, it can be determined whether there is a break between each rewiring layer and the conductive parts located on both sides thereof and adjacent to each other.

[0070] In the embodiment of the present application, by performing a short circuit test on the open circuit test structure, it can be determined whether there is an open circuit in the portion of the conductive structure located in the functional area, so as to prevent the conductive path of the conductive structure located in the functional area from being disconnected and making it impossible to transmit signals.

[0071] In one embodiment, Figure 4As shown, the conductive structure includes a short-circuit test structure 802 located in the test area 101, and the short-circuit test structure 802 includes at least two third sub-test structures 83, each of the third sub-test structures 83 includes a third conductive connection part 831, 832, 833, and the conductive end 8311 of the third conductive connection part 831, 832, 833 away from the second surface 12 and the conductive end 8312 away from the first surface respectively expose the insulating layer 10; each of the third conductive connection parts 831, 832, 833 includes each conductive part 30 located in an opening 131 penetrating the insulating layer 10 and a conductive block 42 located between two adjacent conductive parts 30.

[0072] Figure 3 In the illustrated embodiment, the short circuit test structure 802 includes three third sub-test structures 83. In other embodiments, the short circuit test structure 802 may include two third sub-test structures 83, or four or more third sub-test structures 83.

[0073] When the conductive structure includes a short-circuit test structure located in the test area, the step of determining whether a short circuit exists in a portion of the conductive structure located in the test area. The step of determining whether a short circuit exists in a portion of the conductive structure located in the test area includes the following process: determining whether a short circuit exists between any two of the third sub-test structures; if a short circuit exists between two of the third sub-test structures, determining that a short circuit exists in a portion of the conductive structure located in the test area.

[0074] Specifically, a voltage may be applied to any two conductive ends belonging to different third sub-test structures 83, and the current between the two conductive ends may be detected. If the measured current is within a preset range, it is determined that the two third sub-test structures 83 are short-circuited; if the measured current is not within the preset range, for example, less than the minimum value of the preset range, it indicates that the resistance between the two conductive ends is large, and it is determined that the two third sub-test structures 83 are not short-circuited. In some embodiments, the voltage applied to the two conductive ends may be about 1V, and the maximum and minimum values ​​of the preset range are both in the milliampere level. If the measured current is microamperes or less, it indicates that the two third sub-test structures are not short-circuited.

[0075] In some embodiments, Figure 4When testing the short-circuit test structure shown, a voltage can be applied to the conductive end 8311 or 8312 of the third conductive connection part 831 and the conductive end 8311 or 8312 of the third conductive connection part 832 to detect whether there is a short circuit between the third conductive connection part 831 and the third conductive connection part 832; a voltage can be applied to the conductive end 8311 or 8312 of the third conductive connection part 831 and the conductive end 8311 or 8312 of the third conductive connection part 833 to detect whether there is a short circuit between the third conductive connection part 831 and the third conductive connection part 833; a voltage can be applied to the conductive end 8311 or 8312 of the third conductive connection part 832 and the conductive end 8311 or 8312 of the third conductive connection part 833 to detect whether there is a short circuit between the third conductive connection part 832 and the third conductive connection part 833.

[0076] By performing a short circuit test on the short circuit test structure, it can be determined whether there is a short circuit in the portion of the conductive structure located in the functional area, so as to prevent the structure that is not desired to be connected in the portion of the conductive structure located in the functional area from being connected, thereby causing erroneous signal transmission.

[0077] In one embodiment, Figure 5As shown, the conductive structure includes a parasitic parameter test structure 803 located in the test area 101; the insulating layer 10 includes N insulating film layers 13, N is a positive integer greater than or equal to 3; the conductive wire 41 of the conductive structure includes a plurality of second conductive wires 412 located in the test area 101; the parasitic parameter test structure 803 includes N-1 fourth sub-test structures 84 and at least one fifth sub-test structure 85; each of the fourth sub-test structures 84 includes one second conductive wire 412, and three fourth conductive connecting portions 841 located on the side of the second conductive wire 412 away from the second surface 12 and in contact with the second conductive wire 412, and the three fourth conductive connecting portions 841 are connected to the second conductive wire 412. The fourth conductive connection parts 841 are arranged in parallel; the conductive ends 8311, 8312, and 8313 of each of the fourth conductive connection parts 841 are away from the second surface 12 and expose the insulating layer 10; the second wire 412 corresponds to the three openings 131, and each of the fourth conductive connection parts 841 includes each conductive part 30 located in an opening 131 corresponding to the second wire 412. When the opening 131 includes more than two sub-openings 1311, the fourth conductive connection part 841 also includes a conductive block 42 located between two adjacent conductive parts 30; the second wires 412 of the N-1 fourth sub-test structures 84 are respectively located in different rewiring layers 40. Each of the fifth sub-test structures 85 includes a fifth conductive connection portion 851, and the conductive end 8511 of the fifth conductive connection portion 851 away from the second surface 12 and the conductive end 8512 away from the first surface 11 respectively expose the insulating layer 10; the fifth conductive connection portion 851 includes each conductive portion 30 located in an opening 131 passing through the insulating layer 10 and a conductive block 42 located between two adjacent conductive portions 30.

[0078] In one embodiment, when the conductive structure includes a parasitic parameter test structure located in the test area, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes the following steps:

[0079] First, for each of the fourth sub-test structures, the first parasitic parameter and the second parasitic parameter of the fourth sub-test structure are detected, and the third parasitic parameter of the fifth conductive connection portion is detected; the first parasitic parameter is a parasitic parameter between the conductive ends of two fourth conductive connection portions located on both sides of the three fourth conductive connection portions, and the second parasitic parameter is a parasitic parameter between the conductive ends of two adjacent fourth conductive connection portions of the three fourth conductive connection portions; the third parasitic parameter is a parasitic parameter between the two conductive ends of the fifth conductive connection portion; the parasitic parameters include at least one of a parasitic resistance and a parasitic capacitance;

[0080] Subsequently, for each of the fourth sub-test structures, parasitic parameters of the fourth conductive connection portion and parasitic parameters of the second conductive line per unit length in the fourth sub-test structure are calculated according to the first parasitic parameters and the second parasitic parameters.

[0081] Impedance analysis instruments can be used to detect parasitic parameters. Figure 4 For each fourth sub-test structure 84 shown, the two probes of the impedance analyzer can be respectively contacted with the conductive end 8411 and the conductive end 8413, and an alternating current can be applied to measure the first parasitic parameter; the two probes of the impedance analyzer can be respectively contacted with the conductive end 8411 and the conductive end 8412, and an alternating current can be applied to measure the second parasitic parameter. The first parasitic parameter includes the sum of the parasitic parameters of the conductive connecting parts 841 located on both sides and the part of the second wire 412 located between the central axes of the two fourth conductive connecting parts 841 (the length is d1), and the second parasitic parameter includes the sum of the parasitic parameters of the two adjacent fourth conductive connecting parts 841 and the part of the second wire 412 located between the central axes of the two conductive connecting parts 841 (the length is d2).

[0082] In one embodiment, the parasitic parameter includes a parasitic resistance. For the same fourth sub-test structure 84, the first parasitic parameter includes a first parasitic resistance R1, the second parasitic parameter includes a second parasitic resistance R2, the parasitic resistance of each fourth conductive connection portion 841 is R3, the parasitic resistance of the portion of the second wire 412 with a length of d1 is R4, and the parasitic resistance of the portion of the second wire 412 with a length of d2 is R5. The values ​​of d1 and d2 are known and have been determined before preparing the interposer. The above parameters satisfy the following relationships (1) to (3):

[0083] R1=2R3+R4 (1)

[0084] R2=2R3+R5 (2)

[0085]

[0086] By using equations (1) to (3), R3 and the parasitic resistance per unit length of the second conductive line 412 can be calculated. For each fourth sub-test structure 84, the parasitic resistance of the fourth conductive connection portion 841 and the parasitic resistance per unit length of the second conductive line 412 can be measured respectively.

[0087] In one embodiment, the parasitic parameter includes a parasitic capacitance. For the same fourth sub-test structure 84, the first parasitic parameter includes a first parasitic capacitance C1, the second parasitic parameter includes a second parasitic capacitance C2, the parasitic capacitance of each fourth conductive connection portion 841 is C3, the parasitic capacitance of the portion of the second wire 412 with a length of d1 is C4, and the parasitic capacitance of the portion of the second wire 412 with a length of d2 is C5, then the above parameters satisfy the following relations (4) to (6):

[0088]

[0089] Through equations (4) to (6), C3 and the parasitic capacitance per unit length of the second conductive line 412 can be calculated. For each fourth sub-test structure 84, the parasitic capacitance of the fourth conductive connection portion 841 and the parasitic capacitance per unit length of the second conductive line 412 can be measured respectively.

[0090] In one embodiment, the parasitic parameters include parasitic resistance, parasitic capacitance and parasitic impedance; the first parasitic parameter includes a first parasitic impedance, and the second parasitic parameter includes a second parasitic impedance; for each of the fourth sub-test structures, after calculating the parasitic parameters of the fourth conductive connection portion and the parasitic parameters of the second wire per unit length in the fourth sub-test structure according to the first parasitic parameter and the second parasitic parameter, the testing method further includes:

[0091] For each of the fourth sub-test structures, the parasitic inductance of the fourth conductive connection portion and the parasitic inductance of the second conductive wire per unit length are calculated based on the first parasitic impedance, the second parasitic impedance, the parasitic resistance and parasitic capacitance of the fourth conductive connection portion in the fourth sub-test structure, and the parasitic resistance and parasitic capacitance of the second conductive wire per unit length.

[0092] Specifically, the first parasitic inductance and the second parasitic inductance of the fourth sub-test structure 84 may be calculated using the following equation (5):

[0093] Z=R+j[ω*L-(1 / ω*C)] (5)

[0094] Where, R is resistance, L is inductance, C is capacitance, ω=2*π*f, f is the operating frequency of the AC, and Z can be measured by an impedance analyzer. When Z is the first parasitic impedance, R is the first parasitic resistance, and C is the first parasitic capacitance, the first parasitic inductance can be calculated by equation (5); when Z is the second parasitic impedance, R is the second parasitic resistance, and C is the second parasitic capacitance, the second parasitic inductance can be calculated by equation (5).

[0095] For each of the fourth sub-test structures, the parasitic inductance of the fourth conductive connection portion and the parasitic inductance per unit length of the second conductive wire can be calculated based on the first parasitic inductance and the second parasitic inductance using the following equations (6) to (8):

[0096] L1=2L3+L4 (6)

[0097] L2=2L3+L5 (7)

[0098]

[0099] By using equations (6) to (8), the parasitic inductance L3 of the fourth conductive connection portion and the parasitic inductance per unit length of the second conductive wire 412 can be calculated. For each fourth sub-test structure 84, the parasitic inductance of the fourth conductive connection portion 841 and the parasitic inductance per unit length of the second conductive wire 412 can be measured respectively.

[0100] In one embodiment, Figure 5 As shown, the conductive wires of the conductive structure include at least one third conductive wire 413 and an auxiliary conductive wire 414 located in the test area; the parasitic parameter test structure also includes a sixth sub-test structure 86, the sixth sub-test structure 86 includes one third conductive wire 413, and two sixth conductive connection parts 861 located on the side of the third conductive wire 413 away from the second surface 12, the auxiliary conductive wire 414 located between the first surface 11 and the third conductive wire 413, and two conductive parts 30 located between the auxiliary conductive wire 414 and the third conductive wire 413; each of the sixth conductive connection parts 861 is away from the second surface 12 The conductive end 8611 exposes the insulating layer 10; the third conductive wire 413 is opposite to the two openings 131, and the opening 131 includes at least two sub-openings 1311; the sixth conductive connection part 861 includes each conductive part 30 located in one of the openings 131 corresponding to the third conductive wire 413 and a conductive block 42 located between adjacent conductive parts 30; an insulating film layer 13 is provided between the auxiliary conductive wire 414 and the third conductive wire 413, and the two conductive parts 30 located between the auxiliary conductive wire 414 and the third conductive wire 413 are in contact with the third conductive wire 413 and the auxiliary conductive wire 414 respectively. The dimensions of each conductive part 30 of the sixth sub-test structure 86 and each conductive part 30 of the fourth sub-test structure 84 are the same, including height and cross section.

[0101] In one embodiment, the first parasitic parameter includes a first parasitic resistance, and the second parasitic parameter includes a second parasitic resistance;

[0102] When the parasitic parameter test structure includes the sixth sub-test structure, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes:

[0103] detecting a third parasitic resistance between two conductive ends of the same sixth sub-test structure;

[0104] The parasitic resistance of the conductive end is calculated based on the resistance per unit length of the second conductive line located in the same layer as the auxiliary conductive line, the third parasitic resistance, the parasitic resistance of the fourth conductive connecting part including only one conductive part, the fourth parasitic resistance and the fifth parasitic resistance; the fourth parasitic resistance is the parasitic resistance of the fourth conductive connecting part in the fourth sub-test structure where the second conductive line located in the same rewiring layer as the third conductive line is located, and the fifth parasitic resistance is the parasitic resistance per unit length of the second conductive line located in the same rewiring layer as the third conductive line.

[0105] An impedance analyzer may be used to detect the third parasitic resistance. Specifically, the two probes of the impedance analyzer may be respectively contacted with the two conductive ends 8611, and an alternating current may be applied to measure the third parasitic resistance. The fourth conductive connection portion 841 in the fourth sub-test structure 84 where the second conductive wire 412 located in the same rewiring layer as the third conductive wire 413 is located has the same structure as the sixth conductive connection portion 861, and the parasitic resistances of the two are the same. Figure 5 In the illustrated embodiment, the fourth conductive connection portion in the fourth sub-test structure where the second conductive line 412 located in the same rewiring layer as the third conductive line 413 is located is the fourth conductive connection portion 8414, the fourth conductive connection portion including only one conductive portion 30 is the fourth conductive connection portion 8415, and the parasitic resistance of the conductive portion 30 of the fourth conductive connection portion 8415 is the same as the parasitic resistance of the conductive portion 30 in contact with the auxiliary conductive line 414; the second conductive line located in the same layer as the auxiliary conductive line 414 is the second conductive line 4121, and the parasitic resistance per unit length of the second conductive line 4121 is the same as the parasitic resistance per unit length of the auxiliary conductive line 414.

[0106] The parasitic resistance of the conductive end can be calculated using the following calculation formulas (9) to (12):

[0107]

[0108] R8=R ′ d3 (10)

[0109] R9=R ” (d4-d3) (11)

[0110] R11=R10-R7

[0111] Wherein, d3 is the length of the portion of the auxiliary wire 414 located between the central axes of the two conductive parts 30 in contact with it, R8 is the parasitic resistance of the portion of the auxiliary wire 414 located between the central axes of the two conductive parts 30 in contact with it; d4 is the length of the portion of the third wire 413 located between the central axes of the two sixth conductive connecting parts 861, and R9 is the parasitic resistance of the portion of the third wire 413 with a length of (d4-d3); the values ​​of d3 and d4 are known and have been determined before preparing the interposer. R7 is the parasitic resistance of each conductive part 30 in contact with the auxiliary wire 414; R6 is the third parasitic resistance; R9 is the fourth parasitic resistance of the fourth conductive connecting part 8414; R11 is the parasitic resistance of the fourth conductive connecting part 8415; R10 is the parasitic resistance of the conductive end; R' is the parasitic resistance per unit length of the second wire 4121 located on the same layer as the auxiliary wire 414; and R" is the fifth parasitic resistance per unit length of the second wire 4121 located on the same layer as the third wire 413.

[0112] In one embodiment, Figure 6 As shown, the conductive wires of the conductive structure include a fourth conductive wire 415 located in the test area 101; the extension direction of the second conductive wire 412 is different from the extension direction of the fourth conductive wire 415; the parasitic parameter test structure also includes a seventh sub-test structure, the seventh sub-test structure includes the fourth conductive wire 415, and two seventh conductive connection parts located on the side of the fourth conductive wire 415 away from the second surface and connected to the fourth conductive wire 415, the fourth conductive wire 415 corresponds to two of the openings, each of the seventh conductive connection parts includes a conductive part located in an opening corresponding to the fourth conductive wire 415, when the opening includes more than two sub-openings, the seventh conductive connection part also includes a conductive block located between two adjacent conductive parts; the conductive end of the seventh conductive connection part away from the second surface exposes the insulating layer.

[0113] When the parasitic parameter test structure includes the seventh sub-test structure, the test method further includes the following steps:

[0114] First, detecting a fourth parasitic parameter of the seventh sub-test structure; the fourth parasitic parameter is a parasitic parameter between conductive ends of two fourth conductive connection portions among the three seventh conductive connection portions;

[0115] Subsequently, the parasitic resistance of the fourth wire is determined based on the fourth parasitic parameter and the parasitic resistance of the fourth conductive connection portion in the fourth sub-test structure where the second wire is located in the same rewiring layer as the fourth wire, and the parasitic resistance of the fourth wire per unit length is calculated based on the length of the fourth wire and the parasitic resistance of the fourth wire.

[0116] If the fourth conductive connection portion and the seventh conductive connection portion in the fourth sub-test structure where the second conductive line located in the same rewiring layer as the fourth conductive line have the same structure, the parasitic resistances of the two are the same. By comparing the resistance of the fourth conductive line per unit length with the resistance of the second conductive line per unit length, it can be determined whether the extension direction of the conductive line has an effect on the magnitude of the parasitic resistance.

[0117] In some embodiments, the conductive wires of the conductive structure may include at least two fourth conductive wires 415 extending in different directions. For each fourth conductive wire, the above steps may be used to determine the parasitic resistance of the fourth conductive wire per unit length. This is more helpful in determining the influence of different extension directions of the conductive wire on the magnitude of the parasitic resistance.

[0118] The interposer and the testing method of the interposer provided in the embodiments of the present application can provide good guidance for the subsequent process optimization of preparing the interposer by testing the parasitic parameters.

[0119] In one embodiment, Figure 7 As shown, the conductive wires of the conductive structure include a plurality of fifth conductive wires 416 located in the test area 101; the conductive structure includes a signal crosstalk test structure 804 located in the test area 101; the signal crosstalk test structure 804 includes a plurality of eighth sub-test structures 87, the eighth sub-test structure 87 includes one fifth conductive wire 416, and two eighth conductive connecting portions 871 located on a side of the fifth conductive wire 416 away from the second surface 12 and connected to the fifth conductive wire 416, the fifth conductive wire 416 corresponds to the two openings 131; each of the eighth conductive wires 871 is connected to the second surface 12 of the second surface 12, and the fifth conductive wire 416 corresponds to the second ... The conductive end 8411 of the connecting portion 871 is away from the second surface 12, exposing the insulating layer 10; each of the eighth conductive connecting portions 871 includes each conductive portion 30 located in an opening 131 corresponding to the fifth conductive wire 416, and when the opening 131 includes more than two sub-openings 131, the eighth conductive connecting portion 871 also includes a conductive block 42 located between two adjacent conductive portions 30; the extension directions of each of the fifth conductive wires 416 in the signal crosstalk test structure 804 are parallel to each other, and at least two of the fifth conductive wires 416 are located in different rewiring layers 40.

[0120] Figure 7 In the illustrated embodiment, the signal crosstalk test structure 804 includes three eighth sub-test structures 87 , and the fifth conductive lines 416 of the three eighth sub-test structures 87 are respectively located in different redistribution layers 40 .

[0121] In one embodiment, when the conductive structure includes a signal crosstalk test structure 804 located in the test area 101, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes:

[0122] First, applying a test signal to the conductive ends of the eighth conductive connection parts in at least two of the eighth sub-test structures that are away from the second surface, respectively, wherein the test signal is a pulse signal or a sinusoidal signal;

[0123] Subsequently, receiving output signals of each of the eighth sub-test structures;

[0124] Subsequently, for each of the eighth sub-test signals, a difference between parameters of the test signal and the output signal is determined according to the test signal and the output signal of the eighth sub-test structure, wherein the parameter includes at least one of frequency, amplitude and phase difference.

[0125] The differences in frequency, amplitude and phase difference between the test signal of the eighth sub-test structure and the output signal can reflect the degree to which the wires of the eighth sub-test structure are interfered by the signals of other wires.

[0126] In this embodiment, the test signal may be applied through the conductive end of the eighth sub-test structure, and the output signal may be received through the conductive end of the eighth sub-test structure.

[0127] The interposer and the testing method of the interposer provided in the embodiments of the present application can provide good guidance for the subsequent process optimization of preparing the interposer by testing the signal crosstalk of the wires.

[0128] In the structure of the test area provided in the embodiment of the present application, different test structures can share some structures. For example, the first sub-test structure 81 of the open circuit test structure 801 can be reused as the signal crosstalk test structure 804 including the eighth sub-test structure 87; the second sub-test structure 82 of the open circuit test structure 801 can be reused as the third sub-test structure 83 of the short circuit test structure 802; the second sub-test structure 82 of the open circuit test structure 801 can be reused as the fifth sub-test structure 85 of the fourth sub-test structure 84. In this way, the structure of the test area 101 can be simplified.

[0129] The present application also provides a semiconductor structure, such as Figure 8 As shown, the semiconductor structure includes a plurality of chips 70 and an intermediate layer as described in any of the above embodiments; each chip 70 is located on a side of the insulating layer 10 away from the second surface 12 and is electrically connected to a conductive portion 30 located in an opening 131 of the functional area 102 .

[0130] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without causing conflicts. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the drawings; all modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. An interposer, characterized in that: The intermediary layer includes a test area and a functional area; the intermediary layer includes: An insulating layer, located in the test area and the functional area; the insulating layer comprises a plurality of insulating film layers stacked in layers; the insulating layer is provided with a plurality of openings, each of the openings comprises a sub-opening or two or more sub-openings arranged along the stacking direction of the insulating film layers, and each of the sub-openings penetrates one of the insulating film layers; some of the openings are located in the test area, and some of the openings are located in the functional area; A conductive structure, comprising a plurality of conductive parts and a plurality of rewiring layers; one conductive part is respectively arranged in each of the sub-openings; the rewiring layer is arranged between any two adjacent insulating film layers; each of the rewiring layers comprises a plurality of conductive wires and a plurality of conductive blocks; the conductive block is located between two adjacent conductive parts in the same opening, each conductive wire corresponds to at least two openings, and contacts with one conductive part located in the corresponding opening; at least one conductive wire and a plurality of conductive blocks are located in the test area, and at least one conductive wire and a plurality of conductive blocks are located in the functional area; the portion of the conductive structure located in the test area is insulated from the portion located in the functional area; the portion of the conductive structure located in the test area is used to test whether there is a short circuit or an open circuit; The conductive structure includes a parasitic parameter test structure located in the test area; the insulating layer includes a first surface and a second surface opposite to each other; the insulating layer includes N insulating film layers, N is a positive integer greater than or equal to 2; the conductive wires of the conductive structure include a plurality of second conductive wires located in the test area; the parasitic parameter test structure includes N-1 fourth sub-test structures and at least one fifth sub-test structure; each of the fourth sub-test structures includes a second conductive wire and three fourth conductive connection parts located on a side of the second conductive wire away from the second surface and in contact with the second conductive wire, and the three fourth conductive connection parts are arranged in parallel; the second conductive wire corresponds to the three openings, and each fourth conductive connection part includes a fourth conductive connection part located at a side corresponding to the second surface. For each conductive part in an opening corresponding to the second wire, when the opening includes more than two sub-openings, the fourth conductive connection part also includes a conductive block located between two adjacent conductive parts; the conductive end of each fourth conductive connection part away from the second surface is exposed from the insulating layer; the second conductive wires of N-1 fourth sub-test structures are respectively located in different rewiring layers; each fifth sub-test structure includes a fifth conductive connection part, and the conductive end of the fifth conductive connection part away from the second surface and the conductive end away from the first surface are respectively exposed from the insulating layer; the fifth conductive connection part includes a conductive part located in an opening passing through the insulating layer and a conductive block located between two adjacent conductive parts.

2. The interposer according to claim 1, characterized in that: The insulating layer comprises a first surface and a second surface opposite to each other; the insulating layer comprises N insulating film layers, where N is a positive integer greater than or equal to 2; the conductive wires of the conductive structure comprise a plurality of first conductive wires located in the test area; the conductive structure comprises an open circuit test structure located in the test area, and the open circuit test structure comprises N-1 first sub-test structures and at least one second sub-test structure; Each of the first sub-test structures includes a first conductive wire and two first conductive connection parts located on the side of the first conductive wire away from the second surface and in contact with the first conductive wire, and the conductive end of the first conductive connection part away from the second surface is exposed from the insulating layer; each of the first conductive wires corresponds to two of the openings, and each of the first conductive connection parts includes each of the conductive parts located in an opening corresponding to the first conductive wire, and when the opening includes more than two sub-openings, the first conductive connection part also includes a conductive block located between two adjacent conductive parts; the first conductive wires of N-1 first sub-test structures are respectively located in different rewiring layers; each of the second sub-test structures includes a second conductive connection part, and the conductive end of the second conductive connection part away from the second surface and the conductive end away from the first surface are respectively exposed from the insulating layer; the second conductive connection part includes each of the conductive parts located in an opening penetrating the insulating layer and a conductive block located between two adjacent conductive parts.

3. The interposer according to claim 1, characterized in that: The insulating layer includes a first surface and a second surface relative to each other; the conductive structure includes a short-circuit test structure located in the test area, the short-circuit test structure includes at least two third sub-test structures, each of the third sub-test structures includes a third conductive connection part; each of the third conductive connection parts includes each conductive part located in an opening penetrating the insulating layer and a conductive block located between two adjacent conductive parts; the conductive end of the third conductive connection part away from the second surface and the conductive end away from the first surface are respectively exposed from the insulating layer.

4. The interposer according to claim 1, characterized in that: The insulating layer includes a first surface and a second surface that are opposite to each other; the conductive wires of the conductive structure include at least one third conductive wire and an auxiliary conductive wire located in the test area; the parasitic parameter test structure also includes a sixth sub-test structure, the sixth sub-test structure includes one third conductive wire, and two sixth conductive connection parts located on the side of the third conductive wire away from the second surface, the auxiliary conductive wire located between the first surface and the third conductive wire, and two conductive parts located between the auxiliary conductive wire and the third conductive wire; the conductive end of each sixth conductive connection part away from the second surface is exposed from the insulating layer; the third conductive wire is opposite to two openings, and the opening includes at least two sub-openings; the sixth conductive connection part includes each conductive part located in one of the openings corresponding to the third conductive wire and a conductive block located between adjacent conductive parts; an insulating film layer is provided between the auxiliary conductive wire and the third conductive wire, and the two conductive parts located between the auxiliary conductive wire and the third conductive wire are in contact with the third conductive wire and the auxiliary conductive wire respectively; the sizes of each conductive part of the sixth sub-test structure and each conductive part of the fourth sub-test structure are the same.

5. The interposer according to claim 1, characterized in that: The conductive wires of the conductive structure include a fourth conductive wire located in the test area; the extension direction of the second conductive wire is different from the extension direction of the fourth conductive wire; the parasitic parameter test structure also includes a seventh sub-test structure, the seventh sub-test structure includes the fourth conductive wire, and two seventh conductive connection parts located on the side of the fourth conductive wire away from the second surface and connected to the conductive wire, the fourth conductive wire corresponds to two openings, each of the seventh conductive connection parts includes a conductive part located in an opening corresponding to the fourth conductive wire, when the opening includes more than two sub-openings, the seventh conductive connection part also includes a conductive block located between two adjacent conductive parts; the conductive end of the seventh conductive connection part away from the second surface exposes the insulating layer.

6. The interposer according to claim 1, characterized in that: The insulating layer includes a first surface and a second surface that are opposite to each other; the conductive wires of the conductive structure include a plurality of fifth conductive wires located in the test area; the conductive structure includes a signal crosstalk test structure located in the test area; the signal crosstalk test structure includes a plurality of eighth sub-test structures, the eighth sub-test structure includes one fifth conductive wire, and two eighth conductive connection parts located on the side of the fifth conductive wire away from the second surface and connected to the fifth conductive wire, the fifth conductive wire corresponds to two openings; the conductive end of each eighth conductive connection part away from the second surface is exposed from the insulating layer; each eighth conductive connection part includes a conductive part located in an opening corresponding to the fifth conductive wire, and when the opening includes more than two sub-openings, the eighth conductive connection part also includes a conductive block located between two adjacent conductive parts; the extension directions of each of the conductive wires in the signal crosstalk test structure are parallel to each other, and at least two of the fifth conductive wires are located in different rewiring layers.

7. A semiconductor structure, characterized in that: The semiconductor structure comprises a plurality of chips and the intermediate layer according to any one of claims 1 to 6; each of the chips is located on one side of the insulating layer and is respectively electrically connected to a conductive part located in an opening of the functional area.

8. A method for testing an interposer, characterized in that: Used to test the interposer according to any one of claims 1 to 6; the testing method comprises: Determine whether a portion of the conductive structure located in the test area has a short circuit or an open circuit; If a short circuit and / or an open circuit exists in the portion of the conductive structure located in the test area, it is determined that the portion of the conductive structure located in the functional area does not meet the requirements.

9. The method for testing the interposer according to claim 8, characterized in that: When the conductive structure includes a circuit-breaking test structure located in the test area, the step of determining whether a circuit is broken in a portion of the conductive structure located in the test area includes: For each of the first sub-test structures, determining whether the first sub-test structure has a short circuit; for each of the second sub-test structures, determining whether the second sub-test structure has a short circuit; If at least one of the first sub-test structures has a short circuit, it is determined that the portion of the conductive structure located in the test area has a short circuit; if at least one of the second sub-test structures has a short circuit, it is determined that the portion of the conductive structure located in the test area has a short circuit.

10. The method for testing the interposer according to claim 8, characterized in that: When the conductive structure includes a short-circuit test structure located in the test area, the step of determining whether a short circuit exists in a portion of the conductive structure located in the test area includes: Determine whether there is a short circuit between any two of the third sub-test structures; If there is a short circuit between two of the third sub-test structures, it is determined that a short circuit exists in a portion of the conductive structure located in the test area.

11. The method for testing the interposer according to claim 8, characterized in that: When the conductive structure includes a parasitic parameter test structure located in the test area, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes: For each of the fourth sub-test structures, a first parasitic parameter and a second parasitic parameter of the fourth sub-test structure are detected; a third parasitic parameter of the fifth conductive connection portion is detected; the first parasitic parameter is a parasitic parameter between conductive ends of two fourth conductive connection portions located on both sides of the three fourth conductive connection portions, and the second parasitic parameter is a parasitic parameter between conductive ends of two adjacent fourth conductive connection portions of the three fourth conductive connection portions; the third parasitic parameter is a parasitic parameter between two conductive ends of the fifth conductive connection portion; the parasitic parameter includes at least one of a parasitic resistance and a parasitic capacitance; For each of the fourth sub-test structures, parasitic parameters of the fourth conductive connection portion and parasitic parameters of the second conductive line per unit length in the fourth sub-test structure are calculated according to the first parasitic parameters and the second parasitic parameters.

12. The method for testing the interposer according to claim 11, characterized in that: The parasitic parameters include parasitic resistance, parasitic capacitance and parasitic impedance; the first parasitic parameters include first parasitic impedance, and the second parasitic parameters include second parasitic impedance; for each of the fourth sub-test structures, after calculating the parasitic parameters of the fourth conductive connection portion and the parasitic parameters of the second wire per unit length in the fourth sub-test structure according to the first parasitic parameters and the second parasitic parameters, the testing method further includes: For each of the fourth sub-test structures, the parasitic inductance of the fourth conductive connection portion and the parasitic inductance of the second conductive wire per unit length are calculated based on the first parasitic impedance, the second parasitic impedance, the parasitic resistance and parasitic capacitance of the fourth conductive connection portion, and the parasitic resistance and parasitic capacitance of the second conductive wire per unit length.

13. The method for testing the interposer according to claim 11, characterized in that: The first parasitic parameter includes a first parasitic resistance, and the second parasitic parameter includes a second parasitic resistance; When the parasitic parameter test structure includes the sixth sub-test structure, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes: detecting a third parasitic resistance between two conductive ends of the sixth sub-test structure; The parasitic resistance of the conductive end is calculated based on the resistance per unit length of the second conductive wire located in the same rewiring layer as the auxiliary conductive wire, the third parasitic resistance, the parasitic resistance of the fourth conductive connecting part including only one conductive part, the fourth parasitic resistance and the fifth parasitic resistance; the fourth parasitic resistance is the parasitic resistance of the fourth conductive connecting part in the fourth sub-test structure where the second conductive wire located in the same rewiring layer as the third conductive wire is located, and the fifth parasitic resistance is the parasitic resistance per unit length of the second conductive wire located in the same rewiring layer as the third conductive wire, and the parasitic resistance of the conductive end is calculated.

14. The method for testing the interposer according to claim 9, characterized in that: When the conductive structure includes a signal crosstalk test structure located in the test area, after determining that a portion of the conductive structure located in the test area does not have a short circuit or an open circuit, the test method further includes: Applying a test signal to the conductive ends of the eighth conductive connection parts away from the second surface in at least two of the eighth sub-test structures at the same time, wherein the test signal is a pulse signal or a sinusoidal signal; receiving output signals of each of the eighth sub-test structures; For each of the eighth sub-test structures, a difference between parameters of the test signal and the output signal is determined according to the test signal and the output signal of the eighth sub-test structure, wherein the parameter includes at least one of a frequency, an amplitude and a phase difference.

Images