Interposer and method for testing same, and semiconductor structure

Abstract

The present application provides an interposer and a method for testing same, and a semiconductor structure. The interposer comprises a test region and a functional region. The interposer comprises an insulating layer and a conductive structure which are located in the test region and the functional region. The insulating layer comprises a plurality of insulating film layers and is provided with a plurality of holes, and each hole of the insulating layer comprises one sub-hole or at least two sub-holes. The conductive structure comprises a plurality of conductive portions and a plurality of rewiring layers; each sub-hole is internally provided with a conductive portion; a rewiring layer is provided between any two adjacent insulating film layers; each rewiring layer comprises a plurality of conductive wires and a plurality of conductive blocks; a conductive block is provided between two adjacent conductive portions in at least one hole, and each conductive wire is separately in contact with a conductive portion in at least one corresponding hole; at least one conductive wire and a plurality of conductive blocks are respectively provided in the test region and the functional region; a portion of the conductive structure located in the test region is insulated from a portion of the conductive structure located in the functional region; and the portion of the conductive structure located in the test region is used for testing whether there is a short circuit or an open circuit in the portion.

Description

Interposer, test method thereof, and semiconductor structure TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an interposer, a test method thereof, and a semiconductor structure. BACKGROUND

[0002] In the field of semiconductor, an interposer can realize high-density interconnection between chips, and chip integration using the interposer can realize more complex multi-chip module design, improve system performance, and reduce overall size, which is an important technology to improve chip integration and improve integrated circuit performance.

[0003] SUMMARY

[0004] The present application provides an interposer, a test method thereof, and a semiconductor structure.

[0005] According to a first aspect of the present application, an interposer is provided. The interposer includes a test region and a functional region; the interposer includes an insulating layer located in the test region and the functional region; the insulating layer includes a plurality of insulating film layers stacked; wherein the insulating layer is provided with a plurality of openings, each of the openings includes one sub-opening or at least two sub-openings arranged along the stacking direction of the plurality of insulating film layers, each of the sub-openings penetrates one of the insulating film layers; part of the plurality of openings is located in the test region, and part of the plurality of openings is located in the functional region; a conductive structure includes a plurality of conductive parts and a plurality of redistribution layers; wherein each of the sub-openings is provided with one of the conductive parts; the redistribution layer is arranged between any two adjacent insulating film layers; each of the redistribution layers includes a plurality of conductive blocks and a plurality of conductive lines; each of the conductive blocks is located between two adjacent conductive parts in the same opening; each of the conductive lines corresponds to at least one of the openings and is in contact with one of the conductive parts in the corresponding opening; at least one of the conductive lines and a plurality of the conductive blocks are located in the test region, and at least one of the conductive lines and a plurality of the conductive blocks are located in the functional region; part of the conductive structure located in the test region is insulated from part of the conductive structure located in the functional region; part of the conductive structure located in the test region is used to test whether the conductive structure has short circuit and / or open circuit.

[0006] In one embodiment, the insulating layer includes opposite first and second surfaces; the insulating layer includes N insulating film layers, N being a positive integer greater than or equal to 2; the plurality of conductive lines of the conductive structure includes a plurality of first conductive lines located in the test area; the conductive structure includes an open circuit test structure located in the test area, the open circuit test structure including N-1 first sub-test structures and at least one second sub-test structure; each first sub-test structure includes one first conductive line and two first conductive connection portions located on a side of the first conductive line away from the second surface and in contact with the first conductive line, wherein the conductive end of each first conductive connection portion away from the second surface is exposed from the insulating layer; each first conductive line corresponds to two openings, each first conductive connection portion includes the conductive portion located in one opening corresponding to the first conductive line, and when the opening includes at least two sub-openings, the first conductive connection portion further includes a conductive block located between two adjacent conductive portions; the first conductive lines of the N-1 first sub-test structures are located in different redistribution layers, respectively; each second sub-test structure includes one second conductive connection portion, wherein the conductive end of the second conductive connection portion away from the second surface and the conductive end of the second conductive connection portion away from the first surface are exposed from the insulating layer, respectively; the second conductive connection portion includes a plurality of conductive portions located in one opening penetrating the insulating layer and a conductive block located between two adjacent conductive portions.

[0007] In one embodiment, the insulating layer includes opposite first and second surfaces; the conductive structure includes a short circuit test structure located in the test area, the short circuit test structure including at least two third sub-test structures, each third sub-test structure including one third conductive connection portion, wherein the third conductive connection portion includes a plurality of conductive portions located in one opening penetrating the insulating layer and a conductive block located between two adjacent conductive portions; the conductive end of the third conductive connection portion away from the second surface and the conductive end of the third conductive connection portion away from the first surface are exposed from the insulating layer, respectively.

[0008] In one embodiment, the conductive structure includes a parasitic parameter test structure in the test region; the insulating layer includes opposite first and second surfaces; the insulating layer includes N insulating film layers, N being a positive integer greater than or equal to 2; the plurality of conductive lines of the conductive structure includes a plurality of second conductive lines in the test region; the parasitic parameter test structure includes N-1 fourth sub-test structures and at least one fifth sub-test structure; each fourth sub-test structure includes one second conductive line and three fourth conductive connections on a side of the second conductive line away from the second surface and in contact with the second conductive line, wherein the three fourth conductive connections are arranged side by side along the second conductive line; the second conductive line corresponds to three openings, each fourth conductive connection includes a conductive part in one opening corresponding to the second conductive line, and when the opening includes at least two sub-openings, the fourth conductive connection further includes a conductive block between adjacent two conductive parts; the conductive end of each fourth conductive connection away from the second surface is exposed from the insulating layer; the second conductive lines of the N-1 fourth sub-test structures are respectively located in different redistribution layers; each fifth sub-test structure includes a fifth conductive connection, and the conductive end of the fifth conductive connection away from the second surface and the conductive end of the fifth conductive connection away from the first surface are respectively exposed from the insulating layer; the fifth conductive connection includes a plurality of conductive parts in one opening penetrating the insulating layer and a conductive block between adjacent two conductive parts.

[0009] In one embodiment, the plurality of conductive lines of the conductive structure includes at least one third conductive line and an auxiliary conductive line in the test region; the parasitic parameter test structure further includes a sixth sub-test structure, the sixth sub-test structure includes one third conductive line, two sixth conductive connections on a side of the third conductive line away from the second surface, the auxiliary conductive line between the first surface and the third conductive line, and two conductive parts between the auxiliary conductive line and the third conductive line; the conductive end of each sixth conductive connection away from the second surface is exposed from the insulating layer; the third conductive line corresponds to two openings, and the opening includes at least two sub-openings; the sixth conductive connection includes a plurality of conductive parts in one opening corresponding to the third conductive line and a conductive block between adjacent conductive parts; one insulating film layer is arranged between the auxiliary conductive line and the third conductive line, and the two conductive parts between the auxiliary conductive line and the third conductive line are respectively in contact with the third conductive line and the auxiliary conductive line; the size of each conductive part of the sixth sub-test structure and the size of each conductive part of the fourth sub-test structure are the same.

[0010] In one embodiment, the plurality of conductive lines of the conductive structure includes a fourth conductive line located in the test region; the plurality of second conductive lines extend in a direction different from that of the fourth conductive line; the parasitic parameter test structure further includes a seventh sub-test structure including the fourth conductive line and two seventh conductive connection portions located on a side of the fourth conductive line away from the second surface and connected to the fourth conductive line, the fourth conductive line corresponding to two of the openings, each of the seventh conductive connection portions including a conductive portion located in one of the openings corresponding to the fourth conductive line, and when the opening includes at least two sub-openings, the seventh conductive connection portion further includes a conductive block located between two adjacent conductive portions; and a conductive end of the seventh conductive connection portion away from the second surface is exposed from the insulating layer.

[0011] In one embodiment, the insulating layer includes opposite first and second surfaces; the plurality of conductive lines of the conductive structure includes a plurality of fifth conductive lines located in the test region; the conductive structure includes a signal crosstalk test structure located in the test region; the signal crosstalk test structure includes a plurality of eighth sub-test structures, each of the eighth sub-test structures including one of the fifth conductive lines and two eighth conductive connection portions located on a side of the fifth conductive line away from the second surface and connected to the fifth conductive line, the fifth conductive line corresponding to two of the openings; a conductive end of each of the eighth conductive connection portions away from the second surface is exposed from the insulating layer; each of the eighth conductive connection portions includes a conductive portion located in one of the openings corresponding to the fifth conductive line, and when the opening includes at least two sub-openings, the eighth conductive connection portion further includes a conductive block located between two adjacent conductive portions; and the fifth conductive lines in the signal crosstalk test structure extend in parallel to each other, and at least two of the fifth conductive lines are located in different redistribution layers.

[0012] According to a second aspect of the embodiments of the present application, a semiconductor structure is provided, including a plurality of chips and the interposer of any of the above embodiments; each of the chips is located on a side of the insulating layer away from the second surface and is electrically connected to a conductive portion located in an opening in the functional region.

[0013] According to a third aspect of the embodiments of the present application, a test method of an interposer is provided, for testing the interposer of any of the above embodiments; the test method includes: determining whether a part of the conductive structure located in the test region has a short circuit and / or an open circuit; and if the part of the conductive structure located in the test region has a short circuit and / or an open circuit, determining that a part of the conductive structure located in the functional region does not meet the requirements.

[0014] In one embodiment, when the conductive structure comprises the open circuit test structure in the test area, the step of determining whether the part of the conductive structure in the test area has an open circuit comprises: determining whether each of the first sub-test structures has an open circuit; determining whether each of the second sub-test structures has an open circuit; determining that the part of the conductive structure in the test area has an open circuit if at least one of the first sub-test structures has an open circuit; and determining that the part of the conductive structure in the test area has an open circuit if at least one of the second sub-test structures has an open circuit.

[0015] In one embodiment, when the conductive structure comprises the short circuit test structure in the test area, the step of determining whether the part of the conductive structure in the test area has a short circuit comprises: determining whether any two of the third sub-test structures have a short circuit; and determining that the part of the conductive structure in the test area has a short circuit if any two of the third sub-test structures have a short circuit.

[0016] In one embodiment, when the conductive structure comprises the parasitic parameter test structure in the test area, after determining that the part of the conductive structure in the test area has neither a short circuit nor an open circuit, the test method further comprises: detecting a first parasitic parameter value and a second parasitic parameter value of each of the fourth sub-test structures; detecting a third parasitic parameter value of the fifth conductive connection; the first parasitic parameter value is a parasitic parameter value between two conductive ends of two fourth conductive connections that are not adjacent in the three fourth conductive connections, and the second parasitic parameter value is a parasitic parameter value between the conductive ends of two fourth conductive connections that are adjacent in the three fourth conductive connections; the third parasitic parameter value is a parasitic parameter value between the two conductive ends of the fifth conductive connection; the parasitic parameter value comprises at least one of a parasitic resistance value and a parasitic capacitance value; and for each of the fourth sub-test structures, calculating a parasitic parameter value of the fourth conductive connection in the fourth sub-test structure and a parasitic parameter value per unit length of the second wire according to the first parasitic parameter value and the second parasitic parameter value.

[0017] In one embodiment, the parasitic parameter values include parasitic resistance values, parasitic capacitance values and parasitic impedance values; the first parasitic parameter value includes a first parasitic impedance value, and the second parasitic parameter value includes a second parasitic impedance value; after the parasitic parameter values of the fourth conductive connection and the parasitic parameter values per unit length of the second conductive line in each fourth sub-test structure are calculated according to the first parasitic parameter value and the second parasitic parameter value, the test method further comprises: for each fourth sub-test structure, calculating the parasitic inductance value of the fourth conductive connection and the parasitic inductance value per unit length of the second conductive line according to the first parasitic impedance value, the second parasitic impedance value, the parasitic resistance value and the parasitic capacitance value of the fourth conductive connection, and the parasitic resistance value and the parasitic capacitance value per unit length of the second conductive line.

[0018] In one embodiment, the first parasitic parameter value includes a first parasitic resistance value, and the second parasitic parameter value includes a second parasitic resistance value; when the parasitic parameter test structure includes a sixth sub-test structure, after it is determined that the conductive structure located in the test area does not have short circuit and open circuit, the test method further comprises: detecting a third parasitic resistance value between two conductive ends of the sixth sub-test structure; calculating the parasitic resistance value of the conductive end of the fourth conductive connection according to the resistance value per unit length of the second conductive line in the same redistribution layer as the auxiliary conductive line, the third parasitic resistance value, the parasitic resistance value of the fourth conductive connection including only one conductive part, a fourth parasitic resistance value and a fifth parasitic resistance value; the fourth parasitic resistance value is the parasitic resistance value of the fourth conductive connection in the fourth sub-test structure of the second conductive line in the same redistribution layer as the third conductive line, and the fifth parasitic resistance value is the parasitic resistance value per unit length of the second conductive line in the same redistribution layer as the third conductive line.

[0019] In one embodiment, when the conductive structure includes a signal crosstalk test structure located in the test area, after it is determined that the conductive structure located in the test area does not have short circuit and open circuit, the test method further comprises: respectively applying test signals to the conductive end of the eighth conductive connection away from the second surface in at least two eighth sub-test structures, the test signals being pulse signals or sine signals; receiving output signals of each eighth sub-test structure; for each eighth sub-test structure, determining the difference between the parameter values of the test signal and the output signal of the eighth sub-test structure according to the test signal and the output signal of the eighth sub-test structure, the parameter values including at least one of frequency, amplitude and phase difference. BRIEF DESCRIPTION OF DRAWINGS

[0020] FIG. 1 is a top view of an interposer according to an example embodiment of the present application.

[0021] Fig. 2 is a partial sectional view of the interposer shown in Fig. 1 taken along section AA in the functional area.

[0022] Fig. 3 is a partial sectional view of the interposer shown in Fig. 1 taken along section AA in the test area.

[0023] Fig. 4 is a partial sectional view of the interposer shown in Fig. 1 taken along section AA in the test area.

[0024] Fig. 5 is a partial sectional view of the interposer shown in Fig. 1 taken along section AA in the test area.

[0025] Fig. 6 is a partial sectional view of the interposer shown in Fig. 1 taken along section AA in the test area.

[0026] Fig. 7 is a partial sectional view of the interposer shown in Fig. 1 taken along section AA in the test area.

[0027] Fig. 8 is a sectional view of a semiconductor structure according to an example embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings. When the following description refers to the drawings, identical or similar elements in different drawings are denoted by identical reference numerals unless otherwise indicated. The embodiments described below and the features in the embodiments can be combined with each other without conflict.

[0029] If the present application has terms related to directionality or position relationship (for example, up, down, left, right, front, back, inner, outer, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative position relationship, movement, etc. between components in a certain posture; if the posture changes, the directionality or position relationship also changes accordingly. In addition, the terms "first", "second", etc. in the embodiments of the present application are only used for convenience of description, and cannot be understood as indicating or implying relative importance.

[0030] With the increase of the types and number of chips integrated on the interposer, the wiring density, wiring complexity and the number of conductive vias in the interposer are increasing, and the test difficulty of the interposer circuit break and short circuit is also increasing. At present, the microscope observation method cannot meet the test requirements of the interposer.

[0031] The embodiment of the present application provides a interposer. As shown in Fig. 1, the interposer 100 comprises a test area 101 and a functional area 102. As shown in Fig. 2 and Fig. 3, the interposer 100 comprises an insulating layer 10 and a conductive structure.

[0032] The insulating layer 10 is located in the test area 101 and the functional area 102, and comprises opposite first and second surfaces 11 and 12. The insulating layer 10 comprises a plurality of insulating film layers 13 arranged in a stack. The insulating layer 10 is provided with a plurality of openings 131, each of which comprises one sub-opening 1311 or at least two sub-openings 1311 arranged in the stacking direction of the plurality of insulating film layers 13, each of the sub-openings 1311 penetrating one of the insulating film layers 13. Part of the openings 131 are located in the test area 101, and part of the openings 131 are located in the functional area 102.

[0033] The conductive structure comprises a plurality of conductive parts 30 and a plurality of redistribution layers 40. Each of the sub-openings 1311 is provided with one of the conductive parts 30. The redistribution layer 40 is arranged between any two adjacent insulating film layers 13. Each of the redistribution layers 40 comprises a plurality of conductive lines 41 and a plurality of conductive blocks 42. Each of the conductive blocks 42 is located between two adjacent conductive parts 30 in the same opening 131, and is in contact with the two adjacent conductive parts 30. Each of the conductive lines 41 corresponds to at least one of the openings 131, and is in contact with the conductive part 30 located in the corresponding opening 131. Specifically, the conductive line 41 is in contact with the conductive part 30 located in the corresponding opening 131 and closest to the conductive line 41. At least one of the conductive lines 41 and the plurality of conductive blocks 42 are located in the test area 101, and at least one of the conductive lines 41 and the plurality of conductive blocks 42 are located in the functional area 102. The conductive structure located in the test area 101 is insulated from the conductive structure located in the functional area 102. The conductive structure located in the test area 101 is used to test whether the conductive structure is short-circuited and / or broken.

[0034] In the semiconductor field, during the fabrication of the interposer, each conductor 41 and each conductive block 42 located in the same redistribution layer 40 is formed simultaneously, and each sub-aperture 1311 penetrating the same insulating film layer 13 is formed in the same process step. During the fabrication of the redistribution layer 40, the conductor 41 may break or the surface of the redistribution layer 40 in contact with the conductive portion 30 may be contaminated with non-conductive stains, which will cause the conductive path in the interposer to be open. During the formation of the interposer, if the conductive block 42 is misaligned with the corresponding conductive portion 30, it may also cause the conductive path in the interposer to be open, or the conductive block 42 may come into contact with a non-corresponding conductive portion 30, resulting in a short circuit. Since the portions of each conductor 41 and each conductive block 42 located in the same redistribution layer 40 located in the test area 101 and the functional area 102 are formed simultaneously, and the portions of each sub-aperture 1311 penetrating the same insulating film layer 13 in the test area 101 and the functional area 102 are formed simultaneously, if there is an open circuit or short circuit problem in the portion of the conductive structure located in the test area 101, the functional area 102 will also have the same problem.

[0035] The intermediate layer provided in this application embodiment can determine whether there are short circuits or open circuits in the part of the conductive structure located in the test area by testing the part of the conductive structure located in the test area. In turn, it can determine whether there are short circuits or open circuits in the part of the conductive structure located in the functional area. Since the part of the conductive structure located in the test area is insulated from the part located in the functional area, the test signal will not flow to the functional area during the test process of applying a test signal to the part of the conductive structure located in the test area. This can avoid the test signal being too large and causing damage to the part of the conductive structure located in the functional area.

[0036] This application embodiment also provides a testing method for an intermediary layer, used to test the intermediary layer; the testing method includes the following steps: determining whether there is a short circuit or open circuit in the portion of the conductive structure located in the test area; if there is a short circuit and / or open circuit in the portion of the conductive structure located in the test area, then it is determined that the portion of the conductive structure located in the functional area does not meet the requirements.

[0037] As analyzed above, if it is determined that the portion of the conductive structure located in the test area has at least one problem, namely short circuit and open circuit, it can be determined that the portion of the conductive structure located in the functional area has the same problem. Therefore, it can be determined that the portion of the conductive structure located in the functional area does not meet the requirements.

[0038] In this embodiment, the portion of the conductive structure located in the test area 101 is used only for testing and is not used to connect to electrical components such as chips; the portion of the conductive structure located in the functional area 102 is used for electrical connection with electrical components, enabling signal communication and signal output between different electrical components.

[0039] In one embodiment, as shown in FIG1, the test region 101 is located on one side of the functional region 102. This allows the portion of the conductive structure located in the functional region 102 to be removed when it is determined that the portion of the interposer layer located in the test region 101 meets the requirements, thus retaining only the portion of the interposer layer located in the functional region 102, which helps to reduce the size of the semiconductor structure including the interposer layer.

[0040] In one embodiment, as shown in FIG2, within the functional area 102, some of the openings 131 extend from the first surface 11 toward the second surface 12, and some of the openings 131 extend from the second surface 12 toward the first surface 11. Some of the openings 131 penetrate the insulating layer 10, meaning that the opening 131 includes a plurality of sub-openings 1311 penetrating all insulating film layers 13. Some of the openings 131 include one or more sub-openings 1311 penetrating a portion of the insulating film layer 13. When an opening 131 includes a plurality of sub-openings 1311, the conductive portions 30 within each sub-opening 1311 are electrically connected. Specifically, adjacent conductive portions 30 within the same opening 131 can be electrically connected through a conductive block 42 located between them.

[0041] In one embodiment, as shown in Figures 1 to 3, the interposer layer further includes a plurality of first solder balls 50 located on the first surface 11 and a plurality of second solder balls 60 located on the second surface 12. Each first solder ball 50 is electrically connected to a conductive portion 30, and each second solder ball 60 is electrically connected to a conductive portion 30. The first solder balls 50 can be used for soldering electrical components, and the second solder balls 60 can be used for soldering circuit boards. The conductive end mentioned later can be either the first solder ball 50 or the second solder ball 60. In other embodiments, the first surface 11 may not have the first solder balls 50, and the electrical components can be electrically connected to the surface of the conductive portion 30 exposed in the insulating layer 10 via a bonding process. The conductive end mentioned later can also be the surface of the conductive portion 30 exposed in the insulating layer 10.

[0042] In one embodiment, in the intermediate layer, except for the insulating film layer 13 which is the furthest from the first surface 11, the thickness of each insulating film layer 13 may be the same, and the length and diameter of the openings 131 of each insulating film layer 13 may be the same; the cross-section and length of each conductive block 42 may be the same.

[0043] In one embodiment, as shown in FIG3, the insulating layer 10 includes N insulating film layers 13, where N is a positive integer greater than or equal to 2; the plurality of wires 41 of the conductive structure includes a plurality of first wires 411 located in the test area 101; the conductive structure includes a circuit breaker test structure 801 located in the test area 101, and the circuit breaker test structure 801 includes N-1 first sub-test structures 81; each first sub-test structure 81 includes a first wire 411 and two first conductive connection portions 81 located on the side of the first wire 411 away from the second surface 12 and in contact with the first wire 411. 11. The conductive end 8111 of each first conductive connection 811 away from the second surface 12 exposes the insulating layer 10; each first wire 411 corresponds to two openings 131, and each first conductive connection 811 includes a conductive part 30 located in one of the openings 131 corresponding to the first wire 411. When the opening 131 includes at least two sub-openings 1311, the first conductive connection 811 also includes a conductive block 42 located between two adjacent conductive parts 30; the first wires 411 of N-1 first sub-test structures 81 are respectively located in different redistribution layers 40. In the embodiment shown in FIG2, N equals 4, that is, the insulating layer 10 includes 4 insulating film layers 13, and the open circuit test structure 801 includes 3 first sub-test structures 81.

[0044] In one embodiment, when the conductive structure includes the above-described open circuit test structure, the step of determining whether the portion of the conductive structure located in the test area has an open circuit includes the following process: for each first sub-test structure, determining whether the first sub-test structure has an open circuit; if at least one first sub-test structure has an open circuit, determining that the portion of the conductive structure located in the test area has an open circuit.

[0045] For each of the first sub-test structures 81, the current flowing through the first sub-test structure 81 can be tested by applying a voltage to the conductive terminals 8111 of the two first conductive connection portions 811 of the first sub-test structure 81. If the measured current is within a preset range, it is determined that the first sub-test structure 81 has no open circuit; if the measured current is not within the preset range, for example, less than the minimum value of the preset range, it indicates that the resistance value of the first sub-test structure 81 is very large, and it is determined that the first sub-test structure 81 has an open circuit. In some embodiments, the voltage applied to the first sub-test structure 81 can be about 1V, and the maximum and minimum values ​​of the preset range of current are both in the milliampere level. If the measured current is in the microampere level or smaller, it indicates that the first sub-test structure 81 has an open circuit.

[0046] In this embodiment, since the first conductors 411 of the N-1 first sub-test structures 81 are located in different redistribution layers 40, by testing each first sub-test structure 81, it can be determined whether there is an open circuit in the conductors 41 in the redistribution layer 40, and whether there is an open circuit in the first conductive connection portion 811, that is, whether there is an open circuit between the conductive portion 30 located on the side of each redistribution layer 40 facing the first surface 11 and adjacent to it.

[0047] In one embodiment, as shown in FIG3, the circuit breaker test structure 801 includes at least one second sub-test structure 82; each second sub-test structure 82 includes a second conductive connection portion 821, wherein the conductive end 8211 of the second conductive connection portion 821 away from the second surface 12 and the conductive end 8211 away from the first surface 11 are respectively exposed to the insulating layer 10; the second conductive connection portion 821 includes a plurality of conductive portions 30 located in an opening 131 penetrating the insulating layer 10 and a conductive block 42 located between two adjacent conductive portions 30.

[0048] When the open circuit test structure includes a second sub-test structure, the step of determining whether there is an open circuit in the portion of the conductive structure located in the test area further includes the following process: for each second sub-test structure, determine whether there is an open circuit in the second sub-test structure; if at least one second sub-test structure has an open circuit, determine that there is an open circuit in the portion of the conductive structure located in the test area.

[0049] The current flowing through the second sub-test structure 82 can be tested by applying a voltage to the two conductive terminals 8211 of the second conductive connection portion 821 of the second sub-test structure 82. If the measured current is within a preset range, it is determined that the second sub-test structure 82 is not open-circuited; if the measured current is not within the preset range, for example, less than the minimum value of the preset range, it indicates that the resistance of the second sub-test structure 82 is very large, and it is determined that the second sub-test structure 82 is open-circuited. In some embodiments, the voltage applied to the second sub-test structure 82 may be around 1V, and the maximum and minimum values ​​of the preset current range are both in the milliampere range. If the measured current is in the microampere range or less, it indicates that the second sub-test structure 82 is open-circuited.

[0050] By testing the second sub-test structure 82, it can be determined whether there is an open circuit between each redistribution layer and the conductive parts located on both sides and adjacent to it.

[0051] In this embodiment of the application, by performing an open circuit test on the open circuit test structure, it is possible to determine whether there is an open circuit in the part of the conductive structure located in the functional area, so as to prevent the conductive path of the conductive structure located in the functional area from being broken and thus unable to transmit signals.

[0052] In one embodiment, as shown in FIG4, the conductive structure includes a short-circuit test structure 802 located in the test area 101. The short-circuit test structure 802 includes at least two third sub-test structures 83. Each third sub-test structure 83 includes a third conductive connection portion 831, 832, 833. The conductive ends 8311 of the third conductive connection portions 831, 832, 833 away from the second surface 12 and the conductive ends 8312 away from the first surface 11 are respectively exposed in the insulating layer 10. Each third conductive connection portion 831, 832, 833 includes a plurality of conductive portions 30 located in an opening 131 penetrating the insulating layer 10 and a conductive block 42 located between two adjacent conductive portions 30.

[0053] In the embodiment shown in Figure 4, the short-circuit test structure 802 includes three third sub-test structures 83. In other embodiments, the short-circuit test structure 802 may include two third sub-test structures 83, or four or more third sub-test structures 83.

[0054] When the conductive structure includes a short-circuit test structure located in the test area, the step of determining whether a short circuit exists in the portion of the conductive structure located in the test area includes the following process: determining whether there is a short circuit between any two of the third sub-test structures; if there is a short circuit between the two third sub-test structures, determining that there is a short circuit in the portion of the conductive structure located in the test area.

[0055] Specifically, a voltage can be applied to any two conductive terminals belonging to two different third sub-test structures 83, and the current between the two conductive terminals can be detected. If the measured current is within a preset range, it is determined that there is a short circuit between the two third sub-test structures 83; if the measured current is not within the preset range, for example, less than the minimum value of the preset range, it indicates that the resistance between the two conductive terminals is very large, and it is determined that there is no short circuit between the two third sub-test structures 83. In some embodiments, the voltage applied to the two conductive terminals can be around 1V, and the maximum and minimum values ​​of the preset range of current are both in the milliampere level. If the measured current is in the microampere level or less, it indicates that there is no short circuit between the two third sub-test structures 83.

[0056] In some embodiments, when testing the short-circuit test structure shown in FIG4, a short circuit between the third conductive connection portion 831 and the third conductive connection portion 832 can be detected by applying a voltage to the conductive end 8311 or 8312 of the third conductive connection portion 831 and the conductive end 8311 or 8312 of the third conductive connection portion 832; a short circuit between the third conductive connection portion 831 and the third conductive connection portion 833 can be detected by applying a voltage to the conductive end 8311 or 8312 of the third conductive connection portion 831 and the conductive end 8311 or 8312 of the third conductive connection portion 833; and a short circuit between the third conductive connection portion 832 and the third conductive connection portion 833 can be detected by applying a voltage to the conductive end 8311 or 8312 of the third conductive connection portion 832 and the conductive end 8311 or 8312 of the third conductive connection portion 833.

[0057] By performing short-circuit tests on the short-circuit test structure, it can be determined whether there is a short circuit in the part of the conductive structure located in the functional area, so as to prevent unwanted connections in the part of the conductive structure located in the functional area from causing erroneous signal transmission.

[0058] In one embodiment, as shown in FIG5, the conductive structure includes a parasitic parameter test structure 803 located in the test area 101; the insulating layer 10 includes N insulating film layers 13, where N is a positive integer greater than or equal to 2; the plurality of wires 41 of the conductive structure includes a plurality of second wires 412 located in the test area 101; the parasitic parameter test structure 803 includes N-1 fourth sub-test structures 84 and at least one fifth sub-test structure 85; each of the fourth sub-test structures 84 includes one second wire 412 and three fourth conductive connection portions 841 located on the side of the second wire 412 away from the second surface 12 and in contact with the second wire 412, the three fourth conductive connection portions 841... Parts 841 are arranged side by side along the second conductor 412; the conductive ends 8411, 8412, and 8413 of each of the fourth conductive connection parts 841 away from the second surface 12 are exposed in the insulating layer 10; the second conductor 412 corresponds to the three openings 131, and each of the fourth conductive connection parts 841 includes a conductive part 30 located in one of the three openings 131 corresponding to the second conductor 412. When the opening 131 includes at least two sub-openings 1311, the fourth conductive connection part 841 also includes a conductive block 42 located between two adjacent conductive parts 30; the second conductors 412 of the N-1 fourth sub-test structures 84 are respectively located in different redistribution layers 40. Each of the fifth sub-test structures 85 includes a fifth conductive connection portion 851, wherein the conductive end 8511 of the fifth conductive connection portion 851 away from the second surface 12 and the conductive end 8512 away from the first surface 11 are respectively exposed in the insulating layer 10; the fifth conductive connection portion 851 includes a plurality of conductive portions 30 located in an opening 131 penetrating the insulating layer 10 and a conductive block 42 located between two adjacent conductive portions 30.

[0059] In one embodiment, when the conductive structure includes a parasitic parameter test structure located in the test area, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes the following steps:

[0060] First, for each of the fourth sub-test structures, the first parasitic parameter value and the second parasitic parameter value of the fourth sub-test structure are detected, and the third parasitic parameter value of the fifth conductive connection is detected; the first parasitic parameter value is the parasitic parameter value between the two conductive ends of the two fourth conductive connections located on opposite sides (not adjacent) among the three fourth conductive connections; the second parasitic parameter value is the parasitic parameter value between the two conductive ends of the two adjacent fourth conductive connections among the three fourth conductive connections; the third parasitic parameter value is the parasitic parameter value between the two conductive ends of the fifth conductive connection; the parasitic parameter value includes at least one of parasitic resistance value and parasitic capacitance value;

[0061] Subsequently, for each of the fourth sub-test structures, the parasitic parameter values ​​of the fourth conductive connection portion and the parasitic parameter values ​​per unit length of the second conductor in the fourth sub-test structure are calculated based on the first parasitic parameter value and the second parasitic parameter value.

[0062] The parasitic parameter values ​​can be detected using an impedance analyzer. For each fourth sub-test structure 84 shown in Figure 5, the first parasitic parameter value can be measured by contacting the two probes of the impedance analyzer with conductive ends 8411 and 8413 respectively and applying alternating current. The second parasitic parameter value can be measured by contacting the two probes of the impedance analyzer with conductive ends 8411 and 8412 respectively (or vice versa) and applying alternating current. The first parasitic parameter value includes the sum of the parasitic parameter values ​​of the portions of the two fourth conductive connections 841 located on both sides and the second wire 412 located between the central axes of the two fourth conductive connections 841 (length d1). The second parasitic parameter value includes the sum of the parasitic parameter values ​​of the portions of the two adjacent fourth conductive connections 841 and the second wire 412 located between the central axes of the two fourth conductive connections 841 (length d2).

[0063] In one embodiment, the parasitic parameter value includes the parasitic resistance value. For the same fourth sub-test structure 84, the first parasitic parameter value includes the first parasitic resistance value R1, the second parasitic parameter value includes the second parasitic resistance value R2, the parasitic resistance value of each fourth conductive connection 841 is R3, the parasitic resistance value of the portion of the second conductor 412 with length d1 is R4, and the parasitic resistance value of the portion of the second conductor 412 with length d2 is R5. The values ​​of d1 and d2 are known and have been determined before the preparation of the interposer. The above parameter values ​​satisfy the following relationships (1) to (3): R1 = 2R3 + R4 (1) R2 = 2R3 + R5 (2)

[0064] Using equations (1) to (3), the parasitic resistance per unit length of R3 and the second conductor 412 can be calculated. For each of the fourth sub-test structures 84, the parasitic resistance of the fourth conductive connection 841 and the parasitic resistance per unit length of the second conductor 412 can be measured respectively.

[0065] In one embodiment, the parasitic parameter value includes the parasitic capacitance value. For the same fourth sub-test structure 84, the first parasitic parameter value includes the first parasitic capacitance value C1, and the second parasitic parameter value includes the second parasitic capacitance value C2. C1 and C2 are measured by an impedance analyzer. The parasitic capacitance value of each fourth conductive connection 841 is C3. The parasitic capacitance value of the portion of the second conductor 412 with length d1 is C4, and the parasitic capacitance value of the portion of the second conductor 412 with length d2 is C5. Then, the above parameter values ​​satisfy the following relationships (4) to (6):

[0066] Using equations (4) to (6), the parasitic capacitance per unit length of C3 and the second conductor 412 can be calculated. For each of the fourth sub-test structures 84, the parasitic capacitance of the fourth conductive connection 841 and the parasitic capacitance per unit length of the second conductor 412 can be measured respectively.

[0067] In one embodiment, the parasitic parameter values ​​include parasitic resistance, parasitic capacitance, and parasitic impedance; the first parasitic parameter value includes a first parasitic impedance value, and the second parasitic parameter value includes a second parasitic impedance value; for each of the fourth sub-test structures, after calculating the parasitic parameter values ​​of the fourth conductive connection portion and the parasitic parameter values ​​per unit length of the second wire in the fourth sub-test structure based on the first and second parasitic parameter values, the test method further includes:

[0068] For each of the fourth sub-test structures, the parasitic inductance of the fourth conductive connection and the parasitic inductance of the second conductor per unit length are calculated based on the first parasitic impedance value, the second parasitic impedance value, the parasitic resistance and parasitic capacitance values ​​of the fourth conductive connection in the fourth sub-test structure, and the parasitic resistance and parasitic capacitance values ​​of the second conductor per unit length.

[0069] Specifically, the first and second parasitic inductance values ​​of the fourth sub-test structure 84 can be calculated using the following relationship (7): Z=R+j[ω*L-(1 / ω*C)] (7)

[0070] In the formula, R is the resistance value, L is the inductance value, C is the capacitance value, ω=2*π*f, f is the operating frequency of the AC power, and Z is the impedance value, which can be measured by an impedance analyzer. When Z is the first parasitic impedance value Z1, R is the first parasitic resistance value R1, and C is the first parasitic capacitance value C1, the first parasitic inductance value L1 can be calculated by the relationship (7); when Z is the second parasitic impedance value Z2, R is the second parasitic resistance value R2, and C is the second parasitic capacitance value C2, the second parasitic inductance value L2 can be calculated by the relationship (7).

[0071] For each of the fourth sub-test structures, the parasitic inductance of the fourth conductive connection and the parasitic inductance per unit length of the second conductor can be calculated using the following formulas (8) to (10) based on the first parasitic inductance value L1 and the second parasitic inductance value L2: L1 = 2L3 + L4 (8) L2 = 2L3 + L5 (9)

[0072] Where L4 is the parasitic inductance of the portion of the second conductor 412 with length d1, and L5 is the parasitic inductance of the portion of the second conductor 412 with length d2, the parasitic inductance L3 of the fourth conductive connection and the parasitic inductance per unit length of the second conductor 412 can be calculated using equations (8) to (10). For each of the fourth sub-test structures 84, the parasitic inductance of the fourth conductive connection 841 and the parasitic inductance per unit length of the second conductor 412 can be measured respectively.

[0073] In one embodiment, as shown in FIG5, the plurality of wires 41 of the conductive structure include at least one third wire 413 and an auxiliary wire 414 located in the test area 101; the parasitic parameter test structure 803 further includes a sixth sub-test structure 86, the sixth sub-test structure 86 including one third wire 413, two sixth conductive connection portions 861 located on the side of the third wire 413 away from the second surface 12, the auxiliary wire 414 located between the first surface 11 and the third wire 413, and two conductive portions 30 located between the auxiliary wire 414 and the third wire 413; each of the sixth conductive connection portions 861 is located away from the first surface 11 and the second surface 12. The conductive end 8611 of the second surface 12 exposes the insulating layer 10; the third conductor 413 corresponds to the two openings 131, and each of the two openings 131 includes at least two sub-openings 1311; the sixth conductive connection portion 861 includes each conductive portion 30 located in one of the openings 131 corresponding to the third conductor 413 and a conductive block 42 located between adjacent conductive portions 30; an insulating film layer 13 is provided between the auxiliary conductor 414 and the third conductor 413, and the two conductive portions 30 located between the auxiliary conductor 414 and the third conductor 413 are in contact with the third conductor 413 and the auxiliary conductor 414, respectively. The dimensions of each conductive portion 30 of the sixth sub-test structure 86 and each conductive portion 30 of the fourth sub-test structure 84 can be the same, and the dimensions include height and cross-section.

[0074] In one embodiment, the first parasitic parameter value includes a first parasitic resistance value, and the second parasitic parameter value includes a second parasitic resistance value;

[0075] When the parasitic parameter test structure includes a sixth sub-test structure, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes:

[0076] The third parasitic resistance value between the two conductive terminals of the same sixth sub-test structure is detected;

[0077] The parasitic resistance value of the conductive end of the fourth conductive connection is calculated based on the resistance value per unit length of the second conductor located in the same redistribution layer as the auxiliary conductor, the third parasitic resistance value, the parasitic resistance value of the fourth conductive connection including only one conductive part, the fourth parasitic resistance value, and the fifth parasitic resistance value. The fourth parasitic resistance value is the parasitic resistance value of the fourth conductive connection in the fourth sub-test structure where the second conductor located in the same redistribution layer as the third conductor is located, and the fifth parasitic resistance value is the parasitic resistance value per unit length of the second conductor located in the same redistribution layer as the third conductor.

[0078] The third parasitic resistance value can be detected using an impedance analyzer. Specifically, the sixth sub-test structure 86 includes two conductive terminals 8611. The two probes of the impedance analyzer can be contacted with the two conductive terminals 8611 respectively, and an alternating current can be applied to measure the third parasitic resistance value. Since the fourth conductive connection portion 841 in the fourth sub-test structure 84, where the second conductor 412 is located on the same redistribution layer as the third conductor 413, has the same structure as the sixth conductive connection portion 861, their parasitic resistance values ​​are the same. In the embodiment shown in Figure 5, the fourth conductive connection portion in the fourth sub-test structure 84 where the second conductor 412, which is located in the same redistribution layer as the third conductor 413, is the fourth conductive connection portion 8414. The fourth conductive connection portion that includes only one conductive portion 30 is the fourth conductive connection portion 8415. The parasitic resistance value of the conductive portion 30 of the fourth conductive connection portion 8415 is the same as the parasitic resistance value of the conductive portion 30 that is in contact with the auxiliary conductor 414. The second conductor located in the same redistribution layer as the auxiliary conductor 414 is the second conductor 4121. The parasitic resistance value per unit length of the second conductor 4121 is the same as the parasitic resistance value per unit length of the auxiliary conductor 414.

[0079] The parasitic resistance value of the conductive end of the fourth conductive connection 8415 can be calculated using the following formulas (11) to (14): R8=R′d3 (12) R9=R”(d4-d3) (13) R11=R10+R7 (14)

[0080] Wherein, d3 is the length of the portion of the auxiliary wire 414 located between the central axes of the two conductive parts 30 in contact with it, R8 is the parasitic resistance value of the portion of the auxiliary wire 414 located between the central axes of the two conductive parts 30 in contact with it; d4 is the length of the portion of the third wire 413 located between the central axes of the two sixth conductive connection parts 861, R9 is the parasitic resistance value of the portion of the third wire 413 with a length of (d4-d3); the values ​​of d3 and d4 are known and have been determined before the preparation of the interposer layer. R7 is the parasitic resistance value of each conductive part 30 in contact with the auxiliary wire 414; R6 is the third parasitic resistance value between the two conductive ends 8611 of the sixth sub-test structure 86; R9 is the fourth parasitic resistance value of the fourth conductive connection part 8414; R11 is the parasitic resistance value of the fourth conductive connection part 8415; R10 is the parasitic resistance value of the conductive end of the fourth conductive connection part 8415; R' is the parasitic resistance value per unit length of the second wire 4121 located in the same redistribution layer as the auxiliary wire 414; R” is the fifth parasitic resistance value per unit length of the second wire 4121 located in the same redistribution layer as the third wire 413.

[0081] In one embodiment, as shown in FIG6, the plurality of wires 41 of the conductive structure includes a fourth wire 415 located in the test area 101; the extension direction of the plurality of second wires 412 is different from the extension direction of the fourth wire 415; the parasitic parameter test structure further includes a seventh sub-test structure, the seventh sub-test structure including the fourth wire 415 and two seventh conductive connection portions located on the side of the fourth wire 415 away from the second surface and connected to the fourth wire 415, the fourth wire 415 corresponds to two openings 131, each of the seventh conductive connection portions includes a conductive portion 30 located in one of the openings 131 corresponding to the fourth wire 415, when the opening 131 includes at least two sub-openings 1311, the seventh conductive connection portion further includes a conductive block 42 located between two adjacent conductive portions 30; the conductive end of the seventh conductive connection portion away from the second surface 12 exposes the insulating layer 10.

[0082] When the parasitic parameter test structure includes a seventh sub-test structure, the test method further includes the following steps:

[0083] First, the fourth parasitic parameter value of the seventh sub-test structure is detected; the fourth parasitic parameter value is the parasitic parameter value between the conductive ends of two of the three seventh conductive connections;

[0084] Subsequently, based on the fourth parasitic parameter value and the parasitic resistance value of the fourth conductive connection in the fourth sub-test structure where the second conductor is located in the same redistribution layer as the fourth conductor, the parasitic resistance value of the fourth conductor is determined, and the parasitic resistance value per unit length of the fourth conductor is calculated based on the length of the fourth conductor and the parasitic resistance value of the fourth conductor.

[0085] If the fourth conductive connection portion in the fourth sub-test structure, which is located on the same redistribution layer as the fourth conductive wire, has the same structure as the seventh conductive connection portion, then their parasitic resistance values ​​are the same. By comparing the resistance value per unit length of the fourth conductive wire and the resistance value per unit length of the second conductive wire, it can be determined whether the extension direction of the wire affects the magnitude of the parasitic resistance value.

[0086] In some embodiments, the plurality of wires 41 of the conductive structure may include at least two fourth wires 415 with different extending directions. For each fourth wire, the parasitic resistance value per unit length of the fourth wire can be determined using the steps described above. This is more helpful in determining the influence of different extending directions of the wires on the magnitude of the parasitic resistance value.

[0087] The intermediate layer and its testing method provided in this application can provide good guidance for optimizing the subsequent preparation process of the intermediate layer by testing the parasitic parameter values.

[0088] In one embodiment, as shown in FIG7, the plurality of wires 41 of the conductive structure include a plurality of fifth wires 416 located in the test area 101; the conductive structure includes a signal crosstalk test structure 804 located in the test area 101; the signal crosstalk test structure 804 includes a plurality of eighth sub-test structures 87, each eighth sub-test structure 87 including one fifth wire 416 and two eighth conductive connection portions 871 located on the side of the fifth wire 416 away from the second surface 12 and connected to the fifth wire 416, the fifth wire 416 being paired with the two openings 131. The conductive ends 8711 of each of the eighth conductive connections 871, away from the second surface 12, are exposed in the insulating layer 10; each of the eighth conductive connections 871 includes a conductive portion 30 located in an opening 131 corresponding to the fifth conductor 416, and when the opening 131 includes at least two sub-openings 1311, the eighth conductive connection 871 also includes a conductive block 42 located between two adjacent conductive portions 30; the extension directions of each of the fifth conductors 416 in the signal crosstalk test structure 804 are parallel to each other, and at least two of the fifth conductors 416 are located in different redistribution layers 40.

[0089] In the embodiment shown in Figure 7, the signal crosstalk test structure 804 includes three eighth sub-test structures 87, and the fifth conductors 416 of the three eighth sub-test structures 87 are located in different redistribution layers 40. In other embodiments, the signal crosstalk test structure 804 may include two eighth sub-test structures 87, or four or more eighth sub-test structures 87.

[0090] In one embodiment, when the conductive structure includes a signal crosstalk test structure 804 located in the test area 101, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes:

[0091] First, a test signal is applied to the conductive end of the eighth conductive connection portion away from the second surface in at least two of the eighth sub-test structures. The test signal is a pulse signal or a sine wave signal.

[0092] Subsequently, the output signals of each of the eighth sub-test structures are received;

[0093] Subsequently, for each of the eighth sub-test structures, the difference between the parameter values ​​of the test signal and the output signal is determined based on the test signal and the output signal of the eighth sub-test structure. The parameter values ​​include at least one of frequency, amplitude, and phase difference.

[0094] The difference in frequency, amplitude, and phase between the test signal and the output signal of the eighth sub-test structure can reflect the degree of signal interference from other wires to the conductors of the eighth sub-test structure.

[0095] In this embodiment, a test signal can be applied through the conductive terminal of the eighth sub-test structure, and an output signal can be received through the conductive terminal of the eighth sub-test structure.

[0096] The interposer and its testing method provided in this application, by testing the signal crosstalk of the conductor, can provide good guidance for optimizing the subsequent fabrication process of the interposer.

[0097] In the test area structure provided in this application embodiment, different test structures can share some structures. For example, the first sub-test structure 81 of the open circuit test structure 801 can be reused as the eighth sub-test structure 87 of the signal crosstalk test structure 804; the second sub-test structure 82 of the open circuit test structure 801 can be reused as the third sub-test structure 83 of the short circuit test structure 802; and the second sub-test structure 82 of the open circuit test structure 801 can be reused as the fourth sub-test structure 84 or the fifth sub-test structure 85 of the parasitic parameter test structure 803. This simplifies the structure of the test area 101.

[0098] This application also provides a semiconductor structure, as shown in FIG8. The semiconductor structure includes a plurality of chips 70 and an interposer layer as described in any of the above embodiments. Each chip 70 is located on the side of the insulating layer 10 away from the second surface 12, and is electrically connected to a conductive portion 30 located in an opening 131 in the functional area 102.

[0099] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An intermediary layer (100), comprising a test area (101) and a functional area (102); the intermediary layer (100) comprising: An insulating layer (10) is located in the test area (101) and the functional area (102); the insulating layer (10) includes a plurality of stacked insulating film layers (13); wherein, The insulating layer (10) is provided with a plurality of openings (131), each of the openings (131) including one sub-opening (1311) or at least two sub-openings (1311) arranged along the stacking direction of the plurality of insulating film layers (13), and each of the sub-openings (1311) penetrates one of the insulating film layers (13). Some of the plurality of openings (131) are located in the test area (101), and some of the plurality of openings (131) are located in the functional area (102); The conductive structure includes multiple conductive portions (30) and multiple redistribution layers (40), wherein, Each of the sub-openings (1311) is provided with a conductive part (30); A redistribution layer (40) is provided between any two adjacent insulating film layers (13); Each of the redistribution layers (40) includes a plurality of conductors (41) and a plurality of conductive blocks (42). Each conductive block (42) is located between two adjacent conductive portions (30) within the same opening (131). Each conductor (41) corresponds to at least one opening (131) and is in contact with one of the conductive portions (30) located within the corresponding opening (131). Wherein, at least one of the wires (41) and a plurality of the conductive blocks (42) are located in the test area (101), and at least one of the wires (41) and a plurality of the conductive blocks (42) are located in the functional area (102); The portion of the conductive structure located in the test area (101) is insulated from the portion located in the functional area (102); the portion of the conductive structure located in the test area (101) is used to test whether the conductive structure has a short circuit and / or an open circuit.

2. The intermediary layer according to claim 1, characterized in that, The insulating layer (10) includes opposing first surfaces (11) and second surfaces (12); The insulating layer (10) comprises N insulating film layers (13), where N is a positive integer greater than or equal to 2; The plurality of wires (41) of the conductive structure include a plurality of first wires (411) located in the test area (101); The conductive structure includes an open circuit test structure (801) located in the test area (101), and the open circuit test structure (801) includes N-1 first sub-test structures (81) and at least one second sub-test structure (82); Each of the first sub-test structures (81) includes a first conductor (411) and two first conductive links located on the side of the first conductor (411) away from the second surface (12) and in contact with the first conductor (411). The connecting part (811), in which, The conductive end of each of the first conductive connections (811) away from the second surface (12) exposes the insulating layer (10); Each of the first conductors (411) corresponds to one of the two openings (131). Each of the first conductive connection portions (811) includes a conductive portion (30) located in an opening (131) corresponding to the first conductor (411). When the opening (131) includes at least two sub-openings (1311), the first conductive connection portion (811) also includes a conductive block (42) located between two adjacent conductive portions (30). The first conductors (411) of the N-1 first sub-test structures (81) are located in different rewiring layers (40); Each of the second sub-test structures (82) includes a second conductive connection portion (821), wherein, The conductive end of the second conductive connection portion (821) away from the second surface (12) and the conductive end away from the first surface (11) respectively expose the insulating layer (10); The second conductive connection portion (821) includes a plurality of conductive portions (30) located within an opening (131) penetrating the insulating layer (10) and a conductive block (42) located between two adjacent conductive portions (30).

3. The intermediary layer according to claim 1, characterized in that, The insulating layer (10) includes opposing first surfaces (11) and second surfaces (12); The conductive structure includes a short-circuit test structure (802) located in the test area (101), and the short-circuit test structure (802) includes at least two third sub-test structures (83). Each of the third sub-test structures (83) includes a third conductive connection (831, 832, 833), wherein, The third conductive connection portion (831, 832, 833) includes a plurality of conductive portions (30) located within an opening (131) penetrating the insulating layer (10) and a conductive block (42) located between two adjacent conductive portions (30); The conductive ends of the third conductive connection portions (831, 832, 833) away from the second surface (12) and away from the first surface (11) respectively expose the insulating layer (10).

4. The intermediary layer according to claim 1, characterized in that, The conductive structure includes a parasitic parameter test structure (803) located in the test area (101); The insulating layer (10) includes opposing first surfaces (11) and second surfaces (12); The insulating layer (10) comprises N insulating film layers (13), where N is a positive integer greater than or equal to 2; The plurality of wires (41) of the conductive structure include a plurality of second wires (412) located in the test area (101); The parasitic parameter test structure (803) includes N-1 fourth sub-test structures (84) and at least one fifth sub-test structure (85); Each of the fourth sub-test structures (84) includes a second conductor (412) and three fourth conductive connections (841) located on the side of the second conductor (412) away from the second surface (12) and in contact with the second conductor (412), wherein, The three fourth conductive connections (841) are arranged side by side along the second conductor (412); The second conductor (412) corresponds to the three openings (131). Each of the fourth conductive connection portions (841) includes a conductive portion (30) located in an opening (131) corresponding to the second conductor (412). When the opening (131) includes at least two sub-openings (1311), the fourth conductive connection portion (841) also includes a conductive block (42) located between two adjacent conductive portions (30). The conductive end of each of the fourth conductive connection portions (841) away from the second surface (12) exposes the insulating layer (10); The second conductors (412) of the N-1 fourth sub-test structures (84) are located in different rewiring layers (40); Each of the fifth sub-test structures (85) includes a fifth conductive connection portion (851), wherein, The fifth conductive connection portion (851) exposes the insulating layer (10) at its conductive end away from the second surface (12) and at its conductive end away from the first surface (11); The fifth conductive connection (851) includes a plurality of conductive portions (30) located in an opening (131) penetrating the insulating layer (10) and a conductive block (42) located between two adjacent conductive portions (30).

5. The intermediary layer according to claim 4, characterized in that, The plurality of wires (41) of the conductive structure include at least one third wire (413) and an auxiliary wire (414) located in the test area (101); The parasitic parameter test structure (803) further includes a sixth sub-test structure (86), which includes a third conductor (413), two sixth conductive connections (861) located on the side of the third conductor (413) away from the second surface (12), an auxiliary conductor (414) located between the first surface (11) and the third conductor (413), and two conductive parts (30) located between the auxiliary conductor (414) and the third conductor (413); wherein, The conductive end of each of the sixth conductive connection portions (861) away from the second surface (12) exposes the insulating layer (10); The third conductor (413) corresponds to the two openings (131), and the openings (131) include at least two sub-openings (1311); The sixth conductive connection (861) includes one of the connections located corresponding to the third conductor (413). Multiple conductive parts (30) within the opening (131) and conductive blocks (42) located between adjacent conductive parts (30); An insulating film layer (13) is provided between the auxiliary wire (414) and the third wire (413), and two conductive parts (30) located between the auxiliary wire (414) and the third wire (413) are in contact with the third wire (413) and the auxiliary wire (414) respectively. The conductive parts (30) of the sixth sub-test structure (86) and the conductive parts (30) of the fourth sub-test structure (84) are all the same size.

6. The intermediary layer according to claim 4, characterized in that, The plurality of wires (41) of the conductive structure include a fourth wire (415) located in the test area (101); The extension direction of the plurality of second conductors (412) is different from the extension direction of the fourth conductor (415); The parasitic parameter testing structure further includes a seventh sub-test structure, which includes the fourth conductor (415) and two seventh conductive connections located on the side of the fourth conductor (415) away from the second surface (12) and connected to the fourth conductor (415). The fourth conductor (415) corresponds to the two openings (131). Each of the seventh conductive connection portions includes a conductive portion (30) located in an opening (131) corresponding to the fourth conductor (415). When the opening (131) includes at least two sub-openings (1311), the seventh conductive connection portion also includes a conductive block (42) located between two adjacent conductive portions (30). The conductive end of the seventh conductive connection portion away from the second surface (12) exposes the insulating layer (10).

7. The intermediary layer according to claim 1, characterized in that, The insulating layer (10) includes opposing first surfaces (11) and second surfaces (12); The plurality of wires (41) of the conductive structure include a plurality of fifth wires (416) located in the test area (101); The conductive structure includes a signal crosstalk test structure (804) located in the test area (101); the signal crosstalk test structure (804) includes a plurality of eighth sub-test structures (87). Each of the eighth sub-test structures (87) includes one fifth conductor (416) and two eighth conductive connections (871) located on the side of the fifth conductor (416) away from the second surface (12) and connected to the fifth conductor (416), wherein, The fifth conductor (416) corresponds to the two openings (131); The conductive end of each of the eighth conductive connection portions (871) away from the second surface (12) exposes the insulating layer (10); Each of the eighth conductive connection portions (871) includes a conductive portion (30) located within an opening (131) corresponding to the fifth conductor (416), wherein the opening (131) includes at least two sub-openings (1311). The eighth conductive connection part (871) also includes a conductive block (42) located between two adjacent conductive parts (30); The extension directions of each of the fifth conductors (416) in the signal crosstalk test structure (804) are parallel to each other, and at least two of the fifth conductors (416) are located in different redistribution layers (40).

8. A semiconductor structure, comprising: Multiple chips (70), and The intermediary layer as described in any one of claims 1 to 7; Each of the chips (70) is located on one side of the insulating layer (10) and is electrically connected to the conductive part (30) located in the opening (131) of the functional area (102).

9. A testing method for an intermediary layer, used to test the intermediary layer according to any one of claims 1 to 7; the testing method comprising: Determine whether there is a short circuit and / or open circuit in the portion of the conductive structure located in the test area; If the portion of the conductive structure located in the test area has a short circuit and / or an open circuit, then the portion of the conductive structure located in the functional area is determined to not meet the requirements.

10. The testing method for the intermediary layer according to claim 9, characterized in that, When the conductive structure includes an open-circuit test structure located in the test area, the step of determining whether there is an open circuit in the portion of the conductive structure located in the test area includes: For each of the first sub-test structures, determine whether the first sub-test structure has an open circuit; for each of the second sub-test structures, determine whether the second sub-test structure has an open circuit. If at least one of the first sub-test structures has an open circuit, it is determined that the portion of the conductive structure located in the test area has an open circuit; if at least one of the second sub-test structures has an open circuit, it is determined that the portion of the conductive structure located in the test area has an open circuit.

11. The testing method for the intermediary layer according to claim 9, characterized in that, When the conductive structure includes a short-circuit test structure located in the test area, the step of determining whether a short circuit exists in the portion of the conductive structure located in the test area includes: Determine whether there is a short circuit between any two of the third sub-test structures; If a short circuit exists between two of the third sub-test structures, it is determined that the portion of the conductive structure located in the test area has a short circuit.

12. The testing method for the intermediary layer according to claim 9, characterized in that, When the conductive structure includes a parasitic parameter test structure located in the test area, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes: For each of the fourth sub-test structures, the first parasitic parameter value and the second parasitic parameter value of the fourth sub-test structure are detected. Parasitic parameter values; detecting the third parasitic parameter value of the fifth conductive connection; the first parasitic parameter value is the parasitic parameter value between the two conductive ends of two non-adjacent fourth conductive connections among the three fourth conductive connections; the second parasitic parameter value is the parasitic parameter value between the two conductive ends of two adjacent fourth conductive connections among the three fourth conductive connections; the third parasitic parameter value is the parasitic parameter value between the two conductive ends of the fifth conductive connection; the parasitic parameter value includes at least one of parasitic resistance value and parasitic capacitance value; For each of the fourth sub-test structures, the parasitic parameter values ​​of the fourth conductive connection portion and the parasitic parameter values ​​per unit length of the second conductor in the fourth sub-test structure are calculated based on the first parasitic parameter value and the second parasitic parameter value.

13. The testing method for the intermediary layer according to claim 12, characterized in that, The parasitic parameter values ​​include parasitic resistance, parasitic capacitance, and parasitic impedance; the first parasitic parameter value includes a first parasitic impedance value, and the second parasitic parameter value includes a second parasitic impedance value; for each of the fourth sub-test structures, after calculating the parasitic parameter values ​​of the fourth conductive connection portion and the parasitic parameter values ​​per unit length of the second conductor in the fourth sub-test structure based on the first and second parasitic parameter values, the test method further includes: For each of the fourth sub-test structures, the parasitic inductance of the fourth conductive connection and the parasitic inductance of the second wire per unit length are calculated based on the first parasitic impedance value, the second parasitic impedance value, the parasitic resistance value and the parasitic capacitance value of the fourth conductive connection, and the parasitic resistance value and the parasitic capacitance value of the second wire per unit length.

14. The testing method for the intermediary layer according to claim 12, characterized in that, The first parasitic parameter value includes a first parasitic resistance value, and the second parasitic parameter value includes a second parasitic resistance value; When the parasitic parameter test structure includes a sixth sub-test structure, after determining that there is no short circuit or open circuit in the portion of the conductive structure located in the test area, the test method further includes: The third parasitic resistance value between the two conductive terminals of the sixth sub-test structure is detected; The parasitic resistance value of the conductive end of the fourth conductive connection is calculated based on the resistance value per unit length of the second conductor located in the same redistribution layer as the auxiliary conductor, the third parasitic resistance value, the parasitic resistance value of the fourth conductive connection including only one conductive part, the fourth parasitic resistance value, and the fifth parasitic resistance value. Wherein, the fourth parasitic resistance value is the parasitic resistance value of the fourth conductive connection portion in the fourth sub-test structure where the second conductor is located in the same redistribution layer as the third conductor, and the fifth parasitic resistance value is the parasitic resistance value per unit length of the second conductor located in the same redistribution layer as the third conductor.

15. The testing method for the intermediary layer according to claim 10, characterized in that, When the conductive structure includes a signal crosstalk test structure located in the test area, after determining that there are no short circuits or open circuits in the portion of the conductive structure located in the test area, the test method further includes: Test signals are applied to the conductive ends of the eighth conductive connection portions in at least two of the eighth sub-test structures that are away from the second surface, and the test signals are pulse signals or sine signals. Receive the output signals of each of the eighth sub-test structures; For each of the eighth sub-test structures, the difference between the parameter values ​​of the test signal and the output signal is determined based on the test signal and the output signal of the eighth sub-test structure, wherein the parameter values ​​include at least one of frequency, amplitude and phase difference.

Images