A compensation alignment bonding method for LED display panel

Abstract

The present invention discloses a compensated alignment bonding method for an LED display panel, comprising: placing a first substrate on a heating platform, fixing a second substrate above the first substrate, and aligning the bump array on the first substrate with the bump array on the second substrate; heating the first and second substrates to a preset temperature, and then performing pressure welding on the first and second substrates; cooling the substrates to room temperature, and measuring the thermal expansion offset between the bump arrays on the first and second substrates; and compensating the bump arrays on the first or second substrate based on the thermal expansion offset. The present invention compensates for the lateral offset of the bump arrays on the first or second substrate, thereby reducing the offset of the eutectic microstructure formed after alignment bonding, alleviating the thermal stress of the eutectic microstructure, and improving the display quality of the LED display panel.

Description

Technical Field

[0001] The present invention relates to the technical field of LED display panels, and in particular to a compensation alignment bonding method for LED display panels. Background Art

[0002] Currently, high-density Micro LED display panels are typically fabricated by fabricating bump arrays on separate Micro LED and CMOS substrates. High-precision alignment equipment is then used to align the bump arrays on the two substrates. Finally, pressure and heating are applied to diffuse the microstructures of the two bump arrays to form a eutectic microstructure, enabling the integration of the Micro LED chip array on the CMOS substrate to form a Micro LED display panel. During the high-precision alignment and bonding of the bump arrays on the Micro LED substrate and the bump array on the CMOS substrate, the sapphire substrate of the Micro LED substrate and the silicon substrate of the CMOS substrate have different thermal expansion coefficients, resulting in different expansion degrees during heating. After alignment at room temperature, the eutectic microstructure formed during heating and bonding can easily shift or even break due to thermal stress, affecting the display quality of the resulting Micro LED display panel. Summary of the Invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art. The present invention provides a compensating alignment bonding method for an LED display panel, which performs lateral offset compensation on the bump array on the first substrate or the second substrate, thereby reducing the offset of the eutectic microstructure formed after alignment bonding, reducing the thermal stress of the eutectic microstructure, and improving the display quality of the LED display panel.

[0004] The present invention provides a compensation alignment bonding method for an LED display panel, the compensation alignment bonding method for an LED display panel comprising:

[0005] Placing a first substrate on a heating platform, fixing a second substrate above the first substrate, and aligning the bump array on the first substrate with the bump array on the second substrate;

[0006] heating the first substrate and the second substrate, and when heated to a preset temperature, performing pressure welding on the bump array on the first substrate and the bump array on the second substrate;

[0007] Cooling the first and second substrates after press welding to room temperature, and measuring the thermal expansion offset of the bump array on the first substrate and the bump array on the second substrate;

[0008] The bump array on the first substrate or the second substrate is compensated based on the thermal expansion offset.

[0009] Furthermore, fixing the second substrate on top of the first substrate includes:

[0010] The second substrate is sucked by a pressure-heated transfer head disposed above the heating platform to fix the second substrate above the first substrate.

[0011] Furthermore, aligning the bump array on the first substrate with the bump array on the second substrate includes:

[0012] The bump array on the first substrate is aligned with the bump array on the second substrate at room temperature.

[0013] Furthermore, the heating of the first substrate and the second substrate, and after heating to a preset temperature, performing pressure welding on the bump array on the first substrate and the bump array on the second substrate comprises:

[0014] The first substrate and the second substrate are heated, and when heated to a first preset temperature, the bump array on the first substrate and the bump array on the second substrate are press-welded.

[0015] Furthermore, the first preset temperature is greater than the melting point of the solder on the bump array provided on the first substrate and the bump array provided on the second substrate.

[0016] Furthermore, aligning the bump array on the first substrate with the bump array on the second substrate includes:

[0017] heating the first substrate, and obtaining a first substrate first offset of the bump array on the first substrate when the first substrate is heated to a second preset temperature;

[0018] heating the second substrate and observing the bump array on the second substrate; stopping heating when the second substrate first offset of the bump array on the second substrate is equal to the first offset of the first substrate; and obtaining the temperature at this time as a third preset temperature;

[0019] The second substrate is fixed above the first substrate, and the bump array on the first substrate at the second preset temperature is aligned with the bump array on the second substrate at a third preset temperature.

[0020] Furthermore, the second preset temperature is lower than the melting point of the solder of the bump array provided on the first substrate, and the third preset temperature is lower than the melting point of the solder on the bump array provided on the second substrate.

[0021] Furthermore, the heating of the first substrate to a second preset temperature and obtaining a first offset of the bump array on the first substrate includes:

[0022] Measuring the spacing distance between the center bump and the outermost bump in the bump array on the first substrate at room temperature;

[0023] Heating the first substrate to a second preset temperature, and measuring the distance between a center bump and an outermost bump in the bump array on the first substrate at the second preset temperature;

[0024] The spacing distance between the center bump and the outermost bump in the bump array on the first substrate at the second preset temperature is compared with the spacing distance between the center bump and the outermost bump in the bump array on the first substrate at room temperature to obtain a first offset of the first substrate.

[0025] Furthermore, heating the second substrate, observing the bump array on the second substrate, and stopping heating when the second substrate first offset of the bump array on the second substrate is equal to the first offset of the first substrate, and obtaining the temperature at this time as a third preset temperature includes:

[0026] Measuring the spacing distance between the center bump and the outermost bump in the bump array on the second substrate at room temperature;

[0027] Continuously heating the second substrate, measuring the distance between the center bump and the outermost bump in the bump array on the second substrate during the heating process, and comparing the distance between the center bump and the outermost bump in the bump array on the second substrate at room temperature to obtain a first offset of the second substrate;

[0028] When the first offset of the second substrate is equal to the first offset of the first substrate, heating is stopped, and the temperature at this time is obtained as a third preset temperature.

[0029] Furthermore, the heating of the first substrate and the second substrate, and press-welding the bump array on the first substrate and the bump array on the second substrate after heating to a preset temperature, further comprises:

[0030] The first substrate and the second substrate are heated, and when heated to a fourth preset temperature, the bump array on the first substrate and the bump array on the second substrate are press-welded.

[0031] Furthermore, the fourth preset temperature is ≥ melting point temperature of solder on the bump array provided on the first substrate and the bump array provided on the second substrate*2-second preset temperature-third preset temperature.

[0032] Furthermore, measuring the thermal expansion offset of the bump array on the first substrate and the bump array on the second substrate at this time includes:

[0033] Measuring the maximum offset distance between the spacing distance between the center bump and the outermost bump in the bump array on the first substrate and the spacing distance between the center bump and the outermost bump in the bump array on the second substrate;

[0034] Obtaining the number of intervals from a central bump to an outermost bump in the bump array on the first substrate, and calculating a unit interval offset distance based on the maximum offset distance and the number of intervals;

[0035] The offset distance of the corresponding bump is calculated based on the number of intervals between each bump and the central bump in the bump array on the first substrate and the unit interval offset distance.

[0036] Furthermore, compensating the bump array on the first substrate or the second substrate based on the thermal expansion offset includes:

[0037] Offset compensation is performed on each bump in the bump array on the first substrate or the second substrate based on the offset distance of the corresponding bump.

[0038] The present invention provides a compensated alignment bonding method for an LED display panel. Before a first substrate and a second substrate are aligned and bonded, a bump array on the first substrate is aligned with a bump array on the second substrate, and the first substrate and the second substrate are heated to a certain temperature and then press-welded. The thermal expansion offset of the first substrate and the second substrate is obtained by measurement, and lateral distance compensation is performed on each bump of the bump array on the first substrate or the second substrate based on the thermal expansion offset, so that the press-welding effect between the first substrate and the second substrate is better, the offset of the eutectic microstructure formed after the alignment bonding is reduced, the thermal stress of the eutectic microstructure is reduced, and the display quality of the LED display panel is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 This is a flow chart of the compensation alignment bonding method of the LED display panel in the first embodiment of the present invention;

[0041] Figure 2This is a flow chart of measuring the thermal expansion offset of the bump array on the first substrate and the bump array on the second substrate in the first embodiment of the present invention;

[0042] Figure 3 Schematic diagram of the compensation alignment spacing structure of the LED display panel in the first embodiment of the present invention;

[0043] Figure 4 1 is a first structural diagram of the N-pole bump of the second substrate in the first embodiment of the present invention;

[0044] Figure 5 1 is a second structural diagram of the N-pole bump of the second substrate in the first embodiment of the present invention;

[0045] Figure 6 1 is a diagram of the P-pole bump structure of the first substrate in the first embodiment of the present invention;

[0046] Figure 7 This is a flow chart of a compensation alignment bonding method for an LED display panel in a second embodiment of the present invention;

[0047] Figure 8 This is a flow chart of aligning the bump array on the first substrate with the bump array on the second substrate in the second embodiment of the present invention;

[0048] Figure 9 This is a flow chart of obtaining a first offset of a first substrate of a bump array on the first substrate in the second embodiment of the present invention;

[0049] Figure 10 This is a flow chart of obtaining the third preset temperature in the second embodiment of the present invention;

[0050] Figure 11 This is a flow chart of measuring the thermal expansion offset of the bump array on the first substrate and the bump array on the second substrate in the second embodiment of the present invention;

[0051] Figure 12 Schematic diagram of the compensation alignment spacing structure of the LED display panel in the second embodiment of the present invention;

[0052] Figure 13 This is a first structural diagram of the N-pole bump of the second substrate in the second embodiment of the present invention;

[0053] Figure 14 This is a second structural diagram of the N-pole bump of the second substrate in the second embodiment of the present invention;

[0054] Figure 15 This is a diagram of the P-pole bump structure of the first substrate in the second embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0056] In the present invention, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts or their combinations disclosed in this specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts or their combinations exist or are added.

[0057] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0058] Example 1

[0059] Embodiment 1 of the present invention provides a compensation alignment bonding method for an LED display panel, which includes: placing a first substrate on a heating platform, fixing a second substrate above the first substrate, and aligning the bump array on the first substrate with the bump array on the second substrate; heating the first substrate and the second substrate, and when heated to a preset temperature, press-welding the bump array on the first substrate and the bump array on the second substrate; cooling the press-welded first and second substrates to room temperature, and measuring the thermal expansion offset of the bump array on the first substrate and the bump array on the second substrate at this time; and compensating the bump array on the first substrate or the second substrate based on the thermal expansion offset.

[0060] In an optional implementation of this embodiment, as Figure 1 As shown, Figure 1 A flow chart of a compensation alignment bonding method for an LED display panel in a first embodiment of the present invention is shown, comprising the following steps:

[0061] S101, placing a first substrate on a heating platform, fixing a second substrate above the first substrate, and aligning the bump array on the first substrate with the bump array on the second substrate;

[0062] In an optional implementation of this embodiment, the first substrate is a CMOS substrate, and the second substrate is a Micro LED substrate, or the first substrate is a Micro LED substrate, and the second substrate is a CMOS substrate, according to actual design requirements.

[0063] It should be noted that the thermal expansion coefficient of the first substrate is different from the thermal expansion coefficient of the second substrate, that is, the thermal expansion coefficient of the CMOS substrate is different from the thermal expansion coefficient of the Micro LED substrate.

[0064] In an optional implementation of this embodiment, a pressure-heated transfer head disposed above the heating platform absorbs the second substrate and fixes the second substrate above the first substrate.

[0065] In an optional implementation of this embodiment, the bump array on the first substrate is aligned with the bump array on the second substrate at room temperature;

[0066] Specifically, the number and positions of the bumps in the bump array on the first substrate are the same as the number and positions of the bumps in the bump array on the second substrate. In this step, the bumps in the bump array on the first substrate are aligned with the bumps in the bump array on the second substrate at room temperature.

[0067] S102, heating the first substrate and the second substrate, and when heated to a preset temperature, performing pressure welding on the bump array on the first substrate and the bump array on the second substrate;

[0068] In an optional implementation of this embodiment, the first substrate and the second substrate are heated, and after being heated to a first preset temperature, the bump array on the first substrate and the bump array on the second substrate are press-welded.

[0069] In an optional implementation of this embodiment, the first preset temperature is greater than the melting point of the solder on the bump array provided on the first substrate and the bump array provided on the second substrate.

[0070] Specifically, a first preset temperature G is set, and the first preset temperature G is greater than the melting point temperature S of the solder on the bump array provided on the first substrate and the bump array provided on the second substrate, that is, G>S.

[0071] In an optional implementation of this embodiment, after the first substrate and the second substrate are heated to a first preset temperature, the solder points on the bump array provided on the first substrate and the bump array provided on the second substrate are melted, and after the bumps of the bump array on the first substrate are aligned one-to-one with the bumps of the bump array on the second substrate, press welding is performed.

[0072] S103, cooling the first substrate and the second substrate after the press welding to room temperature, and measuring the thermal expansion offset of the bump array on the first substrate and the bump array on the second substrate;

[0073] In an optional implementation of this embodiment, after the press-welding is completed, the press-welded first substrate and the second substrate are cooled to room temperature.

[0074] In an optional implementation of this embodiment, as Figure 2 As shown, Figure 2 A flow chart of measuring the thermal expansion offset of a bump array on a first substrate and a bump array on a second substrate in Embodiment 1 of the present invention is shown, including the following steps:

[0075] S201, measuring the maximum offset distance between the spacing distance from the center bump to the outermost bump in the bump array on the first substrate and the spacing distance from the center bump to the outermost bump in the bump array on the second substrate;

[0076] In an optional implementation of this embodiment, as Figure 3 As shown, Figure 3 A schematic diagram of the compensation alignment spacing structure of the LED display panel in the first embodiment of the present invention is shown.

[0077] In an optional implementation of this embodiment, the first substrate 1 includes a silicon substrate 11, a plurality of solder pads 12 arranged on the silicon substrate 11, and bumps arranged on the solder pads 12, which form a bump array of the first substrate 1, including the first bumps 13 at the extreme edges on the left and right sides and the second bump 14 in the center.

[0078] In an optional implementation of this embodiment, the second substrate 2 includes a sapphire substrate 21, a buffer layer 22, an N-type layer 23, and a plurality of bumps arranged on the N-type layer 23, which form a bump array of the second substrate 2, including third bumps 24 at the extreme edges on the left and right sides and a fourth bump 25 in the center.

[0079] In an optional implementation of this embodiment, the bump array on the second substrate 2 is composed of P-pole bumps located in the center array and N-pole bumps located in the periphery. Figure 3In the structure shown, the third bumps 24 at the extreme edges on the left and right sides are N-pole bumps, and the remaining bumps, including the fourth bump 25 at the center, are P-pole bumps.

[0080] In an optional implementation of this embodiment, the N-pole bump has two structures.

[0081] Specifically, such as Figure 4 As shown, Figure 4 FIG. 1 shows a first structural diagram of the N-pole bump of the second substrate in the first embodiment of the present invention. Figure 4 That is Figure 3 In the enlarged view at point a, the N-pole convex point includes a light-emitting layer 34, a P-type layer 33, an electrode layer 32, and an electrical connection layer 31, wherein the light-emitting layer 34, the P-type layer 33, and the electrode layer 32 are arranged in sequence from top to bottom, and the electrical connection layer 31 is arranged on the side of the electrode layer 32, extending along the sides of the electrode layer 32, the P-type layer 33, and the light-emitting layer 34, and contacting the N-type layer 23.

[0082] More, such as Figure 5 As shown, Figure 5 FIG2 shows a second structure diagram of the N-pole bump of the second substrate in the first embodiment of the present invention. Figure 5 That is Figure 3 In the enlarged view at a, the N-pole bump only includes the electrode layer 32. Figure 5 The electrode layer 32 in Figure 4 The electrode layer 32 in the same material has the same function. Figure 5 The height of the electrode layer 32 in Figure 4 The stacking heights of the middle light emitting layer 34 , the P-type layer 33 , and the electrode layer 32 are consistent.

[0083] In an optional implementation of this embodiment, as Figure 6 As shown, Figure 6 FIG. 1 shows a P-pole bump structure diagram of the first substrate in the first embodiment of the present invention. Figure 6 That is Figure 3 In the enlarged view at b, the P-pole convex point includes a light-emitting layer 37, a P-type layer 36, and an electrode layer 35. The light-emitting layer 37, the P-type layer 36, the electrode layer 35 and Figure 4 The light-emitting layer 34, the P-type layer 33, and the electrode layer 32 of the middle N-pole bump are made of the same material, have the same height, and achieve the same function.

[0084] In an optional implementation of this embodiment, the maximum offset distance E of the spacing distance between the second bump 14 at the center of the bump array on the first substrate 1 and the first bump 13 at the outermost edge and the spacing distance between the fourth bump 25 at the center of the bump array on the second substrate 2 and the third bump 24 at the outermost edge is measured.

[0085] It should be noted that the convex point on the left edge or the convex point on the right edge can be selected.

[0086] S202, obtaining the number of intervals from the center bump to the outermost bump in the bump array on the first substrate, and calculating a unit interval offset distance based on the maximum offset distance and the number of intervals;

[0087] In an optional implementation of this embodiment, the number n of intervals from the second bump 14 at the center to the first bump 13 at the outermost edge of the bump array on the first substrate is obtained, and the unit interval offset distance l is calculated based on the maximum offset distance E and the number n of intervals, using the following formula:

[0088]

[0089] Where l is the unit interval offset distance, E is the maximum offset distance, and n is the number of intervals.

[0090] Specifically, in Figure 3 In the embodiment, the number of intervals between the second bumps 14 and the first bumps 13 is 3.

[0091] It should be noted that, according to the linear expansion coefficient formula α=ΔL / (L*ΔT), under the same temperature and material conditions, the linear expansion in the lateral direction is proportional to the linear body size. Since an object usually expands from the center to the surrounding area when thermal expansion occurs, it expands to both sides in the lateral direction. Since the spacing distances between adjacent bumps in the bump array provided on the first substrate are the same, the offset distance from the center bump to the outermost bump is proportional to the number of spacings, and the ratio is the unit spacing offset distance.

[0092] S203, calculating the offset distance of the corresponding bump based on the number of intervals between each bump and the central bump in the bump array on the first substrate and the unit interval offset distance.

[0093] In an optional implementation of this embodiment, the offset distances that each bump needs to be offset to both sides are calculated based on the number of intervals between each bump and the central bump in the bump array on the first substrate and the unit interval offset distance.

[0094] Specifically, the number of intervals between the bumps of the bump array on the first substrate, such as the first bump 13 at the outermost edge and the second bump 14 at the center, is 3, and the offset distance E3 of the first bump 13 at the outermost edge is l*3.

[0095] S104 , compensating the bump array on the first substrate or the second substrate based on the thermal expansion offset.

[0096] In an optional implementation of this embodiment, based on the offset distance corresponding to each bump in the bump array on the first substrate calculated in step S203, offset compensation is performed on each bump in the bump array on the first substrate.

[0097] Specifically, according to the offset distance corresponding to each convex point, the convex point is moved in a corresponding direction by the corresponding offset distance to complete the offset compensation, where the direction is the direction away from the central convex point.

[0098] It should be noted that, in this embodiment, the compensation operation is preferably performed on the first substrate, and in practical applications, the compensation operation may also be performed on the second substrate.

[0099] It should be noted that since the first substrate and the second substrate are both rectangular in shape, and thermal expansion has a greater impact on the length direction of the substrate and a smaller impact on the width direction of the substrate, in this embodiment, the offset compensation direction is usually the length direction of the substrate.

[0100] In summary, embodiment 1 of the present invention provides a compensated alignment bonding method for an LED display panel. Before the first substrate and the second substrate are aligned and bonded, the bump array on the first substrate is aligned with the bump array on the second substrate, and the first substrate and the second substrate are heated to a certain temperature and then press-welded. The thermal expansion offset of the first substrate and the second substrate is obtained by measurement, and the lateral distance compensation is performed on each bump of the bump array on the first substrate or the second substrate based on the thermal expansion offset, so that the press-welding effect between the first substrate and the second substrate is better, the offset of the eutectic microstructure formed after the alignment bonding is reduced, the thermal stress of the eutectic microstructure is reduced, and the display quality of the LED display panel is improved.

[0101] Example 2

[0102] Embodiment 2 of the present invention provides a compensation alignment bonding method for an LED display panel, which includes: placing a first substrate on a heating platform, fixing a second substrate above the first substrate, and aligning the bump array on the first substrate with the bump array on the second substrate; heating the first substrate and the second substrate, and when heated to a preset temperature, press-welding the bump array on the first substrate and the bump array on the second substrate; cooling the first and second substrates after press-welding to room temperature, and measuring the thermal expansion offset of the bump array on the first substrate and the bump array on the second substrate at this time; and compensating the bump array on the first substrate or the second substrate based on the thermal expansion offset.

[0103] In an optional implementation of this embodiment, as Figure 7 As shown, Figure 7 A flow chart of a compensation alignment bonding method for an LED display panel in a second embodiment of the present invention is shown, comprising the following steps:

[0104] S701, placing a first substrate on a heating platform, fixing a second substrate above the first substrate, and aligning the bump array on the first substrate with the bump array on the second substrate;

[0105] In an optional implementation of this embodiment, the first substrate is a CMOS substrate, and the second substrate is a Micro LED substrate, or the first substrate is a Micro LED substrate, and the second substrate is a CMOS substrate, according to actual design requirements.

[0106] It should be noted that the thermal expansion coefficient of the first substrate is different from the thermal expansion coefficient of the second substrate, that is, the thermal expansion coefficient of the CMOS substrate is different from the thermal expansion coefficient of the Micro LED substrate.

[0107] In an optional implementation of this embodiment, a pressure-heated transfer head disposed above the heating platform absorbs the second substrate and fixes the second substrate above the first substrate.

[0108] In an optional implementation of this embodiment, as Figure 8 As shown, Figure 8 A flowchart of aligning the bump array on the first substrate with the bump array on the second substrate in the second embodiment of the present invention is shown, including the following steps:

[0109] S801, heating the first substrate, and when heated to a second preset temperature, obtaining a first substrate first offset of a bump array on the first substrate;

[0110] In an optional implementation of this embodiment, the second preset temperature is lower than the melting point temperature of the solder of the bump array provided on the first substrate, and the third preset temperature is lower than the melting point temperature of the solder on the bump array provided on the second substrate.

[0111] Specifically, a second preset temperature H is set, and the second preset temperature H is lower than the melting point temperature S of the solder of the bump array provided on the first substrate, that is, H<S.

[0112] Furthermore, a third preset temperature I is set, and the third preset temperature I is lower than the melting point temperature S of the solder of the bump array provided on the second substrate, that is, I<S.

[0113] In an optional implementation of this embodiment, as Figure 9 As shown, Figure 9 A flow chart of obtaining a first offset of a first substrate of a bump array on the first substrate in a second embodiment of the present invention is shown, including the following steps:

[0114] S901, measuring the distance between the center bump and the outermost bump in the bump array on the first substrate at room temperature;

[0115] In an optional implementation of this embodiment, the spacing distance a from the center bump to the outermost bump in the bump array on the first substrate is measured at room temperature.

[0116] S902, heating the first substrate to a second preset temperature, and measuring the distance between the center bump and the outermost bump in the bump array on the first substrate at the second preset temperature;

[0117] In an optional implementation of this embodiment, after the first substrate is heated to a second preset temperature H, a spacing distance b between a center bump and an outermost bump in the bump array on the first substrate at the second preset temperature H is measured.

[0118] S903: Compare the spacing distance between the center bump and the outermost bump in the bump array on the first substrate at the second preset temperature with the spacing distance between the center bump and the outermost bump in the bump array on the first substrate at room temperature to obtain a first offset of the first substrate.

[0119] In an optional implementation of this embodiment, the spacing distance b from the center bump to the outermost bump in the bump array on the first substrate at the second preset temperature is subtracted from the spacing distance a from the center bump to the outermost bump in the bump array on the first substrate at room temperature to obtain the first offset c of the first substrate, c=ba.

[0120] S802, heating the second substrate, observing the bump array on the second substrate, and stopping heating when the second substrate first offset of the bump array on the second substrate is equal to the first offset of the first substrate, and obtaining the temperature at this time as a third preset temperature;

[0121] In an optional implementation of this embodiment, as Figure 10 As shown, Figure 10 The flowchart of obtaining the third preset temperature in the second embodiment of the present invention is shown, including the following steps:

[0122] S1001, measuring the distance between the center bump and the outermost bump in the bump array on the second substrate at room temperature;

[0123] In an optional implementation of this embodiment, the spacing distance d between the center bump and the outermost bump in the bump array on the second substrate is measured at room temperature.

[0124] S1002, continuously heating the second substrate, measuring the distance between the center bump and the outermost bump in the bump array on the second substrate during the heating process, and comparing the distance between the center bump and the outermost bump in the bump array on the second substrate at room temperature to obtain a first offset of the second substrate;

[0125] In an optional implementation of this embodiment, the spacing distance e between the center bump and the outermost bump in the bump array on the second substrate during the heating process is measured and compared with the spacing distance d from the center bump to the outermost bump in the bump array on the second substrate at room temperature to obtain the first offset f of the second substrate, f=ed.

[0126] S1003 : When the first offset of the second substrate is equal to the first offset of the first substrate, stop heating, and obtain the temperature at this time as a third preset temperature.

[0127] In an optional implementation of this embodiment, when the first offset f of the second substrate is equal to the first offset c of the first substrate, that is, f=c, ba=ed, heating is stopped and the temperature at this time is obtained as a third preset temperature I.

[0128] S803 , fixing the second substrate above the first substrate, and aligning the bump array on the first substrate at the second preset temperature with the bump array on the second substrate at the third preset temperature.

[0129] In an optional implementation of this embodiment, the number and positions of bumps in the bump array on the first substrate are the same as the number and positions of bumps in the bump array on the second substrate. In this step, the bumps in the bump array on the first substrate at the second preset temperature are aligned with the bumps in the bump array on the second substrate at a third preset temperature.

[0130] S702, heating the first substrate and the second substrate, and when heated to a preset temperature, performing pressure welding on the bump array on the first substrate and the bump array on the second substrate;

[0131] In an optional implementation of this embodiment, the first substrate and the second substrate are heated, and after being heated to a fourth preset temperature, the bump array on the first substrate and the bump array on the second substrate are press-welded.

[0132] In an optional implementation of this embodiment, the fourth preset temperature is ≥ the melting point temperature of the solder on the bump array provided on the first substrate and the bump array provided on the second substrate*2-the second preset temperature-the third preset temperature.

[0133] Specifically, a fourth preset temperature J is set, wherein the fourth preset temperature J≥the melting point temperature S*2 of the solder on the bump array on the first substrate and the bump array on the second substrate-the second preset temperature H-the third preset temperature I, that is, J≥2S-HI.

[0134] In an optional implementation of this embodiment, after the first substrate and the second substrate are heated to a fourth preset temperature, the solder points on the bump array provided on the first substrate and the bump array provided on the second substrate are melted, and after the bumps of the bump array on the first substrate are aligned one-to-one with the bumps of the bump array on the second substrate, press welding is performed.

[0135] S703, cooling the first substrate and the second substrate after the press welding to room temperature, and measuring the thermal expansion offset of the bump array on the first substrate and the bump array on the second substrate;

[0136] In an optional implementation of this embodiment, after the press-welding is completed, the press-welded first substrate and the second substrate are cooled to room temperature.

[0137] In an optional implementation of this embodiment, as Figure 11 As shown, Figure 11 A flow chart of measuring the thermal expansion offset of a bump array on a first substrate and a bump array on a second substrate in a second embodiment of the present invention is shown, including the following steps:

[0138] S1101, measuring the maximum offset distance between the spacing distance from the center bump to the outermost bump in the bump array on the first substrate and the spacing distance from the center bump to the outermost bump in the bump array on the second substrate;

[0139] In an optional implementation of this embodiment, as Figure 12 As shown, Figure 12 A schematic diagram of the compensation alignment spacing structure of the LED display panel in the second embodiment of the present invention is shown.

[0140] In an optional implementation of this embodiment, the first substrate 1 includes a silicon substrate 11, a plurality of solder pads 12 arranged on the silicon substrate 11, and bumps arranged on the solder pads 12, which form a bump array of the first substrate 1, including the first bumps 13 at the extreme edges on the left and right sides and the second bump 14 in the center.

[0141] In an optional implementation of this embodiment, the second substrate 2 includes a sapphire substrate 21, a buffer layer 22, an N-type layer 23, and a plurality of bumps arranged on the N-type layer 23, which form a bump array of the second substrate 2, including third bumps 24 at the extreme edges on the left and right sides and a fourth bump 25 in the center.

[0142] In an optional implementation of this embodiment, the bump array on the second substrate 2 is composed of P-pole bumps located in the center array and N-pole bumps located in the periphery. Figure 12 In the structure shown, the third bumps 24 at the extreme edges on the left and right sides are N-pole bumps, and the remaining bumps, including the fourth bump 25 at the center, are P-pole bumps.

[0143] In an optional implementation of this embodiment, the N-pole bump has two structures.

[0144] Specifically, such as Figure 13 As shown, Figure 13 FIG. 1 shows a first structural diagram of the N-pole bump of the second substrate in the second embodiment of the present invention. Figure 13 That is Figure 12 In the enlarged view at point a, the N-pole convex point includes a light-emitting layer 34, a P-type layer 33, an electrode layer 32, and an electrical connection layer 31, wherein the light-emitting layer 34, the P-type layer 33, and the electrode layer 32 are arranged in sequence from top to bottom, and the electrical connection layer 31 is arranged on the side of the electrode layer 32, extending along the sides of the electrode layer 32, the P-type layer 33, and the light-emitting layer 34, and contacting the N-type layer 23.

[0145] More, such as Figure 14 As shown, Figure 14 FIG2 shows a second structure diagram of the N-pole bump of the second substrate in the first embodiment of the present invention. Figure 14 That is Figure 12 In the enlarged view at a, the N-pole bump only includes the electrode layer 32. Figure 14 The electrode layer 32 in Figure 13 The electrode layer 32 in the same material has the same function. Figure 14 The height of the electrode layer 32 is Figure 13 The stacking heights of the middle light emitting layer 34 , the P-type layer 33 , and the electrode layer 32 are consistent.

[0146] In an optional implementation of this embodiment, as Figure 15 As shown, Figure 15 FIG. 1 shows a P-pole bump structure diagram of the first substrate in the second embodiment of the present invention. Figure 15 That is Figure 12In the enlarged view at b, the P-pole convex point includes a light-emitting layer 37, a P-type layer 36, and an electrode layer 35. The light-emitting layer 37, the P-type layer 36, the electrode layer 35 and Figure 13 The light-emitting layer 34, the P-type layer 33, and the electrode layer 32 of the middle N-pole bump are made of the same material, have the same height, and achieve the same function.

[0147] In an optional implementation of this embodiment, the maximum offset distance E of the spacing distance between the second bump 14 at the center of the bump array on the first substrate 1 and the first bump 13 at the outermost edge and the spacing distance between the fourth bump 25 at the center of the bump array on the second substrate 2 and the third bump 24 at the outermost edge is measured.

[0148] It should be noted that the convex point on the left edge or the convex point on the right edge can be selected.

[0149] S1102, obtaining the number of intervals from the center bump to the outermost bump in the bump array on the first substrate, and calculating a unit interval offset distance based on the maximum offset distance and the number of intervals;

[0150] In an optional implementation of this embodiment, the number n of intervals from the second bump 14 at the center to the first bump 13 at the outermost edge of the bump array on the first substrate is obtained, and the unit interval offset distance l is calculated based on the maximum offset distance E and the number n of intervals, using the following formula:

[0151]

[0152] Where l is the unit interval offset distance, E is the maximum offset distance, and n is the number of intervals.

[0153] Specifically, in Figure 10 In the embodiment, the number of intervals between the second bumps 14 and the first bumps 13 is 3.

[0154] It should be noted that, according to the linear expansion coefficient formula α=ΔL / (L*ΔT), under the same temperature and material conditions, the linear expansion in the lateral direction is proportional to the linear body size. Since an object usually expands from the center to the surrounding area when thermal expansion occurs, it expands to both sides in the lateral direction. Since the spacing distances between adjacent bumps in the bump array provided on the first substrate are the same, the offset distance from the center bump to the outermost bump is proportional to the number of spacings, and the ratio is the unit spacing offset distance.

[0155] S1103, calculating the offset distance of the corresponding bump based on the number of intervals between each bump and the central bump in the bump array on the first substrate and the unit interval offset distance.

[0156] In an optional implementation of this embodiment, the offset distances that each bump needs to be offset to both sides are calculated based on the number of intervals between each bump and the central bump in the bump array on the first substrate and the unit interval offset distance.

[0157] Specifically, the number of intervals between the bumps of the bump array on the first substrate, such as the first bump 13 at the outermost edge and the second bump 14 at the center, is 3, and the offset distance E3 of the first bump 13 at the outermost edge is l*3.

[0158] S704: Compensate the bump array on the first substrate or the second substrate based on the thermal expansion offset.

[0159] In an optional implementation of this embodiment, based on the offset distance corresponding to each bump in the bump array on the first substrate calculated in step S1103, offset compensation is performed on each bump in the bump array on the first substrate.

[0160] Specifically, according to the offset distance corresponding to each convex point, the convex point is moved in a corresponding direction by the corresponding offset distance to complete the offset compensation, where the direction is the direction away from the central convex point.

[0161] It should be noted that, in this embodiment, the compensation operation is preferably performed on the first substrate, and in practical applications, the compensation operation may also be performed on the second substrate.

[0162] It should be noted that since the first substrate and the second substrate are both rectangular in shape, and thermal expansion has a greater impact on the length direction of the substrate and a smaller impact on the width direction of the substrate, in this embodiment, the offset compensation direction is usually the length direction of the substrate.

[0163] It should be noted that, considering that the materials of the first substrate and the second substrate are different and their specific heat capacities are different, if heating is started from room temperature, the speed of the thermal expansion process of the two is different, which affects the subsequent welding efficiency. In this embodiment, the first substrate is first heated to a second preset temperature, which is lower than the melting point of the solder but is relatively close. The second substrate is then heated to a third preset temperature, so that the bump arrays of the first substrate at the second preset temperature and the second substrate at the third preset temperature are also one-to-one corresponding to those at room temperature. The first substrate and the second substrate are then heated to a fourth preset temperature and then press-welded. This can improve the overall efficiency.

[0164] In summary, the second embodiment of the present invention provides a compensation alignment bonding method for an LED display panel. Before the first substrate and the second substrate are aligned and bonded, the bump array on the first substrate is aligned with the bump array on the second substrate, and the first substrate and the second substrate are heated to a certain temperature and then press-welded. The thermal expansion offset of the first substrate and the second substrate is obtained by measuring, and the lateral distance compensation is performed on each bump in the bump array on the first substrate or the second substrate based on the thermal expansion offset, so that the press-welding effect between the first substrate and the second substrate is better, and the eutectic formed after the alignment bonding is reduced. The offset of the microstructure is reduced, the thermal stress of the eutectic microstructure is reduced, and the display quality of the LED display panel is improved; in addition, the bump array on the first substrate is aligned with the bump array on the second substrate, the first substrate is heated to a second preset temperature, and the second substrate is heated to a third preset temperature, so that the bump array of the first substrate at the second preset temperature and the bump array of the second substrate at the third preset temperature can be aligned, and then the first substrate and the second substrate are heated to a fourth preset temperature and then press-welded, so as to avoid affecting the subsequent press-welding efficiency due to the difference in thermal expansion coefficients between the two, thereby improving the overall efficiency.

[0165] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0166] In addition, the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A compensation alignment bonding method for an LED display panel, characterized in that: The compensation alignment bonding method of the LED display panel includes: Placing a first substrate on a heating platform, fixing a second substrate above the first substrate, and aligning the bump array on the first substrate with the bump array on the second substrate; The aligning the bump array on the first substrate with the bump array on the second substrate includes: heating the first substrate, and when heated to a second preset temperature, obtaining a first substrate first offset of the bump array on the first substrate; heating the second substrate, observing the bump array on the second substrate, and when the second substrate first offset of the bump array on the second substrate is equal to the first substrate first offset, stopping heating and obtaining a temperature at this time as a third preset temperature; fixing the second substrate above the first substrate, and aligning the bump array on the first substrate at the second preset temperature with the bump array on the second substrate at the third preset temperature; heating the first substrate and the second substrate, and when heated to a preset temperature, performing pressure welding on the bump array on the first substrate and the bump array on the second substrate; Cooling the first and second substrates after press welding to room temperature, and measuring the thermal expansion offset of the bump array on the first substrate and the bump array on the second substrate; The bump array on the first substrate or the second substrate is compensated based on the thermal expansion offset.

2. The compensation alignment bonding method of the LED display panel according to claim 1, wherein: The step of fixing the second substrate on top of the first substrate comprises: The second substrate is sucked by a pressure-heated transfer head disposed above the heating platform to fix the second substrate above the first substrate.

3. The compensation alignment bonding method of the LED display panel according to claim 1, wherein: The second preset temperature is lower than the melting point of the solder of the bump array disposed on the first substrate, and the third preset temperature is lower than the melting point of the solder on the bump array disposed on the second substrate.

4. The compensation alignment bonding method of the LED display panel according to claim 1, wherein: The step of heating the first substrate to a second preset temperature and obtaining a first offset of the first substrate of the bump array on the first substrate comprises: Measuring the spacing distance between the center bump and the outermost bump in the bump array on the first substrate at room temperature; Heating the first substrate to a second preset temperature, and measuring the distance between a center bump and an outermost bump in the bump array on the first substrate at the second preset temperature; The spacing distance between the center bump and the outermost bump in the bump array on the first substrate at the second preset temperature is compared with the spacing distance between the center bump and the outermost bump in the bump array on the first substrate at room temperature to obtain a first offset of the first substrate.

5. The compensation alignment bonding method of the LED display panel according to claim 1, wherein: The step of heating the second substrate, observing the bump array on the second substrate, and stopping heating when the second substrate first offset of the bump array on the second substrate is equal to the first substrate first offset, and obtaining the temperature at this time as a third preset temperature includes: Measuring the spacing distance between the center bump and the outermost bump in the bump array on the second substrate at room temperature; Continuously heating the second substrate, measuring the distance between the center bump and the outermost bump in the bump array on the second substrate during the heating process, and comparing the distance between the center bump and the outermost bump in the bump array on the second substrate at room temperature to obtain a first offset of the second substrate; When the first offset of the second substrate is equal to the first offset of the first substrate, heating is stopped, and the temperature at this time is obtained as a third preset temperature.

6. The compensation alignment bonding method of the LED display panel according to claim 1, wherein: The step of heating the first substrate and the second substrate and, after heating to a preset temperature, performing pressure welding on the bump array on the first substrate and the bump array on the second substrate further comprises: The first substrate and the second substrate are heated, and when heated to a fourth preset temperature, the bump array on the first substrate and the bump array on the second substrate are press-welded.

7. The compensation alignment bonding method of the LED display panel according to claim 6, wherein: The fourth preset temperature is ≥ the melting point temperature of the solder on the bump array provided on the first substrate and the bump array provided on the second substrate*2-the second preset temperature-the third preset temperature.

8. The compensation alignment bonding method of an LED display panel according to claim 1, wherein: The measuring of the thermal expansion offset of the bump array on the first substrate and the bump array on the second substrate comprises: Measuring the maximum offset distance between the spacing distance between the center bump and the outermost bump in the bump array on the first substrate and the spacing distance between the center bump and the outermost bump in the bump array on the second substrate; Obtaining the number of intervals from a central bump to an outermost bump in the bump array on the first substrate, and calculating a unit interval offset distance based on the maximum offset distance and the number of intervals; The offset distance of the corresponding bump is calculated based on the number of intervals between each bump and the central bump in the bump array on the first substrate and the unit interval offset distance.

9. The compensation alignment bonding method of an LED display panel according to claim 8, wherein: The compensating the bump array on the first substrate or the second substrate based on the thermal expansion offset comprises: Offset compensation is performed on each bump in the bump array on the first substrate or the second substrate based on the offset distance of the corresponding bump.

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