A full-cycle soft-switching operation method for a heterogeneous device hybrid DAB topology

Abstract

The present invention discloses a heterogeneous device hybrid DAB topology and a full-cycle soft-switching operation method. The topology includes: an input-side bridge arm group, a transformer group, and an output-side bridge arm group. The full-cycle soft-switching operation method of the topology includes: an energy forward transmission state and an energy reverse transmission state. The present invention can realize soft switching of all switching tubes, and adopts Si IGBTs at the ZCS switch and SiC MOSFETs at the ZVS switch, completely eliminating switching losses during the HDH-DAB operation process and maximizing the operating efficiency of the HDH-DAB. In addition, the present invention adopts anti-parallel IGBT devices in the output-side bridge arm group, so that the HDH-DAB has the ability of bidirectional energy transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and in particular to a full-cycle soft switching operation method of a heterogeneous device hybrid DAB topology. Background Art

[0002] Double Active Bridge (DAB) is widely used in DC microgrids, solid-state transformers, energy storage systems and other fields due to its inherent advantages such as zero voltage turn-on, current isolation and bidirectional energy flow.

[0003] Existing DABs mainly use Si-based insulated-gate bipolar transistors (IGBTs) or SiC-based metal-oxide semiconductor field-effect transistors (MOSFETs).

[0004] The topology of traditional DAB is as follows Figure 1 As shown in Figure 1, common modulation methods include single phase shift (SPS), extended phase shift (EPS), double phase shift (DPS), and triple phase shift (TPS). SPS is widely used due to its simple operation. However, when the converter is lightly loaded or when there is a mismatch between the input and output voltages, SPS can experience soft switching loss, significantly reducing converter efficiency. Furthermore, due to the presence of tail current during the turn-off process of Si IGBTs, their turn-off time is longer than their turn-on time, and turn-off losses are greater than turn-on losses. Zero current switching (ZCS) can reduce IGBT switching losses while increasing IGBT switching speed. If ZCS can be achieved, the switching frequency of IGBT-based DABs can be further increased, thereby improving their power density. With the deepening of wide-bandgap semiconductor research and the development of its manufacturing process, a new generation of wide-bandgap semiconductor devices, represented by SiC-based metal-oxide semiconductor field-effect transistors (MOSFETs), has become commercialized. Compared to Si IGBTs, ZVS is more suitable for SiC MOSFETs, which have larger parasitic capacitances.

[0005] There are two DC converter structures that can achieve ZCS: Figure 2 As shown, Figure 2 (a) is the first solution: the two transformer primaries are connected to different full-bridge ports, and a small power converter is used to adjust the main power converter current waveform. This solution can achieve soft switching of the main power converter over the full load range, but the small power converter cannot achieve soft switching of all components and the number of converter switches is large. Figure 2 (b) is the second solution: the main and auxiliary power full bridges are integrated through bridge arm reuse, and capacitors are connected in parallel at both ends of the auxiliary power bridge arm switch tube, achieving a reduction in the number of switch tubes and soft switching of all switch tubes within the full load range. It can be seen that both solutions in the figure use an uncontrolled rectifier bridge composed of diodes on the secondary side of the transformer. Neither can achieve bidirectional energy transmission and cannot be used in bidirectional energy flow scenarios such as power electronic transformers. Summary of the Invention

[0006] In view of this, the present invention provides a full-cycle soft switching operation method for a heterogeneous device hybrid DAB topology, which is used to at least solve the problems of low DAB operation efficiency and inability to achieve bidirectional energy transmission in the prior art.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A heterogeneous device hybrid DAB topology includes: an input side bridge arm group, a transformer group, and an output side bridge arm group;

[0009] The input side bridge arm includes the input capacitor bridge arm, the main power bridge arm and the auxiliary power bridge arm. The input voltage V in The positive and negative electrodes are connected to the two ends of the input capacitor bridge arm, the main power bridge arm and the auxiliary power bridge arm respectively, wherein the input capacitor bridge arm includes the input capacitor C i1 and C i2 , C i1 The negative electrode and C i2 The node formed by the positive electrodes is point B. The main power bridge arm includes IGBTs Q1 and Q2 connected in series, and Q1 and Q2 contain anti-parallel diodes. The emitter of Q1 is connected to the collector of Q2 to form a node at point A. The auxiliary power bridge arm includes MOSFETs Q3 and Q4 connected in series. The source of Q3 and the drain of Q4 are connected to form a node at point C.

[0010] The transformer group includes the main power transformer T r1 , auxiliary power transformer T r2 and transmission inductance L, T r1 The positive electrode of the primary side is connected to one end of the transmission inductor L, T r1 The primary negative electrode is connected to point B; T r2 The positive electrode of the primary side is connected to the other end of L and point A respectively, T r2 The primary negative electrode is connected to point C; T r1 The secondary negative electrode and Tr2 The secondary side positive pole is connected;

[0011] The output side bridge arm group includes 4 IGBT groups and output capacitor C o Each IGBT group includes two anti-parallel IGBTs, where the forward IGBTs in the first to fourth IGBT groups are S 11 、S 21 、S 31 and S 41 , reverse IGBT is S 12 、S 22 、S 32 and S 42 ;

[0012] The node where the emitter of the forward IGBT and the collector of the reverse IGBT in each IGBT group are connected is used as the first common terminal, the node where the collector of the forward IGBT and the emitter of the reverse IGBT are connected is used as the second common terminal, and the node where the first common terminal of the first IGBT group and the second common terminal of the second IGBT group are connected is connected to T r1 The secondary positive electrode, the node where the second common terminal of the first IGBT group and the second common terminal of the third IGBT group are connected is connected to C o The positive electrode of the third IGBT group and the node where the first common terminal of the third IGBT group and the second common terminal of the fourth IGBT group are connected are connected to T r2 The node where the first common terminal of the second IGBT group and the first common terminal of the fourth IGBT group are connected is connected to C o The negative electrode, C o The positive and negative poles are used as the output voltage V o The positive and negative poles.

[0013] Preferably, in the input side bridge arm group, the collector of Q1 is connected to C i1 The positive electrode of Q2 is connected to the positive electrode of Q3 and the drain of Q3, and the emitter of Q2 is connected to C i2 The cathode of Q4 is connected to the source of Q4.

[0014] Preferably, in the first IGBT group, S 11 The collector and S 12 The emitter is connected to S 11 The emitter and S 12 In the second IGBT group, S 21 The collector and S 22 The emitter is connected to S 21 The emitter and S 22 The collector of the third IGBT group is connected; in the third IGBT group, S 31 The collector and S 32 The emitter is connected to S 31The emitter and S 32 In the fourth IGBT group, S 41 The collector and S 42 The emitter is connected to S 41 The emitter and S 42 The collector is connected;

[0015] S 11 Emitter and S 12 The junction formed by the collector and S 21 Collector and S 22 The emitter forms a junction connected to the T r1 The secondary side positive pole is connected;

[0016] S 31 Emitter and S 32 The junction formed by the collector and S 41 Collector and S 42 The emitter forms a junction connected to the T r2 The secondary negative terminal is connected;

[0017] S 11 Collector and S 12 The emitter forms a junction, S 31 Collector and S 32 The emitter forms a junction with the output capacitor C O The positive pole is connected and connected to the positive pole of the output voltage;

[0018] S 21 Emitter and S 22 The junction formed by the collector, S 41 Emitter and S 42 The junction formed by the collector and the output capacitor C O The negative pole is connected to the negative pole of the output voltage.

[0019] A full-cycle soft switching operation method for a heterogeneous device hybrid DAB topology, including: an energy forward transmission state and an energy reverse transmission state;

[0020] In the forward energy transfer state, the first half cycle is divided into forward mode 1, forward mode 2, and forward mode 3; the second half cycle is symmetrical to the first half cycle;

[0021] The time period [t0, t1) is positive mode 1, at time t0, Q1 and S 12 、S 42 and Q4 to achieve ZCS conduction, Q2, S 22 and S 32 To achieve ZCS shutdown, the current i1 flows through Q1, L, and T in the time period t0-t1. r1 Primary side, C i1And i1 is in increasing state, current i2 flows through Q1, T r2 Primary side, Q4, C i2 、C i1 ; Where: t0 is the moment when the current half cycle starts;

[0022] The period [t1, t2) is the forward mode 2, the current i1 is in a decreasing state, Q4 realizes ZVS shutdown at t1, Q1, S 12 and S 42 Keep conducting, i2 charges the parasitic capacitance of Q4 and discharges the parasitic capacitance of Q3; when the voltage across the parasitic capacitance of Q3 is less than 0, the body diode of Q3 is turned on, and i2 flows through the body diode of Q3;

[0023] The time period [t2, t3] is forward mode 3, the current i1 remains unchanged, the body diode of Q3 is turned off at t2, the voltage across the parasitic capacitor of Q3 is 0, and the voltage across the parasitic capacitor of Q4 is V in , the current in the converter is kept at 0, by C O Supply power to the load, S 12 and S 42 Turn on; at t3, the positive half cycle ends, Q1, S 12 、S 42 To achieve ZCS shutdown, Q2, S 22 、S 32 Achieve ZCS conduction, Q3 achieves ZVZCS conduction;

[0024] In the reverse energy transfer state, each half cycle is divided into reverse mode 1, reverse mode 2 and reverse mode 3;

[0025] The time period [t0, t1) is reverse mode 1: Q1, S 11 、S 41 and Q3 to achieve ZCS conduction, Q2, S 21 and S 31 Achieve ZCS shutdown; current i1 flows through Q1 anti-parallel diode, C i1 、T r1 The primary side and L and i1 are in decreasing state, current i2 flows through Q1 anti-parallel diode, Q3 and T r2 original edge;

[0026] The period [t1, t2) is reverse mode 2: at t1, Q3 realizes ZVS shutdown, i2 charges the parasitic capacitance of Q3 and discharges the parasitic capacitance of Q4. When the voltage across the parasitic capacitance of Q4 is less than 0, the body diode of Q4 is turned on, and i2 flows through the body diode of Q4. The current i1 flows through the anti-parallel diode of Q1, C i1 、T r1The primary side and L and i1 are in increasing state, the current i2 flows through the anti-parallel diode Q1, C i1 、C i2 , Q4 body diode and T r2 original edge;

[0027] The period [t2, t3] is reverse mode 3: at t2, the Q4 body diode is naturally turned off, the voltage across the Q4 parasitic capacitor is 0, and the voltage across the Q3 parasitic capacitor is V in , the current in the converter is kept at 0, by the capacitor C i1 、C i2 Supply power to the load; at t3, the positive half cycle ends, Q1, S 11 and S 41 To achieve ZCS shutdown, Q2, S 21 and S 31 Achieve ZCS conduction, Q4 achieves ZVZCS conduction.

[0028] Preferably, in forward mode 1, the voltage across L is:

[0029] v L (t) = V in / 2-V O / N1+V in N2 / N1 (1)

[0030] Among them, N1 and N2 are T r1 、T r2 The ratio of the secondary winding turns to the primary winding turns;

[0031] The inductor current is:

[0032]

[0033] The output current is:

[0034] i O =i1(t) / N1 (3)

[0035] In forward mode 2, the voltage across L is:

[0036] v L (t) = V in / 2-V O / N1 (4)

[0037] The inductor current is:

[0038]

[0039] Preferably, in reverse mode 1, the voltage across L is:

[0040] v L(t) = V in / 2-V O / N1 (6)

[0041] The inductor current is:

[0042]

[0043] Output current:

[0044] i O (t)=-N1i1(t) (8)

[0045] In this mode, the voltage across the inductor is:

[0046] v L (t) = V in / 2-V O / N1+V in N2 / N1 (9)

[0047] The inductor current is:

[0048]

[0049] It can be seen from the above technical solution that, compared with the prior art, the present invention discloses a full-cycle soft switching operation method for a heterogeneous device hybrid DAB topology, which has the following beneficial effects:

[0050] (1) The HDH-DAB topology disclosed in the present invention can achieve soft switching of all switch tubes, and adopts Si IGBT at the ZCS switch and SiC MOSFET at the ZVS switch, which completely eliminates the switching loss during the operation of the HDH-DAB and maximizes the operating efficiency of the HDH-DAB;

[0051] (2) By using anti-parallel IGBT devices in the output side bridge arm group, HDH-DAB has the ability to transmit energy in both directions. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0053] Figure 1 This is a schematic diagram of the traditional DAB topology;

[0054] Figure 2Schematic diagram of existing ZCS DC conversion topology; (a) is scheme 1; (b) is scheme 2;

[0055] Figure 3 Schematic diagram of the HDH-DAB topology provided by the present invention;

[0056] Figure 4 The energy forward transmission waveform provided by the present invention;

[0057] Figure 5 A schematic diagram of the current path in forward transmission mode 1 provided by the present invention;

[0058] Figure 6 A schematic diagram of the current path in forward transmission mode 2 provided by the present invention;

[0059] Figure 7 A schematic diagram of the current path in forward transmission mode 3 provided by the present invention;

[0060] Figure 8 The energy reverse transmission waveform provided by the present invention;

[0061] Figure 9 A schematic diagram of the reference direction of the HDH-DAB energy reverse transmission current provided by the present invention;

[0062] Figure 10 A schematic diagram of the current path in reverse transmission mode 1 provided by the present invention;

[0063] Figure 11 A schematic diagram of the current path in reverse transmission mode 2 provided by the present invention;

[0064] Figure 12 A schematic diagram of the current path in reverse transmission mode 3 provided by the present invention;

[0065] Figure 13 Output current waveform diagram provided by an embodiment of the present invention;

[0066] Figure 14 A block diagram of closed-loop control of forward energy transmission provided by an embodiment of the present invention;

[0067] Figure 15 A block diagram of closed-loop control of reverse energy transmission provided by an embodiment of the present invention;

[0068] Figure 16 Output voltage waveform diagram under forward energy transmission provided by an embodiment of the present invention;

[0069] Figure 17 The inductor current waveform diagram under forward energy transmission provided by the embodiment of the present invention;

[0070] Figure 18The voltage and current waveforms of Q1 provided in the embodiment of the present invention;

[0071] Figure 19 The voltage and current waveforms of Q3 provided by the embodiment of the present invention;

[0072] Figure 20 The S provided in the embodiment of the present invention 11 Voltage and current waveforms;

[0073] Figure 21 Output voltage waveform diagram under reverse energy transmission provided by an embodiment of the present invention;

[0074] Figure 22 The inductor current waveform diagram under reverse energy transmission provided by the embodiment of the present invention;

[0075] Figure 23 This is a diagram showing the voltage and current waveforms of Q1 during reverse energy transmission according to an embodiment of the present invention;

[0076] Figure 24 This is a diagram showing the voltage and current waveforms of Q3 under reverse energy transmission according to an embodiment of the present invention;

[0077] Figure 25 The energy reverse transmission provided by the embodiment of the present invention is S 11 Voltage and current waveforms. DETAILED DESCRIPTION

[0078] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0079] The present invention proposes a heterogeneous device hybrid DAB (HDH-DAB) topology, such as Figure 3 As shown, it includes: an input side bridge arm group, a transformer group and an output side bridge arm group;

[0080] The input side bridge arm includes the input capacitor bridge arm, the main power bridge arm and the auxiliary power bridge arm. The input voltage V in The positive and negative electrodes are connected to the two ends of the input capacitor bridge arm, the main power bridge arm and the auxiliary power bridge arm respectively, wherein the input capacitor bridge arm includes the input capacitor C i1 and C i2 , C i1 The negative electrode and C i2The node formed by the positive electrodes is point B. The main power bridge arm includes IGBTs Q1 and Q2 connected in series, and Q1 and Q2 contain anti-parallel diodes. The emitter of Q1 is connected to the collector of Q2 to form a node at point A. The auxiliary power bridge arm includes MOSFETs Q3 and Q4 connected in series. The source of Q3 and the drain of Q4 are connected to form a node at point C.

[0081] The transformer group includes the main power transformer T r1 , auxiliary power transformer T r2 and transmission inductance L, T r1 The positive electrode of the primary side is connected to one end of the transmission inductor L, T r1 The primary negative electrode is connected to point B; T r2 The positive electrode of the primary side is connected to the other end of L and point A respectively, T r2 The primary negative electrode is connected to point C; T r1 The secondary negative electrode and T r2 The secondary side positive pole is connected;

[0082] The output side bridge arm group includes 4 IGBT groups and output capacitor C o Each IGBT group includes two anti-parallel IGBTs, where the forward IGBTs in the first to fourth IGBT groups are S 11 、S 21 、S 31 and S 41 , reverse IGBT is S 12 、S 22 、S 32 and S 42 ;

[0083] The node where the emitter of the forward IGBT and the collector of the reverse IGBT in each IGBT group are connected is used as the first common terminal, the node where the collector of the forward IGBT and the emitter of the reverse IGBT are connected is used as the second common terminal, and the node where the first common terminal of the first IGBT group and the second common terminal of the second IGBT group are connected is connected to T r1 The secondary positive electrode, the node where the second common terminal of the first IGBT group and the second common terminal of the third IGBT group are connected is connected to C o The positive electrode of the third IGBT group and the node where the first common terminal of the third IGBT group and the second common terminal of the fourth IGBT group are connected are connected to T r2 The node where the first common terminal of the second IGBT group and the first common terminal of the fourth IGBT group are connected is connected to C o The negative electrode, C o The positive and negative poles are used as the output voltage V o The positive and negative poles.

[0084] In order to further implement the above technical solution, in the input side bridge arm group, the collector of Q1 is connected to C i1 The positive electrode of Q2 is connected to the positive electrode of Q3 and the drain of Q3, and the emitter of Q2 is connected to C i2 The cathode of Q4 is connected to the source of Q4.

[0085] In order to further implement the above technical solution, in the first IGBT group, S 11 The collector and S 12 The emitter is connected to S 11 The emitter and S 12 In the second IGBT group, S 21 The collector and S 22 The emitter is connected to S 21 The emitter and S 22 The collector of the third IGBT group is connected; in the third IGBT group, S 31 The collector and S 32 The emitter is connected to S 31 The emitter and S 32 In the fourth IGBT group, S 41 The collector and S 42 The emitter is connected to S 41 The emitter and S 42 The collector is connected;

[0086] S 11 Emitter and S 12 The junction formed by the collector and S 21 Collector and S 22 The emitter forms a junction connected to the T r1 The secondary side positive pole is connected;

[0087] S 31 Emitter and S 32 The junction formed by the collector and S 41 Collector and S 42 The emitter forms a junction connected to the T r2 The secondary negative terminal is connected;

[0088] S 11 Collector and S 12 The emitter forms a junction, S 31 Collector and S 32 The emitter forms a junction with the output capacitor C O The positive pole is connected and connected to the positive pole of the output voltage;

[0089] S 21 Emitter and S 22 The junction formed by the collector, S 41 Emitter and S 42The junction formed by the collector and the output capacitor C O The negative pole is connected to the negative pole of the output voltage.

[0090] A full-cycle soft switching operation method for a heterogeneous device hybrid DAB topology, including: an energy forward transmission state and an energy reverse transmission state;

[0091] The waveform of HDH-DAB in the forward energy transmission state is as follows Figure 4 As shown. When energy is transferred in the forward direction, the secondary side S 11 、S 21 、S 31 、S 41 In the forward energy transfer state, the first half cycle is divided into forward mode 1, forward mode 2 and forward mode 3;

[0092] The period [t0, t1) is the forward mode 1. At t0, Q1 is turned on, Q2 is turned off, and S 12 、S 42 conduction, S 22 、S 32 Since there is no current flowing in the converter before time t0, Q1 and S 12 、S 42 , Q4 is ZCS conduction, Q2, S 22 、S 32 It is ZCS shutdown. Where: t0 is the moment when the current half cycle starts; current i1 flows through Q1, L, T r1 Primary side, C i1 And i1 is in increasing state, current i2 flows through Q1, T r2 Primary side, Q4, C i2 、C i1 ,like Figure 5 shown.

[0093] The time period [t1, t2) is the forward mode 2. At t1, Q4 is turned off, i2 charges the parasitic capacitance of Q4, and discharges the parasitic capacitance of Q3. Since the voltage across the capacitor cannot change suddenly, Q4 can achieve ZVS shutdown. When the voltage across the parasitic capacitance of Q3 is less than 0, the body diode of Q3 is turned on, and i2 flows through the body diode of Q3. Since i2 is large at t1, the parasitic capacitance charging and discharging time is very short and can be ignored. Current i1 flows through Q1, L, and T in sequence. r1 Primary side, C i1 And i1 is in a decreasing state, current i2 flows through Q1, T r2 Primary side, Q3 body diode, such as Figure 6 shown.

[0094] The time period [t2, t3] is forward mode 3. At t2, the current in the converter decays to 0, and the Q3 body diode is naturally turned off. At this time, the voltage across the parasitic capacitor of Q3 is 0, and the voltage across the parasitic capacitor of Q4 is V in Due to the single-phase current-carrying characteristics of the output side full bridge, the current in the converter remains at 0, and the output side capacitor C O Supply power to the load. At t3, the positive half cycle ends, Q1, S 12 、S 42 Turn off, Q2, Q3, S 22 、S 32 Since L limits the rapid rise of the current in the converter, the current in the converter remains at 0 when the switch tube switches. 12 、S 42 Achieve ZCS shutdown, Q2, Q3, S 22 、S 32 In addition, since the voltage across Q3 is 0, Q3 actually achieves ZVZCS conduction. Figure 7 shown.

[0095] The waveform of HDH-DAB in reverse energy transmission state is as follows Figure 8 As shown, the current i in and i o The reference direction is Figure 9 As shown. When energy is transferred in the reverse direction, S 12 、S 22 、S 32 、S 42 In the reverse energy transfer state, each half cycle is divided into reverse mode 1, reverse mode 2 and reverse mode 3;

[0096] The time period [t0, t1) is reverse mode 1: t0 is the moment when a cycle starts. At this moment, Q1 is turned on, Q2 is turned off, and S 11 、S 41 conduction, S 21 、S 31 Since there is no current flowing in the converter before t0, Q1 and S 11 、S 41 , Q3 is ZCS conduction, Q2, S 21 、S 31 It is ZCS shutdown. Current i1 flows through Q1 anti-parallel diode, C i1 、T r1 The primary side, L and i1 are in decreasing state, current i2 flows through Q1 anti-parallel diode, Q3, T r2 The modal current path is as follows Figure 10 shown.

[0097] The time period [t1, t2) is reverse mode 2: Q3 is turned off at t1, i2 charges the parasitic capacitance of Q3 and discharges the parasitic capacitance of Q4. Since the voltage across the capacitor cannot change suddenly, Q3 can achieve ZVS shutdown. When the voltage across the parasitic capacitance of Q4 is less than 0, the body diode of Q4 is turned on and i2 flows through the body diode of Q4. Since i2 is large at t1, the parasitic capacitance charging and discharging time is very short and can be ignored. Current i1 flows through the anti-parallel diode of Q1, C i1 、T r1 The primary side, L and i1 are in increasing state, and the current i2 flows through the anti-parallel diode Q1, C i1 、C i2 , Q4 body diode, T r2 Original edge, such as Figure 11 shown.

[0098] The time period [t2, t3] is reverse mode 3: At t2, the current in the converter decays to 0, and the Q4 body diode is naturally turned off. At this time, the voltage across the parasitic capacitor of Q4 is 0, and the voltage across the parasitic capacitor of Q3 is V in Due to the single-phase current flow characteristics of the full bridge on the output side, the current in the converter remains at 0, and the capacitor C i1 、C i2 Supply power to the load. At t3, the positive half cycle ends, Q1, S 11 、S 41 Turn off, Q2, Q4, S 21 、S 31 Since L limits the rapid rise of the current in the converter, the current in the converter remains at 0 when the switch tube switches. 11 、S 41 Achieve ZCS shutdown, Q2, Q4, S 21 、S 31 In addition, since the voltage across Q4 is 0, Q4 actually achieves ZVZCS conduction. Figure 12 shown.

[0099] It should be noted that:

[0100] The trigger signal of the switch tube in the first half cycle is as follows Figure 4As shown, the first and second half cycles are symmetrical. In the first half cycle, the primary side is coordinated by the body diodes of Q1, Q4, and Q3, and the secondary side is coordinated by S12 and S42; in the second half cycle, the primary side is coordinated by the body diodes of Q2, Q3, and Q4, and the secondary side is coordinated by S22 and S32. The soft switching of Q1 in the first half cycle is the same as that of Q2 in the second half cycle, with the other switches maintaining a symmetrical relationship. During forward energy flow, the primary bridge outputs a positive voltage in the first half cycle, generating forward current; in the second half cycle, it outputs a negative voltage, generating reverse current.

[0101] In summary, the soft switching characteristics of each switch tube during HDH-DAB energy forward transmission are shown in Table 1.

[0102] Table 1 HDH-DAB switch tube soft switching characteristics

[0103]

[0104] The negative half-cycle switch trigger signal is as follows Figure 8 As shown in Figure 2, the negative half cycle operates similarly to the positive half cycle. At t4, since the current i2 is transferred from Q4 to the Q3 body diode, i O A jump with the same amplitude as i2 appears. In summary, the soft switching characteristics of each switch tube during HDH-DAB energy reverse transmission are shown in Table 2.

[0105] Table 2 HDH-DAB switch tube soft switching characteristics

[0106]

[0107] To further implement the above technical solution, in forward mode 1, the voltage across L is:

[0108] v L (t) = V in / 2-V O / N1+V in N2 / N1 (1)

[0109] Among them, N1 and N2 are T r1 、T r2 The ratio of the secondary winding turns to the primary winding turns;

[0110] The inductor current is:

[0111]

[0112] The output current is:

[0113] i O =i1(t) / N1 (3)

[0114] In forward mode 2, the voltage across L is:

[0115] v L (t) = V in / 2-V O / N1 (4)

[0116] The inductor current is:

[0117]

[0118] To further implement the above technical solution, in reverse mode 1, the voltage across L is:

[0119] v L (t) = V in / 2-V O / N1 (6)

[0120] The inductor current is:

[0121]

[0122] Output current:

[0123] i O (t)=-N1i1(t) (8)

[0124] In this mode, the voltage across the inductor is:

[0125] v L (t) = V in / 2-V O / N1+V in N2 / N1 (9)

[0126] The inductor current is:

[0127]

[0128] The following analysis is based on the HDH-DAB in the forward energy transmission state, and the input voltage V in =2000V, output voltage V O =750V, rated power P N =200kW, switching frequency f s =2kHz.

[0129] N1 and N2 must meet the following requirements:

[0130]

[0131] Therefore, we can deduce:

[0132]

[0133] In the positive half cycle, the total power transmitted by HDH-DAB is:

[0134]

[0135] The power transmitted by the main power transformer is:

[0136]

[0137] Therefore, the ratio of the power transmitted by the main power transformer to the total power is:

[0138]

[0139] The power transmitted by the secondary power full bridge is:

[0140] P a =P t -P m (16)

[0141] Therefore, the ratio of the power transmitted by the main power transformer to the auxiliary power transformer is:

[0142]

[0143] Therefore, when V in With V O After determination, the ratio of the power transmitted by the main power transformer to that of the auxiliary power transformer is only related to the value of N1.

[0144] In this embodiment, P m / P a =9, that is, the main power transformer transmits 90% of the power, and the auxiliary power transformer transmits 10% of the power. in With V O , from formula (17), we can get N1 = 0.675.

[0145] Assume that the inductor current rise time in the first half cycle is T r , the inductor current fall time is T f , then:

[0146]

[0147] From formula (18), we can get:

[0148]

[0149] Take r t =4, substitute V in 、V O Together with N1, we can get N2=0.0469.

[0150] In current critical mode, there are:

[0151]

[0152] Let the peak value of i1 be I peak , within t0~t1:

[0153]

[0154] From formula (18) and (21), we can get:

[0155]

[0156] Load current I load for:

[0157]

[0158] Because I O It is a triangular wave and is in a critical continuous state, such as Figure 13 As shown. From the geometric relationship, we can get:

[0159]

[0160] And the output capacitor C O The charge and discharge time in half a cycle is T s / 4. Substituting the above values into equation (22) yields the transmission inductance L = 15.4 μH. To ensure that the HDH-DAB operates in the discontinuous state of the inductor current, the actual inductance value should be smaller than the calculated value.

[0161] In half a cycle, the output capacitor voltage fluctuation value is:

[0162]

[0163] Therefore, the solution formula for the output capacitance is:

[0164]

[0165] If the voltage fluctuation value of the output capacitor is ΔV=20V, then the output capacitor C O =0.84mF.

[0166] Take HDH-DAB as an example for analysis during forward energy transmission. When the current is in the critical continuous state, the duty cycle of Q3 and Q4 satisfies:

[0167] t2-t1=(0.5-D)T s (27)

[0168] For the transmission inductance L, the volt-second balance can be obtained:

[0169] (V in / 2-VO / N1+V in N2 / N1)DT s +(V in / 2-V O / N1)(0.5-D)T s =0 (28)

[0170] By simplifying formula (12), we can get:

[0171] V O =(2N2D+N1 / 2)V in (29)

[0172] Therefore, the output voltage V can be adjusted by adjusting D. O In addition, the theoretical range of D is [0,0.5], so V O The range is:

[0173] N1V in / 2<V O <(2N2+N1 / 2)V in (30)

[0174] In summary, the closed-loop control block diagram of HDH-DAB in the forward energy transmission state is as follows: Figure 14 As shown;

[0175] Similarly, the HDH-DAB closed-loop control block diagram under the reverse energy transmission state is: Figure 15 As shown; among them, r t It is the ratio of the current rise time to the current fall time.

[0176] In order to better demonstrate the effectiveness of the topology and modulation method disclosed in the present invention, the following simulation examples are used for verification. Figure 3 The HDH-DAB topology shown in the figure is simulated in MATLAB / Simulink. The simulation parameters are shown in Table 3.

[0177] Table 3 Main simulation parameters

[0178] parameter Numerical <![CDATA[Input side voltage V in > 2000V <![CDATA[Output-side voltage V O > 750V <![CDATA[Input-side capacitor C i1 / C i2 > 0.8mF <![CDATA[Output-side capacitor C O > 0.8mF Transmission inductance L 15μH <![CDATA[Main transformer turns ratio N1]]> 0.675 <![CDATA[Turn ratio N2 of the auxiliary transformer]]> 0.0469 <![CDATA[Rated power P N > 200kW <![CDATA[Switching frequency f s > 2kHz

[0179] Figure 16 The HDH-DAB output voltage waveform shows that the output voltage fluctuates around 750V with a fluctuation range of about 30V, slightly larger than the theoretical analysis value.

[0180] Figure 17The waveform of the HDH-DAB inductor current i1 is shown. The figure shows that i1 is discontinuous, confirming the correctness of the theoretical analysis. Voltage fluctuations between the input and output capacitors cause fluctuations in the voltage across the inductor. Therefore, the inductor current does not follow a strictly linear pattern.

[0181] Figure 18 The following figure shows the voltage and current waveforms of Q1. It can be seen that before turning on and off, the current flowing through Q1 is zero, and Q1 achieves ZCS turn-on and turn-off.

[0182] Figure 19 The following figure shows the voltage and current waveforms for Q3. As can be seen from the figure, before forward conduction, the voltage remains at zero, and the current is also zero, thus achieving ZVZCS turn-on. Furthermore, before Q3 turns off, due to the presence of parasitic capacitance, the voltage across it cannot rise rapidly. Instead, it rises linearly after the current drops to zero, thus achieving ZVS turn-off.

[0183] Figure 20 Shown is S 11 Voltage and current waveforms. It can be seen that before turning on and off, the current flowing through S 11 The current is 0, S 11 ZCS is enabled and disabled.

[0184] Figure 21 The output voltage waveform under reverse energy transfer is shown in Figure 1. As can be seen, the output voltage fluctuates around 2000V, with a fluctuation amplitude of approximately 20V.

[0185] Figure 22 The waveform of inductor current i1 during reverse energy transfer is shown in the figure. It can be seen that i1 is discontinuous and negative in the first half of its cycle, confirming the correctness of the theoretical analysis. Voltage fluctuations between the input and output capacitors cause fluctuations in the voltage across the inductor. Therefore, the inductor current does not follow a strictly linear pattern.

[0186] Figure 23 The following figure shows the voltage and current waveforms of Q1 in the reverse energy transfer state. It can be seen that before turning on and off, the current flowing through Q1 is zero, and Q1 achieves ZCS turn-on and turn-off.

[0187] Figure 24 The following figure shows the voltage and current waveforms of Q3 during reverse energy transfer. The figure shows that before forward conduction, the voltage remains at zero, and the current is also zero, thus achieving ZVZCS turn-on. Furthermore, before Q3 turns off, due to the presence of parasitic capacitance, the voltage across it cannot rise rapidly. Instead, it rises linearly after the current drops to zero, thus achieving ZVS turn-off.

[0188] Figure 25The figure shows S under reverse energy transfer. 11 Voltage and current waveforms. It can be seen that before turning on and off, the current flowing through S 11 The current is 0, S 11 ZCS is enabled and disabled.

[0189] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A full-cycle soft switching operation method for a heterogeneous device hybrid DAB topology, characterized in that: The heterogeneous device hybrid DAB topology includes: input side bridge arm group, transformer group and output side bridge arm group; The input side bridge arm includes the input capacitor bridge arm, the main power bridge arm and the auxiliary power bridge arm. The input voltage V in The positive and negative electrodes are connected to the two ends of the input capacitor bridge arm, the main power bridge arm and the auxiliary power bridge arm respectively, wherein the input capacitor bridge arm includes the input capacitor C i1 and C i2 , C i1 The negative electrode and C i2 The node formed by the positive electrodes is point B. The main power bridge arm includes IGBTs Q1 and Q2 connected in series, and Q1 and Q2 contain anti-parallel diodes. The emitter of Q1 is connected to the collector of Q2 to form a node at point A. The auxiliary power bridge arm includes MOSFETs Q3 and Q4 connected in series. The source of Q3 and the drain of Q4 are connected to form a node at point C. The transformer group includes the main power transformer T r1 , auxiliary power transformer T r2 and transmission inductance L, T r1 The positive electrode of the primary side is connected to one end of the transmission inductor L, T r1 The primary negative electrode is connected to point B; T r2 The positive electrode of the primary side is connected to the other end of L and point A respectively, T r2 The primary negative electrode is connected to point C; T r1 The secondary negative electrode and T r2 The secondary side positive pole is connected; The output side bridge arm group includes 4 IGBT groups and output capacitor C o Each IGBT group includes two anti-parallel IGBTs, where the forward IGBTs in the first to fourth IGBT groups are S 11 、S 21 、S 31 and S 41 , reverse IGBT is S 12 、S 22 、S 32 and S 42 ; The node where the emitter of the forward IGBT and the collector of the reverse IGBT in each IGBT group are connected is used as the first common terminal, the node where the collector of the forward IGBT and the emitter of the reverse IGBT are connected is used as the second common terminal, and the node where the first common terminal of the first IGBT group and the second common terminal of the second IGBT group are connected is connected to T r1 The secondary positive terminal, the node where the second common terminal of the first IGBT group and the second common terminal of the third IGBT group are connected are connected to C o The positive electrode of the third IGBT group and the node where the first common terminal of the third IGBT group and the second common terminal of the fourth IGBT group are connected are connected to T r2 The node where the first common terminal of the second IGBT group and the first common terminal of the fourth IGBT group are connected is connected to C o The negative electrode, C o The positive and negative poles are used as the output voltage V o The positive and negative poles; The full-cycle soft switching operation method of the heterogeneous device hybrid DAB topology includes: energy forward transfer state and energy reverse transfer state; In the forward energy transfer state, the first half cycle is divided into forward mode 1, forward mode 2, and forward mode 3; the second half cycle is symmetrical to the first half cycle; The time period [t0, t1) is positive mode 1, at time t0, Q1 and S 12 、S 42 and Q4 to achieve ZCS conduction, Q2, S 22 and S 32 To achieve ZCS shutdown, the current i1 flows through Q1, L, and T in the time period t0-t1. r1 Primary side, C i1 And i1 is in increasing state, current i2 flows through Q1, T r2 Primary side, Q4, C i2 、C i1 ; Where: t0 is the moment when the current half cycle starts; The period [t1, t2) is the forward mode 2, the current i1 is in a decreasing state, Q4 realizes ZVS shutdown at t1, Q1, S 12 and S 42 Keep conducting, i2 charges the parasitic capacitance of Q4 and discharges the parasitic capacitance of Q3; when the voltage across the parasitic capacitance of Q3 is less than 0, the body diode of Q3 is turned on, and i2 flows through the body diode of Q3; The time period [t2, t3] is forward mode 3, the current i1 remains unchanged, the body diode of Q3 is turned off at t2, the voltage across the parasitic capacitor of Q3 is 0, and the voltage across the parasitic capacitor of Q4 is V in , the current in the converter is kept at 0, by C O Supply power to the load, S 12 and S 42 Turn on; at t3, the positive half cycle ends, Q1, S 12 、S 42 To achieve ZCS shutdown, Q2, S 22 、S 32 Achieve ZCS conduction, Q3 achieves ZVZCS conduction; In the reverse energy transfer state, each half cycle is divided into reverse mode 1, reverse mode 2 and reverse mode 3; The time period [t0, t1) is reverse mode 1: Q1, S 11 、S 41 and Q3 to achieve ZCS conduction, Q2, S 21 and S 31 Achieve ZCS shutdown; current i1 flows through Q1 anti-parallel diode, C i1 、T r1 The primary side and L and i1 are in decreasing state, current i2 flows through Q1 anti-parallel diode, Q3 and T r2 original edge; The period [t1, t2) is reverse mode 2: at t1, Q3 realizes ZVS shutdown, i2 charges the parasitic capacitance of Q3 and discharges the parasitic capacitance of Q4. When the voltage across the parasitic capacitance of Q4 is less than 0, the body diode of Q4 is turned on, and i2 flows through the body diode of Q4. The current i1 flows through the anti-parallel diode of Q1, C i1 、T r1 The primary side and L and i1 are in increasing state, the current i2 flows through the anti-parallel diode Q1, C i1 、C i2 , Q4 body diode and T r2 original edge; The period [t2, t3] is reverse mode 3: at t2, the Q4 body diode is naturally turned off, the voltage across the Q4 parasitic capacitor is 0, and the voltage across the Q3 parasitic capacitor is V in , the current in the converter is kept at 0, by the capacitor C i1 、C i2 Supply power to the load; at t3, the positive half cycle ends, Q1, S 11 and S 41 To achieve ZCS shutdown, Q2, S 21 and S 31 Achieve ZCS conduction, Q4 achieves ZVZCS conduction.

2. The full-cycle soft switching operation method of a heterogeneous device hybrid DAB topology according to claim 1 is characterized in that: In the input side bridge arm group, the collector of Q1 is connected to C i1 The positive electrode of Q2 is connected to the positive electrode of Q3 and the drain of Q3, and the emitter of Q2 is connected to C i2 The cathode of Q4 is connected to the source of Q4.

3. The full-cycle soft switching operation method of a heterogeneous device hybrid DAB topology according to claim 1 is characterized in that: In the first IGBT group, S 11 The collector and S 12 The emitter is connected to S 11 The emitter and S 12 In the second IGBT group, S 21 The collector and S 22 The emitter is connected to S 21 The emitter and S 22 The collector of the third IGBT group is connected; in the third IGBT group, S 31 The collector and S 32 The emitter is connected to S 31 The emitter and S 32 In the fourth IGBT group, S 41 The collector and S 42 The emitter is connected to S 41 The emitter and S 42 The collector is connected; S 11 Emitter and S 12 The junction formed by the collector and S 21 Collector and S 22 The emitter forms a junction connected to the T r1 The secondary side positive pole is connected; S 31 Emitter and S 32 The junction formed by the collector and S 41 Collector and S 42 The emitter forms a junction connected to the T r2 The secondary negative terminal is connected; S 11 Collector and S 12 The emitter forms a junction, S 31 Collector and S 32 The emitter forms a junction with the output capacitor C O The positive pole is connected and connected to the positive pole of the output voltage; S 21 Emitter and S 22 The junction formed by the collector, S 41 Emitter and S 42 The junction formed by the collector and the output capacitor C O The negative pole is connected to the negative pole of the output voltage.

4. The full-cycle soft switching operation method of a heterogeneous device hybrid DAB topology according to claim 1 is characterized in that: In forward mode 1, the voltage across L is: in L (t)=V in / 2-V O / N1+V in N2 / N1 (1) Among them, N1 and N2 are T r1 、T r2 The ratio of the secondary winding turns to the primary winding turns; The inductor current is: The output current is: i O =i1(t) / N1 (3) In forward mode 2, the voltage across L is: in L (t)=V in / 2-V O / N1 (4) The inductor current is:

5. The full-cycle soft switching operation method of a heterogeneous device hybrid DAB topology according to claim 1 is characterized in that: In reverse mode 1, the voltage across L is: in L (t)=V in / 2-V O / N1 (6) The inductor current is: Output current: i O (t)=-N1i1(t) (8) In this mode, the voltage across the inductor is: in L (t)=V in / 2-V O / N1+V in N2 / N1 (9) The inductor current is: Among them, N1 and N2 are T r1 、T r2 The ratio of the number of turns of the secondary winding to the number of turns of the primary winding.

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