Multipath data processing and caching system

Abstract

The application relates to the technical field of wireless optical communication, and particularly provides a multi-path data processing and caching system, which comprises a single-photon array detector, a time-to-digital converter, an optical module, a signal acquisition board card and a data processing and caching module which are sequentially connected; the single-photon array detector is used for detecting optical signals and outputting multi-path electric signals; the time-to-digital converter is used for converting the electric signals into timestamp data, wherein all the timestamp data constitute a timestamp data stream; the optical module is used for transmitting the timestamp data stream to the signal acquisition board card; the signal acquisition board card is used for transmitting the timestamp data stream to the data processing and caching module; and the data processing and caching module is used for sequentially performing data processing and caching on the timestamp data stream. Therefore, the single-photon array detector, the time-to-digital converter, the optical module, the signal acquisition board card and the data processing and caching module are combined, which is helpful for accurately and timely processing and caching multi-path high-speed timestamp data.

Description

Technical Field

[0001] This invention relates to the field of wireless optical communication technology, and more specifically to a multi-channel data processing and caching system. Background Technology

[0002] In recent years, to meet the high-speed data transmission requirements of deep space exploration missions, multi-pixel SNSPDs (Superconducting Nanowire Single Photon Detectors) have made continuous breakthroughs in key performance aspects such as saturation count rate, temporal jitter, and detection efficiency, and have been widely used in high-speed photon counting communication systems due to their superior performance. Considering the further improvement in the single-pixel saturation count rate of superconducting nanowire single-photon detectors, free-space optical communication has now achieved total photon count rates of tens of Gbps and communication rates of hundreds of Mbps to over Gbps. At such high photon count rates, accurately and rapidly processing and buffering high-speed detection signals (such as multiple high-speed timestamp data) from multiple detection channels in real time is a complex task. Summary of the Invention

[0003] To solve one of the above-mentioned technical problems, the present invention proposes the following technical solution.

[0004] The first aspect of the present invention provides a multi-channel data processing and caching system, comprising a single-photon array detector, a time-to-digital converter, an optical module, a signal acquisition board, and a data processing and caching module connected in sequence.

[0005] The single-photon array detector is used to detect optical signals and output multiple electrical signals related to the detected photon events; the time-to-digital converter is used to convert each electrical signal into timestamp data, wherein all timestamp data constitute a timestamp data stream; the optical module is used to transmit the timestamp data stream to the signal acquisition board; the signal acquisition board is used to transmit the timestamp data stream to the data processing and caching module; the data processing and caching module is used to sequentially process and cache the timestamp data stream.

[0006] In addition, the multi-channel data processing and caching system according to the above embodiments of the present invention may also have the following additional technical features.

[0007] According to one embodiment of the present invention, the data processing and caching module includes a parallel data extraction unit, a data caching and compensation unit, and a serial data processing and storage unit connected in sequence.

[0008] The parallel data extraction unit is used to extract multiple parallel data streams from the timestamp data stream according to a preset parallel channel, and transmit the multiple parallel data streams to the data caching and compensation unit; the data caching and compensation unit is used to cache and compensate the multiple parallel data streams to obtain a serial data stream, and transmit the serial data stream to the serial data processing and storage unit; the serial data processing and storage unit is used to perform data processing and storage sequentially.

[0009] According to an embodiment of the present invention, the data processing and caching module further includes a data verification and parsing unit, wherein the data verification and parsing unit is connected between the signal acquisition board and the parallel data extraction unit, and the data verification and parsing unit is used to perform frame format verification on the timestamp data stream, and when the verification passes, to parse the timestamp data stream and transmit it to the parallel data extraction unit.

[0010] According to one embodiment of the present invention, the data caching and compensation unit includes multiple first FIFO (First In First Out) memories, multiplexers, and a lookup table. The input of each first FIFO memory is connected to the parallel data extraction unit, the output of each first FIFO memory is connected to the input of the multiplexer, the output of the multiple multiplexers is connected to the lookup table, and the lookup table is also connected to the serial data processing and storage unit.

[0011] According to one embodiment of the present invention, the serial data processing and storage unit includes a data processing subunit, wherein the data processing subunit is used to perform data processing through the following steps:

[0012] Using the timestamp data of the detected start photon as the start timestamp data, the time difference value is obtained by subtracting the start timestamp data from each data in the serial data stream; based on the time difference value and the width of the preset time slot, the number of time slots between each detected photon and the start photon is determined.

[0013] According to one embodiment of the present invention, the serial data processing and storage unit further includes a data storage and reset subunit. The data storage and reset subunit includes multiple BRAM (Bipolar Random Access Memory) caches and multiple second FIFO memories, wherein the BRAM caches and the second FIFO memories are connected in a one-to-one correspondence.

[0014] The BRAM buffer is used to store the operation address of the corresponding BRAM buffer. The operation address of the BRAM buffer is the number of time slots between each detected photon and the starting photon. This value indicates the relative time of the occurrence of the corresponding photon compared to the starting photon, and is also used for subsequent point-to-point reset of the BRAM buffer. The BRAM buffer is used to store binary data. The data initialization value of all its operation addresses is 0. The binary data 1 indicates that a photon has been detected, and the binary data 0 indicates that no photon has been detected.

[0015] According to one embodiment of the present invention, the multi-channel data processing and caching system further includes a serial data readout module, which is connected to the BRAM cache and is used to read out the data stored in the BRAM cache.

[0016] According to one embodiment of the present invention, the depth of the first FIFO memory is determined based on the size of the timestamp data stream and the preset number of parallel channels.

[0017] According to one embodiment of the present invention, the single-photon array detector is a superconducting nanowire single-photon array detector.

[0018] According to one embodiment of the present invention, the optical module is a 40G SFP+ optical module or a 10G SFP+ optical module.

[0019] The technical solution of this invention, which combines a single-photon array detector, a time-to-digital converter, an optical module, a signal acquisition board, and a data processing and caching module, helps to accurately and in real-time process and cache multiple high-speed timestamp data. Attached Figure Description

[0020] Figure 1 This is a structural block diagram of a multi-channel data processing and caching system according to an embodiment of the present invention.

[0021] Figure 2 This is a structural block diagram of a data processing and caching module according to an embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram of the structure of a multi-channel data processing and caching system as an example of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] In common high-speed array photon detection pulse signal acquisition schemes, high sampling rate analog-to-digital conversion is limited by high-speed clock signals and cross-clock domain sampling involves stringent wiring and timing requirements, which limits the sensitivity and rate improvement of high-speed communication reception.

[0025] In this embodiment of the invention, the low-duty-cycle sparse signal is processed by converting the electrical signal into a photonic timestamp using a time-to-digital converter, which significantly reduces the data transmission bandwidth and processing clock requirements. To further improve the transmission rate, this embodiment of the invention uses an optical module interface to achieve inter-board transmission of high-speed timestamp data streams. However, processing the large amounts of high-speed data generated by each channel of the time-to-digital converter quickly and timely remains challenging. Therefore, there is an urgent need for a scheme that enables real-time reading and buffering of high-speed signals between the time-to-digital converter and the FPGA (Field Programmable Gate Array) development board to achieve effective utilization of multi-channel timestamp data. To this end, this embodiment of the invention achieves effective utilization of multi-channel timestamp data through a data processing and buffering module. A detailed description follows.

[0026] Figure 1 This is a structural block diagram of a multi-channel data processing and caching system according to an embodiment of the present invention.

[0027] like Figure 1 As shown, the multi-channel data processing and caching system includes a single-photon array detector 1, a time-to-digital converter 2, an optical module 3, a signal acquisition board 4, and a data processing and caching module 5 connected in sequence.

[0028] The single-photon array detector 1 is used to detect optical signals and output multiple electrical signals related to the detected photon events; the time-to-digital converter 2 is used to convert each electrical signal into timestamp data, wherein all timestamp data constitute a timestamp data stream (serial data); the optical module 3 is used to transmit the timestamp data stream to the signal acquisition board; the signal acquisition board 4 is used to transmit the timestamp data stream to the data processing and buffering module; the data processing and buffering module 5 is used to process and buffer the timestamp data stream sequentially.

[0029] Understandably, a single-photon array detector has one input and multiple outputs. It is used to detect one input optical signal and output multiple electrical signals related to the detected photon event.

[0030] Among them, the single-photon array detector 1 can be a superconducting nanowire single-photon array detector. The optical module 3 can be a 40G SFP+ optical module or a 10G SFP+ optical module.

[0031] Specifically, the single-photon array detector 1 detects one input optical pulse signal, and its internal readout circuit outputs multiple corresponding electrical signals. Multiple channels may simultaneously detect the optical pulse, resulting in multiple identical timestamp data points. Therefore, any one of these timestamp data points can be selected. The (multi-channel) time-digital converter (TDC) 2 converts the electrical signals from the readout circuit into timestamp data (digitized signals), thus obtaining high-speed signals from multiple detection channels. Each timestamp data point represents the absolute time of detection of a corresponding photon and corresponds one-to-one with the electrical signals output by the detector. All timestamp data points constitute a timestamp data stream. This timestamp data stream is transmitted to the signal acquisition board 4 via the optical module 3. The optical module 3 packages the timestamp data stream using communication messages before transmitting it to the signal acquisition board 4. The signal acquisition board 4 then transmits the data to the pre-loaded data processing and buffering module 5, which performs real-time processing and buffering of the input real-time, high-speed data stream.

[0032] The embodiments of this invention employ the above-described scheme, using a single-photon array detector and a time-to-digital converter, which can improve the communication rate. The use of optical modules and signal acquisition boards enables high-speed real-time transmission of multiple channels of high-resolution timestamp data, further improving transmission rates, achieving high-speed data acquisition, and facilitating real-time processing of high-speed data.

[0033] Therefore, the multi-channel data processing and caching system of this invention, which combines a single-photon array detector, a time-to-digital converter, an optical module, a signal acquisition board, and a data processing and caching module, helps to accurately and in real-time process and cache multiple channels of high-speed timestamp data.

[0034] In one embodiment, such as Figure 2 As shown, the data processing and caching module 5 includes a parallel data extraction unit 52, a data caching and compensation unit 53, and a serial data processing and storage unit 54 connected in sequence.

[0035] The parallel data extraction unit 52 is used to extract multiple parallel data streams from the timestamp data stream according to the preset parallel channels, and transmit the multiple parallel data streams to the data buffer and compensation unit; the data buffer and compensation unit 53 is used to buffer and compensate the multiple parallel data streams to obtain a serial data stream, and transmit the serial data stream to the serial data processing and storage unit; the serial data processing and storage unit 54 is used to perform data processing and storage in sequence.

[0036] Among them, the preset parallel channel refers to the multi-channel that is set in advance to extract multiple serial timestamp data streams in parallel. After being preset, the number of channels can be adaptively updated according to the actual data throughput.

[0037] Furthermore, referring to Figure 2 The data processing and caching module 5 also includes a data verification and parsing unit 51, which is connected between the signal acquisition board 4 and the parallel data extraction unit 52.

[0038] The data verification and parsing unit 51 is used to verify the frame format of the timestamp data stream, and when the verification is successful, it parses the timestamp data stream and transmits it to the parallel data extraction unit 52.

[0039] Specifically, after receiving the real-time, high-speed timestamp data stream, the data verification and parsing unit 51 analyzes and verifies the frame format of the timestamp data stream. If the verification passes, the timestamp data stream is parsed and transmitted to the parallel data extraction unit 51. If the verification fails (indicating that an error or loss occurred during data transmission), the corresponding data is discarded. The parallel data extraction unit 52 extracts data from the received timestamp data stream based on preset multi-channel parallel processing, extracting multiple parallel data streams and transmitting them to the data caching and compensation unit 53. The data caching and compensation unit 53 caches and compensates the multiple parallel data streams to obtain a serial data stream (sparse data) based on the multiple parallel data streams, and transmits it to the serial data processing and storage unit 54. The serial data processing and storage unit 54 processes and stores the data sequentially.

[0040] In one example, such as Figure 3 As shown, the data caching and compensation unit 53 includes multiple first FIFO (First In First Out) memory modules. Figure 3 The diagram shows two FIFO memories, namely FIFO1 and FIFO2, a multiplexer (MUX), and a lookup table (LUT). The input of each first FIFO memory is connected to the parallel data extraction unit 52, and the output of each first FIFO memory is connected to the input of the multiplexer (MUX). The outputs of the multiplexer (MUX) are connected to the lookup table (LUT), which is also connected to the serial data processing and storage unit 54.

[0041] The depth of the first FIFO memory is determined based on the size of the timestamp data stream and the preset number of parallel channels. The number of parallel channels can be determined adaptively based on the actual data throughput.

[0042] Specifically, Figure 3The operation mechanism of the data buffering and compensation unit 53 is illustrated using two parallel data streams (which are obtained by dividing and extracting the output data of all TDC channels) as an example. The timestamp information of the two merged streams is buffered into the corresponding FIFOs at a clock speed of 156.25MHz (the specific clock can be determined according to actual needs when there are three or other streams). The FIFO depth is determined by the current timestamp data volume. At the same time, the output enable of the two buffer FIFOs is selected by the multiplexer MUX to realize the alternating and merging output of the two data streams, resulting in a single serial data stream. The serial data stream is compensated for non-ideal factors by a pre-stored lookup table (LUT) to correct the errors introduced during detector detection and acquisition. The corrected serial data stream is then input into the serial data processing and storage unit 54 for further processing, i.e., the corrected serial data stream is processed and then stored.

[0043] Furthermore, the serial data processing and storage unit 54 includes a data processing subunit 541 and a data storage and reset subunit 542 connected in sequence.

[0044] The data processing subunit 541 is used to process data through the following steps: using the timestamp data of the detected start photon as the start timestamp data, subtracting each data in the serial data stream from the start timestamp data to obtain a time difference value; determining the number of time slots between each detected photon and the start photon based on the time difference value and the width of the preset time slot, and transmitting it to the data storage and reset subunit 542; the data storage and reset subunit 542 is used to store whether a photon was detected at each time according to the number of time slots.

[0045] The starting timestamp data can be pre-assumed or any of the timestamp data output by each time-to-digital converter. The preset timeslot width refers to the width or range of the timeslot set in advance according to actual needs. For example, it can be 1ns, 600ps, 500ps, etc. Different timeslot widths determine the final effective communication rate, and this embodiment of the invention does not impose any restrictions on this.

[0046] Reference Figure 3 The data storage and reset subunit 542 includes multiple BRAM (Bipolar Random Access Memory) caches (BRAM0~BRAMn, where n is an integer greater than or equal to 1) and multiple second FIFO memories (FIFO3~FIFOn, where n is an integer greater than or equal to 3). The BRAM caches are connected one-to-one with the second FIFO memories, and the BRAM caches are also connected to the data processing subunit 541.

[0047] The second FIFO memory (FIFO3~FIFOn, n≥3) is used to store the operation addresses of the corresponding BRAM buffers (BRAM0~BRAMn, n≥1). The operation address of the BRAM buffer is the number of time slots between each detected photon and the starting photon. This value indicates the relative time of occurrence of each corresponding photon compared to the starting photon. It is also used for point-to-point reset of the BRAM buffer after reading the data from all addresses of the BRAM buffer. The BRAM buffer is used to store binary data. The data initialization value of all operation addresses of the BRAM buffer is 0. The binary data 1 indicates that a photon was detected (a photon detection event occurred), and the binary data 0 indicates that no photon was detected (no photon detection event occurred).

[0048] Reference Figure 2 and Figure 3 The multi-channel data processing and caching system also includes a serial data readout module 6, which is connected to the BRAM cache and is used to read the data stored in the BRAM cache.

[0049] Specifically, after receiving the corrected serial data stream (sparse data), the serial data processing and storage unit 54 first preprocesses the sparse data through the data processing subunit 541. This preprocessing process uses the timestamp data corresponding to the received initial photon as the starting point timestamp data. Taking the first photon as an example, the difference between the subsequent timestamp data and the starting point timestamp data is calculated, and combined with the width of the preset time slot, to determine the number of time slots that the photon represented by the current timestamp data is separated from the first photon. By analyzing the number of photons falling into different time slots, the current photon distribution can be analyzed for subsequent synchronization algorithm processing.

[0050] The processed serial data stream (the number of time slots, i.e., the number of time slots between the occurrence time of each photon and the occurrence time of the photon corresponding to the starting timestamp data) is input into the data storage and reset subunit 542. This subunit contains a serial data buffer (BRAM) and a second FIFO memory storing the BRAM operation addresses. The data at all addresses in the BRAM is initialized to 0. This subunit can adjust the specific number of BRAM and second FIFO memories according to the data throughput. The second FIFO memory stores the number of time slots between the photon represented by the current timestamp data and the first photon. This value indicates the relative time of each photon compared to the occurrence time of the starting photon. It should be noted that detecting a photon can be regarded as event "1", and not detecting a photon can be regarded as event "0". The binary data 1 or 0 is stored in each address in the BRAM according to the BRAM operation address to realize the storage of whether a photon was detected. By storing the number of time slots in the second FIFO memory, the BRAM address bits can be precisely assigned, which can save the process of writing a lot of events "0" for not detecting photons, greatly reducing the writing clock requirements. After the data at all addresses in the BRAM is read by the serial data read module 6, the second FIFO memory outputs the address bits previously operated on in the BRAM, performing a point-to-point initial reset of the BRAM to facilitate rapid pipelined operations and increase data throughput. All data buffered in the BRAM is read out by the serial data read module 6 according to actual needs.

[0051] This enables high-speed parallel data readout, storage, and post-processing for photon counting communication. It can read, cache, and process sparse photon data at the level of hundreds of megabytes per second in real time, effectively meeting the photon signal readout requirements of high-speed photon counting communication receivers.

[0052] In summary, by combining a single-photon array detector 1, a time-to-digital converter 2, an optical module 3, a signal acquisition board 4, a data processing and caching module 5, and a serial data readout module 6, it is possible to accurately process large amounts of high-speed timestamp data from multiple detection channels in parallel. Specifically, using the time-to-digital converter to convert detection pulses into photon timestamps to process sparse signals with low duty cycles significantly reduces the data transmission bandwidth and processing clock requirements. The use of an optical module interface enables inter-board transmission of high-speed timestamp data streams. This solves the problem of transmission rate limitations due to data transmission bandwidth and processing clock in real-time inter-board transmission of high-speed timestamp data streams in array detectors. It allows for accurate and real-time processing and caching of multiple high-speed timestamp data streams, and enables a high-speed signal real-time readout and caching scheme between the time-to-digital converter and the FPGA development board under the same clock frequency, thus achieving effective utilization of high-speed data from multi-channel arrays.

[0053] In summary, the embodiments of this invention not only solve the problem of accurately and rapidly processing and buffering large amounts of high-speed detection signals (such as multiple high-speed timestamp digital signals) in real time, but also address the limitations of high-sampling-rate analog-to-digital conversion due to high-speed clock signals and the stringent wiring and timing requirements involved in cross-clock domain sampling. Furthermore, they solve the problem of quickly and timely processing large amounts of high-speed data generated by each channel of the time-to-digital converter. This reduces hardware complexity, further enhances the rapid and real-time processing capabilities of multi-channel array signals, expands the data throughput of high-speed photonic communication systems, and can achieve data transmission rates exceeding hundreds of megabits per second, making it suitable for high-speed real-time single-photon detection and communication scenarios.

[0054] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A multi-channel data processing and caching system, characterized in that, It includes a single-photon array detector, a time-to-digital converter, an optical module, a signal acquisition board, and a data processing and buffering module, connected in sequence. The single-photon array detector is used to detect optical signals and output multiple electrical signals related to the detected photon events; The time-to-digital converter is used to convert each of the electrical signals into timestamp data, wherein all the timestamp data constitute a timestamp data stream; The optical module is used to transmit the timestamp data stream to the signal acquisition board; The signal acquisition board is used to transmit the timestamp data stream to the data processing and caching module; The data processing and caching module is used to sequentially process and cache the timestamp data stream. The data processing and caching module includes a parallel data extraction unit, a data caching and compensation unit, and a serial data processing and storage unit connected in sequence. The parallel data extraction unit is used to extract multiple parallel data streams from the timestamp data stream according to a preset parallel channel, and then transmits these multiple parallel data streams to the data caching and compensation unit. The data caching and compensation unit is used to cache and compensate the multiple parallel data streams to obtain a serial data stream, and then transmits this serial data stream to the serial data processing and storage unit. The serial data processing and storage unit is used to perform data processing and storage sequentially. The data caching and compensation unit includes multiple first FIFO memories, a multiplexer, and a lookup table. The input of each first FIFO memory is connected to the parallel data extraction unit, the output of each first FIFO memory is connected to the input of the multiplexer, the output of the multiplexer is connected to the lookup table, and the lookup table is also connected to the serial data processing and storage unit. The serial data processing and storage unit includes a data processing subunit, which performs data processing through the following steps: using the timestamp data of the detected initial photon as the initial timestamp data, subtracting each data point in the serial data stream from the initial timestamp data to obtain a time difference value; and determining the number of time slots between each detected photon and the initial photon based on the time difference value and the width of a preset time slot. The serial data processing and storage unit further includes a data storage and reset subunit. The data storage and reset subunit includes multiple BRAM buffers and multiple second FIFO memories, wherein each BRAM buffer and second FIFO memory is connected in a one-to-one correspondence. The BRAM buffer is also connected to the data processing subunit. The second FIFO memory stores the operation address of the corresponding BRAM buffer. The operation address of the BRAM buffer is the number of time slots between each detected photon and the starting photon. This number indicates the relative time of the corresponding photon compared to the starting photon and is also used for subsequent point-to-point reset of the BRAM buffer. The BRAM buffer stores binary data, with all its operation addresses initialized to 0. Binary data 1 indicates that a photon has been detected, and binary data 0 indicates that no photon has been detected.

2. The multi-channel data processing and caching system according to claim 1, characterized in that, The data processing and caching module further includes a data verification and parsing unit, which is connected between the signal acquisition board and the parallel data extraction unit. The data verification and parsing unit is used to perform frame format verification on the timestamp data stream, and when the verification passes, parse the timestamp data stream and transmit it to the parallel data extraction unit.

3. The multi-channel data processing and caching system according to claim 1, characterized in that, It also includes a serial data readout module, which is connected to the BRAM buffer and is used to read the data stored in the BRAM buffer.

4. The multi-channel data processing and caching system according to claim 1, characterized in that, The depth of the first FIFO memory is determined based on the size of the timestamp data stream and the preset number of parallel channels.

5. The multi-channel data processing and caching system according to claim 1, characterized in that, The single-photon array detector is a superconducting nanowire single-photon array detector.

6. The multi-channel data processing and caching system according to claim 1, characterized in that, The optical module is either a 40G SFP+ optical module or a 10G SFP+ optical module.

Images