Semiconductor memory device

Abstract

The present application provides a semiconductor memory device, which relates to the technical field of data storage in information technology and is used to solve the problem of low usage times and service life of semiconductor memory devices. The semiconductor memory device has a data security area and a data storage area. The semiconductor device includes a plurality of magnetic tunnel junctions, and the plurality of magnetic tunnel junctions are distributed in the data security area and the data storage area. The magnetic tunnel junctions in the first short-circuit state in the data security area are changed from the first short-circuit state to the normal state by applying pressure. The normal state includes the parallel state or the antiparallel state, so that the semiconductor memory device can be restored to a normal device for use, thereby increasing the usage times and service life of the semiconductor memory device.

Description

Technical Field

[0001] This application relates to the technical field of data storage in information technology, and in particular, to a semiconductor storage device. Background Art

[0002] Integrated circuits are the foundation of the information industry. Whether it is cloud computing, big data, the Internet of Things, or smartphones, their development directly depends on the technological progress of integrated circuits. With the development of the electronic information industry, while information technology brings convenience to people's lives, it also brings potential data security risks. Currently, in many network communication systems, when the static keys stored in specific devices or components are leaked, the security factors of these systems will be exposed. Current security chips have disadvantages such as high cost and limited space, so it is urgent to adopt other means to overcome this problem.

[0003] In recent years, Magnetic Random Access Memory (MRAM) based on spintronic technology has received wide attention. As a new type of semiconductor storage device, MRAM uses the giant magnetoresistance effect of the magnetic tunnel junction to achieve information storage due to the different high and low resistance states of the magnetic tunnel junction in the parallel state and the antiparallel state. Especially in Spin Orbit Torque MRAM (SOT-MRAM), the high tolerance and reliability brought by the separation of the read and write channels, as well as the high-speed switching performance and ultra-low write power consumption of the spin orbit torque effect itself, make it promising as the next-generation magnetic random memory write technology. In addition to being used for storage, MRAM also needs to add a security module to achieve identity authentication or hardware matching.

[0004] However, in the existing PUF (Physically Unclonable Function) module based on MRAM memory, its logical states mainly include the parallel state, the antiparallel state, the short-circuit state, and the open-circuit state. However, this module can only transition from the magnetic initial state (parallel / antiparallel) to the short-circuit state or the open-circuit state. The short-circuit state is obtained by applying a voltage to break down the barrier layer (magnesium oxide) in the middle of the magnetic tunnel junction, and this process is irreversible and can only be used once. Summary of the Invention

[0005] In view of the above problems, an embodiment of this application provides a semiconductor storage device for restoring a device in the first short-circuit state to a normal device, and at the same time increasing the number of uses and the service life of the semiconductor storage device.

[0006] According to some embodiments, the present application provides a semiconductor memory device, which has a data security area and a data storage area. The semiconductor device includes a plurality of magnetic tunnel junctions, and the plurality of magnetic tunnel junctions are distributed in the data security area and the data storage area;

[0007] The magnetic tunnel junctions in the first short-circuit state in the data security area are changed from the first short-circuit state to the normal state by applying pressure, and the normal state includes a parallel state or an antiparallel state.

[0008] In some possible embodiments, all the magnetic tunnel junctions in the data security area are in the first short-circuit state.

[0009] In some possible embodiments, a first preset voltage is applied to a first target magnetic tunnel junction in the data security area to partially change it to the normal state. Before applying the first preset voltage, the first target magnetic tunnel junction is in the first short-circuit state.

[0010] In some possible embodiments, a second preset voltage is applied to a second target magnetic tunnel junction in the data security area to change all of them to the normal state. Before applying the second preset voltage, the second target magnetic tunnel junction is in the first short-circuit state.

[0011] In some possible embodiments, the magnetic tunnel junctions in the data security area are used for data storage.

[0012] In some possible embodiments, a third preset voltage is applied to a third target magnetic tunnel in the data security area to change it to a second short-circuit state. Before applying the third preset voltage, the third target magnetic tunnel junction is in the first short-circuit state or the normal state.

[0013] In some possible embodiments, a fourth preset voltage is applied to a fourth target magnetic tunnel junction in the data security area to change it to an open state. Before applying the fourth preset voltage, the fourth target magnetic tunnel junction is in the first short-circuit state or the normal state or the second short-circuit state.

[0014] In some possible embodiments, a first preset voltage is applied to a first target magnetic tunnel junction in the data security area to partially change it to the normal state. Before applying the first preset voltage, the first target magnetic tunnel junction is in the first short-circuit state;

[0015] A second preset voltage is applied to a second target magnetic tunnel junction in the data security area to change all of them to the normal state. Before applying the second preset voltage, the second target magnetic tunnel junction is in the first short-circuit state;

[0016] By applying a third preset voltage to a third target magnetic tunnel junction in the data security region to transform it into a second short - circuit state, where, before applying the third preset voltage, the third target magnetic tunnel junction is in the first short - circuit state or the normal state;

[0017] By applying a fourth preset voltage to a fourth target magnetic tunnel junction in the data security region to transform it into an open - circuit state, where, before applying the fourth preset voltage, the fourth target magnetic tunnel junction is in the first short - circuit state or the normal state or the second short - circuit state;

[0018] Wherein, the first preset voltage < the second preset voltage < the third preset voltage < the fourth preset voltage.

[0019] In some possible embodiments, the states of several magnetic tunnel junctions in the data security region are read and corresponding keys are generated.

[0020] In some possible embodiments, the first short - circuit state is formed during the manufacturing process of the semiconductor memory device.

[0021] The semiconductor memory device provided by the embodiments of the present application has at least the following advantages:

[0022] The semiconductor memory device provided by the embodiments of the present application has a data security region and a data storage region. The semiconductor device includes a plurality of magnetic tunnel junctions, and the plurality of magnetic tunnel junctions are distributed in the data security region and the data storage region. The magnetic tunnel junctions in the first short - circuit state in the data security region are transformed from the first short - circuit state to the normal state by applying pressure. The normal state includes a parallel state or an anti - parallel state, so that the semiconductor memory device in the first short - circuit state can be restored to a normal device for use. At the same time, after being restored from the first short - circuit state to the normal state, it can further be transformed into other states (such as the second short - circuit state or the open - circuit state), thereby increasing the number of uses and the service life of the semiconductor memory device, and it can be used up to four times at most. Description of the Drawings

[0023] Figure 1 Schematic diagram of the semiconductor memory device in the embodiments of the present application;

[0024] Figure 2 Schematic diagram of the arrangement of a plurality of magnetic tunnel junctions in the embodiments of the present application;

[0025] Figure 3 Schematic diagram of the film - layer structure of the semiconductor memory device in the embodiments of the present application;

[0026] Figure 4 Schematic diagram of the relationship between the short - circuit ratio and the magnitude of the applied voltage in the embodiments of the present application;

[0027] Figure 5 Schematic diagram of the relationship between the resistance value and the applied voltage in the embodiments of the present application.

[0028] Description of the reference numerals:

[0029] 10 - Data security area; 20 - Data storage area;

[0030] 30 - Control circuit area; 40 - Magnetic tunnel junction;

[0031] 41 - Free layer; 42 - Barrier layer;

[0032] 43 - Reference layer; 44 - Pinned layer;

[0033] 50 - Spin - orbit torque layer; 60 - Top electrode. Detailed implementation manners

[0034] In the related art, the short - circuit state of a semiconductor memory device is obtained by applying a voltage to break down the barrier layer of the magnetic tunnel junction. After the barrier layer is broken down, it cannot be restored, and this process is irreversible. That is, the magnetic tunnel junction in the short - circuit state cannot be restored to the normal state again, and this magnetic tunnel junction cannot be used as a normal device again, that is, it can only be used once.

[0035] The embodiments of the present application provide a semiconductor memory device, which has a data security area and a data storage area. The semiconductor device includes a plurality of magnetic tunnel junctions, and the plurality of magnetic tunnel junctions are distributed in the data security area and the data storage area. The magnetic tunnel junction in the first short - circuit state in the data security area is changed from the first short - circuit state to the normal state by applying pressure, so that the semiconductor memory device in the first short - circuit state can be restored to a normal device for use. At the same time, after being restored from the first short - circuit state to the normal state, it can further be changed to other states, such as the second short - circuit state or the open - circuit state, thereby increasing the number of uses and the service life of the semiconductor memory device, and it can be used up to four times at most.

[0036] In order to make the above - mentioned objects, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present application.

[0037] Refer to Figure 1, embodiments of the present application provide a semiconductor memory device, which can be a chip. The semiconductor memory device has a data security area 10 and a data storage area 20. The data security area 10 and the data storage area 20 are adjacent, and the two are two independent areas on a single semiconductor memory device.

[0038] The semiconductor memory device also has a control circuit area 30, which is used to form a control circuit to control the reading or writing of data, etc. The control circuit area 30, the data security area 10, and the data storage area 20 are adjacent, and the three are independent of each other. The arrangement form of the control circuit area 30, the data security area 10, and the data storage area 20 is not limited.

[0039] Refer to Figure 2 , the semiconductor memory device includes a plurality of magnetic tunnel junctions 40, and the plurality of magnetic tunnel junctions 40 are distributed in the data security area 10 and the data storage area 20. The plurality of magnetic tunnel junctions 40 in the data security area 10 can be used as a PUF module to improve security performance. The PUF module is a new type of security module implemented from the physical layer of the semiconductor device structure. It mainly generates a unique and non-replicable identifier through inevitable process errors during the manufacturing process, and generates a challenge-response relationship that is independent of each other between device units on the input and output signals. The plurality of magnetic tunnel junctions 40 in the data storage area 20 can be used as a storage module for storing data.

[0040] In some possible examples, the plurality of magnetic tunnel junctions 40 in the data security area 10 can be arranged in a multi-row and multi-column array. In the formed array, the spacing between any two adjacent magnetic tunnel junctions 40 in the same row can be set to be equal or unequal according to actual needs, or the spacing between any two adjacent magnetic tunnel junctions 40 in the same column can be set to be equal or unequal according to actual needs. The plurality of magnetic tunnel junctions 40 in the data storage area 20 can be arranged in a multi-row and multi-column array. In the formed array, the spacing between any two adjacent magnetic tunnel junctions 40 in the same row can be set to be equal or unequal according to actual needs, or the spacing between any two adjacent magnetic tunnel junctions 40 in the same row can be set to be equal or unequal according to actual needs.

[0041] Preferably, the plurality of magnetic tunnel junctions 40 in the data security area 10 and the data storage area 20 are arranged in an array, that is, the plurality of magnetic tunnel junctions 40 in the data security area 10 and the data storage area 20 are arranged in an array as a whole. The formed array is located in the data security area 10 and the data storage area 20, and the spacing between any two adjacent magnetic tunnel junctions 40 in the same column or the same row is equal. In this way, the plurality of magnetic tunnel junctions 40 in the data security area 10 can be compatible with the manufacturing process of the plurality of magnetic tunnel junctions 40 in the data storage area 20, that is, they can be prepared simultaneously.

[0042] In some possible embodiments, the magnetic tunnel junctions 40 in the data security region 10 have the same structure as the magnetic tunnel junctions 40 in the data storage region 20. Refer to Figure 3 , the magnetic tunnel junction 40 includes a reference layer 43, a barrier layer 42, and a free layer 41 stacked in sequence from top to bottom. The magnetization direction of the reference layer 43 is fixed, the magnetization direction of the free layer 41 can be changed, and the barrier layer 42 separates the reference layer 43 and the free layer 41. When the magnetization directions of the free layer 41 and the reference layer 43 are the same, the magnetic tunnel junction 40 is in a parallel state with a low tunneling magnetoresistance; when the magnetization directions of the free layer 41 and the reference layer 43 are different, the magnetic tunnel junction 40 is in an antiparallel state with a high tunneling magnetoresistance.

[0043] In some possible implementation manners, the material of the free layer 41 is a magnetic material, such as including cobalt iron (CoFe), cobalt iron boron (CoFeB), etc., and the thickness of the free layer 41 is 0.1 nm to 5 nm. The material of the reference layer 43 is a magnetic material, such as including cobalt iron (CoFe), cobalt iron boron (CoFeB), etc., and the thickness of the reference layer 43 is 0.1 nm to 5 nm. The material of the barrier layer 42 is an insulating material, such as including metal oxide materials such as magnesium oxide (MgO), aluminum oxide (Al2O3), etc., and the thickness of the barrier layer 42 is 0.1 nm to 3 nm.

[0044] In other embodiments, the magnetic tunnel junction 40 further includes a pinning layer 44, and the thickness of the pinning layer 44 is 1 nm - 40 nm. The pinning layer 44 is disposed on a side of the reference layer 43 away from the barrier layer 42 for pinning the magnetization direction of the reference layer 43 in a fixed direction, for example, pinning the magnetization direction of the reference layer 43 in its major axis direction. The pinning layer 44 can be a single layer or a stack. Exemplarily, the pinning layer 44 includes a ferromagnetic material layer and an antiferromagnetic material layer, and the ferromagnetic material layer and the antiferromagnetic material layer are alternately stacked.

[0045] For example, the pinning layer 44 includes two opposite ferromagnetic material layers, an antiferromagnetic material layer disposed between the two ferromagnetic material layers, and an antiferromagnetic layer disposed on a side of each ferromagnetic material layer away from the antiferromagnetic material layer. Among them, the two ferromagnetic material layers and the antiferromagnetic material layer form an artificial antiferromagnetic structure. The material of the ferromagnetic material layer includes CoFe, Co, CoFeB, etc., and the material of the antiferromagnetic layer includes manganese alloys, such as IrMn, PtMn, NiMn, FeMn, etc.

[0046] On one side of the pinned layer 44 of the magnetic tunnel junction 40 away from the barrier layer 42, a top electrode 60 is further provided. On one side of the free layer 41 away from the barrier layer 42, a spin-orbit torque layer 50 is further provided, and a bottom electrode, with the bottom electrode being further away from the free layer 41. The spin-orbit torque layer 50 can generate a spin current when current flows through it to generate a torque and change the logic state of the magnetic tunnel junction 40, and the top electrode 60 and the bottom electrode externally connect the magnetic tunnel junction 40.

[0047] Among them, the material of the spin-orbit torque layer 50 is a conductive material with a high spin-charge conversion efficiency, including but not limited to heavy metals (such as W, Pt, etc.), topological insulators (such as Bi2Se3, Bi2Te3, etc.), and antiferromagnetic materials (such as IrMn, PtMn, etc.). The materials of the top electrode 60 and the bottom electrode include metals, such as copper, etc. An auxiliary layer can also be provided between the spin-orbit torque layer 50 and the bottom electrode. The auxiliary layer is used to assist in writing data into the magnetic tunnel junction 40 and reduce dynamic loss, and its materials include thermoelectric materials, piezoelectric materials, etc.

[0048] In the embodiment of the present application, at least some of the magnetic tunnel junctions 40 in the data security region 10 are in the first short-circuit state. Exemplarily, all of the magnetic tunnel junctions 40 in the data security region 10 are in the first short-circuit state. The magnetic tunnel junctions 40 in the first short-circuit state in the data security region 10 are changed from the first short-circuit state to the normal state by applying pressure, and the normal state includes a parallel state or an antiparallel state.

[0049] Among them, the first short-circuit state is usually formed during the preparation process of the semiconductor memory device. Exemplarily, the bottom electrode spacing (the first spacing) between two adjacent magnetic tunnel junctions 40 in the data security region 10 is less than or the bottom electrode spacing of the critical tunnel junction. During the process of etching to form the magnetic tunnel junction 40, more metal redeposition materials can be generated, and it is easier to distribute the generated large amount of metal redeposition materials on the side walls of each magnetic tunnel junction 40.

[0050] The metal redeposition material is in parallel with the magnetic tunnel junction 40 to form a short-circuit state, and this short-circuit state is the first short-circuit state. The resistance value of the magnetic tunnel junction 40 in the first short-circuit state suddenly decreases and is lower than the resistance value of the magnetic tunnel junction 40 in the normal state, corresponding to the data "S". The parallel state means that the magnetization directions between the free layer 41 and the reference layer 43 are the same, corresponding to the data "0". The antiparallel state means that the magnetization directions of the free layer 41 and the reference layer 43 are opposite, corresponding to the data "1".

[0051] In the embodiment of the present application, by applying a voltage, the magnetic tunnel junction 40 in the first short-circuit state in the data security region 10 is changed from the first short-circuit state to the normal state, that is, at least part of the metal redeposition on the side wall of the magnetic tunnel junction 40 is eliminated by using the voltage, so that it is restored to a normal device (specifically, by applying a voltage across the upper and lower ends of the target magnetic tunnel junction). Therefore, compared with the existing PUF module that can only be changed from the normal state to the short-circuit state but cannot be restored to the normal state, the present application can reversibly change the short-circuit state to the normal state for use.

[0052] In the embodiment of the present application, the magnetic tunnel junction 40 in the data security region 10 is in the first short-circuit state. By applying different voltages, different logic states can be obtained. In some possible embodiments, by applying a first preset voltage to the first target magnetic tunnel junction in the data security region 10, part of it is changed to the normal state. Among them, before applying the first preset voltage, the first target magnetic tunnel junction is in the first short-circuit state. After applying the first preset voltage, part of the first target magnetic tunnel junctions are changed to the normal state.

[0053] Among them, the number of the first target magnetic tunnel junctions whose states are changed is positively correlated with the magnitude of the first preset voltage. Refer to Figure 4 , the first preset voltage is between V11 and V16. Before applying the first preset voltage, 100% of the first target magnetic tunnel junctions are in the first short-circuit state. After applying the first preset voltage, part of the first target magnetic tunnel junctions are changed to the normal state, and the remaining first target magnetic tunnel junctions are still in the first short-circuit state. Assume that there are still m% of the first short-circuit states in the first target magnetic tunnel in the data security region 10 under the voltage V13, and V16 = βV13, where β is a constant.

[0054] In some possible embodiments, by applying a second preset voltage to the second target magnetic tunnel junction in the data security region 10, all of them are changed to the normal state. Among them, before applying the second preset voltage, the second target magnetic tunnel junction is in the first short-circuit state. After applying the second preset voltage, all the second target magnetic tunnel junctions are changed to the normal state.

[0055] Refer to Figure 4 , the value of the second preset voltage is greater than or equal to V16, and 0% of the second target magnetic tunnel junctions are in the first short-circuit state, that is, 100% of the second target magnetic tunnel junctions are changed to the normal state. At this time, all the second target magnetic tunnel junctions are changed to the normal state. In addition, in addition to being used as a PUF module to enhance the chip security, the second target magnetic tunnel junction can also be used for data storage to increase the storage capacity of the semiconductor device structure.

[0056] In some possible embodiments, a third preset voltage is applied to a third target magnetic tunnel junction within the data security region 10 to cause at least a part of it to transform into a second short-circuit state. Before the application of the third preset voltage, the third target magnetic tunnel junction is in a first short-circuit state or a normal state. The second short-circuit state means that there is a short circuit between the free layer 41 and the reference layer 43 in the magnetic tunnel junction 40, the resistance value of the magnetic tunnel junction 40 suddenly decreases, and is lower than the resistance value of the magnetic tunnel junction 40 in the normal state, corresponding to the data "S", and the third preset voltage is greater than the second preset voltage.

[0057] Among them, the second short-circuit state is also a short-circuit state. The second short-circuit state is caused by the breakdown of the barrier layer 42, resulting in a short circuit between the free layer 41 and the reference layer 43. The second short-circuit state is irreversible, that is, the second short-circuit state cannot be restored to the normal state, nor can it be restored to the first short-circuit state. The first short-circuit state is caused by the metal re-deposited material appearing on the side wall of the barrier layer 42, resulting in a short circuit between the free layer 41 and the reference layer 43. The first short-circuit state is reversible, that is, the first short-circuit state can be restored to the normal state by applying a voltage.

[0058] In some possible implementation manners, before the application of the third preset voltage, the third target magnetic tunnel junction is in the first short-circuit state. After the application of the third preset voltage, the third target magnetic tunnel junction transforms from the first short-circuit state to the second short-circuit state.

[0059] In some other possible implementation manners, before the application of the third preset voltage, the third target magnetic tunnel junction is in the normal state. After the application of the third preset voltage, the third target magnetic tunnel junction transforms from the normal state to the second short-circuit state. Among them, before the application of the third preset voltage, the third target magnetic tunnel junction can be transformed from the first short-circuit state to the normal state by applying a voltage.

[0060] In some possible embodiments, a fourth preset voltage is applied to a fourth target magnetic tunnel junction within the data security region 10 to cause at least a part of it to transform into an open-circuit state. Among them, before the application of the fourth preset voltage, the fourth target magnetic tunnel junction is in the first short-circuit state or the normal state or the second short-circuit state. The open-circuit state means that the resistance value of the magnetic tunnel junction 40 suddenly increases and is higher than the resistance value of the magnetic tunnel junction 40 in the normal state, corresponding to the data "O". The open-circuit state is caused by the breakdown of the spin-orbit torque layer, resulting in a short circuit between the free layer 41 and the reference layer 43. The open-circuit state is irreversible, that is, the open-circuit state cannot be restored to the second short-circuit state, nor can it be restored to the normal state, nor can it be restored to the first short-circuit state. The fourth preset voltage is greater than the third preset voltage. Refer to Figure 5 , the fourth preset voltage is greater than VBD2, the fourth target magnetic tunnel junction is in the open-circuit state, and the resistance value of the magnetic tunnel junction 40 is high. The third preset voltage is greater than VBD1 and less than VBD2.

[0061] In some possible implementation manners, before applying the fourth preset voltage, the fourth target magnetic tunnel junction is in a first short-circuit state. After applying the fourth preset voltage, the fourth target magnetic tunnel junction changes from the first short-circuit state to an open-circuit state.

[0062] In some other possible implementation manners, before applying the fourth preset voltage, the fourth target magnetic tunnel junction is in a normal state. After applying the fourth preset voltage, the fourth target magnetic tunnel junction changes from the normal state to an open-circuit state. Among them, before applying the fourth preset voltage, the fourth target magnetic tunnel junction can change from the first short-circuit state to the normal state by applying pressure.

[0063] In still some other possible implementation manners, before applying the fourth preset voltage, the fourth target magnetic tunnel junction 40 is in a second short-circuit state. After applying the fourth preset voltage, the fourth target magnetic tunnel junction changes from the second short-circuit state to an open-circuit state. Before applying the fourth preset voltage, the fourth target magnetic tunnel junction can change from the first short-circuit state or the normal state to the second short-circuit state by applying pressure.

[0064] In some preferred embodiments, by applying a first preset voltage to the first target magnetic tunnel junction in the data security region 10, part of it is changed to the normal state. Among them, before applying the first preset voltage, the first target magnetic tunnel junction is in the first short-circuit state. By applying a second preset voltage to the second target magnetic tunnel junction in the data security region 10, all of it is changed to the normal state. Among them, before applying the second preset voltage, the second target magnetic tunnel junction is in the first short-circuit state.

[0065] And by applying a third preset voltage to the third target magnetic tunnel in the data security region 10, at least part of it is changed to the second short-circuit state. Among them, before applying the third preset voltage, the third target magnetic tunnel junction is in the first short-circuit state or the normal state. By applying a fourth preset voltage to the fourth target magnetic tunnel junction in the data security region 10, at least part of it is changed to the open-circuit state. Among them, before applying the fourth preset voltage, the fourth target magnetic tunnel junction is in the first short-circuit state or the normal state or the second short-circuit state. Among them, the first preset voltage < the second preset voltage < the third preset voltage < the fourth preset voltage.

[0066] For example, all the magnetic tunnel junctions 40 in the data security region 10 are in the first short circuit state. A first preset voltage is randomly applied to some of the magnetic tunnel junctions 40 in the data security region 10. Some of the magnetic tunnel junctions 40 to which the first preset voltage is applied are converted into the normal state (parallel state or antiparallel state), and the other part of the magnetic tunnel junctions 40 to which the first preset voltage is applied remains in the first short circuit state. A third preset voltage is applied to some of the magnetic tunnel junctions 40 that are in the first short circuit state and to which the first preset voltage is applied. Some of these magnetic tunnel junctions 40 are converted into the second short circuit state, and the other part of the magnetic tunnel junctions 40 remains in the first short circuit state. Some of the magnetic tunnel junctions 40 in the data security region 10 that are not applied with the first preset voltage are applied with a second preset voltage, and all the magnetic tunnel junctions 40 to which the second preset voltage is applied are converted into the normal state. The other part of the magnetic tunnel junctions 40 is applied with a fourth preset voltage, and all of them are converted into the open state.

[0067] As Figure 1 shown, there are four logic states in total in the magnetic tunnel junctions 40 of the data security region 10: short circuit state (including the first short circuit state and the second short circuit state), parallel state, antiparallel state, and open state. On the basis of not changing the size of the magnetic tunnel junctions 40, the logic states of the magnetic tunnel junctions 40 can be controlled by applying voltage, and a semiconductor memory device with multiple logic states can be formed. This semiconductor memory device can accommodate more magnetic tunnel junctions 40 under the same size, randomly form more types of logic data, increase the inter-chip Hamming distance, and improve the safety factor. At the same time, the magnetic tunnel junctions in the first short circuit state in the data storage region 20 can reversibly return to the normal state, and can further be converted into the second short circuit state or the open state, thereby improving the usage times and service life of the semiconductor memory device, and it can be used up to four times at most.

[0068] By reading the states of several magnetic tunnel junctions 40 in the data security region 10 and generating corresponding keys. Exemplarily, a specific reference circuit is used to determine the resistance states of several magnetic tunnel junctions 40 in the data security region 10, so as to determine the logic states of these several magnetic tunnel junctions 40. Refer to Figure 5 , the resistance values of the magnetic tunnel junctions 40 in the first short circuit state and the second short circuit state (both are Short states) are lower than the resistance values of the magnetic tunnel junctions 40 in the normal state, and the resistance value of the magnetic tunnel junction 40 in the open state (Open state) is higher than the resistance value of the magnetic tunnel junction 40 in the normal state.

[0069] Correspondingly, the binary "11" is used to represent that the magnetic tunnel junction 40 is in the antiparallel state, the binary "01" is used to represent that the magnetic tunnel junction 40 is in the parallel state, the binary "10" is used to represent that the magnetic tunnel junction 40 is in the open state, and the binary "00" is used to represent that the magnetic tunnel junction 40 is in the short-circuit state. Thus, the logical states of several magnetic tunnel junctions 40 in the data security region 10 are combined to form a corresponding key to enhance the security performance.

[0070] Continuing to refer to Figure 1 , at least some of the magnetic tunnel junctions 40 in the data storage region 20 are in the first short-circuit state. Exemplarily, all of the magnetic tunnel junctions 40 in the data storage region 20 are in the first short-circuit state. The magnetic tunnel junctions 40 in the first short-circuit state in the data storage region 20 are changed from the first short-circuit state to the normal state by applying pressure. The normal state includes the parallel state or the antiparallel state.

[0071] The magnetic tunnel junctions 40 in the first short-circuit state in the data storage region 20 can be reversibly restored to the normal state, that is, the magnetic tunnel junctions 40 in the first short-circuit state in the data storage region 20 are changed from the first short-circuit state to the normal state by applying pressure, and can further be changed to the second short-circuit state or the open state, thereby increasing the number of uses and the service life of the semiconductor device structure, and can be used up to four times at most.

[0072] In some possible embodiments, the first short-circuit state is generally formed during the manufacturing process of the semiconductor memory device. Exemplarily, the bottom electrode spacing (second spacing) between two adjacent magnetic tunnel junctions 40 in the data storage region 20 is less than or equal to the bottom electrode spacing of the critical tunnel junction. During the process of etching to form the magnetic tunnel junction 40, more metal re-deposited materials can be generated, and it is easier to distribute a large amount of generated metal re-deposited materials on the sidewalls of each magnetic tunnel junction 40. The metal re-deposited materials are connected in parallel with the magnetic tunnel junction 40 to form a short-circuit state, and this short-circuit state is the first short-circuit state.

[0073] In other examples, the bottom electrode spacing (third spacing) between two adjacent magnetic tunnel junctions 40 in the data security region 10 and the data storage region 20 is less than or equal to the bottom electrode spacing of the critical tunnel junction, so that the sidewalls of the adjacent magnetic tunnel junctions 40 in the data security region 10 and the data storage region 20 are distributed with metal re-deposited materials. Among them, the third spacing, the second spacing, and the first spacing can be equal to facilitate the preparation of the magnetic tunnel junctions 40 in the data security region 10 and the data storage region 20.

[0074] In summary, the semiconductor memory device provided by the embodiment of the present application has a data security area 10 and a data storage area 20. The semiconductor device includes a plurality of magnetic tunnel junctions 40, and the plurality of magnetic tunnel junctions 40 are distributed in the data security area 10 and the data storage area 20. The magnetic tunnel junctions 40 in the first short-circuit state in the data security area 10 are changed from the first short-circuit state to the normal state by applying pressure. The normal state includes the parallel state or the antiparallel state, so that the semiconductor memory device in the first short-circuit state can be restored to a normal device for use. At the same time, after being restored from the first short-circuit state to the normal state, it can be further changed to the second short-circuit state or the open state, thereby increasing the number of times of use and the service life of the semiconductor memory device, and it can be used up to four times at most.

[0075] The embodiments or implementation manners in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. The description with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor memory device, characterized in that: The semiconductor memory device has a data security area and a data storage area, and the semiconductor device includes a plurality of magnetic tunnel junctions, and the plurality of magnetic tunnel junctions are distributed in the data security area and the data storage area; The magnetic tunnel junction in the data security area which is in a first short-circuit state is transformed from the first short-circuit state to a normal state by applying pressure, and is further transformed into a second short-circuit state or an open-circuit state by applying pressure, wherein the normal state includes a parallel state or an anti-parallel state; Wherein, the metal redeposition material generated in the process of etching to form the magnetic tunnel junction is distributed on the sidewall of the magnetic tunnel junction, so that the magnetic tunnel junction has a first short-circuit state.

2. The semiconductor memory device according to claim 1, wherein: All the magnetic tunnel junctions within the data security area are in the first short-circuit state.

3. The semiconductor memory device according to claim 1, wherein: A first preset voltage is applied to the first target magnetic tunnel junction in the data security area to partially transform it into the normal state, wherein before applying the first preset voltage, the first target magnetic tunnel junction is in the first short-circuit state.

4. The semiconductor memory device according to claim 1, wherein: The second target magnetic tunnel junctions in the data security area are all transformed into a normal state by applying a second preset voltage to the second target magnetic tunnel junctions, wherein before applying the second preset voltage, the second target magnetic tunnel junctions are in the first short-circuit state.

5. The semiconductor memory device according to claim 4, wherein: The second target magnetic tunnel junction within the data security area is used for data storage.

6. The semiconductor memory device according to claim 1, wherein: The third target magnetic tunnel in the data security area is at least partially transformed into a second short-circuit state by applying a third preset voltage to the third target magnetic tunnel, wherein before applying the third preset voltage, the third target magnetic tunnel junction is in the first short-circuit state or the normal state.

7. The semiconductor memory device according to claim 1, wherein: The fourth target magnetic tunnel junction in the data security area is at least partially converted into an open-circuit state by applying a fourth preset voltage to the fourth target magnetic tunnel junction, wherein before applying the fourth preset voltage, the fourth target magnetic tunnel junction is in the first short-circuit state, the normal state or the second short-circuit state.

8. The semiconductor memory device according to claim 1, wherein: Applying a first preset voltage to a first target magnetic tunnel junction in the data security region to partially transform the first target magnetic tunnel junction into the normal state, wherein before applying the first preset voltage, the first target magnetic tunnel junction is in the first short-circuit state; Applying a second preset voltage to the second target magnetic tunnel junctions in the data security area to make them all transform into the normal state, wherein before applying the second preset voltage, the second target magnetic tunnel junctions are in the first short-circuit state; Applying a third preset voltage to the third target magnetic tunnel in the data security area to make it at least partially transform into a second short-circuit state, wherein before applying the third preset voltage, the third target magnetic tunnel junction is in the first short-circuit state or the normal state; Applying a fourth preset voltage to a fourth target magnetic tunnel junction in the data security area to at least partially convert it into an open circuit state, wherein before applying the fourth preset voltage, the fourth target magnetic tunnel junction is in the first short circuit state, the normal state, or the second short circuit state; Among them, the first preset voltage<the second preset voltage<the third preset voltage<the fourth preset voltage.

9. The semiconductor memory device according to claim 1, wherein: The states of several magnetic tunnel junctions in the data security area are read and corresponding keys are generated.

10. The semiconductor memory device according to any one of claims 1 to 9, characterized in that: The first short-circuit state is formed during the preparation of the semiconductor memory device.

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