Integrated circuit failure rate sensitivity analysis method, system, device and medium

Abstract

The present invention provides an integrated circuit failure rate sensitivity analysis method, system, device and medium, including: obtaining an original circuit having several design parameters; changing one of the design parameters of the original circuit by a small change to obtain a new circuit; setting a set of compression and expansion factors, and respectively estimating the compression and expansion failure rate and the variance of the compression and expansion failure rate of the original circuit and the compression and expansion failure rate variance of the new circuit based on a scaled variance sampling method for each compression and expansion factor; determining the optimal solution of the sensitivity coefficient of the original circuit failure rate with respect to one of the design parameters based on all the estimation results of the compression and expansion failure rates and the variance of the compression and expansion failure rates of the original circuit and the new circuit; determining the sensitivity of the original circuit failure rate with respect to one of the design parameters based on the optimal solution of the sensitivity coefficient. The present invention can accurately estimate the sensitivity of the extremely low failure rate of the integrated circuit with respect to the circuit design parameters within a limited computational cost.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to an integrated circuit failure rate sensitivity analysis method, system, device and medium. Background Art

[0002] In recent years, with the continuous reduction of the feature size of integrated circuits (ICs) and the continuous improvement of integration, the process deviation introduced in the IC manufacturing process has become increasingly serious. Process deviation can usually be characterized as the mismatch / deviation of device parameters. Although the industry has adopted various methods (such as resolution enhancement technology RET, etc.) to control it, this random fluctuation of device parameters still makes the performance response of the entire chip easily deviate from the design indicators, causing serious failure rate problems. The design and optimization of very large-scale integrated circuits must take the yield / failure rate as a key indicator for system performance optimization. How to improve circuit design to improve the yield has also become a key issue.

[0003] In response to the above problems, the sensitivity of integrated circuit yield / failure rate can be defined to quantify the impact of circuit design parameters (such as the aspect ratio of transistors, etc.) on yield / failure rate. By analyzing the sensitivity of yield / failure rate to different design parameters, on the one hand, it can help designers identify which parameters are the key factors that cause circuit failure, and further understand and reveal the potential mechanism of circuit failure; on the other hand, once the key design factors and failure mechanisms are identified, the circuit design can be optimized based on this information, the circuit performance indicators can be improved, and the yield rate can be increased.

[0004] It is worth noting that it is already very difficult to accurately estimate the yield / failure rate of large-scale integrated circuits. Since current on-chip systems usually contain millions or even tens of millions of circuit units, once a unit fails, the entire system will fail. Therefore, in order to ensure a sufficiently high yield, each unit must have an extremely low failure rate. For example, for an SRAM array containing millions (i.e., 106) bit units, the failure rate of a single unit (i.e., the unit-level failure rate) must be less than 10 −6, otherwise at least one bit cell in the entire array will not work properly, and the entire circuit will fail. To estimate this extremely low failure rate, the traditional Monte Carlo (MC) algorithm requires a large amount of sampling and tube-level simulation, which is too computationally expensive. For large-scale SoC systems, since a tube-level simulation requires a lot of time and computing resources, the cost of MC analysis is almost unbearable. In order to accurately evaluate the failure rate within a limited computing time, a lot of research work has been carried out at home and abroad in recent years, and methods such as Importance Sampling (IS), failure region boundary modeling methods (such as Broken Spheres Method, etc.), Subset Simulation (SUS) methods, Scaled-Sigma Sampling (SSS) circuit performance distribution analytical model methods (such as modeling and analysis methods based on probability distribution functions such as Gaussian distribution function and non-central F distribution function) have been proposed. However, there is currently no relevant solution for the rapid evaluation of yield / failure rate sensitivity of large-scale integrated circuits. Summary of the invention

[0005] The object of the present invention is to provide an integrated circuit failure rate sensitivity analysis method, system, device and medium to accurately estimate the sensitivity of an integrated circuit's extremely low failure rate to circuit design parameters within a limited computing cost.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides an integrated circuit failure rate sensitivity analysis method, comprising:

[0008] Get the original circuit C, which has several design parameters ;

[0009] One of the design parameters of the original circuit C is w d Change-Small Change , to obtain a new circuit C d new ;

[0010] Set a set of compression factors { s q ; q = 1, 2, …, Q}, and for each of the compression and expansion factors s q , respectively estimate the compression and expansion failure rate of the original circuit C based on the scaled variance sampling method and compression failure rate Variance , and the compression and expansion failure rate of the new circuit and compression failure rate Variance ;

[0011] Based on the compression and expansion failure rate of the original circuit C and compression failure rate Variance , and the new circuit C d new The compression failure rate and compression failure rate Variance Q estimation results are used to determine the failure rate of the original circuit C with respect to one of the design parameters w d The optimal solution of the sensitivity coefficient;

[0012] Based on the optimal solution of the sensitivity coefficient, determine the failure rate of the original circuit C with respect to one of the design parameters w d Sensitivity .

[0013] Furthermore, the compression failure rate of the original circuit C is estimated based on the scaled variance sampling method. and compression failure rate Variance ,include:

[0014] According to the corresponding compression factor s q , based on the scaled variance sampling method, the process deviation parameters of the original circuit C are sampled to obtain N q The original circuit sampling points {x (n) ; n = 1, 2, …, N q};

[0015] Based on each of the original circuit sampling points, the original circuit C is simulated using the Monte Carlo method to determine whether each of the original circuit sampling points is invalid;

[0016] According to the results of whether the sampling points of the original circuit are invalid I (x (n) ), estimate the compression and expansion failure rate of the original circuit ;

[0017] The compression and expansion failure rate based on the original circuit , estimate the variance of the compression and expansion failure rate of the original circuit .

[0018] Furthermore, the compression failure rate of the new circuit is estimated based on the scaled variance sampling method. and compression failure rate Variance ,include:

[0019] According to the corresponding compression factor s q , based on the scaled variance sampling method for the new circuit C d new The process deviation parameters are sampled to obtain N d,q new New circuit sampling points {x (m) ; m = 1, 2, ..., N q new};

[0020] Based on each of the new circuit sampling points, the new circuit is analyzed using the Monte Carlo method. C new Performing simulation to determine whether each of the new circuit sampling points fails;

[0021] According to the result of whether each of the new circuit sampling points fails I d new (x (m) ), estimate the compression and expansion failure rate of the new circuit ;

[0022] Companding failure rate based on the new circuit , estimate the variance of the compression failure rate of the new circuit .

[0023] Further, according to the result of whether each of the original circuit sampling points is invalid I (x (n) ), the compression and expansion failure rate of the original circuit is estimated according to the following formula (18): :

[0024] (18)

[0025] The compression and expansion failure rate based on the original circuit , the variance of the compression and expansion failure rate of the original circuit is estimated according to the following formula (20): :

[0026] (20)

[0027] Among them, when Original circuit sampling points When failure occurs, =1, when Original circuit sampling points When not invalid, =0.

[0028] Further, according to the result of whether each of the new circuit sampling points fails , the compression and expansion failure rate of the new circuit is estimated according to the following formula (26): :

[0029] (26)

[0030] Companding failure rate based on the new circuit , the variance of the compression and expansion failure rate of the new circuit is estimated according to the following formula (28): :

[0031] (28)

[0032] Among them, when New circuit sampling points When failure occurs, =1, when New circuit sampling points When not invalid, =0.

[0033] Furthermore, the compression and expansion failure rate based on the original circuit C is and compression failure rate Variance , and the new circuit C d new The compression failure rate and compression failure rate Variance Q estimation results are used to determine the failure rate of the original circuit C with respect to one of the design parameters w d The optimal solution of the sensitivity coefficient includes:

[0034] right Find the logarithm and make a first-order Taylor expansion approximation to get:

[0035] (twenty one)

[0036] Then the vector Satisfies the following joint Gaussian distribution:

[0037] (twenty two)

[0038] in,

[0039] (twenty three)

[0040] (twenty four)

[0041] (25)

[0042] right Find the logarithm and make a first-order Taylor expansion approximation to get:

[0043] (29)

[0044] Then the vector Satisfies the following joint Gaussian distribution:

[0045] (30)

[0046] in,

[0047] (31)

[0048] (32)

[0049] (33)

[0050] According to formulas (22) and (30), when the design parameters w d change When , the change of compression and expansion failure rate satisfies the following Gaussian distribution:

[0051] (34)

[0052] The maximum likelihood method is used to solve the following optimization problem:

[0053] (35)

[0054] in,

[0055] (36)

[0056] Then we get the coefficient The optimal solution is:

[0057] (37)

[0058] in, and is the sensitivity coefficient.

[0059] Further, based on the optimal solution of the sensitivity coefficient, the failure rate of the original circuit C with respect to one of the design parameters is determined according to the following formula (17): w d Sensitivity :

[0060] (17)

[0061] in, and is the sensitivity coefficient.

[0062] In a second aspect, the present invention provides an integrated circuit failure rate sensitivity analysis system, comprising:

[0063] The circuit acquisition module is used to obtain the original circuit C, which has several design parameters. , where D is the total number of design parameters;

[0064] A circuit construction module is used to make one of the design parameters of the original circuit C w d Change-Small Change , to obtain a new circuit C d new ;

[0065] Estimation module, used to set a set of compression factors { s q ; q = 1, 2, ..., Q}, Q is the total number of compression factors, and for each of the compression factors s q , respectively estimate the compression and expansion failure rate of the original circuit C based on the scaled variance sampling method and compression failure rate Variance , and the compression and expansion failure rate of the new circuit and compression failure rate Variance ;

[0066] A coefficient acquisition module for companding failure rate based on the original circuit C and compression failure rate Variance , and the new circuit C d new The compression failure rate and compression failure rate Variance Q estimation results are used to determine the failure rate of the original circuit C with respect to one of the design parameters w d The optimal solution of the sensitivity coefficient;

[0067] A sensitivity acquisition module is used to determine the failure rate of the original circuit C with respect to one of the design parameters based on the optimal solution of the sensitivity coefficient. w d Sensitivity .

[0068] In a third aspect, the present invention provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the integrated circuit failure rate sensitivity analysis method as described above when executing the computer program.

[0069] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the integrated circuit failure rate sensitivity analysis method as described above.

[0070] By adopting the above technical solution, the present invention has the following beneficial effects:

[0071] The present invention is based on a scaled variance sampling method and can accurately analyze the sensitivity between the extremely low failure rate of integrated circuits and the corresponding design parameters within a limited computing cost to quantify the influence of circuit design parameters on the failure rate. It can not only help designers identify the key factors that lead to circuit failure and further understand the potential mechanism of circuit failure, but also once the key design factors and failure mechanisms are identified, the circuit design can be optimized based on this information, the performance indicators can be improved, and the yield rate can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 This is a flow chart of an integrated circuit failure rate sensitivity analysis method according to Embodiment 1 of the present invention;

[0073] Figure 2 This is a structural block diagram of an integrated circuit failure rate sensitivity analysis system according to Embodiment 2 of the present invention;

[0074] Figure 3 This is a hardware architecture diagram of an electronic device according to Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0076] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The singular forms "a", "the" and "the" used in the present disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0077] Before introducing the integrated circuit failure rate sensitivity analysis method, system, device and medium of the present invention, the implementation principle of the present invention is first introduced as follows:

[0078] Assuming the given circuit C The design parameters (such as transistor aspect ratio, etc.) can be used D Dimension variables Characterization; After the process deviation parameters are processed by principal component analysis, they can be used M dimensional independent random variables Characterization. They are independent of each other and have a standard normal distribution with a mean of 0 and a variance of 1. Their joint probability density function (PDF) is f (x) can be expressed as a high-dimensional normal distribution:

[0079] (1)

[0080] here represents the L2 norm of the vector. Then the failure rate of the circuit can be obtained by the following integration:

[0081] (2)

[0082] in:

[0083] (3)

[0084] Here, It represents all failure areas that do not meet the given performance indicators within the process deviation parameter space.

[0085] If a design parameter in the circuit A small change , we get a new circuit C d new Similar to formulas (2)-(3), the failure rate of the new circuit can also be estimated: :

[0086] (4)

[0087] in:

[0088] (5)

[0089] Here, Indicates that within the process deviation parameter space, the new circuit C d new All failure areas that do not meet the given performance indicators. C The failure rate of the design parameters w d The sensitivity of can be defined as:

[0090] (6)

[0091] Here we use the proportion form to evaluate the variable w d When a change occurs, the degree of impact on the failure rate is w d When the ratio changes by a certain percentage, the failure rate will change by how many times.

[0092] It is worth noting that for integrated circuits with extremely low failure rates, only when the sampling point of the process deviation parameter x is located in the probability density function f (x) The circuit will fail only when it is in the tail region. That is to say, within the process deviation space, the probability of sampling to the failure point is very small. And a very large number of samples are required to accurately estimate the extremely low failure rate in this case. P f and Therefore, if formula (6) is used directly to estimate the sensitivity of circuit failure rate, the calculation cost will be very high.

[0093] To address this problem, the compression factor s , by scaling up the standard deviation of x, we can get the compressed probability density function:

[0094] (7)

[0095] Then the circuit C The failure rate after compression and expansion can be expressed as:

[0096] (8)

[0097] If M The dimensional process deviation space is evenly divided to obtain a series of hyperrectangles with the same volume. C The compression failure rate P g ( s ) is approximately:

[0098] (9)

[0099] in, represents the volume of a single hyperrectangle, represents the hyper-rectangular area of ​​all failures. P g ( s ) to find the logarithm:

[0100] (10)

[0101] According to the "soft maximum" theory, we have:

[0102] (11)

[0103] Therefore, the compression and expansion failure rate in the formula P g ( s ) can be expressed as:

[0104] (12)

[0105] in,

[0106] (13)

[0107] Similarly, similar to formula (12), when the design parameters in the circuit are A small change After that, the new circuit C new The compression failure rate The logarithm of can also be expressed as:

[0108] (14)

[0109] The design parameters w d The impact on the compression and expansion failure rate can be quantified as:

[0110] (15)

[0111] If the coefficient can be determined The value of can be determined according to formulas (6) and (15), s = 1, find the design parameters w d The actual failure rate P f Impact:

[0112] (16)

[0113] Then, the failure rate with respect to the design parameters can be calculated based on formula (6): w d Sensitivity:

[0114] (17)

[0115] The problem is that it is difficult to directly determine the coefficients based on their physical definitions (such as formula (13)). and For example, γ is determined by a hyperrectangle falling into the failure region Ω and near the origin x = 0. In practice, it is not possible to directly find the value of γ without knowing the failure region Ω. Therefore, the present application can firstly give the compression factor s A set of reasonable values ​​for s q ; q = 1, 2, ..., Q}. For each value s q , using the Monte Carlo method, based on sampling points, the original circuit can be estimated C The compression and expansion failure rate is:

[0116] (18)

[0117] here Satisfies the following Gaussian distribution:

[0118] (19)

[0119] The variance is:

[0120] (20)

[0121] right Find the logarithm and make a first-order Taylor expansion approximation to get:

[0122] (twenty one)

[0123] therefore, Q dimensional random variable vector Satisfies the following joint Gaussian distribution:

[0124] (twenty two)

[0125] in,

[0126] (twenty three)

[0127] (twenty four)

[0128] (25)

[0129] Similar to the above method, for each value s q , or based on N d,q new sampling points, using the Monte Carlo algorithm to estimate the new circuit C new The compression and expansion failure rate is:

[0130] (26)

[0131] in Satisfies the following Gaussian distribution:

[0132] (27)

[0133] (28)

[0134] Similarly to formula (21), w Find the logarithm and make a first-order Taylor expansion approximation to get:

[0135] (29)

[0136] Then the vector Satisfies the following joint Gaussian distribution:

[0137] (30)

[0138] in,

[0139] (31)

[0140] (32)

[0141] (33)

[0142] Next, according to formulas (22) and (30), when the design parametersw d change When , the change of compression and expansion failure rate satisfies the Gaussian distribution:

[0143] (34)

[0144] Then the maximum likelihood method is used to solve the following optimization problem:

[0145] (35)

[0146] in,

[0147] (36)

[0148] You can get the coefficient The optimal solution is:

[0149] (37)

[0150] Then and Substituting the optimal solution of into formula (17), we can calculate the actual failure rate of the circuit with respect to the design parameters w d sensitivity.

[0151] Example 1

[0152] like Figure 1 As shown, this embodiment provides an integrated circuit failure rate sensitivity analysis method, which specifically includes the following steps:

[0153] S1, obtain the original circuit C, which has several design parameters , where D is the total number of design parameters.

[0154] S2, one of the design parameters of the original circuit C Change-Small Change (Right now wd become ）， Keeping other design parameters unchanged, we can get a new circuit C d new .

[0155] S3, set a set of compression and expansion factors { s q ; q = 1, 2, ..., Q}, Q is the total number of compression factors, and for each compression factor s q Perform the following steps respectively:

[0156] S31, estimation of the compression failure rate of the original circuit C based on the scaled variance sampling method and compression failure rate Variance , the specific process is as follows:

[0157] First, according to the corresponding compression factor s q , based on the scaled variance sampling method, the process deviation parameter x of the original circuit C is sampled to obtain N q Sampling points {x (n) ; n = 1, 2, ..., N q}, recorded as the original circuit sampling point;

[0158] Then, based on the original circuit sampling points {x (n) ; n = 1, 2, ..., N q}, the original circuit C is simulated by using the Monte Carlo method to determine whether each sampling point of the original circuit fails;

[0159] Then, according to the results of whether the sampling points of the original circuit are invalid I (x (n) ), the compression and expansion failure rate of the original circuit C is estimated according to the following formula (18): :

[0160] (18)

[0161] Among them, when Original circuit sampling points When failure occurs, =1, when Original circuit sampling points When it is not invalid, =0.

[0162] Finally, based on the compression and expansion failure rate of the original circuit , estimate the variance of the compression and expansion failure rate of the original circuit :

[0163] (20)

[0164] S32, Estimation of the companding failure rate of new circuits based on scaled variance sampling method and compression failure rate Variance , the specific process is as follows:

[0165] First, according to the corresponding compression factors q , based on the scaled variance sampling method for the new circuit C d new The process deviation parameters are sampled to obtain N d,q new Sampling points {x (m) ; m = 1, 2, ..., N q new}, recorded as the new circuit sampling point;

[0166] Then, based on each new circuit sampling point {x (m) ; m = 1, 2, ..., N q new}, Monte Carlo method is used to analyze the new circuit C new Conduct simulation to determine whether each new circuit sampling point fails;

[0167] Then, according to the results of whether the sampling points of each new circuit are invalid I d new (x (m) ), the compression and expansion failure rate of the new circuit is estimated according to the following formula (26): :

[0168] (26)

[0169] Among them, when New circuit sampling points When failure occurs, =1, when New circuit sampling points When it is not invalid, =0.

[0170] Finally, the compression failure rate based on the new circuit , the variance of the compression failure rate of the new circuit is estimated according to the following formula (28): :

[0171] (28)

[0172] S4, compression and expansion failure rate based on the original circuit C and compression failure rate Variance , and new circuits C d new The compression failure rate and compression failure rate Variance Q estimation results are used to determine the failure rate of the original circuit C with respect to one of the design parameters w d The optimal solution of the sensitivity coefficient is as follows:

[0173] right Find the logarithm and make a first-order Taylor expansion approximation to get:

[0174] (twenty one)

[0175] Then the vector Satisfies the following joint Gaussian distribution:

[0176] (twenty two)

[0177] in,

[0178] (twenty three)

[0179] (twenty four)

[0180] (25)

[0181] right Find the logarithm and make a first-order Taylor expansion approximation to get:

[0182] (29)

[0183] Then the vector Satisfies the following joint Gaussian distribution:

[0184] (30)

[0185] in,

[0186] (31)

[0187] (32)

[0188] (33)

[0189] According to formulas (22) and (30), when the design parameters w d change When , the change of compression and expansion failure rate satisfies the following Gaussian distribution:

[0190] (34)

[0191] The maximum likelihood method is used to solve the following optimization problem:

[0192] (35)

[0193] in,

[0194] (36)

[0195] Then we get the coefficient The optimal solution is:

[0196] (37)

[0197] in, and is the sensitivity coefficient.

[0198] S5, based on sensitivity coefficient and The optimal solution is to determine the failure rate of the original circuit C with respect to one of the design parameters according to the following formula (17): w d Sensitivity :

[0199] (17)

[0200] This embodiment is based on the scaled variance sampling method and can accurately analyze the sensitivity between the extremely low failure rate of the integrated circuit and the corresponding design parameters within a limited computing cost to quantify the impact of the circuit design parameters on the failure rate. It can not only help designers identify the key factors that cause circuit failure and further understand the potential mechanism of circuit failure, but also once the key design factors and failure mechanisms are identified, the circuit design can be optimized based on this information, the performance indicators can be improved, and the yield rate can be increased.

[0201] Example 2

[0202] This embodiment provides an integrated circuit failure rate sensitivity analysis system. Figure 2 As shown, the system includes:

[0203] The circuit acquisition module is used to obtain the original circuit C, which has several design parameters. , where D is the total number of design parameters;

[0204] Circuit building module, used to make one of the design parameters of the original circuit C w d Change-Small Change , to obtain a new circuit C d new ;

[0205] Estimation module, used to set a set of compression factors { s q ; q = 1, 2, ..., Q}, Q is the total number of compression factors, and for each compression factor s q , respectively estimate the compression and expansion failure rate of the original circuit C based on the scaled variance sampling method and compression failure rate Variance , and the compression failure rate of the new circuit and compression failure rate Variance ;

[0206] Coefficient acquisition module, used for compression and expansion failure rate based on the original circuit C and compression failure rate Variance , and new circuits C d new The compression failure rate and compression failure rate Variance Q estimation results are used to determine the failure rate of the original circuit C with respect to one of the design parameters w d The optimal solution of the sensitivity coefficient;

[0207] The sensitivity acquisition module is used to determine the failure rate of the original circuit C with respect to one of the design parameters based on the optimal solution of the sensitivity coefficient. w d Sensitivity .

[0208] In this embodiment, the estimation module estimates the compression and expansion failure rate of the original circuit C based on the following steps: and compression failure rate Variance :

[0209] According to the corresponding compression factor s q , based on the scaled variance sampling method, the process deviation parameters of the original circuit C are sampled to obtain N q The original circuit sampling points {x (n) ; n = 1, 2, ..., N q};

[0210] Based on the sampling points of each original circuit, the Monte Carlo method is used to simulate the original circuit C to determine whether each sampling point of the original circuit fails;

[0211] According to the results of whether the sampling points of each original circuit are invalid I (x (n) ), estimate the compression and expansion failure rate of the original circuit ;

[0212] Companding failure rate based on the original circuit , estimate the variance of the compression and expansion failure rate of the original circuit .

[0213] In this embodiment, the estimation module estimates the variance of the compression and expansion failure rate of the new circuit based on the following steps, including:

[0214] According to the corresponding compression factor s q , based on the scaled variance sampling method for the new circuit C d new The process deviation parameters are sampled to obtain N d,q new New circuit sampling points {x (m) ; m = 1, 2, ..., N q new};

[0215] Based on the sampling points of each new circuit, the Monte Carlo method is used to C new Conduct simulation to determine whether each new circuit sampling point fails;

[0216] According to the results of whether the sampling points of each new circuit are invalid I d new (x (m) ), estimate the compression failure rate of the new circuit ;

[0217] Companding failure rate based on new circuit , estimate the variance of the compression failure rate of the new circuit .

[0218] In this embodiment, the estimation module specifically determines whether each original circuit sampling point is invalid. I (x (n) ), the compression and expansion failure rate of the original circuit is estimated according to the following formula (18): :

[0219] (18)

[0220] The estimation module is based on the compression and expansion failure rate of the original circuit. , the variance of the compression and expansion failure rate of the original circuit is estimated according to the following formula (20): :

[0221] (20)

[0222] Among them, when Original circuit sampling points When failure occurs, =1, when Original circuit sampling points When not invalid, =0.

[0223] In this embodiment, the estimation module specifically determines whether each new circuit sampling point is invalid. , the compression and expansion failure rate of the new circuit is estimated according to the following formula (26): :

[0224] (26)

[0225] The estimation module is specifically based on the compression and expansion failure rate of the new circuit , the variance of the compression failure rate of the new circuit is estimated according to the following formula (28): :

[0226] (28)

[0227] Among them, when New circuit sampling points When failure occurs, =1, when New circuit sampling points When not invalid, =0.

[0228] In this embodiment, the coefficient acquisition module is specifically used for:

[0229] right Find the logarithm and make a first-order Taylor expansion approximation to get:

[0230] (twenty one)

[0231] Then the vector Satisfies the following joint Gaussian distribution:

[0232] (twenty two)

[0233] in,

[0234] (twenty three)

[0235] (twenty four)

[0236] (25)

[0237] right Find the logarithm and make a first-order Taylor expansion approximation to get:

[0238] (29)

[0239] Then the vector Satisfies the following joint Gaussian distribution:

[0240] (30)

[0241] in,

[0242] (31)

[0243] (32)

[0244] (33)

[0245] According to formulas (22) and (30), when the design parameters w d change When , the change of compression and expansion failure rate satisfies the following Gaussian distribution:

[0246] (34)

[0247] The maximum likelihood method is used to solve the following optimization problem:

[0248] (35)

[0249] in,

[0250] (36)

[0251] Then we get the coefficient The optimal solution is:

[0252] (37)

[0253] in, and is the sensitivity coefficient.

[0254] In this embodiment, the sensitivity acquisition module is specifically used to determine the failure rate of the original circuit C with respect to one of the design parameters according to the following formula (17): wd Sensitivity :

[0255] (17)

[0256] in, and is the sensitivity coefficient.

[0257] This embodiment is based on the scaled variance sampling method and can accurately analyze the sensitivity between the extremely low failure rate of the integrated circuit and the corresponding design parameters within a limited computing cost to quantify the impact of the circuit design parameters on the failure rate. It can not only help designers identify the key factors that cause circuit failure and further understand the potential mechanism of circuit failure, but also once the key design factors and failure mechanisms are identified, the circuit design can be optimized based on this information, the performance indicators can be improved, and the yield rate can be increased.

[0258] Example 3

[0259] The present embodiment provides an electronic device, which can be expressed in the form of a computing device (for example, a server device), including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the steps of the integrated circuit failure rate sensitivity analysis method provided in Embodiment 1 can be implemented when the processor executes the computer program.

[0260] Figure 3 FIG. 4 shows a schematic diagram of the hardware structure of this embodiment. Figure 3 As shown, the electronic device 30 specifically includes:

[0261] At least one processor 31, at least one memory 32, and a bus 33 for connecting different system components (including the processor 31 and the memory 32), wherein:

[0262] The bus 33 includes a data bus, an address bus, and a control bus.

[0263] The memory 32 includes a volatile memory, such as a random access memory (RAM) 321 and / or a cache memory 322 , and may further include a read-only memory (ROM) 323 .

[0264] The memory 32 also includes a program / utility 325 having a set (at least one) of program modules 324, such program modules 324 including but not limited to: an operating system, one or more application programs, other program modules and program data, each of which or some combination may include an implementation of a network environment.

[0265] The processor 31 executes various functional applications and data processing by running the computer program stored in the memory 32, such as the steps of the integrated circuit failure rate sensitivity analysis method provided in Embodiment 1 of the present invention.

[0266] The electronic device 30 can further communicate with one or more external devices 34 (e.g., keyboards, pointing devices, etc.). Such communication can be performed through an input / output (I / O) interface 35. In addition, the electronic device 30 can also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) through a network adapter 36. The network adapter 36 communicates with other modules of the electronic device 30 through a bus 33. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 30, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.

[0267] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0268] Example 4

[0269] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps of the integrated circuit failure rate sensitivity analysis method provided in Embodiment 1 are implemented.

[0270] The readable storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.

[0271] In a possible implementation manner, the present invention can also be implemented in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps of the integrated circuit failure rate sensitivity analysis method provided in Example 1.

[0272] Among them, the program code for executing the present invention can be written in any combination of one or more programming languages, and the program code can be executed completely on the user device, partially on the user device, as an independent software package, partially on the user device and partially on a remote device, or completely on the remote device.

[0273] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. A method for analyzing the sensitivity of integrated circuit failure rate, characterized in that: include: Get the original circuit C, which has several design parameters ; One of the design parameters of the original circuit C is w d Change-Small Change , to obtain a new circuit C d new ; Set a set of compression factors { s q ; q = 1, 2, …, Q }, and for each of the compression and expansion factors s q , respectively estimate the compression and expansion failure rate of the original circuit C based on the scaled variance sampling method and compression failure rate Variance , and the compression and expansion failure rate of the new circuit and compression failure rate Variance ; Based on the compression and expansion failure rate of the original circuit C and compression failure rate Variance , and the new circuit C d new The compression failure rate and compression failure rate Variance Q estimation results are used to determine the failure rate of the original circuit C with respect to one of the design parameters w d The optimal solution of the sensitivity coefficient; Based on the optimal solution of the sensitivity coefficient, determine the failure rate of the original circuit C with respect to one of the design parameters w d Sensitivity ; The scaling variance sampling method is used to estimate the compression and expansion failure rate of the original circuit C. and compression failure rate Variance ,include: According to the corresponding compression factor s q , based on the scaled variance sampling method, the process deviation parameters of the original circuit C are sampled to obtain N q The original circuit sampling points {x (n) ; n = 1, 2, …, N q }; Based on each of the original circuit sampling points, the original circuit C is simulated using the Monte Carlo method to determine whether each of the original circuit sampling points is invalid; According to the results of whether the sampling points of the original circuit are invalid I (x (n) ), estimate the compression and expansion failure rate of the original circuit ; The compression and expansion failure rate based on the original circuit , estimate the variance of the compression and expansion failure rate of the original circuit ; The scaling variance sampling method is used to estimate the compression failure rate of the new circuit and compression failure rate Variance ,include: According to the corresponding compression factor s q , based on the scaled variance sampling method for the new circuit C d new The process deviation parameters are sampled to obtain N d,q new New circuit sampling points {x (m) ; m = 1, 2, ..., N q new }; Based on each of the new circuit sampling points, the new circuit is analyzed using the Monte Carlo method. C new Performing simulation to determine whether each of the new circuit sampling points fails; According to the result of whether each of the new circuit sampling points fails I d new (x (m) ), estimate the compression and expansion failure rate of the new circuit ; Companding failure rate based on the new circuit , estimate the variance of the compression failure rate of the new circuit .

2. The sensitivity analysis method according to claim 1, characterized in that: According to the results of whether the sampling points of the original circuit are invalid I (x (n) ), the compression and expansion failure rate of the original circuit is estimated according to the following formula (18): : (18) The compression and expansion failure rate based on the original circuit , the variance of the compression and expansion failure rate of the original circuit is estimated according to the following formula (20): : (20) Among them, when Original circuit sampling points When failure occurs, =1, when Original circuit sampling points When not invalid, =0.

3. The sensitivity analysis method according to claim 1, characterized in that: According to the result of whether each of the new circuit sampling points fails , the compression and expansion failure rate of the new circuit is estimated according to the following formula (26): : (26) Companding failure rate based on the new circuit , the variance of the compression and expansion failure rate of the new circuit is estimated according to the following formula (28): : (28) Among them, when New circuit sampling points When failure occurs, =1, when New circuit sampling points When not invalid, =0.

4. The sensitivity analysis method according to claim 1, characterized in that: The compression and expansion failure rate based on the original circuit C and compression failure rate Variance , and the new circuit C d new The compression failure rate and compression failure rate Variance Q estimation results are used to determine the failure rate of the original circuit C with respect to one of the design parameters w d The optimal solution of the sensitivity coefficient includes: right Find the logarithm and make a first-order Taylor expansion approximation to get: (21) Then the vector Satisfies the following joint Gaussian distribution: (22) in, (23) (24) (25) right Find the logarithm and make a first-order Taylor expansion approximation to get: (29) Then the vector Satisfies the following joint Gaussian distribution: (30) in, (31) (32) (33) According to formulas (22) and (30), when the design parameters w d change When , the change of compression and expansion failure rate satisfies the following Gaussian distribution: (34) The maximum likelihood method is used to solve the following optimization problem: (35) in, (36) Then we get the coefficient The optimal solution is: (37) in, and is the sensitivity coefficient.

5. The sensitivity analysis method according to claim 1, characterized in that: Based on the optimal solution of the sensitivity coefficient, the failure rate of the original circuit C with respect to one of the design parameters is determined according to the following formula (17): w d Sensitivity : (17) in, and is the sensitivity coefficient.

6. An integrated circuit failure rate sensitivity analysis system, characterized in that: include: The circuit acquisition module is used to obtain the original circuit C, which has several design parameters. , where D is the total number of design parameters; A circuit construction module is used to make one of the design parameters of the original circuit C w d Change-Small Change , to obtain a new circuit C d new ; Estimation module, used to set a set of compression factors { s q ; q = 1, 2, ..., Q }, Q is the total number of compression factors, and for each of the compression factors s q , respectively estimate the compression and expansion failure rate of the original circuit C based on the scaled variance sampling method and compression failure rate Variance , and the compression and expansion failure rate of the new circuit and compression failure rate Variance ; A coefficient acquisition module for companding failure rate based on the original circuit C and compression failure rate Variance , and the new circuit C d new The compression failure rate and compression failure rate Variance Q estimation results are used to determine the failure rate of the original circuit C with respect to one of the design parameters w d The optimal solution of the sensitivity coefficient; A sensitivity acquisition module is used to determine the failure rate of the original circuit C with respect to one of the design parameters based on the optimal solution of the sensitivity coefficient. w d Sensitivity ; The estimation module estimates the compression and expansion failure rate of the original circuit C based on the following steps: and compression failure rate Variance : According to the corresponding compression factor s q , based on the scaled variance sampling method, the process deviation parameters of the original circuit C are sampled to obtain N q The original circuit sampling points {x (n) ; n = 1, 2, …, N q }; Based on each of the original circuit sampling points, the original circuit C is simulated using the Monte Carlo method to determine whether each of the original circuit sampling points is invalid; According to the results of whether the sampling points of the original circuit are invalid I (x (n) ), estimate the compression and expansion failure rate of the original circuit ; The compression and expansion failure rate based on the original circuit , estimate the variance of the compression and expansion failure rate of the original circuit ; The estimation module estimates the compression and expansion failure rate of the new circuit based on the following steps: and compression failure rate Variance : According to the corresponding compression factor s q , based on the scaled variance sampling method for the new circuit C d new The process deviation parameters are sampled to obtain N d,q new New circuit sampling points {x (m) ; m = 1, 2, ..., N q new }; Based on each of the new circuit sampling points, the new circuit is analyzed using the Monte Carlo method. C new Performing simulation to determine whether each of the new circuit sampling points fails; According to the result of whether each of the new circuit sampling points fails I d new (x (m) ), estimate the compression and expansion failure rate of the new circuit ; Companding failure rate based on the new circuit , estimate the variance of the compression failure rate of the new circuit .

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that: When the processor executes the computer program, the steps of the integrated circuit failure rate sensitivity analysis method according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the integrated circuit failure rate sensitivity analysis method according to any one of claims 1 to 5 are implemented.

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