A time-series ECO method, system, and medium based on resynthesis

Abstract

This invention discloses a timing ECO method, system, and medium based on resynthesis. Leveraging the powerful timing optimization capabilities of synthesis tools, the method generates a new netlist with shorter critical paths using tightened timing constraints. Based on this, an algorithm uses the optimized logic structure in the new netlist to partially replace critical paths in the old netlist, while preserving as much of the original logic as possible. This achieves timing repair with minimal modification to the old netlist. The invention aims to use the optimized logic structure in the new netlist to partially replace critical paths in the old netlist, while preserving as much of the original logic as possible. This achieves timing repair with minimal modification to the old netlist, enabling low-cost, high-efficiency, and quick resolution of serious timing violations occurring in the later stages of chip design, saving significant manpower and time, and shortening the chip design cycle.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design automation, and specifically to a timing ECO method, system, and medium based on resynthesis. Background Technology

[0002] ECO (Engineering Change Order) refers to a small-scale adjustment made by designers in the later stages of the design process based on issues revealed in static timing analysis and post-simulation. This adjustment aims to optimize the circuit and standard cell layout while maintaining the original design layout and routing, correcting remaining violations and ultimately meeting chip approval standards. With the increasing complexity of IC (Integrated Circuit) design, ECO technology has become essential for resolving functional and / or timing defects discovered in the later stages of design. To correct timing violations in the later stages, backend designers typically adjust gate sizes and buffer insertions during the ECO process. However, these methods are insufficient for more severe timing violations, such as incorrect timing constraints set by the synthesis engineer or changes in frontend timing requirements.

[0003] When the situations described above exist, traditional timing ECO methods are insufficient. This often necessitates extensive logic refactoring of the netlist to reduce the number of logic levels. If this is delegated manually to designers, it results in a massive workload and is highly prone to errors. Currently, the industry standard solution for such situations is to restart the physical design, which undoubtedly increases project costs and extends the chip design cycle. Therefore, to reduce costs, accelerate the design cycle, and minimize the additional workload for designers, it is necessary to research more powerful incremental timing ECO techniques to improve the handling capacity of timing violations.

[0004] For integrated circuit design, due to the long physical design cycle, physical design usually begins only after the register-transfer-level (RTL) netlist is frozen. However, if the front-end timing requirements change or incorrect timing constraints are found during synthesis in the later stages of physical design, serious timing violations will occur in the back-end, which usually cannot be repaired by conventional timing optimization methods. Summary of the Invention

[0005] The technical problem to be solved by this invention is to provide a timing ECO method, system, and medium based on resynthesis, which addresses the above-mentioned problems in the prior art. This invention aims to use the optimized logic structure in the new netlist to partially replace the critical path in the old netlist, while preserving as much of the original logic in the old netlist as possible. It can achieve the purpose of timing repair with minimal modification to the old netlist, and solve serious timing violations that occur in the later stages of chip design in a low-cost, high-efficiency, and short-time manner, saving a lot of manpower and time and shortening the chip design cycle.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A time-series ECO method based on resynthesis includes the following steps:

[0008] S101 reads circuit information, including the old netlist G1 that needs timing ECO, and the new netlist G2 generated by resynthesizing the RTL code based on the old netlist G1 with tightened timing constraints. In the setup script, it sets the equivalence information file, standard cell library, timing constraint file, and timing violation path information; and converts the read circuit information into data structures in the program.

[0009] S102, match the old netlist G1 and the new netlist G2;

[0010] S103, Locate the combinational logic block C1 where the timing violation path is located in the old netlist G1, and extract the combinational logic block C2 that matches the combinational logic block C1 in the new netlist G2 according to the matching relationship.

[0011] S104, use the method of combining simulation and SAT solver to locate equivalent points and store the mapping relationship between equivalent points. Two points with a mapping relationship are called equivalent points. The equivalent point refers to the Boolean equivalence of the net of combinational logic block C1 with one or more nets in combinational logic block C2.

[0012] S105, establish network flow model M1 for combinational logic block C1 and network flow model M2 for combinational logic block C2;

[0013] S106, calculate the timing information of combinational logic block C1 and combinational logic block C2 respectively, and assign weights to each edge in network flow model M1 and M2 based on the calculated timing information;

[0014] S107, use the maximum flow algorithm to calculate the maximum flow for network flow models M1 and M2 respectively, generate corresponding residual networks, use the residual networks to calculate cut sets, and perform cut set matching. Through the matching relationship, merge the right part of combinational logic block C1 and the left part of combinational logic block C2 along the tangent to generate a new combinational logic block C1′. The part that belongs to combinational logic block C2 before merging is the modified part of the circuit.

[0015] S108, apply the new combinational logic block C1′ to the old netlist G1 as the output of netlist G1′ after timing ECO.

[0016] Optionally, when matching the old netlist G1 and the new netlist G2 in step S102, key points including timing units, module input / output ports, and IP module input / output ports are matched using a name matching method.

[0017] Optionally, step S104 includes:

[0018] S201, Connect the main inputs of combinational logic block C1 and combinational logic block C2 in pairs according to the matching relationship to generate a new set of main inputs PI′;

[0019] S202, assign a set of random simulated values ​​to the new main input PI′, so that the main inputs of combinational logic block C1 and combinational logic block C2 obtain the same random simulated values;

[0020] S203, according to the circuit logic relationship, the random analog value is propagated to each net in the circuit of combinational logic block C1 and combinational logic block C2, and the analog value of each net is recorded.

[0021] S204, group the nets according to the simulated values, and the nets with the same simulated values ​​are a candidate equivalent group CG;

[0022] S205, assign an input mask to each input in the new master input PI′, propagate the input mask backward, and calculate the input signature for each net;

[0023] S206, Based on the input signature, further classify the obtained candidate equivalence group CG, remove potential non-equivalence points, and obtain a new candidate equivalence group CG′;

[0024] S207, use the SAT solver to perform pairwise verification on the nets in the new candidate equivalence group CG′. Simultaneously, consider N equivalence and mark the nets that satisfy the verification result as equivalent points. Store the equivalence information of the equivalence points in the circuit equivalence information EQ_Info obtained by locating the equivalence points. The circuit equivalence information EQ_Info stores the equivalence relationship between each group of equivalence points, and each group of equivalence points is accompanied by an equivalence mark. The equivalence mark is either the direct equivalence mark POSITIVE_EQUAL or the N equivalence mark NEGATIVE_EQUAL. N equivalence means that the logic of the two nets is mutually inverted.

[0025] Optionally, step S105 includes:

[0026] S301, a directed graph D1 is established for combinational logic block C1, and a directed graph D2 is established for combinational logic block C2. The nodes in the directed graphs D1 and D2 correspond to the logic units in the combinational logic block circuit, and the edges correspond to the connections between pins. The mapping relationship between combinational logic blocks C1 and C2 and directed graphs D1 and D2 is stored.

[0027] S302, add a source node S to directed graph D1, add directed edges to all input nodes in directed graph D1 such that source node S points to all input nodes through directed edges, add a sink node T to directed graph D1, add directed edges to all output nodes in directed graph D1 such that all output nodes point to sink node T through directed edges; add a source node S to directed graph D2, add directed edges to all input nodes in directed graph D2 such that source node S points to all input nodes through directed edges, add a sink node T to directed graph D2, add directed edges to all output nodes in directed graph D2 such that all output nodes point to sink node T through directed edges;

[0028] S303, add a reverse edge to each edge in directed graphs D1 and D2, store all edges in an array, and make the forward edge index adjacent to the corresponding reverse edge index, thereby obtaining the network flow model M1 of combinational logic block C1 and the network flow model M2 of combinational logic block C2.

[0029] Optionally, step S106 includes:

[0030] S401 calculates the equivalent logic levels for combinational logic blocks C1 and C2.

[0031] S402, using the maximum equivalent logic level of combinational logic block C2, calculate the net relaxation value Slack for combinational logic blocks C1 and C2. For an N-input M-output logic gate G... i The relaxation value of any input wire j The expression for the computation function is:

[0032] ,

[0033] In the above formula, This indicates taking the minimum value. ~ These are logic gates G i The relaxation values ​​of output ports 0 to M-1 This indicates taking the maximum value. ~ Don't use logic gate G i The equivalent logic levels of input ports 0 to N-1, This represents the equivalent logic level of the input net j;

[0034] S403, use the circuit equivalence information EQ_Info obtained in step S207 to assign weights to the edges in the directed graph D1. If a certain net in combinational logic block C1 has a net that is equivalent to another net in another combinational logic block C2, then set the weight to 0; otherwise, set the weight to the preset maximum integer constant F_Max.

[0035] S404, using the timing information obtained in steps S401 and S402, update the relaxation value of the corresponding wire mesh for any edge i that was assigned a weight of 0 in step S403 according to the following formula. :

[0036] ,

[0037] In the above formula, This represents the original relaxation value of the net before it was updated, slack. i A value greater than 1 indicates that the edge is a non-temporal violation path, slack i A weight of 1 indicates that the edge is a temporal violation path; then, it is determined whether the temporal optimization of any edge i assigned a weight of 0 meets the requirements. If the temporal optimization fails, and edge i is not a temporal violation path, the weight of edge i is updated according to the following formula:

[0038] ,

[0039] If edge i is a temporal violation path, then update the weight of edge i according to the following formula:

[0040] ,

[0041] Once the time-series optimization has been achieved, the weight of edge i is updated according to the following formula:

[0042] ,

[0043] in, Let i be the weight of edge i. , , A constant factor, This indicates the degree of improvement in the logic level of a certain net in combinational logic block C2 compared to the equivalent logic level of the net in combinational logic block C1 that is equivalent to it. Let i be the equivalent logical series of edge i. Let C1 be the maximum logic level of the combinational logic block. It is the maximum logic level of combinational logic block C2.

[0044] Optionally, in step S401, when calculating the equivalent logic levels for combinational logic blocks C1 and C2, for a logic gate G with N inputs... i The expression for the calculation function of the equivalent logic series of the output net j is:

[0045] ,

[0046] In the above formula, This represents the equivalent logic series of net j; This indicates taking the maximum value. ~ These are logic gates G i The equivalent logic levels of input ports 0 to N-1, Represents logic gate G i Its own delay (used to replace the internal delay of the logic gate), its value is G. i Half of the input pin; This represents the fanout number of net j (used to replace the load capacitance of the net).

[0047] Optionally, step S107 includes:

[0048] S501, run the maximum flow algorithm on the network flow model M1 to obtain the residual network M1′. If the maximum flow value F1 returned by the maximum flow algorithm is greater than the preset maximum integer constant F_Max, it is determined that there is no solution, and the process ends and exits; otherwise, jump to step S502.

[0049] S502, Start a depth-first traversal from the source node of the residual network M1′. When an edge with a flow of 0 is encountered, the traversal ends and the process returns. The edge with a flow of 0 refers to the edge with a weight of 0 in the residual network M1′. Mark the traversed nodes.

[0050] S503, traverse all positive edges in the residual network M1′. If one of the nodes connected to its two ends is marked and the other is not marked, then the edge is a cut edge. All cut edges form a cut set T1. At the same time, record the net corresponding to the edge in the cut set T1 and store it in the set S1.

[0051] S504. Using the circuit equivalence information EQ_Info obtained in step S207, traverse all edges in the network flow model M2. If its net is equivalent to the net in set S1, then set the weight of the edge to 0.

[0052] S505, run the maximum flow algorithm on the network flow model M2 to obtain the residual network M2′. If the maximum flow value F2 returned by the maximum flow algorithm is greater than the preset maximum integer constant F_Max, it is determined that there is no solution, and the process ends and exits; otherwise, jump to step S506.

[0053] S506: Start from the source node in the residual network M2′ and perform a depth-first traversal. When an edge with a flow of 0 is encountered, the traversal ends and returns. Mark the traversed nodes.

[0054] S507, Traverse all positive edges in the residual network M2′. If one of the nodes connected to the edge is marked and the other is not marked, then the edge is a cut edge. All cut edges form a cut set T2.

[0055] S508, using the circuit equivalence information EQ_Info obtained in step S207, the edges in cut set T1 and cut set T2 are matched with each other to generate a matching relationship R. The matching relationship R stores the equivalence relationships of all edges in cut set T1 and cut set T2.

[0056] S509 uses cut sets T1 and T2 and matching relation R to cut and merge combinational logic blocks C1 and C2. During merging, if the net equivalence relation of the two pins to be connected is POSITIVE_EQUAL, they are directly connected; if the net equivalence relation of the two pins to be connected is NEGATIVE_EQUAL, an inverter needs to be inserted in the middle of the connection. The merged combinational logic block is the new combinational logic block C1′, where the part that belonged to combinational logic block C2 before merging is the modified part of the circuit.

[0057] Furthermore, the present invention also provides a timing ECO system based on resynthesis, including an interconnected microprocessor and a memory, wherein the microprocessor is programmed or configured to execute the timing ECO method based on resynthesis.

[0058] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program or instructions that are programmed or configured to execute the resynthesis-based timing ECO method by a processor.

[0059] Furthermore, the present invention also provides a computer program product, including a computer program or instructions that are programmed or configured to execute the resynthesis-based timing ECO method via a processor.

[0060] Compared with existing technologies, this invention has the following advantages: This invention provides a method for quickly repairing serious timing violations that occur in the later stages of physical design. Leveraging the powerful timing optimization capabilities of synthesis tools, it uses a resynthesis strategy to assist the old netlist in timing optimization, which can quickly reduce the timing convergence difficulty and accelerate the timing convergence speed during the physical design phase. This invention is applicable to various types of digital chip designs, accurately locates timing violation paths, and minimizes the impact on the old netlist. This invention saves significant manpower and time costs and shortens the chip design cycle. Attached Figure Description

[0061] Figure 1 This is a schematic diagram of the implementation process in an embodiment of the present invention.

[0062] Figure 2 This is a schematic diagram of extracting combinational logic blocks with matching points as boundaries in an embodiment of the present invention.

[0063] Figure 3 This is a schematic diagram of the equivalence point search strategy in an embodiment of the present invention.

[0064] Figure 4 This is a schematic diagram of the input signature calculation method in an embodiment of the present invention.

[0065] Figure 5 This is a schematic diagram of a network flow model with added source and sink nodes in an embodiment of the present invention.

[0066] Figure 6 This is a schematic diagram of the circuit cutting and merging algorithm in an embodiment of the present invention.

[0067] Figure 7 This is a schematic diagram of the combinational logic block after ECO in an embodiment of the present invention. Detailed Implementation

[0068] This invention relates to the field of integrated circuit design automation, specifically to a method for timing optimization of an old netlist requiring timing repair by using a newly synthesized netlist to assist in such optimization. This method is used to optimize and repair serious timing violations discovered in the later stages of integrated circuit design. Figure 1 As shown, the timing ECO method based on resynthesis in this embodiment includes the following steps:

[0069] S101 reads circuit information, including the old netlist G1 that requires timing ECO, and the new netlist G2 generated by resynthesizing the RTL code based on the old netlist G1 with tightened timing constraints. The setup script sets the equivalence information (SetupVerification for Formality) file (.svf file), standard cell library (.lib file), timing constraint file (.sdc file), and timing violation path information; it then converts the read circuit information into data structures in the program.

[0070] S102, match the old netlist G1 and the new netlist G2;

[0071] S103, locate the combinational logic block C1 containing the timing violation path in the old netlist G1, and extract the combinational logic block C2 that matches combinational logic block C1 in the new netlist G2 according to the matching relationship; such as Figure 2 As shown, when locating the combinational logic block C1 where the timing violation path is located in the old netlist G1, the timing violation path (critical path) in the old netlist G1 can be located, and the combinational logic involved in the path can be extracted as a combinational logic block C1.

[0072] S104, use a combination of simulation and SAT solver to locate equivalence points and store the mapping relationship between equivalence points. Two points with a mapping relationship are called equivalence points. The equivalence point refers to the Boolean equivalence between the net of combinational logic block C1 and one or more nets in combinational logic block C2.

[0073] S105, establish network flow model M1 for combinational logic block C1 and network flow model M2 for combinational logic block C2;

[0074] S106, calculate the timing information of combinational logic block C1 and combinational logic block C2 respectively, and assign weights to each edge in network flow model M1 and M2 based on the calculated timing information;

[0075] S107, use the maximum flow algorithm to calculate the maximum flow for network flow models M1 and M2 respectively, generate corresponding residual networks, use the residual networks to calculate cut sets, and perform cut set matching. Through the matching relationship, merge the right part of combinational logic block C1 and the left part of combinational logic block C2 along the tangent to generate a new combinational logic block C1′. The part that belongs to combinational logic block C2 before merging is the modified part of the circuit.

[0076] S108, apply the new combinational logic block C1′ to the old netlist G1 as the output of netlist G1′ after timing ECO.

[0077] In step S102 of this embodiment, when matching the old netlist G1 and the new netlist G2, key points including timing units, module input / output ports, and IP module input / output ports are matched using a name matching method.

[0078] In this embodiment, step S104 includes:

[0079] S201, Connect the primary inputs of combinational logic block C1 and combinational logic block C2 in pairs according to the matching relationship to generate a new set of primary inputs PI′;

[0080] S202, assign a set of random simulated values ​​to the new main input PI′, so that the main inputs of combinational logic block C1 and combinational logic block C2 obtain the same random simulated values;

[0081] S203, according to the circuit logic relationship, the random analog value is propagated to each net in the circuit of combinational logic block C1 and combinational logic block C2, and the analog value of each net is recorded.

[0082] S204, group the nets according to the simulated values, and the nets with the same simulated values ​​are a candidate equivalent group CG;

[0083] S205, assign an input mask to each input in the new master input PI′, propagate the input masks backward, and calculate the input signature for each net. Figure 4 This is a diagram illustrating the calculation of an input signature. Figure 4 In the diagram, the input mask chalk for PI0 to PI4 is 00001, 00010, 00100, 01000, 100000. For example, the input signature of signal in2 obtained by passing PI1 and PI2 through a NAND gate is 00110, and the input signature of signal out obtained by passing PI0 (00001) and signal in2 (00110) through a NAND gate G is 00111, and so on.

[0084] S206, Based on the input signature, further classify the obtained candidate equivalence group CG, remove potential non-equivalence points, and obtain a new candidate equivalence group CG′;

[0085] S207, use the SAT solver to perform pairwise verification on the nets in the new candidate equivalence group CG′. Simultaneously, considering N-equivalence, nets whose verification results satisfy each other are marked as equivalent points, and the equivalence information of these points is stored in the circuit equivalence information EQ_Info obtained from locating the equivalence points. The circuit equivalence information EQ_Info stores the equivalence relationship between each group of equivalence points, and each group of equivalence points is accompanied by an equivalence marker, which is either a direct equivalence marker POSITIVE_EQUAL or an N-equivalence marker NEGATIVE_EQUAL; N-equivalence means that the logic of the two nets is mutually inverted. For example... Figure 3 As shown, the SAT solver can determine whether a net of combinational logic block C1 is equivalent to a net of combinational logic block C2. Figure 2 The “random input vector” in this context is the random simulated value in step S202.

[0086] In this embodiment, step S105 includes:

[0087] S301, a directed graph D1 is established for combinational logic block C1, and a directed graph D2 is established for combinational logic block C2. The nodes in the directed graphs D1 and D2 correspond to the logic units in the combinational logic block circuit, and the edges correspond to the connections between pins. The mapping relationship between combinational logic blocks C1 and C2 and directed graphs D1 and D2 is stored.

[0088] S302: Add a source node S to directed graph D1, add directed edges to all input nodes in directed graph D1 such that source node S points to all input nodes through directed edges, add a sink node T to directed graph D1, and add directed edges to all output nodes in directed graph D1 such that all output nodes point to sink node T through directed edges; add a source node S to directed graph D2, add directed edges to all input nodes in directed graph D2 such that source node S points to all input nodes through directed edges, add a sink node T to directed graph D2, and add directed edges to all output nodes in directed graph D2 such that all output nodes point to sink node T through directed edges; an example is as follows. Figure 5 As shown, S is the source node, T is the sink node, and V1-V12 are nodes. The dashed arrows represent edges that originate from the source node S and reach the sink node T, while the solid arrows represent edges that are ordinary nodes V1-V12.

[0089] S303, add a reverse edge to each edge in directed graphs D1 and D2, store all edges in an array, and make the forward edge index adjacent to the corresponding reverse edge index, thereby obtaining the network flow model M1 of combinational logic block C1 and the network flow model M2 of combinational logic block C2.

[0090] In this embodiment, step S106 includes:

[0091] S401 calculates the equivalent logic levels for combinational logic blocks C1 and C2.

[0092] S402, using the maximum equivalent logic level of combinational logic block C2, calculate the net relaxation value Slack for combinational logic blocks C1 and C2. For an N-input M-output logic gate G... i The relaxation value of any input wire j The expression for the computation function is:

[0093] ,

[0094] In the above formula, This indicates taking the minimum value. ~ These are logic gates G i The relaxation values ​​of output ports 0 to M-1 This indicates taking the maximum value. ~ Don't use logic gate G i The equivalent logic levels of input ports 0 to N-1, This represents the equivalent logic level of the input net j;

[0095] S403, use the circuit equivalence information EQ_Info obtained in step S207 to assign weights to the edges in the directed graph D1. If a certain net in combinational logic block C1 has a net that is equivalent to another net in another combinational logic block C2, then set the weight to 0; otherwise, set the weight to the preset maximum integer constant F_Max.

[0096] S404, using the timing information obtained in steps S401 and S402, update the relaxation value of the corresponding wire mesh for any edge i that was assigned a weight of 0 in step S403 according to the following formula. :

[0097] ,

[0098] In the above formula, This represents the original relaxation value of the net before it was updated, slack. i A value greater than 1 indicates that the edge is a non-temporal violation path, slack i A weight of 1 indicates that the edge is a temporal violation path; then, it is determined whether the temporal optimization of any edge i assigned a weight of 0 meets the requirements. If the temporal optimization fails, and edge i is not a temporal violation path, the weight of edge i is updated according to the following formula:

[0099] ,

[0100] If edge i is a temporal violation path, then update the weight of edge i according to the following formula:

[0101] ,

[0102] Once the time-series optimization has been achieved, the weight of edge i is updated according to the following formula:

[0103] ,

[0104] in, Let i be the weight of edge i. , , A constant factor, This indicates the degree of improvement in the logic level of a certain net in combinational logic block C2 compared to the equivalent logic level of the net in combinational logic block C1 that is equivalent to it. Let i be the equivalent logical series of edge i. Let C1 be the maximum logic level of the combinational logic block. It is the maximum logic level of combinational logic block C2.

[0105] When calculating the logic level for combinational logic blocks C1 and C2, this embodiment uses an equivalent logic level instead to make the logic level closer to the actual timing information. Specifically, in step S401 of this embodiment, when calculating the equivalent logic level for combinational logic blocks C1 and C2, for an N-input logic gate G... i The expression for the calculation function of the equivalent logic series of the output net j is:

[0106] ,

[0107] In the above formula, This represents the equivalent logic series of net j; This indicates taking the maximum value. ~ These are logic gates G i The equivalent logic levels of input ports 0 to N-1, Represents logic gate G i Its own delay (used to replace the internal delay of the logic gate), its value is G. i Half of the input pin; This represents the fanout number of net j (used to replace the load capacitance of the net).

[0108] like Figure 6 As shown, step S107 in this embodiment includes:

[0109] S501, run the maximum flow algorithm (known method, see reference: Shao Liping. Research on maximum flow algorithm of network [D]. Nanjing University of Posts and Telecommunications, 2019) to obtain the residual network M1′. If the maximum flow value F1 returned by the maximum flow algorithm is greater than the preset maximum integer constant F_Max, it is determined that there is no solution, and the process ends and exits; otherwise, jump to step S502.

[0110] S502, Start a depth-first traversal from the source node of the residual network M1′. When an edge with a flow of 0 is encountered, the traversal ends and the process returns. The edge with a flow of 0 refers to the edge with a weight of 0 in the residual network M1′. Mark the traversed nodes.

[0111] S503, traverse all positive edges in the residual network M1′. If one of the nodes connected to its two ends is marked and the other is not marked, then the edge is a cut edge. All cut edges form a cut set T1. At the same time, record the net corresponding to the edge in the cut set T1 and store it in the set S1.

[0112] S504. Using the circuit equivalence information EQ_Info obtained in step S207, traverse all edges in the network flow model M2. If its net is equivalent to the net in set S1, then set the weight of the edge to 0.

[0113] S505, run the maximum flow algorithm on the network flow model M2 to obtain the residual network M2′. If the maximum flow value F2 returned by the maximum flow algorithm is greater than the preset maximum integer constant F_Max, it is determined that there is no solution, and the process ends and exits; otherwise, jump to step S506.

[0114] S506: Start from the source node in the residual network M2′ and perform a depth-first traversal. When an edge with a flow of 0 is encountered, the traversal ends and returns. Mark the traversed nodes.

[0115] S507, Traverse all positive edges in the residual network M2′. If one of the nodes connected to the edge is marked and the other is not marked, then the edge is a cut edge. All cut edges form a cut set T2.

[0116] S508, using the circuit equivalence information EQ_Info obtained in step S207, the edges in cut set T1 and cut set T2 are matched with each other to generate a matching relationship R. The matching relationship R stores the equivalence relationships of all edges in cut set T1 and cut set T2.

[0117] S509 uses cutsets T1 and T2 and matching relation R to cut and merge combinational logic blocks C1 and C2. During merging, if the net equivalence relation of the two pins to be connected is POSITIVE_EQUAL, they are directly connected; if the net equivalence relation is NEGATIVE_EQUAL, an inverter needs to be inserted in the middle of the connection. The merged combinational logic block is the new combinational logic block C1', where the part that belonged to combinational logic block C2 before merging is the modified part of the circuit, such as... Figure 7 As shown.

[0118] In summary, this embodiment implements a method for rapidly repairing timing violations using a resynthesized netlist based on the timing ECO method. Leveraging the powerful timing optimization capabilities of synthesis tools, the new netlist generated with tightened timing constraints has shorter critical paths. Based on this, an algorithm uses the optimized logic structure in the new netlist to partially replace the critical paths in the old netlist, while preserving as much of the original logic as possible. This achieves timing repair with minimal modification to the old netlist, enabling low-cost, high-efficiency, and quick resolution of serious timing violations occurring in the later stages of chip design, saving significant manpower and time, and shortening the chip design cycle.

[0119] Furthermore, this embodiment also provides a timing ECO system based on resynthesis, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the timing ECO method based on resynthesis.

[0120] Furthermore, this embodiment also provides a computer-readable storage medium storing a computer program or instructions that are programmed or configured to execute the resynthesis-based timing ECO method by a processor.

[0121] Furthermore, this embodiment also provides a computer program product, including a computer program or instructions that are programmed or configured to execute the resynthesis-based timing ECO method via a processor.

[0122] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0123] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A time-series ECO method based on resynthesis, characterized in that, Includes the following steps: S101 reads circuit information, including the old netlist G1 that needs timing ECO, and the new netlist G2 generated by resynthesizing the RTL code based on the old netlist G1 with tightened timing constraints. In the setup script, it sets the equivalence information file, standard cell library, timing constraint file, and timing violation path information; and converts the read circuit information into data structures in the program. S102, match the old netlist G1 and the new netlist G2; S103, Locate the combinational logic block C1 where the timing violation path is located in the old netlist G1, and extract the combinational logic block C2 that matches the combinational logic block C1 in the new netlist G2 according to the matching relationship. S104, use the method of combining simulation and SAT solver to locate equivalent points and store the mapping relationship between equivalent points. Two points with a mapping relationship are called equivalent points. The equivalent point refers to the Boolean equivalence of the net of combinational logic block C1 with one or more nets in combinational logic block C2. S105, establish network flow model M1 for combinational logic block C1 and network flow model M2 for combinational logic block C2; S106, calculate the timing information of combinational logic block C1 and combinational logic block C2 respectively, and assign weights to each edge in network flow model M1 and M2 based on the calculated timing information; S107, use the maximum flow algorithm to calculate the maximum flow for network flow models M1 and M2 respectively, generate corresponding residual networks, use the residual networks to calculate cut sets, and perform cut set matching. Through the matching relationship, merge the right part of combinational logic block C1 and the left part of combinational logic block C2 along the tangent to generate a new combinational logic block C1′. The part that belongs to combinational logic block C2 before merging is the modified part of the circuit. S108, apply the new combinational logic block C1′ to the old netlist G1 as the output of netlist G1′ after timing ECO.

2. The time-series ECO method based on resynthesis according to claim 1, characterized in that, In step S102, when matching the old netlist G1 and the new netlist G2, key points including timing units, module input / output ports, and IP module input / output ports are matched using a name matching method.

3. The time-series ECO method based on resynthesis according to claim 1, characterized in that, Step S104 includes: S201, Connect the main inputs of combinational logic block C1 and combinational logic block C2 in pairs according to the matching relationship to generate a new set of main inputs PI′; S202, assign a set of random simulated values ​​to the new main input PI′, so that the main inputs of combinational logic block C1 and combinational logic block C2 obtain the same random simulated values; S203, according to the circuit logic relationship, the random analog value is propagated to each net in the circuit of combinational logic block C1 and combinational logic block C2, and the analog value of each net is recorded. S204, group the nets according to the simulated values, and the nets with the same simulated values ​​are a candidate equivalent group CG; S205, assign an input mask to each input in the new master input PI′, propagate the input mask backward, and calculate the input signature for each net; S206, Based on the input signature, further classify the obtained candidate equivalence group CG, remove potential non-equivalence points, and obtain a new candidate equivalence group CG′; S207, use the SAT solver to perform pairwise verification on the nets in the new candidate equivalence group CG′. Simultaneously, consider N equivalence and mark the nets that satisfy the verification result as equivalent points. Store the equivalence information of the equivalence points in the circuit equivalence information EQ_Info obtained by locating the equivalence points. The circuit equivalence information EQ_Info stores the equivalence relationship between each group of equivalence points, and each group of equivalence points is accompanied by an equivalence mark. The equivalence mark is either the direct equivalence mark POSITIVE_EQUAL or the N equivalence mark NEGATIVE_EQUAL. N equivalence means that the logic of the two nets is mutually inverted.

4. The time-series ECO method based on resynthesis according to claim 1, characterized in that, Step S105 includes: S301, a directed graph D1 is established for combinational logic block C1, and a directed graph D2 is established for combinational logic block C2. The nodes in the directed graphs D1 and D2 correspond to the logic units in the combinational logic block circuit, and the edges correspond to the connections between pins. The mapping relationship between combinational logic blocks C1 and C2 and directed graphs D1 and D2 is stored. S302, add a source node S to directed graph D1, add directed edges to all input nodes in directed graph D1 such that source node S points to all input nodes through directed edges, add a sink node T to directed graph D1, add directed edges to all output nodes in directed graph D1 such that all output nodes point to sink node T through directed edges; add a source node S to directed graph D2, add directed edges to all input nodes in directed graph D2 such that source node S points to all input nodes through directed edges, add a sink node T to directed graph D2, add directed edges to all output nodes in directed graph D2 such that all output nodes point to sink node T through directed edges; S303, add a reverse edge to each edge in directed graphs D1 and D2, store all edges in an array, and make the forward edge index adjacent to the corresponding reverse edge index, thereby obtaining the network flow model M1 of combinational logic block C1 and the network flow model M2 of combinational logic block C2.

5. The time-series ECO method based on resynthesis according to claim 3, characterized in that, Step S106 includes: S401 calculates the equivalent logic levels for combinational logic blocks C1 and C2. S402, using the maximum equivalent logic level of combinational logic block C2, calculate the net relaxation value Slack for combinational logic blocks C1 and C2. For an N-input M-output logic gate G... i The relaxation value of any input wire j The expression for the computation function is: ， In the above formula, This indicates taking the minimum value. ~ These are logic gates G i The relaxation values ​​of output ports 0 to M-1 This indicates taking the maximum value. ~ Don't use logic gate G i The equivalent logic levels of input ports 0 to N-1, This represents the equivalent logic level of the input net j; S403, use the circuit equivalence information EQ_Info obtained in step S207 to assign weights to the edges in the directed graph D1. If a certain net in combinational logic block C1 has a net that is equivalent to another net in another combinational logic block C2, then set the weight to 0; otherwise, set the weight to the preset maximum integer constant F_Max. S404, using the timing information obtained in steps S401 and S402, update the relaxation value of the corresponding wire mesh for any edge i that was assigned a weight of 0 in step S403 according to the following formula. : ， In the above formula, This represents the original relaxation value of the net before it was updated, slack. i A value greater than 1 indicates that the edge is a non-temporal violation path, slack i A weight of 1 indicates that the edge is a temporal violation path; then, it is determined whether the temporal optimization of any edge i assigned a weight of 0 meets the requirements. If the temporal optimization fails, and edge i is not a temporal violation path, the weight of edge i is updated according to the following formula: ， If edge i is a temporal violation path, then update the weight of edge i according to the following formula: ， Once the time-series optimization has been achieved, the weight of edge i is updated according to the following formula: ， in, Let i be the weight of edge i. , , A constant factor, This indicates the degree of improvement in the logic level of a certain net in combinational logic block C2 compared to the equivalent logic level of the net in combinational logic block C1 that is equivalent to it. Let i be the equivalent logical series of edge i. Let C1 be the maximum logic level of the combinational logic block. It is the maximum logic level of combinational logic block C2.

6. The time-series ECO method based on resynthesis according to claim 5, characterized in that, In step S401, when calculating the equivalent logic levels for combinational logic blocks C1 and C2, for a logic gate G with N inputs... i The expression for the calculation function of the equivalent logic series of the output net j is: ， In the above formula, This represents the equivalent logic series of net j; This indicates taking the maximum value. ~ These are logic gates G i The equivalent logic levels of input ports 0 to N-1, Represents logic gate G i The delay of the logic gate itself is used to replace the internal delay of the logic gate, and its value is G. i Half of the input pin; The fan-out number of net j is used in place of the net's load capacitance.

7. The time-series ECO method based on resynthesis according to claim 3, characterized in that, Step S107 includes: S501, run the maximum flow algorithm on the network flow model M1 to obtain the residual network M1′. If the maximum flow value F1 returned by the maximum flow algorithm is greater than the preset maximum integer constant F_Max, it is determined that there is no solution, and the process ends and exits; otherwise, jump to step S502. S502, Start a depth-first traversal from the source node of the residual network M1′. When an edge with a flow of 0 is encountered, the traversal ends and the process returns. The edge with a flow of 0 refers to the edge with a weight of 0 in the residual network M1′. Mark the traversed nodes. S503, traverse all positive edges in the residual network M1′. If one of the nodes connected to its two ends is marked and the other is not marked, then the edge is a cut edge. All cut edges form a cut set T1. At the same time, record the net corresponding to the edge in the cut set T1 and store it in the set S1. S504. Using the circuit equivalence information EQ_Info obtained in step S207, traverse all edges in the network flow model M2. If its net is equivalent to the net in set S1, then set the weight of the edge to 0. S505, run the maximum flow algorithm on the network flow model M2 to obtain the residual network M2′. If the maximum flow value F2 returned by the maximum flow algorithm is greater than the preset maximum integer constant F_Max, it is determined that there is no solution, and the process ends and exits; otherwise, jump to step S506. S506: Start from the source node in the residual network M2′ and perform a depth-first traversal. When an edge with a flow of 0 is encountered, the traversal ends and returns. Mark the traversed nodes. S507, Traverse all positive edges in the residual network M2′. If one of the nodes connected to the edge is marked and the other is not marked, then the edge is a cut edge. All cut edges form a cut set T2. S508, using the circuit equivalence information EQ_Info obtained in step S207, the edges in cut set T1 and cut set T2 are matched with each other to generate a matching relationship R. The matching relationship R stores the equivalence relationships of all edges in cut set T1 and cut set T2. S509 uses cut sets T1 and T2 and matching relation R to cut and merge combinational logic blocks C1 and C2. During merging, if the net equivalence relation of the two pins to be connected is POSITIVE_EQUAL, they are directly connected; if the net equivalence relation of the two pins to be connected is NEGATIVE_EQUAL, an inverter needs to be inserted in the middle of the connection. The merged combinational logic block is the new combinational logic block C1′, where the part that belonged to combinational logic block C2 before merging is the modified part of the circuit.

8. A timing ECO system based on resynthesis, comprising interconnected microprocessors and memory, characterized in that, The microprocessor is programmed or configured to execute the timing ECO method based on resynthesis as described in any one of claims 1 to 7.

9. A computer-readable storage medium storing a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute the timing ECO method based on resynthesis as described in any one of claims 1 to 7 via a processor.

10. A computer program product, comprising a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute the timing ECO method based on resynthesis as described in any one of claims 1 to 7 via a processor.

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