Optical communication transceiver with clock synchronization

Abstract

The present application relates to the technical field of integrated circuits, and discloses an optical communication transceiver with clock synchronization, including: a phase-locked loop, generating multiple clock signals with a first cycle; multiple clock paths, each path includes a phase control module, one or more frequency dividers and an analog-to-digital / digital-to-analog conversion module, the phase control module receives one clock signal respectively, and each clock signal is divided to obtain a divided clock signal with a second cycle; one or more phase detection control modules, each including a phase detector, each phase detector receives the divided clock signals of multiple clock paths, selects one divided clock signal as a reference clock signal, compares the remaining divided clock signals with the reference clock signal, and when a certain path is not aligned with the reference clock signal, the phase detector outputs a detection signal to the corresponding phase control module, and the phase control module adjusts the rising edge of the clock signal of the path to delay a first cycle until the divided clock signal of the path is aligned with the reference clock signal. The present application can align the clock signals of each channel.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an optical communication transceiver with clock synchronization. Background Art

[0002] In optical communication transceivers (especially coherent communication), it is usually composed of two sets of orthogonal signal XI / XQ and YI / YQ channels. The phase-locked loop (PLL) generates a common clock signal (global clock, or PLL clock), which is then transmitted to the four channels XI, XQ, YI, and YQ respectively. Figure 1 shown.

[0003] In each channel, the multi-phase clock required by the analog-to-digital converter and the digital-to-analog converter (AD / DA) is generally generated by a multi-stage cascaded divider, whose period is M times the common period. Due to the limitations of the divider's own characteristics, the first rising edge cannot be accurately generated. Figure 2 As shown in the figure, the clock rising edge of the AD / DA of channel 1 (e.g. channel XI) differs from that of channel 2 (e.g. channel XQ) by one PLL clock cycle. If the signals of each channel are not synchronized, the orthogonality of XI / XQ and YI / YQ will be destroyed, which will deteriorate the system performance and affect the normal operation of the subsequent digital signal processor (DSP) module. Usually, the optical communication system has clear indicator requirements for the AD / DA signal interval (skew) of different channels. Therefore, the AD / DA clock signals of different channels must be synchronized. Summary of the invention

[0004] The purpose of the present application is to provide an optical communication transceiver with clock synchronization, which is used to align the rising edges of clock signals of various channels to synchronize the clock signals.

[0005] The present application discloses an optical communication transceiver with clock synchronization, comprising:

[0006] A phase-locked loop, wherein the phase-locked loop generates a multi-channel clock signal, wherein the multi-channel clock signal has a first period;

[0007] a plurality of clock paths, each clock path comprises a phase control module, one or more frequency dividers and an analog-to-digital / digital-to-analog conversion module coupled in sequence, the phase control module of each clock path receives a clock signal, each clock signal is divided by one or more stages of the one or more frequency dividers, and the divided clock signal is output to the corresponding analog-to-digital / digital-to-analog conversion module, and the divided clock signal has a second period; and

[0008] One or more phase-detection control modules, each of which includes a phase detector, each of which receives the divided clock signals of the multiple clock paths, selects one divided clock signal as a reference clock signal, and compares the remaining divided clock signals with the reference clock signal. When the rising edge of a divided clock signal is not aligned with the rising edge of the reference clock signal, the phase detector outputs a detection signal to the phase control module corresponding to the divided clock signal, and the phase control module adjusts the rising edge of the clock signal to be delayed by a first cycle according to the detection signal until the rising edge of the divided clock signal is aligned with the rising edge of the reference clock signal.

[0009] In a preferred embodiment, each phase detection control module further includes:

[0010] A digital control module, the digital control module is coupled to the corresponding phase detector, and is used to receive a detection signal output by the corresponding phase detector and generate a phase feedback control signal according to the detection signal within a predetermined time;

[0011] A multiplexer, the input ends of which are respectively coupled to the phase detector and the digital control module and are used to output the detection signal output by the phase detector or the phase feedback control signal output by the digital control module to the corresponding phase control module according to a phase control selection signal.

[0012] In a preferred example, when the phase control selection signal is at a low level, the multiplexer outputs the detection signal output by the phase detector to the corresponding phase control module; when the phase control selection signal is at a high level, the multiplexer outputs the phase feedback control signal output by the digital control module to the corresponding phase control module.

[0013] In a preferred example, it includes: a phase detection control module, the phase detection control module includes a phase detector, the phase detector receives the divided clock signals of the multiple clock paths, and selects one divided clock signal as a reference clock signal, compares the remaining divided clock signals with the reference clock signal in turn, and adjusts the rising edge of the divided clock signal to align with the rising edge of the reference clock signal through the corresponding phase control module in turn.

[0014] In a preferred example, it includes: multiple phase-detection control modules, each phase-detection control module corresponds to a clock path, each phase detector receives the divided clock signals of the multiple clock paths, and selects one divided clock signal as a reference clock signal, each phase detector compares the corresponding one divided clock signal with the reference clock signal and adjusts the rising edge of the divided clock signal to align with the rising edge of the reference clock signal through the corresponding phase control module.

[0015] In a preferred example, the phase-locked loop generates N clock signals, and the clock synchronization circuit includes N clock paths and N phase-detection control modules, wherein the value of N is an integer greater than or equal to 2.

[0016] In a preferred example, the second period is M times the first period, where M is an integer greater than or equal to 2.

[0017] In a preferred example, the rising edge of each clock signal is delayed by 1 to M-1 first cycles.

[0018] In a preferred example, each clock path includes K frequency dividers connected in sequence, and the value of K is an integer greater than or equal to 1.

[0019] In the implementation manner of the present application, it can be used to align the rising edges of the clock signals of each channel to synchronize the clock signals. The present application achieves orthogonalization of the IQ two-way signals through simple clock calibration, eliminating a large amount of resource overhead used in orthogonalization compensation and reducing complexity.

[0020] The specification of the present application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of the present application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, and the solution of A+B+C+E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a block diagram of an optical communication transceiver.

[0022] Figure 2 It is a schematic diagram of the clock phase relationship of the optical communication transceiver.

[0023] FIG3( a ) is a schematic diagram of the structure of an optical communication transceiver with clock synchronization according to an embodiment of the present application.

[0024] FIG3( b ) is a schematic structural diagram of an optical communication transceiver with clock synchronization according to another embodiment of the present application.

[0025] Figure 4 It is a schematic diagram of a phase detection process performed by a phase detector according to an embodiment of the present application.

[0026] Figure 5 It is a schematic diagram of a phase control process according to an embodiment of the present application.

[0027] Figure 6 It is a schematic diagram of implementing clock synchronization according to an embodiment of the present application.

[0028] Figure 7 It is a schematic diagram of a phase calibration process according to an embodiment of the present application.

[0029] Figure 8 It is a simulation result of a phase calibration process in one embodiment of the present application.

[0030] In the accompanying drawings, the symbols are as follows:

[0031] 101-Phase-Locked Loop;

[0032] 102.1-102.4, 102'-phase control module;

[0033] 103, 103'-phase detector;

[0034] 104, 104'-digital control module;

[0035] 105, 105]-multiplexer;

[0036] 106- phase control module;

[0037] 107-Analog-to-digital / digital-to-analog conversion module;

[0038] 108-frequency division module. DETAILED DESCRIPTION

[0039] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0040] Description of some concepts:

[0041] Optical communication transceivers are key devices used in fiber-optic communication systems, responsible for converting electrical signals into optical signals for transmission, and converting optical signals back into electrical signals at the receiving end. Its basic functions include sending (transmitting) and receiving (receiving) optical signals.

[0042] A phase-locked loop (PLL) is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator to generate a target frequency. According to the principle of automatic control, this is a typical feedback control circuit that uses an external reference signal to control the frequency and phase of the oscillation signal inside the loop to achieve automatic tracking of the output signal frequency to the input signal frequency. The main components are VCO (voltage-controlled oscillator) and PLL IC (phase-locked loop integrated circuit). The phase-locked loop continuously adjusts the output frequency of the VCO to keep it consistent with the frequency and phase of the reference signal. The phase comparator detects the phase difference between the input reference signal and the VCO output signal and generates an error signal. The loop filter filters the error signal, removes the high-frequency component, and generates a smooth control voltage. The control voltage acts on the VCO to adjust its output frequency so that it gradually approaches the frequency of the reference signal. When the frequency and phase of the VCO output signal are synchronized with the reference signal, the phase difference approaches zero, the system enters a phase-locked state, and maintains a stable output.

[0043] A phase detector is a device that can identify the phase difference of an input signal. It is a circuit that makes the output voltage have a definite relationship with the phase difference between two input signals.

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0045] In one embodiment of the present application, there is a kind of optical communication transceiver with clock synchronization, and the structure includes a phase-locked loop, multiple clock paths, and one or more phase-detection control modules. Figure 3 (a) shows a schematic diagram of the structure of an optical communication transceiver with clock synchronization function in one embodiment, which includes a phase-locked loop 101. The phase-locked loop 101 is used to generate multiple clock signals, and the multiple clock signals can have a first period Tin. In one embodiment, the phase-locked loop 101 is used to generate N clock signals, and the optical communication transceiver includes N clock paths and N phase-detection control modules, wherein N is an integer greater than or equal to 2, for example, it can be 4, 6, or 8, etc. Specifically, if the phase-locked loop 101 generates four clock signals, the optical communication transceiver includes four clock channels and four phase-detection control modules. If the phase-locked loop 101 generates six clock signals, the optical communication transceiver includes six clock channels and six phase-detection control modules. FIG3(a) takes four clock paths as an example for explanation, that is, the optical communication transceiver includes four clock paths XI, XQ, YI, and YQ and four phase detection control modules 102.1, 102.2, 102.3, and 102.4. For example, the phase detection control module 102.1 corresponds to the clock path XI, the phase detection control module 102.2 corresponds to the clock path XQ, the phase detection control module 102.4 corresponds to the clock path YI, and the phase detection control module 102.4 corresponds to the clock path YQ.

[0046] Each clock path in the four clock channels XI, XQ, YI, and YQ includes a phase control module 106, a frequency division module 108, and an analog-to-digital / digital-to-analog conversion module (AD / DA) 107 coupled in sequence, and the frequency division module 108 includes one or more frequency dividers connected in sequence, such as frequency divider 1 to frequency divider k. The phase control module 106 of each clock path receives a clock signal respectively, and each clock signal is divided by one or more stages of frequency division by one or more frequency dividers to obtain a divided clock signal, and the divided clock signal is output to the corresponding analog-to-digital / digital-to-analog conversion module 107, and the divided clock signal has a second period. In one embodiment, the second period is M times the first period, for example, the divided clock signal has a second period M*Tin. The value of M is an integer greater than or equal to 2. For example, M is 2, 4, and so on.

[0047] In one embodiment, k is equal to 4, and each clock path in the four clock channels XI, XQ, YI, and YQ includes 4 frequency dividers connected in sequence, such as frequency divider 1, frequency divider 2, frequency divider 3, and frequency divider 4, which divide the clock signal in sequence. It should be understood that the value of k is an integer greater than or equal to 1. In other embodiments of the present application, k can also be set to 2, 3, 5, 6, etc., and the present application is not limited thereto.

[0048] Each of the four phase detector control modules 102.1, 102.2, 102.3, and 102.4 includes a phase detector 103. Each phase detector 103 receives divided clock signals of multiple clock paths, selects one divided clock signal as a reference clock signal, and each phase detector compares the corresponding one divided clock signal with the selected reference clock. For example, each phase detector 103 receives four clock signals, selects the clock signal of the XI path as the reference clock, and the clock signals of the remaining XQ, YI, and YQ paths as the clocks to be calibrated. Each phase detector compares one clock signal among the clock signals of the XQ, YI, and YQ paths corresponding to it with the reference clock. When the rising edge of a divided clock signal is not aligned with the rising edge of the reference clock signal, the phase detector 103 outputs a detection signal to the phase control module 106 corresponding to the divided clock signal. The phase control module 106 adjusts the rising edge of the clock signal to be delayed by a first cycle according to the detection signal until the rising edge of the divided clock signal is aligned with the rising edge of the reference clock signal.

[0049] If the rising edge of the clock to be calibrated is aligned with the rising edge of the reference clock, the phase detector 103 outputs 0, and if the rising edge of the clock to be calibrated is not aligned with the rising edge of the reference clock, the phase detector 103 outputs 1. When the detection result is 1, the phase detector 103 can directly output the detection result to the corresponding phase control module 106, and the phase control module 106 delays the rising edge of the clock signal output by the PLL to this clock path by one PLL cycle (i.e., the first cycle Tin). When the detection result is 0, the phase detector 103 does not perform any operation.

[0050] When the period of the divided clock signal is M times that of the PLL clock, the rising edge of each clock signal is delayed by 1 to M-1 first periods, that is, each clock is calibrated at most M-1 times to be aligned with the reference clock.

[0051] In one embodiment, each of the four phase detector control modules 102.1, 102.2, 102.3, and 102.4 further includes: a digital control module 104 and a multiplexer 105. The digital control module 104 is coupled to the corresponding phase detector 103, and is used to receive the detection signal output by the corresponding phase detector 103 and generate a phase feedback control signal according to the detection signal within a predetermined time. The input end of the multiplexer 105 is respectively coupled to the phase detector 103 and the digital control module 104, and is used to output the detection signal output by the phase detector 103 or the phase feedback control signal output by the digital control module 104 to the corresponding phase control module 106 according to the phase control selection signal. Compared with the method of directly performing analog calibration on the phase detector, the method of using the digital control module 104 to perform phase calibration can be digitally filtered to avoid erroneous calibration.

[0052] In one embodiment, when the phase control selection signal is at a low level (i.e., 0), the multiplexer 105 outputs the detection signal output by the phase detector 103 to the corresponding phase control module 106. When the phase control selection signal is at a high level (i.e., 1), the multiplexer 105 outputs the phase feedback control signal output by the digital control module 104 to the corresponding phase control module 106.

[0053] It should be noted that the four phase-detection control modules in the present application can be calibrated simultaneously, that is, four-way parallel calibration. In other embodiments, calibration can also be performed sequentially. Figure 3(b) shows a schematic diagram of the structure of an optical communication transceiver with a clock synchronization function in another embodiment. The difference between the embodiment of Figure 3(b) and Figure 3(a) is that it only includes one phase-detection control module 102', and the phase-detection control module 102' includes a phase detector 103'. The phase detector 103' receives the divided clock signals of multiple clock paths, and selects one divided clock signal as the reference clock signal, compares the remaining divided clock signals with the reference clock signal in turn, and adjusts the rising edge of the divided clock signal to align with the rising edge of the reference clock signal through the corresponding phase control module 106 in turn.

[0054] In coherent optical communication, ideally, the I and Q paths of the received signal are completely orthogonal. If the phases of the I and Q paths are unbalanced, the orthogonality of the I and Q paths will be destroyed, the system performance will deteriorate, and the normal operation of the subsequent DSP module will be affected. These orthogonal imbalance phenomena require the use of corresponding algorithms to orthogonalize the signals to compensate for the effects of phase errors. These compensation algorithms usually consume a lot of resources, and the more compensation, the greater the consumption. The present application uses a simple clock calibration to orthogonalize the IQ signals, eliminating a large amount of resource overhead used in orthogonalization compensation and reducing complexity.

[0055] In order to better understand the technical solution of the present application, the implementation method of clock synchronization is described below with reference to a specific example. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0056] (1) Phase detection

[0057] Detect the lowest speed clock in AD / DA. The phase detector detects the reference clock and the clock to be calibrated to determine the phase relationship of the clocks. Figure 4 A schematic diagram showing phase detection by a phase detector in an embodiment is shown.

[0058] (2) Phase control

[0059] When the received phase feedback control signal is zero, the output signal remains unchanged; when the received phase feedback control signal is a high-level step signal, the rising edge of the output clock signal is delayed by one PLL clock cycle (Tin) compared to the previous one. Figure 5 A schematic diagram of a phase control process in one embodiment is shown.

[0060] (3) Overall implementation plan

[0061] The four AD / DAs send clock signals to the PD (phase detector) respectively, and the output signal of the PD is sent to the digital control circuit. The digital control circuit sends the output result to the clock adjustment part (phase control module) of the AD / DA to calibrate the output clock edge.

[0062] Continuing to refer to Figure 3, the AD / DA output clock of the YI channel is used as the reference signal to synchronize the AD / DA clock signals of the XI / XQ / YQ channels. Assuming that the clock signal of the XI channel is calibrated first, if the output signal of the PD is 1, the digital circuit will generate a rising edge signal and send it to the analog calibration part of the XI channel. The falling edge of the output signal clock of the XI channel will be delayed by the Tin time. Then the next phase detection is performed. If the PD output is still 1, the previous action will be repeated, and the falling edge of the output signal clock of the XI channel will be delayed by the Tin time. The above process will be repeated until the output signal of the PD is 0.

[0063] Then perform clock calibration for the XQ / YQ channels.

[0064] Figure 7 The signal phase change diagram of the calibration process is given (taking 6-frequency division as an example). The input PLL clock period is Tin, and the reference clock signal is Figure 7 The second line in . In the initial state, the rising edge of the clock signal to be calibrated lags behind the reference clock by 1*Tin. The two are not synchronized and need phase control operation. After the first phase control, the rising edge of the clock to be calibrated is delayed by 1*Tin time, and now lags behind the rising edge of the reference clock by 2*Tin. After the second phase control, the rising edge of the clock to be calibrated is delayed again by 1*Tin time, and now lags behind the rising edge of the reference clock by 3*Tin. Repeat the operation in sequence. After the fourth phase control, the rising edge of the clock to be calibrated is delayed again by 1*Tin time, and now lags behind the rising edge of the reference clock by 5*Tin. After the fifth phase control, the rising edge of the clock to be calibrated is delayed again by 1*Tin time. At this time, the rising edge of the clock to be calibrated is synchronized with the rising edge of the reference clock, and the calibration is completed.

[0065] from Figure 7 It can be seen that after the M-frequency-divided clock signal is synchronized, the calibration can be completed after at most M-1 phase control operations.

[0066] (4) Simulation results

[0067] Figure 8 The simulation process of the calibration process is given. The right picture shows the clock signal after the calibration is completed. It can be seen that the rising edges of the four signals are completely synchronized.

[0068] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0069] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0070] This specification includes combinations of the various embodiments described herein. Individual references to an embodiment (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0071] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

Claims

1. An optical communication transceiver with clock synchronization, characterized in that: include: A phase-locked loop, wherein the phase-locked loop generates a multi-channel clock signal, wherein the multi-channel clock signal has a first period; A plurality of clock paths, each clock path comprises a phase control module, one or more frequency dividers and an analog-to-digital / digital-to-analog conversion module coupled in sequence, the phase control module of each clock path receives a clock signal, each clock signal is divided by one or more stages of the one or more frequency dividers, and the divided clock signal is output to the corresponding analog-to-digital / digital-to-analog conversion module, and the divided clock signal has a second period; as well as One or more phase-detection control modules, each of which includes a phase detector, each of which receives the divided clock signals of the multiple clock paths, selects one divided clock signal as a reference clock signal, and compares the remaining divided clock signals with the reference clock signal. When the rising edge of a divided clock signal is not aligned with the rising edge of the reference clock signal, the phase detector outputs a detection signal to the phase control module corresponding to the divided clock signal, and the phase control module adjusts the rising edge of the clock signal to be delayed by a first cycle according to the detection signal until the rising edge of the divided clock signal is aligned with the rising edge of the reference clock signal.

2. The optical communication transceiver according to claim 1, characterized in that: Each phase detection control module also includes: A digital control module, the digital control module is coupled to the corresponding phase detector, and is used to receive a detection signal output by the corresponding phase detector and generate a phase feedback control signal according to the detection signal within a predetermined time, wherein the digital control module performs phase calibration by digital filtering to avoid incorrect calibration; A multiplexer, the input ends of which are respectively coupled to the phase detector and the digital control module and are used to output the detection signal output by the phase detector or the phase feedback control signal output by the digital control module to the corresponding phase control module according to a phase control selection signal.

3. The optical communication transceiver according to claim 2, characterized in that: When the phase control selection signal is at a low level, the multiplexer outputs the detection signal output by the phase detector to the corresponding phase control module; when the phase control selection signal is at a high level, the multiplexer outputs the phase feedback control signal output by the digital control module to the corresponding phase control module.

4. The optical communication transceiver according to claim 2, characterized in that: include: A phase detection control module, the phase detection control module includes a phase detector, the phase detector receives the divided clock signals of the multiple clock paths, selects one divided clock signal as a reference clock signal, compares the remaining divided clock signals with the reference clock signal in turn, and adjusts the rising edge of the divided clock signal to align with the rising edge of the reference clock signal through the corresponding phase control module in turn.

5. The optical communication transceiver according to claim 2, characterized in that: include: Multiple phase-detection control modules, each phase-detection control module corresponds to a clock path, each phase detector receives the divided clock signals of the multiple clock paths, and selects one divided clock signal as a reference clock signal, each phase detector compares the corresponding one divided clock signal with the reference clock signal and adjusts the rising edge of the divided clock signal to align with the rising edge of the reference clock signal through the corresponding phase control module.

6. The optical communication transceiver according to claim 1, characterized in that: The phase-locked loop generates N clock signals, and the clock synchronization circuit includes N clock paths and N phase-detection control modules, wherein N is an integer greater than or equal to 2.

7. The optical communication transceiver according to claim 1, characterized in that: The second period is M times the first period, where M is an integer greater than or equal to 2.

8. The optical communication transceiver according to claim 7, characterized in that: The rising edge of each clock signal is delayed by at most M-1 first cycles until the rising edge of the divided clock signal is aligned with the rising edge of the reference clock signal.

9. The optical communication transceiver according to claim 1, characterized in that: Each clock path includes K frequency dividers connected in sequence, and the value of K is an integer greater than or equal to 1.

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