Semiconductor structure, semiconductor fabrication method and memory

Abstract

This disclosure relates to a semiconductor structure, a semiconductor formation method, and a memory. The semiconductor structure includes: a substrate having an array region and a peripheral region; a first stacked structure located in the peripheral region, the first stacked structure including: multiple first semiconductor layers, multiple second semiconductor layers, and a stress relief layer, wherein the first semiconductor layers and second semiconductor layers are stacked alternately in sequence, and the stress relief layer is located on the top first semiconductor layer; a memory structure located in the array region, the memory structure including: a plurality of memory cells stacked in sequence; a first peripheral transistor structure disposed on the top surface of the first stacked structure and electrically connected to the memory cells of the first portion; and a second peripheral transistor structure disposed on the top surface of the substrate and electrically connected to the memory cells of the second portion, thereby optimizing the interconnection between the array region devices and the peripheral region devices in the semiconductor structure and improving the electrical performance of the three-dimensional semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor structure design, and in particular to a semiconductor structure, a semiconductor forming method, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device, and its performance and price are important factors to consider.

[0003] The integration level of semiconductor devices is a crucial factor in determining product prices. To achieve superior performance and lower prices, semiconductor devices are evolving towards higher integration levels. For two-dimensional or planar semiconductor devices, the integration level is primarily determined by the area occupied by a single memory cell. Therefore, the integration level is greatly influenced by the level of fine pattern formation technology. However, achieving fine patterns requires improvements to the process equipment, which is expensive and difficult to implement.

[0004] To further improve the integration of semiconductor devices, three-dimensional semiconductor memory devices have been proposed. However, the interconnection method between array region devices and peripheral region devices for three-dimensional semiconductor memory devices still needs to be improved. Summary of the Invention

[0005] This disclosure provides a semiconductor structure, a semiconductor formation method, and a memory. It proposes a three-dimensional semiconductor structure with an array region and a peripheral region that are adapted to each other, so as to optimize the interconnection between array region devices and peripheral region devices in the semiconductor structure and improve the electrical performance of the three-dimensional semiconductor device.

[0006] One embodiment of this disclosure provides a semiconductor structure, including: a substrate having an array region and a peripheral region; a first stacked structure located in the peripheral region, the first stacked structure including: multiple first semiconductor layers, multiple second semiconductor layers, and a stress relief layer, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately in a direction perpendicular to the substrate surface, and the stress relief layer is located on the top first semiconductor layer; a memory structure located in the array region, the memory structure including: a plurality of memory cells stacked sequentially in a direction perpendicular to the substrate surface; a first peripheral transistor structure disposed on the top surface of the first stacked structure, and the first peripheral transistor structure is electrically connected to the memory cells of a first portion; a second peripheral transistor structure disposed on the top surface of the substrate, and the second peripheral transistor structure is electrically connected to the memory cells of a second portion, wherein the second distance from the memory cells of the second portion to the substrate is less than the first distance from the memory cells of the first portion to the substrate.

[0007] By dividing the peripheral transistor structure into a first peripheral transistor structure and a second peripheral transistor structure, with the first peripheral transistor structure disposed on the surface of the first stacked structure and the second peripheral transistor structure disposed on the substrate surface, i.e., the first peripheral transistor structure and the second peripheral transistor structure are disposed at different heights in the peripheral region, when the peripheral transistors at different heights are interconnected with the memory cells at corresponding heights, the interconnect lines are arranged in parallel to each other, ensuring electrical isolation between the interconnect lines, thereby improving the electrical performance of the three-dimensional semiconductor device.

[0008] For example, the semiconductor structure further includes: a second stacked structure located on the top surface of the first stacked structure, the structure of the second stacked structure being the same as that of the first stacked structure; a third peripheral transistor structure disposed on the top surface of the second stacked structure, and the third peripheral transistor structure being electrically connected to the memory cell of the third part, the third distance from the memory cell of the third part to the substrate being greater than the first distance from the memory cell of the first part to the substrate.

[0009] For example, the material of the second semiconductor layer is different from that of the first semiconductor layer, while the material of the second semiconductor layer is the same as that of the substrate; the material of the stress relief layer is the same as that of the second semiconductor layer.

[0010] For example, the memory cell at the same height as the stress relief layer is isolated from the first peripheral transistor structure and from the second peripheral transistor structure. That is, the memory cell at the same height as the stress relief layer is a dummy memory cell and is not electrically connected to the peripheral area to ensure the consistent performance of the memory cells in the array area.

[0011] For example, in a direction perpendicular to the substrate surface, the thickness of the stress relief layer is greater than the thickness of the second semiconductor layer and greater than the thickness of the first semiconductor layer.

[0012] For example, the material of the first semiconductor layer is SiGe, and the material of the second semiconductor layer is Si.

[0013] For example, at least one of the first peripheral transistor structure and the second peripheral transistor structure includes: a multilayer channel layer spaced apart in a direction perpendicular to the substrate surface, and a first source / drain portion and a second source / drain portion in contact with opposite ends of the multilayer channel layer.

[0014] For example, the semiconductor structure further includes: a first wire step structure electrically connecting a first peripheral transistor structure and a first portion of the memory cell; and a second wire step structure electrically connecting a second peripheral transistor structure and a second portion of the memory cell.

[0015] For example, the first conductive step structure includes: first conductive steps spaced apart and stacked in a direction perpendicular to the substrate surface; the first conductive step includes: a first conductive extension extending in a first direction and a first conductive connection extending in a second direction; one end of the first conductive extension is connected to a memory cell at the same height; one end of the first conductive connection is connected to the first conductive extension; and the other end is connected to a first peripheral transistor structure. The second conductive step structure includes: second conductive steps spaced apart and stacked in a direction perpendicular to the substrate surface; the second conductive step includes: a second conductive extension extending in a first direction and a second conductive connection extending in a third direction; one end of the second conductive extension is connected to a memory cell at the same height; one end of the second conductive connection is connected to the second conductive extension; and the other end is connected to a second peripheral transistor structure. The second direction and the third direction are opposite directions to each other.

[0016] For example, a memory cell includes: a bit line structure; a transistor structure including a word line structure, a source structure, and a drain structure, wherein the source structure and the drain structure are disposed on both sides of the word line structure; the source structure is connected to a first connection portion, and the first connection portion is connected to the bit line structure; the drain structure is connected to a second connection portion, and the second connection portion is connected to a capacitor structure; one of the bit line structure and the word line structure extends in a direction perpendicular to the substrate surface, and the other extends in a first direction, and the bit line structure or word line structure extending in the first direction is electrically connected to a first conductive step structure and a second conductive step structure.

[0017] Another embodiment of this disclosure also provides a semiconductor forming method, comprising: providing a substrate, the substrate including an array region and a peripheral region; forming a stacked structure on the surface of the substrate, the stacked structure including: multiple first semiconductor layers, multiple second semiconductor layers and a stress relief layer, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately in a direction perpendicular to the surface of the substrate, and the stress relief layer is located on the top first semiconductor layer; forming a memory structure based on the stacked structure of the array region; patterning the stacked structure located in the peripheral region to expose the surface of the substrate, the remaining stacked structure constituting a first stacked structure; forming a first peripheral transistor structure on the top surface of the first stacked structure; and forming a second peripheral transistor structure on the substrate surface of the peripheral region.

[0018] For example, forming a stacked structure on a substrate surface includes: forming at least two sub-stacked structures, each sub-stacked structure including: multiple first semiconductor layers and multiple second semiconductor layers, wherein the first semiconductor layers and second semiconductor layers are alternately stacked in a direction perpendicular to the substrate surface, and a stress relief layer is located on the first semiconductor layer at the top of the sub-stacked structure; patterning the stacked structure located in the peripheral region to form a first stacked structure includes: sequentially patterning a portion of the sub-stacked structure in the stacked structure located in the peripheral region to expose the surface of the substrate and the surface of the stress relief layer, wherein the remaining stacked structure constitutes the first stacked structure and the second stacked structure; and forming a third peripheral transistor structure on the top surface of the second stacked structure.

[0019] For example, the step of forming a stacked structure on the substrate surface includes: forming a first semiconductor layer covering the substrate on the substrate surface, and forming a second semiconductor layer covering the first semiconductor layer on the surface of the first semiconductor layer; repeatedly forming a first semiconductor layer on the surface of the second semiconductor layer and forming a second semiconductor layer on the surface of the first semiconductor layer until n first semiconductor layers and n-1 second semiconductor layers are formed to form a sub-stacked structure; forming a stress relief layer covering the first semiconductor layer on the first semiconductor layer at the top of the sub-stacked structure; and forming a sub-stacked structure and a stress relief layer on the surface of the stress relief layer to constitute a stacked structure.

[0020] For example, the first peripheral transistor structure and the second peripheral transistor structure are respectively a P-type transistor or an N-type transistor; the method of forming at least one of the first peripheral transistor structure and the second peripheral transistor structure includes: forming a channel of a P-type transistor based on a first semiconductor layer, or forming a channel of an N-type transistor based on a second semiconductor layer.

[0021] Another embodiment of this disclosure also provides a memory including the semiconductor structure provided in the above embodiments, to optimize the interconnection between array region devices and peripheral region devices in the semiconductor structure and improve the electrical performance of the three-dimensional semiconductor device. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 and Figure 2This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0024] Figure 3 An enlarged schematic diagram of the interconnection between the array region structure and the peripheral region structure provided in an embodiment of this disclosure;

[0025] Figures 4-7 This is a schematic diagram of the structure corresponding to each step in a semiconductor formation method provided in another embodiment of this disclosure. Detailed Implementation

[0026] As the background technology shows, the integration level of semiconductor devices is an important factor in determining product price. In order to achieve excellent performance and low price, semiconductor devices are developing towards higher integration levels. For two-dimensional or planar semiconductor devices, the integration level of semiconductor devices is mainly determined by the area occupied by a unit memory cell. Therefore, the integration level is greatly affected by the level of fine pattern forming technology. However, realizing fine patterns requires improvements to process equipment, which is expensive and difficult to achieve.

[0027] To further improve the integration of semiconductor devices, three-dimensional semiconductor memory devices have been proposed. However, the interconnection method between array region devices and peripheral region devices for three-dimensional semiconductor memory devices still needs to be improved.

[0028] One embodiment of this disclosure provides a semiconductor structure to optimize the interconnection between array region devices and peripheral region devices in the semiconductor structure and improve the electrical performance of the three-dimensional semiconductor device.

[0029] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0030] Figure 1 and Figure 2 This is a schematic diagram of the semiconductor structure provided in this embodiment. Figure 3 The diagram below shows an enlarged view of the interconnection between the array region structure and the peripheral region structure provided in this embodiment. The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0031] refer to Figure 1 Semiconductor structures, including:

[0032] A substrate 100 has an array region 101 and a peripheral region 102. The material of the substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0033] For array region 101, array region 101 has arrayed storage cells, which can be used to store data in semiconductor integrated circuits; for peripheral region 102, peripheral region 102 has a circuit structure for controlling the storage array, which can transfer data to a specified storage cell for storage to realize the write operation, and can also transfer data in a specified storage cell to the circuit structure to realize the read operation.

[0034] The first stacked structure 50 located in the peripheral region 102 includes: multiple first semiconductor layers 10, multiple second semiconductor layers 20 and stress relief layer 30; in a direction perpendicular to the surface of the substrate 100, the first semiconductor layers 10 and the second semiconductor layers 20 are stacked alternately in sequence, and the stress relief layer 30 is located on the top first semiconductor layer 10.

[0035] For the first stack structure 50, refer to Figure 1 The first semiconductor layer 10 is disposed on the substrate 100, the second semiconductor layer 20 is disposed on the first semiconductor layer 10, the first semiconductor layer 10 is stacked on the second semiconductor layer 20, the second semiconductor layer 20 is stacked on the first semiconductor layer 10, until the stress relief layer 30 is stacked on the first semiconductor layer 10.

[0036] The first semiconductor layer 10 and the second semiconductor layer 20 are constructed from different semiconductor materials. These materials can be elemental semiconductor materials or crystalline inorganic compound semiconductor materials. Elemental semiconductor materials can be silicon or germanium, while crystalline inorganic compound semiconductor materials can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium dihydrogen phosphate, etc. For example, the first semiconductor layer 10 is silicon germanide, and the second semiconductor layer 20 is silicon. In other examples, the first semiconductor layer 10 can also be silicon, and the second semiconductor layer 20 can be silicon germanide.

[0037] It should be noted that since both the bottom and top layers of the first stacked structure 50 are first semiconductor layers 10, it can be concluded that the number of first semiconductor layers 10 in the first stacked structure 50 is the number of second semiconductor layers 20 plus 1; furthermore, Figure 1The first stacked structure 50 shown has 5 layers of first semiconductor layer 10 and 4 layers of second semiconductor layer 20. This is only used to illustrate the first stacked structure 50 and does not constitute a limitation on the first stacked structure 50. In other embodiments, the specific number of stacked layers of the first stacked structure 50 is set based on the number of layers of the three-dimensional semiconductor structure to be formed.

[0038] Continue to refer to Figure 1 The semiconductor structure also includes a memory structure 60 located in the array region 101, the memory structure 60 including a plurality of memory cells 80 stacked sequentially in a direction perpendicular to the surface of the substrate 100.

[0039] refer to Figure 1 Each memory cell 80 includes: a bit line structure 21 and a transistor structure including: a word line structure 24, a source structure 23 and a drain structure 25, wherein the source structure 23 and the drain structure 25 are disposed on both sides of the word line structure 24.

[0040] The source structure 23 is connected to the first connection part 22, the first connection part 22 is connected to the bit line structure 21, the drain structure 25 is connected to the second connection part 26, the second connection part 26 is connected to the capacitor structure 27, the capacitor structure 27 is used to store charge, when the charge stored in the capacitor structure 27 is greater than a preset value, that is, the 1 bit data used by the storage unit 80 to store is "1"; when the charge stored in the capacitor structure 27 is less than the preset value, that is, the 1 bit data used by the storage unit 80 to store is "0".

[0041] One of the bit line structure 21 and the word line structure 24 extends in a direction perpendicular to the surface of the substrate 100, and the other extends in a predetermined direction parallel to the plane containing the surface of the substrate 100; it should be noted that, for Figure 1 The storage structure 60 shown has a bit line structure 21 extending in a direction perpendicular to the surface of the substrate 100, and a word line structure 24 extending in a predetermined direction parallel to the plane containing the surface of the substrate 100. This does not constitute a limitation on the storage structure 60. In other embodiments, the bit line structure 21 may be configured to extend in a predetermined direction parallel to the plane containing the surface of the substrate 100, and the word line structure 24 may extend in a direction perpendicular to the surface of the substrate 100.

[0042] It should be noted that the first connecting part 22 serves as an intermediate structure connecting the source structure 23 to the bit line structure 21, and is used to optimize the conductivity between the bit line structure 21 and the source structure 23. In specific applications, it can be omitted, that is, the source structure 23 is directly connected to the bit line structure 21; the second connecting part 26 serves as an intermediate structure connecting the drain structure 25 to the capacitor structure 27, and is used to optimize the conductivity between the capacitor structure 27 and the drain structure 25. In specific applications, it can be omitted, that is, the drain structure 25 is directly connected to the capacitor structure 27; in addition, for Figure 1 The source structure 23 and drain structure 25 shown can be replaced in other embodiments.

[0043] Continue to refer to Figure 1 The semiconductor structure further includes: a first peripheral transistor structure 71 disposed on the top surface of the first stacked structure 50, and the first peripheral transistor structure 71 is electrically connected to the first part of the memory cell 80; a second peripheral transistor structure 72 disposed on the top surface of the substrate 100, and the second peripheral transistor structure 72 is electrically connected to the second part of the memory cell 80; wherein, the second distance between the second part of the memory cell 80 and the substrate 100 is less than the first distance between the first part of the memory cell 80 and the substrate 100.

[0044] Specifically, refer to Figure 1 In a direction perpendicular to the surface of the substrate 100, with the height of the first stacked structure 50 as a preset value, a first distance less than the preset value and a second distance greater than the preset value, that is, the memory cell 80 with a height less than the top surface of the first stacked structure 50 is connected to the peripheral transistor structure disposed on the surface of the substrate 100, namely the second peripheral transistor structure 72; the memory cell 80 with a height greater than the top surface of the first stacked structure 50 is connected to the peripheral transistor structure disposed on the surface of the first stacked structure 50, namely the first peripheral transistor structure 71.

[0045] By dividing the peripheral transistor structure into a first peripheral transistor structure 71 and a second peripheral transistor structure 72, with the first peripheral transistor structure 71 disposed on the surface of the first stacked structure 50 and the second peripheral transistor structure 72 disposed on the surface of the substrate 100, i.e. the first peripheral transistor structure 71 and the second peripheral transistor structure 72 are disposed at different heights in the peripheral region 102, when the peripheral transistors at different heights are interconnected with the memory cells 80 at the corresponding heights, the interconnect lines are arranged in parallel to each other, ensuring electrical isolation between the interconnect lines, thereby improving the electrical performance of the three-dimensional semiconductor device.

[0046] For the first peripheral transistor structure 71 and the second peripheral transistor structure 72, refer to Figure 1 At least one of the first peripheral transistor structure 71 and the second peripheral transistor structure 72 includes: a multilayer channel layer 90 spaced apart in a direction perpendicular to the surface of the substrate 100, and a first source / drain portion 91 and a second source / drain portion 92 in contact with opposite ends of the multilayer channel layer 90.

[0047] refer to Figure 2In some embodiments, the semiconductor structure further includes: a second stacked structure 51 located on the top surface of the first stacked structure 50, the structure of the second stacked structure 51 being the same as that of the first stacked structure 50, the second stacked structure 51 covering only a portion of the top surface of the first stacked structure 50, and the horizontal dimension of the second stacked structure 51 being smaller than that of the first stacked structure 50 in the horizontal direction, so that a first peripheral transistor structure 71 can be formed on the uncovered top surface of the first stacked structure 50.

[0048] Specifically, the second stacked structure 51 includes: multiple first semiconductor layers 10, multiple second semiconductor layers 20 and stress relief layer 30; in a direction perpendicular to the surface of the substrate 100, the first semiconductor layers 10 and the second semiconductor layers 20 are stacked alternately in sequence, and the stress relief layer 30 is located on the top first semiconductor layer 10.

[0049] For the second stack structure 51, refer to Figure 2 The first semiconductor layer 10 is disposed on the stress relief layer 30 of the first stacked structure 50, the second semiconductor layer 20 is disposed on the first semiconductor layer 10, the first semiconductor layer 10 is further stacked on the second semiconductor layer 20, and the second semiconductor layer 20 is further stacked on the first semiconductor layer 10 until the stress relief layer 30 is stacked on the first semiconductor layer 10.

[0050] It should be noted that since both the bottom and top layers of the second stacked structure 51 are the first semiconductor layer 10, it can be concluded that the number of first semiconductor layers 10 in the second stacked structure 51 is the number of second semiconductor layers 20 plus 1; furthermore, Figure 2 The second stacked structure 51 shown has 4 layers of first semiconductor layer 10 and 3 layers of second semiconductor layer 20. This is only used to illustrate the first stacked structure 50 and the second stacked structure 51 and does not constitute a limitation on the first stacked structure 50 and the second stacked structure 51. In other embodiments, the specific number of stacked layers of the first stacked structure 50 and the second stacked structure 51 is set based on the number of layers of the three-dimensional semiconductor structure to be formed.

[0051] Accordingly, the semiconductor structure also includes a third peripheral transistor structure 73 disposed on the top surface of the second stacked structure 51, and the third peripheral transistor structure 73 is electrically connected to the memory cell 80 of the third part, and the third distance from the memory cell 80 of the third part to the substrate 100 is greater than the first distance from the memory cell 80 of the first part to the substrate 100.

[0052] Specifically, refer to Figure 2In a direction perpendicular to the surface of the substrate 100, with the height of the first stacked structure 50 as a first preset value and the height of the second stacked structure 51 as a second preset value, a first distance less than the first preset value, a second distance greater than the first preset value but less than the second preset value, and a third distance greater than the second preset value, i.e., the memory cell 80 with a height less than the top surface of the first stacked structure 50 is connected to the peripheral transistor structure disposed on the surface of the substrate 100, namely the second peripheral transistor structure 72; the memory cell 80 with a height greater than the top surface of the first stacked structure 50 and less than the top surface of the second stacked structure 51 is connected to the peripheral transistor structure disposed on the surface of the first stacked structure 50, namely the first peripheral transistor structure 71; and the memory cell 80 with a height greater than the top surface of the second stacked structure 51 is connected to the peripheral transistor structure disposed on the surface of the second stacked structure 51, namely the third peripheral transistor structure 73.

[0053] The third peripheral transistor structure 73 includes: a multilayer channel layer 90 spaced apart in a direction perpendicular to the surface of the substrate 100, and a first source / drain portion 91 and a second source / drain portion 92 in contact with opposite ends of the multilayer channel layer 90.

[0054] It should be noted that in specific applications, the number of stacked layers of the storage structure 60 in the array region 101 may be too high, so the peripheral region 102 may also include a third stacked structure, a fourth stacked structure, etc., during the fabrication, thereby forming a highly similar peripheral transistor structure. As long as the principle conforms to the relationship between the storage structure 60, the first stacked structure 50, the first peripheral transistor structure 71 and the second peripheral transistor structure 72 mentioned in the above embodiments, they should all fall within the protection scope of this invention.

[0055] In some embodiments, the material of the second semiconductor layer 20 is the same as the material of the substrate 100, that is, the material of the second semiconductor layer 20 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium ionide, etc.

[0056] In some embodiments, the material of the stress relief layer 30 is the same as the material of the second semiconductor layer 10; in some embodiments, the materials of the stress relief layer 30, the second semiconductor layer 10, and the substrate 100 are all the same.

[0057] In some embodiments, the thickness of the stress relief layer 30 is greater than the thickness of the second semiconductor layer 20 and greater than the thickness of the first semiconductor layer 10 in a direction perpendicular to the surface of the substrate 100. Because the stress relief layer 30 is relatively thick, the thickness of the memory structure 80 located at the corresponding height in the array region 101 is also relatively large. To prevent the stacked memory structures 80 from having inconsistent performance, the memory cells 80 located at the same height as the stress relief layer 30 are isolated from the first peripheral transistor structure 71 and from the second peripheral transistor structure 72. That is, the memory cells 80 located at the same height as the stress relief layer 30 are treated as dummy memory cells and are not electrically connected to the peripheral region 102, thereby ensuring consistent performance of the memory cells 80 in the array region 101.

[0058] It should be noted that in other embodiments, since the stress relief layer 30 can be made of other materials, the thickness of the stress relief layer 30 is consistent with the thickness of the first semiconductor layer 10 or the second semiconductor layer 20. In this case, the memory cell 80 located at the same height as the stress relief layer 30 is still a dummy memory cell and is not electrically connected to the peripheral area 102.

[0059] In a specific example, the material of the first semiconductor layer 10 is silicon germanide (SiGe), and the material of the second semiconductor layer 20 is silicon (Si). For the peripheral transistor structure, the first peripheral transistor structure 71 and the second peripheral transistor structure 72 can be set as P-type transistors or N-type transistors, wherein the channel of the P-type transistor is formed based on the first semiconductor layer 10, and the channel of the N-type transistor is formed based on the second semiconductor layer 20, so as to simplify the formation process of the peripheral transistor structure in the semiconductor structure.

[0060] For the interconnection between the memory cell 80 in array region 101 and the peripheral transistor structure in the peripheral region, refer to Figure 3 The semiconductor structure further includes: a first wire step structure electrically connecting the first peripheral transistor structure 71 and the first part of the memory cell 80; and a second wire step structure electrically connecting the second peripheral transistor structure 72 and the second part of the memory cell 80.

[0061] The first conductive step structure includes: first conductive steps stacked at intervals in a direction perpendicular to the surface of the substrate 100. The first conductive step includes: a first conductive extension 411 extending in a first direction (x direction) and a first conductive connection 412 extending in a second direction (y direction). One end of the first conductive extension 411 is connected to a memory cell 80 located at the same height. One end of the first conductive connection 412 is connected to the first conductive extension 411, and the other end is connected to the first peripheral transistor structure 71.

[0062] The second conductive step structure includes: second conductive steps spaced apart and stacked in a direction perpendicular to the surface of the substrate 100. Each second conductive step includes: a second conductive extension 421 extending along a first direction (x-direction) and a second conductive connection 422 extending along a third direction (z-direction). One end of the second conductive extension 421 is connected to a memory cell 80 located at the same height. One end of the second conductive connection 422 is connected to the second conductive extension 421, and the other end is connected to a second peripheral transistor structure 72. The second direction (y-direction) and the third direction (z-direction) are opposite directions to each other.

[0063] In some embodiments, the bit line structure 21 and word line structure 24 extending in a predetermined direction parallel to the plane containing the surface of the substrate 100 are specifically provided to extend in a first direction (x direction), and the bit line structure 21 or word line structure 24 extending in the first direction (x direction) is electrically connected to the first conductive step structure and the second conductive step structure.

[0064] Specifically, refer to Figure 1 The word line structure 24 extends in the first direction (x direction). In the direction perpendicular to the surface of the substrate 100, the word line structure 24 with a height less than a preset value is electrically connected to the second conductive step structure, and the word line structure 24 with a height greater than the preset value is electrically connected to the first conductive step structure.

[0065] In the semiconductor structure provided in this embodiment, the peripheral transistor structure is divided into a first peripheral transistor structure 71 and a second peripheral transistor structure 72. The first peripheral transistor structure 71 is disposed on the surface of the first stacked structure 50, and the second peripheral transistor structure 72 is disposed on the surface of the substrate 100. That is, the first peripheral transistor structure 71 and the second peripheral transistor structure 72 are disposed at different heights in the peripheral region 102. When the peripheral transistors at different heights are interconnected with the memory cells 80 at the corresponding heights, the interconnect lines are arranged in parallel to each other, ensuring electrical isolation between the interconnect lines, thereby improving the electrical performance of the three-dimensional semiconductor device.

[0066] It should be noted that the features disclosed in the semiconductor structure provided in the above embodiments can be arbitrarily combined without conflict to obtain new semiconductor structure embodiments.

[0067] Another embodiment of this disclosure provides a semiconductor forming method, which forms a semiconductor structure to optimize the interconnection between array region devices and peripheral region devices in the semiconductor structure and improve the electrical performance of the three-dimensional semiconductor device.

[0068] Figures 4-7 The accompanying drawings are schematic diagrams of the structures corresponding to each step in the semiconductor formation method provided in this embodiment. The semiconductor formation method provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0069] refer to Figure 4 A substrate 100 is provided, which includes an array region 101 and a peripheral region 102.

[0070] Specifically, for the substrate 100, the material of the substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0071] For array region 101, array region 101 has arrayed storage cells, which can be used to store data in semiconductor integrated circuits; for peripheral region 102, peripheral region 102 has a circuit structure for controlling the storage array, which can transfer data to a specified storage cell for storage to realize the write operation, and can also transfer data in a specified storage cell to the circuit structure to realize the read operation.

[0072] refer to Figure 5 A stacked structure 50b is formed on the surface of the substrate 100. The stacked structure 50b includes: multiple first semiconductor layers 10, multiple second semiconductor layers 20 and stress relief layer 30. In a direction perpendicular to the surface of the substrate 100, the first semiconductor layers 10 and the second semiconductor layers 20 are stacked alternately in sequence, and the stress relief layer 30 is located on the top first semiconductor layer 10.

[0073] refer to Figure 6 and Figure 1 The memory structure 60 is formed by the stacked structure 50b based on the array region 101, the patterned portion is located in the stacked structure 50b of the peripheral region 102 to expose the surface of the substrate 100, and the remaining stacked structure 50b constitutes the first stacked structure 50.

[0074] refer to Figure 1 A first peripheral transistor structure 71 is formed on the top surface of the first stacked structure 50, and a second peripheral transistor structure 72 is formed on the surface of the substrate 100 of the peripheral region 102. The first peripheral transistor structure 71 and the second peripheral transistor structure 72 are interconnected with the memory cell 80.

[0075] In some embodiments, reference Figure 7 The formation of a stacked structure 50b on the surface of substrate 100 includes: forming at least two sub-stacked structures 40, each sub-stacked structure 40 including: multiple first semiconductor layers 10, multiple second semiconductor layers 20 and stress relief layer 30; in a direction perpendicular to the surface of substrate 100, the first semiconductor layers 10 and the second semiconductor layers 20 are stacked alternately in sequence, and the stress relief layer 30 is located on the first semiconductor layer 10 at the top of the sub-stacked structure 40.

[0076] refer to Figure 7 and Figure 2 The stacked structure 50b located in the peripheral region 102 is patterned to form a first stacked structure 50, including: patterning a portion of the sub-stacked structure 40 in the stacked structure 50b located in the peripheral region 102 to expose the surface of the substrate 100 and the surface of the stress relief layer 30, and the remaining stacked structure 50b constitutes the first stacked structure 50 and the second stacked structure 51.

[0077] refer to Figure 2 A first peripheral transistor structure 71 is formed on the top surface of the first stacked structure 50, a second peripheral transistor structure 72 is formed on the surface of the substrate 100 of the peripheral region 102, a third peripheral transistor structure 73 is formed on the top surface of the second stacked structure 51, and the first peripheral transistor structure 71, the second peripheral transistor structure 72 and the third peripheral transistor structure 73 are interconnected with the memory cell 80.

[0078] The step of forming a stacked structure 50b with the surface of the substrate 100 includes: forming a first semiconductor layer 10 covering the substrate 100 on the surface of the substrate 100; forming a second semiconductor layer covering the first semiconductor layer 10 on the surface of the first semiconductor layer 10; repeatedly forming a first semiconductor layer 10 on the surface of the second semiconductor layer 20 and forming a second semiconductor layer 20 on the surface of the first semiconductor layer 10, until n layers of first semiconductor layers 10 and n-1 layers of second semiconductor layers 20 are formed to form a sub-stacked structure 40; forming a stress relief layer 30 covering the first semiconductor layer 10 on the top of the sub-stacked structure 40; forming the sub-stacked structure 40 and the stress relief layer 30 on the surface of the stress relief layer 30 to constitute the stacked structure 50b, where n is a positive integer greater than 1.

[0079] In some embodiments, the material forming the second semiconductor layer 20 is the same as the material forming the substrate 100, that is, the material of the second semiconductor layer 20 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium phosphate, etc.

[0080] In some embodiments, the material forming the stress relief layer 30 is the same as the material forming the second semiconductor layer 10; in some embodiments, the material forming the stress relief layer 30, the material forming the second semiconductor layer 10, and the material forming the substrate 100 are all the same.

[0081] In some embodiments, the thickness of the stress relief layer 30 formed in the direction perpendicular to the surface of the substrate 100 is greater than the thickness of the second semiconductor layer 20 and greater than the thickness of the first semiconductor layer 10. Because the stress relief layer 30 is relatively thick, the thickness of the memory structure 80 formed at the corresponding height in the array region 101 is also relatively large. To prevent the stacked memory structures 80 from having inconsistent performance, the memory cells 80 at the same height as the stress relief layer 30 are isolated from the first peripheral transistor structure 71 and from the second peripheral transistor structure 72. That is, the memory cells 80 at the same height as the stress relief layer 30 are treated as dummy memory cells and are not electrically connected to the peripheral region 102, thereby ensuring consistent performance of the memory cells 80 in the array region 101.

[0082] It should be noted that in other embodiments, since the stress relief layer 30 can be formed based on other materials, the thickness of the formed stress relief layer 30 is consistent with the thickness of the formed first semiconductor layer 10 or the formed second semiconductor layer 20. In this case, the memory cell 80 located at the same height as the stress relief layer 30 is still a dummy memory cell and is not electrically connected to the peripheral area 102.

[0083] In a specific example, the material of the first semiconductor layer 10 is silicon germanide (SiGe), and the material of the second semiconductor layer 20 is silicon (Si). For the peripheral transistor structure, the first peripheral transistor structure 71 and the second peripheral transistor structure 72 can be set as P-type transistors or N-type transistors, wherein the channel of the P-type transistor is formed based on the first semiconductor layer 10, and the channel of the N-type transistor is formed based on the second semiconductor layer 20, so as to simplify the formation process of the peripheral transistor structure in the semiconductor structure.

[0084] It should be noted that the features disclosed in the semiconductor formation method provided in the above embodiments can be arbitrarily combined without conflict to obtain new semiconductor formation method embodiments.

[0085] Another embodiment of this disclosure provides a memory including the semiconductor structure provided in the above embodiments, to optimize the interconnection between array region devices and peripheral region devices in the semiconductor structure and improve the electrical performance of the three-dimensional semiconductor device.

[0086] Specifically, for semiconductor structures, refer to Figure 1By dividing the peripheral transistor structure into a first peripheral transistor structure 71 and a second peripheral transistor structure 72, with the first peripheral transistor structure 71 disposed on the surface of the first stacked structure 50 and the second peripheral transistor structure 72 disposed on the surface of the substrate 100, that is, the first peripheral transistor structure 71 and the second peripheral transistor structure 72 are disposed at different heights in the peripheral region 102, when the peripheral transistors at different heights are interconnected with the memory cells 80 at the corresponding heights, the interconnect lines are arranged in parallel to each other, ensuring electrical isolation between the interconnect lines, thereby improving the electrical performance of the three-dimensional semiconductor device.

[0087] It should be noted that memory can be a storage cell or device based on semiconductor devices or components. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0088] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having an array region and a peripheral region; A first stacked structure located in the peripheral region, the first stacked structure comprising: multiple first semiconductor layers, multiple second semiconductor layers and a stress relief layer, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately in a direction perpendicular to the surface of the substrate, and the stress relief layer is located on the top first semiconductor layer; A storage structure located in the array region, the storage structure comprising: a plurality of storage cells stacked sequentially in a direction perpendicular to the surface of the substrate; A first peripheral transistor structure is disposed on the top surface of the first stacked structure, and the first peripheral transistor structure is electrically connected to the memory cell of the first part via a first conductive step structure. A second peripheral transistor structure is disposed on the top surface of the substrate, and the second peripheral transistor structure is electrically connected to the memory cell of the second part via a second conductive step structure. The second distance from the memory cell of the second part to the substrate is less than the first distance from the memory cell of the first part to the substrate. The first conductive step in the first conductive step structure and the second conductive step in the second conductive step structure are parallel to each other.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A second stacked structure located on the top surface of the first stacked structure, the structure of the second stacked structure being the same as that of the first stacked structure; A third peripheral transistor structure is disposed on the top surface of the second stacked structure, and the third peripheral transistor structure is electrically connected to the memory cell of the third part. The third distance from the memory cell of the third part to the substrate is greater than the first distance from the memory cell of the first part to the substrate.

3. The semiconductor structure according to claim 1, characterized in that, The material of the second semiconductor layer is different from that of the first semiconductor layer, and the material of the second semiconductor layer is the same as that of the substrate; the material of the stress relief layer is the same as that of the second semiconductor layer.

4. The semiconductor structure according to claim 1, characterized in that, The memory cell, which is at the same height as the stress relief layer, is isolated from the first peripheral transistor structure and from the second peripheral transistor structure.

5. The semiconductor structure according to claim 1 or 3, characterized in that, In a direction perpendicular to the substrate surface, the thickness of the stress relief layer is greater than the thickness of the second semiconductor layer and greater than the thickness of the first semiconductor layer.

6. The semiconductor structure according to claim 3, characterized in that, The first semiconductor layer is made of SiGe, and the second semiconductor layer is made of Si.

7. The semiconductor structure according to claim 1, characterized in that, At least one of the first peripheral transistor structure and the second peripheral transistor structure includes: a multilayer channel layer spaced apart in a direction perpendicular to the surface of the substrate, and a first source / drain portion and a second source / drain portion in contact with opposite ends of the multilayer channel layer.

8. The semiconductor structure according to claim 1, characterized in that, include: The first conductive step structure includes: first conductive steps stacked at intervals in a direction perpendicular to the surface of the substrate; the first conductive step includes: a first conductive extension extending in a first direction and a first conductive connection extending in a second direction; one end of the first conductive extension is connected to the memory cell located at the same height; one end of the first conductive connection is connected to the first conductive extension; and the other end is connected to the first peripheral transistor structure. The second conductive step structure includes: second conductive steps stacked at intervals in a direction perpendicular to the surface of the substrate; the second conductive step includes a second conductive extension extending in a first direction and a second conductive connection extending in a third direction; one end of the second conductive extension is connected to the memory cell at the same height; one end of the second conductive connection is connected to the second conductive extension; and the other end is connected to the second peripheral transistor structure. The second direction and the third direction are opposite to each other.

9. The semiconductor structure according to claim 8, characterized in that, The storage unit includes: Bitline structure; A transistor structure includes a word line structure, a source structure, and a drain structure, wherein the source structure and the drain structure are disposed on both sides of the word line structure; The source structure is connected to the first connection portion, and the first connection portion is connected to the bit line structure; The drain structure is connected to the second connection part, and the second connection part is connected to the capacitor structure; One of the bit line structure and the word line structure extends along the direction perpendicular to the substrate surface, and the other extends along the first direction, and the bit line structure or the word line structure extending along the first direction is electrically connected to the first conductive step structure and the second conductive step structure.

10. A method for forming a semiconductor, characterized in that, include: A substrate is provided, the substrate including an array region and a peripheral region; A stacked structure is formed on the surface of the substrate, the stacked structure including: multiple first semiconductor layers, multiple second semiconductor layers and stress relief layer, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately in a direction perpendicular to the surface of the substrate, and the stress relief layer is located on the top first semiconductor layer; A storage structure comprising multiple storage cells is formed based on the stacked structure of the array region; The patterned portion is located in the stacked structure in the peripheral region to expose the surface of the substrate, and the remaining stacked structure constitutes a first stacked structure; A first peripheral transistor structure is formed on the top surface of the first stacked structure; A second peripheral transistor structure is formed on the substrate surface of the peripheral region; The first peripheral transistor structure is electrically connected to the memory cell of the first part via the first conductive step structure; The second peripheral transistor structure is electrically connected to the memory cell of the second part via the second conductive step structure; the second distance from the memory cell of the second part to the substrate is less than the first distance from the memory cell of the first part to the substrate, and the first conductive step in the first conductive step structure and the second conductive step in the second conductive step structure are parallel to each other.

11. The semiconductor formation method according to claim 10, characterized in that, Forming a stacked structure on the surface of the substrate includes: The sub-layer structure comprises at least two sub-layer structures, the sub-layer structure comprising: multiple first semiconductor layers and multiple second semiconductor layers, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately in a direction perpendicular to the surface of the substrate, and the stress relief layer is located on the first semiconductor layer at the top of the sub-layer structure; The process of patterning the stacked structure located in the peripheral region to form the first stacked structure includes: sequentially patterning a portion of the sub-stacked structure in the stacked structure located in the peripheral region to expose the surface of the substrate and the surface of the stress relief layer, with the remaining stacked structure constituting the first stacked structure and the second stacked structure. A third peripheral transistor structure is formed on the top surface of the second stacked structure.

12. The semiconductor formation method according to claim 11, characterized in that, The step of forming a stacked structure on the surface of the substrate includes: A first semiconductor layer covering the substrate is formed on the surface of the substrate, and a second semiconductor layer covering the first semiconductor layer is formed on the surface of the first semiconductor layer; The first semiconductor layer is repeatedly formed on the surface of the second semiconductor layer, and the second semiconductor layer is formed on the surface of the first semiconductor layer, until n first semiconductor layers and n-1 second semiconductor layers are formed to form a sub-stack structure; A stress relief layer covering the first semiconductor layer is formed on the first semiconductor layer at the top of the sub-stack structure; The sub-stack structure and the stress relief layer are formed on the surface of the stress relief layer to constitute the stacked structure.

13. The semiconductor formation method according to claim 10, characterized in that, include: The first peripheral transistor structure and the second peripheral transistor structure are respectively P-type transistors or N-type transistors; A method for forming at least one of the first peripheral transistor structure and the second peripheral transistor structure includes: forming the channel of the P-type transistor based on the first semiconductor layer, or forming the channel of the N-type transistor based on the second semiconductor layer.

14. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 1 to 9.

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