A pattern generator circuit system for a deformable electron beam exposure machine

Abstract

The present invention discloses a pattern generator circuit system for a deformable electron beam exposure machine, comprising a high-speed transmission circuit, a pattern generator main control circuit, a CLK&SFP+ switching circuit, a pattern generator sub-field and shaping control circuit, a beam gate control circuit, a video generation circuit, a motion correction circuit, a beam current detection circuit, a backscattered electron signal detection circuit, a main field switching circuit, a sub-field switching circuit, a shaping switching circuit, a beam gate power supply circuit, a main field power supply circuit, a dynamic image dispersion power supply circuit, a sub-field power supply circuit, a shaping power supply circuit, a backplane circuit, a debugging circuit, and a height detection circuit. The present invention has the advantages of simple structure, modularity, strong anti-interference performance, stable signal transmission, high speed, high precision, and high stability.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of semiconductor preparation, and in particular to a pattern generator circuit system of a deformable electron beam exposure machine. Background Art

[0002] Electron beam lithography (EBLI) is a technique that uses an electron beam to directly trace or project patterns onto a wafer coated with electron resist. This technique achieves extremely high resolution and is primarily used in the manufacture of photomasks or for direct etching of chips. The basic operating principle is to control the on / off, focus, and deflection of the electron beam using a beam gate, focusing, and deflection magnetic fields to create the desired pattern on the workpiece. Deformable EBLI uses a combination of apertures of varying shapes to create a specific beam spot pattern. This allows for simultaneous exposure of larger areas, significantly improving exposure efficiency and making it highly sought after in the semiconductor industry. The pattern generator is a core component in EBLI systems. Located between the computer, a high-precision digital-to-analog converter, and a high-precision deflection amplifier for scanning. Its primary function is to process the exposure pattern data sent by the computer. The hardware units in the pattern generator sequentially generate the x and y coordinates of each point to be exposed by the EBLI. These values ​​are then converted into analog values ​​via a high-speed, high-precision D / A converter. These values ​​then drive the high-precision deflection amplifier to control the deflection of the electron beam in the x and y directions, performing scanning exposure on the mask or wafer placed on the laser worktable. At the same time, the pattern generator also drives the beam gate component to control the electron beam's connection or disconnection, depending on the operating state. Furthermore, the pattern generator converts the scan field size and rotation data sent by the computer, along with the deflection amplifier gain adjustment data, field distortion data, exposure dose adjustment data, and laser stage positioning error data, into digital-to-analog form before sending it to the deflection amplifier for summation. The deflection amplifier controls electron beam deflection, ensuring precise correction of errors such as the laser stage's position error and field distortion during the machining process.

[0003] At present, the research on deformable electron beam exposure machine in China is basically at a blank stage. The pattern generator studied in China is used for direct writing electron beam equipment, and there is no corresponding pattern generator used in deformable electron beam exposure machine. Therefore, it is necessary to study a set of pattern generators suitable for deformable electron beam exposure machine. Summary of the Invention

[0004] In view of the technical problems existing in the prior art, the present invention provides a pattern generator circuit system with a simple structure that can be applied to a deformable electron beam exposure machine.

[0005] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0006] A pattern generator circuit system for a deformable electron beam exposure machine includes a high-speed transmission circuit, a pattern generator main control circuit, a CLK&SFP+ switching circuit, a pattern generator sub-field and shaping control circuit, a beam gate control circuit, a video generation circuit, a motion correction circuit, a beam current detection circuit, a backscattered electron signal detection circuit, a main field switching circuit, a sub-field switching circuit, a shaping switching circuit, a beam gate power supply circuit, a main field power supply circuit, a dynamic image dispersion power supply circuit, a sub-field power supply circuit, a shaping power supply circuit, a backplane circuit, a debugging circuit, and a height detection circuit.

[0007] The high-speed transmission circuit is respectively connected to the server and the pattern generator main control circuit; the pattern generator main control circuit is respectively connected to the CLK&SFP+ switching circuit, the pattern generation sub-field and forming control circuit, the beam gate control circuit, the video generation circuit, the motion correction circuit, the beam detection circuit, the backscattered electron signal detection circuit and the main field switching circuit; the CLK&SFP+ switching circuit is respectively connected to the main field switching circuit, the sub-field switching circuit and the forming switching circuit; the pattern generation sub-field and forming control circuit is respectively connected to the beam gate control circuit, the sub-field switching circuit and the forming switching circuit; the beam gate control circuit is respectively connected to the beam gate power supply circuit; the motion correction circuit is connected to the height detection circuit; the main field switching circuit is respectively connected to the main field power supply circuit and the dynamic image dispersion power supply circuit; the sub-field switching circuit is connected to the sub-field power supply circuit; the forming switching circuit is connected to the forming amplification power supply circuit.

[0008] As a further improvement of the above technical solution:

[0009] The pattern generator main control circuit is connected to the high-speed transmission circuit via the SRIO interface;

[0010] The pattern generator main control circuit is connected to the CLK&SFP+ switching circuit via the SRIO interface;

[0011] The pattern generator main control circuit is connected to the pattern generator sub-field and shaping control circuit via four groups of 40-way parallel buses and an SRIO interface; the four groups of 40-way parallel buses use single-ended signals;

[0012] The pattern generator main control circuit is connected to the beam gate control circuit, the video generation circuit and the motion correction circuit respectively through the SRIO interface;

[0013] The pattern generator main control circuit is connected to the beam detection circuit via an RS485 interface;

[0014] The pattern generator main control circuit is connected to the backscattered electron signal detection circuit via two SMA connectors;

[0015] The pattern generator main control circuit is connected to the main field switching circuit via two groups of 40-way parallel ports, and the 40-way parallel bus uses differential signals.

[0016] The CLK&SFP+ switching circuit is connected to the main field switching circuit, the sub-field switching circuit and the forming switching circuit respectively through optical fiber and SMA connector to transmit clock signals;

[0017] The pattern generating sub-field and shaping control circuit are connected via a set of 40-way parallel buses and a beam gate control circuit;

[0018] The image generating sub-field and shaping control circuits are connected to the sub-field switching circuit and the shaping switching circuit respectively through four groups of 40-way parallel buses;

[0019] The beam gate control circuit is connected to the beam gate power supply circuit via a DB25 connector; the beam gate power supply circuit connects the converted voltage signal to the beam gate via an SMA connector;

[0020] The main field switching circuit is connected to the main field power supply circuit via a 16-bit parallel port;

[0021] The main field switching circuit is connected to the dynamic image dispersion power supply circuit via a 16-bit parallel port;

[0022] The sub-field switching circuits are connected to the sub-field power supply circuits via 16-bit parallel ports respectively;

[0023] The shaping switching circuit is connected to the shaping amplifying power supply circuit via a 16-bit parallel port.

[0024] The main field power supply circuit is connected to the main field deflector via eight SMA connectors;

[0025] The dynamic portrait dispersion power supply circuit is connected to the portrait dispersion deflector via an SMA connector;

[0026] The sub-field power supply circuit is connected to the sub-field deflector via eight SMA connectors;

[0027] The shaping power circuit is connected to the shaping deflector through eight SMA connectors.

[0028] The signal connection lines between the pattern generator main control circuit, CLK&SFP+ switching circuit, pattern generator sub-field and shaping control circuit, beam gate control circuit, video generation circuit and motion correction circuit are all through the backplane circuit.

[0029] The high-speed transmission circuit, pattern generator main control circuit, CLK&SFP+ switching circuit, pattern generator sub-field and shaping control circuit, beam gate control circuit, video generation circuit and motion correction circuit are all placed in the same 6U standard VPX pattern generator frame and inserted in different slots.

[0030] The main control circuit of the graphic generator is a circuit with FPGA+DSP as the core architecture. The FPGA and DSP exchange data through SRIO. Its function is to receive data transmitted from the high-speed transmission circuit, which is received by the FPGA. The FPGA transmits the data to the DSP, which performs graphic algorithm calculations to generate the graphic coordinates required subsequently; at the same time, it receives signals from the beam detection circuit, collects beam concentration information, and adjusts the beam concentration in real time according to actual needs; at the same time, it receives backscattered electron signals sent from the backscattered electron signal detection circuit. This signal is divided into two parts, one for scanning imaging and the other for mark detection.

[0031] The main control circuit of the pattern generator adopts the address selection method to control in a time-sharing manner whether to select sub-field data or shaping data and beam gate control data and send them to the pattern generator sub-field and shaping control circuit. The pattern generator sub-field and shaping control circuit decides to send the data results to the corresponding sub-field switching circuit, shaping switching circuit and beam gate control circuit according to the address selection data.

[0032] The main field switching circuit is a circuit with FPGA as its core structure, which is used to receive the differential signal of the pattern generator main control circuit and convert it into a single-ended signal. The single-ended signal is then converted into a 16-bit parallel differential signal and connected to the main field power supply circuit of the next level.

[0033] The sub-field switching circuit is a circuit with FPGA as the core structure, which is used to receive the differential signal of the image generating sub-field and the shaping control circuit and convert it into a single-ended signal. The single-ended signal is then converted into a 16-bit parallel differential signal and connected to the sub-field power supply circuit of the next level;

[0034] The shaping switching circuit is a circuit with FPGA as the core structure, which is used to receive the differential signals of the image generating sub-field and the shaping control circuit and convert them into single-ended signals. The single-ended signals are then converted into 16-bit parallel differential signals and connected to the shaping power supply circuit of the next level.

[0035] Compared with the prior art, the advantages of the present invention are:

[0036] The present invention realizes the specific design of the pattern generator circuit system and the specific application in the deformable electron beam exposure machine by configuring each circuit and the connection of each circuit; the large data transmission adopts the parallel bus mode, and according to the actual situation, up to four groups of 40-bit parallel buses are used, and the single bus rate is designed to be a single bus design rate of a maximum of 100Mbit / s, and the maximum can reach 4*40*100=16000Mbit / s, which can fully meet the data transmission rate requirements of the deformable beam; the long-distance signal transmission adopts differential signals, which have strong anti-interference performance and can ensure data stability.

[0037] The present invention places all boards with similar functions in the same machine frame and adopts backplane routing, which solves the problem of signal instability caused by signals crossing boards to a certain extent and ensures signal stability. At the same time, the signal for long-distance transmission is introduced into the adapter board. The adapter board adopts FPGA as the core processor architecture and single-ended signal is transmitted within the board, avoiding the problem of signal instability caused by difficult routing. Differential signals are used for connection between boards to ensure signal stability during transmission.

[0038] The pattern generator of the present invention introduces a motion correction board, which is an FPGA+multiplier circuit, and can also be set as an FPGA+DSP circuit. The FPGA is responsible for receiving data, and the multiplier or DSP is responsible for algorithm calculation. The purpose is to perform correction algorithm calculation on the data measured by the laser measurement system, further reducing the measurement error and ensuring the accuracy of the workpiece stage motion control.

[0039] All circuits of the present invention are made into their own boards, and a total of four 6U frames are made, including a pattern generator frame, a main field power frame, a sub-field power frame and a forming power frame. The overall design is flexible and easy to disassemble and assemble. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a block diagram of a pattern generator circuit system in an embodiment of the present invention.

[0041] Figure 2 This is an installation structure diagram of the pattern generator circuit system in an embodiment of the present invention.

[0042] Figure 3 This is an installation structure diagram of the main power supply circuit in an embodiment of the present invention.

[0043] Figure 4 FIG. 1 is an installation structure diagram of a sub-field power supply circuit in an embodiment of the present invention.

[0044] Figure 5 This is a diagram showing the installation structure of a shaped power supply circuit in an embodiment of the present invention.

[0045] Figure 6 This is a timing diagram of the parallel bus in the present invention.

[0046] Figure 7 This is a diagram of the architecture of the motion quadrature circuit in the present invention.

[0047] Legend: 1. High-speed transmission circuit; 2. Pattern generator main control circuit; 3. CLK&SFP+ switching circuit; 4. Pattern generator sub-field and shaping control circuit; 5. Beam gate control circuit; 6. Video generation circuit; 7. Motion correction circuit; 8. Beam detection circuit; 9. Backscattered electron signal detection circuit; 10. Main field switching circuit; 11. Sub-field switching circuit; 12. Shaping switching circuit; 13. Beam gate power supply circuit; 14. Main field power supply circuit; 15. Dynamic image dispersion power supply circuit; 16. Sub-field power supply circuit; 17. Shaping power supply circuit; 18. Backplane circuit; 19. Debug circuit; 20. Height detection circuit. DETAILED DESCRIPTION

[0048] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0049] like Figure 1 As shown, the pattern generator circuit system applied to a deformable electron beam exposure machine according to an embodiment of the present invention includes a high-speed transmission circuit 1, a pattern generator main control circuit 2, a CLK&SFP+ switching circuit 3, a pattern generator sub-field and shaping control circuit 4, a beam gate control circuit 5, a video generation circuit 6, a motion correction circuit 7, a beam current detection circuit 8, a backscattered electron signal detection circuit 9, a main field switching circuit 10, a sub-field switching circuit 11, a shaping switching circuit 12, a beam gate power supply circuit 13, a main field power supply circuit 14, a dynamic image dispersion power supply circuit 15, a sub-field power supply circuit 16, a shaping power supply circuit 17, a backplane circuit 18, a debugging circuit 19, and a height detection circuit 20.

[0050] The high-speed transmission circuit 1 and the server (host computer) are connected via optical fiber, and the interface is implemented in SFP+; the high-speed transmission circuit 1 and the pattern generator main control circuit 2 are connected via the SRIO interface;

[0051] The pattern generator main control circuit 2 is connected to the CLK&SFP+ adapter circuit 3 via the SRIO interface, and the clock signal is transmitted on the SMA. The pattern generator main control circuit 2 is connected to the pattern generator sub-field and shaping control circuit 4 via four groups of 40-way parallel buses and the SRIO interface. The pattern generator main control circuit 2 is respectively connected to the beam gate control circuit 5, the video generation circuit 6, and the motion correction circuit 7 via the SRIO interface. The motion correction circuit 7 is connected to the height detection circuit 20. The pattern generator main control circuit 2 is connected to the beam detection circuit 8 via the RS485 interface. The pattern generator main control circuit 2 is connected to the backscattered electron signal detection circuit 9 via two SMA connectors. The pattern generator main control circuit 2 is connected to the main field adapter circuit 10 via two groups of 40-way parallel ports.

[0052] The CLK&SFP+ switching circuit 3 is connected to the main field switching circuit 10, the sub-field switching circuit 11, and the forming switching circuit 12 respectively through optical fiber (implemented as an SFP+ interface) and SMA connectors to transmit clock signals;

[0053] The sub-field generating and shaping control circuit 4 is connected to the beam gate control circuit 5 via a set of 40-way parallel buses; the sub-field generating and shaping control circuit 4 is connected to the sub-field switching circuit 11 and the shaping switching circuit 12 via four sets of 40-way parallel buses respectively;

[0054] The beam gate control circuit 5 is connected to the beam gate power supply circuit 13 via a DB25 connector; the beam gate power supply circuit 13 connects the converted voltage signal to the beam gate via an SMA connector;

[0055] The video production circuit 6 is used to generate digital video and analog video;

[0056] The motion correction circuit 7 receives the coordinate data of the X, Y, and Yaw directions measured by the laser interferometer measurement system and performs calculation processing;

[0057] The main field switching circuit 10 is connected to the main field power supply circuit 14 through a 16-bit parallel port; the main field power supply circuit 14 is composed of eight identical circuits; the main field switching circuit 10 is connected to the dynamic image dispersion power supply circuit 15 through a 16-bit parallel port;

[0058] The sub-field switching circuit 11 is connected to the sub-field power supply circuit 16 through a 16-bit parallel port. The sub-field power supply circuit 16 is composed of eight identical circuits.

[0059] The shaping switching circuit 12 is connected to the shaping amplifier power supply circuit 17 through a 16-bit parallel port. The shaping amplifier power supply circuit 17 is composed of eight identical circuits.

[0060] The main field power supply circuit 14 is connected to the main field deflector through eight SMA connectors;

[0061] The dynamic portrait dispersion power supply circuit 15 is connected to the portrait dispersion deflector via an SMA connector;

[0062] The sub-field power supply circuit 16 is connected to the sub-field deflector through eight SMA connectors;

[0063] The forming power circuit 17 is connected to the forming deflector through eight SMA connectors;

[0064] The height detection circuit 20 is used to detect the height information of the wafer and send the height information to the motion correction circuit 7 through TCP / IP for orthogonal operation.

[0065] In one specific embodiment, the high-speed transmission circuit 1 is a circuit system based on an FPGA. It is connected to a server host computer via four optical fibers (specifically implemented as SFP+). Each fiber can transmit at a rate of 10 Gbps, for a total transmission rate of up to 40 Gbps. The high-speed transmission circuit 1 is a circuit based on an FPGA core architecture, supplemented by a large storage circuit. The storage circuit is used to store large amounts of exposure pattern data. The overall function of the high-speed transmission circuit 1 is to perform parallel signal processing, pipeline control of data transmission, simultaneous data and command processing, and data compression. The high-speed transmission circuit 1 and subsequent circuits do not require real-time performance. Therefore, the high-speed transmission circuit 1 transmits data to the subsequent pattern generator main control circuit 2 via SRIO. Specifically, the host computer transmits the electron beam exposure data after completing functions such as data format conversion, proximity effect correction, and corresponding corrections to the high-speed transmission circuit 1. The large storage circuit of the high-speed transmission circuit 1 stores the data transmitted by the host computer. The high-speed transmission circuit 1 then transmits the exposure data to the pattern generator main control circuit 2 via the SRIO port.

[0066] In a specific embodiment, the graphic generator main control circuit 2 is a circuit with FPGA+DSP as the core architecture. Data is exchanged between the FPGA and DSP through SRIO. It is the core circuit of subsequent control and its function is to receive data transmitted from the high-speed transmission circuit 1. The FPGA receives the data, and the FPGA transmits the data to the DSP. The DSP performs graphic algorithm calculations to generate the graphic coordinates required subsequently; at the same time, it receives the signal from the beam detection circuit 8, collects the beam concentration information, and adjusts the beam concentration in real time according to actual needs; at the same time, it receives the backscattered electron signal sent by the backscattered electron signal detection circuit 9. The signal is divided into two parts, one part is used for scanning imaging, and the other part is used for mark detection.

[0067] Specifically, the FPGA is responsible for digital correction calculations, electronic image signal acquisition, laser workpiece position error detection, scanning speed control, high-speed data and beam gate control output; the DSP core is responsible for calculating and generating the X and Y coordinates of the exposure pattern and some complex correction calculations. The two cooperate and coordinate with each other, greatly reducing their respective burdens, allowing the entire system to work efficiently; the relevant exposure data for the main field, sub-field, and forming are all generated by this circuit.

[0068] In practical applications, the pattern generator's main control circuit 2 is the core processing and control circuit. It's an FPGA+DSP board circuit. The FPGA portion is responsible for data transmission, while the DSP portion performs pattern algorithm calculations. Ultimately, it generates coordinate data for the main field, sub-field, and shaping directions in eight directions: X, -X, Y, -Y, X+Y, -XY, XY, and -X+Y. Main field data is directly fed into the main field transfer circuit 10 via two 40-channel parallel ports. Sub-field, shaping, and beam gate control data are addressed via four 40-channel parallel buses and fed into the pattern generator, sub-field, and shaping control circuit 4.

[0069] At the same time, the pattern generator main control circuit 2 transmits the main field data to the main field switching circuit via two sets of 40-way parallel buses; these 40-way parallel buses use differential signals. Simultaneously, the sub-field and shaping data are transmitted to the pattern generator sub-field and shaping control circuit 4 via four sets of 40-way parallel buses. These four sets of 40-way parallel buses use single-ended signals, and the maximum design rate of a single bus is 100 Mbit / s. Therefore, the transmission rate to the main field switching circuit can reach 40*2*100=8000 Mbit / s, and the transmission rate to the pattern generator sub-field and shaping control circuit can reach 40*4*100=16000 bit / s.

[0070] The main control circuit 2 of the pattern generator adopts the address selection method to control the time-sharing selection of sub-field data or shaping data and beam gate control data to be sent to the pattern generating sub-field and shaping control circuit 4, so that the pattern generating sub-field and shaping control circuit 4 decides to send the data results to the corresponding sub-field switching circuit 11, shaping switching circuit 12, and beam gate control circuit 5 according to the address selection data.

[0071] In specific applications, the pattern generator main control circuit 2 receives signals from the beam current detection circuit 8 to determine whether the beam current concentration is appropriate and make real-time adjustments. The pattern generator main control circuit 2 also receives signals from the backscattered electron signal detection circuit 9. It sends a portion of the amplified backscattered electrons to the FPGA as an imaging scan signal. The scanned imaging signal is then sent to the video generation circuit 6 to generate a video signal, and a portion is sent to the FPGA as a marker signal to detect the signal.

[0072] In one specific embodiment, the CLK & SFP+ adapter circuit 3 is used to generate a synchronous clock and synchronous SFP+ control signal. This circuit is connected to the pattern generator main control circuit 2 via backplane wiring, and is also connected to the main field adapter circuit 10, the sub-field adapter circuit 11, and the forming adapter circuit 12. The CLK & SFP+ adapter circuit 3 is designed to solve the problems of timing synchronization and command synchronization, and to address long-distance transmission. Since the optical control unit of the electron beam exposure machine is located in a micro-environment room, while the pattern generator is located outdoors, the distance is relatively long, and maintaining timing synchronization and command synchronization between the main field, sub-field, and forming is required.

[0073] In specific applications, the CLK&SFP+ switching circuit 3 contains a circuit with an FPGA as the core processor, which is used to maintain clock synchronization and control data synchronization among the main field, sub-field, and shaping circuits. The CLK&SFP+ switching circuit 3 receives the CLK signal and control data signal from the pattern generator main control circuit 2, and sends the CLK and control data to the main field switching circuit 10, the sub-field switching circuit 11, and the shaping switching circuit 12 respectively.

[0074] In one embodiment, the sub-field and shaping control circuit 4 utilizes an FPGA as its core architecture, receiving control data related to sub-fields, shaping, and beam gates processed by the pattern generator main control circuit. It is connected to the pattern generator main control circuit 2 via four 40-way parallel buses. The address of the sub-field and shaping control circuit 4 is identified by the pattern generator main control circuit 2 through address selection to determine whether the data being transmitted is sub-field, shaping, or beam gate data. This data is then sent to the corresponding sub-field, shaping, or beam gate ports. Specifically, sub-field data is sent to the sub-field switching circuit 11 via four 40-way parallel buses; shaping data is sent to the shaping switching circuit 12 via four 40-way parallel buses; and beam gate data is sent to the beam gate control circuit via the 40-way parallel buses.

[0075] In one embodiment, the beam gate control circuit 5 utilizes an FPGA as its core architecture and receives control data from the image generation sub-field and shaping control circuit 4 via a 40-way parallel port. Given the extremely fast opening time required for the deformable beam gate, typically in the nanosecond range, a significantly faster data transmission rate is required. Therefore, a 40-way parallel bus is used for data transmission. With a single bus design maximum rate of 100 Mbit / s, the data transmission rate to the beam gate control circuit can reach 40**100 = 4000 Mbit / s, meeting the required data transmission rate.

[0076] In a specific embodiment, the video generation circuit 6 and the pattern generator main control circuit 2 exchange data via SRIO. The video generation circuit 6 receives the electronic imaging signal from the pattern generator main control circuit 2 and converts the imaging signal into analog video and digital video.

[0077] In one specific embodiment, motion correction circuit 7 receives data from the laser interferometer measurement system, processes the data, and transmits it to the pattern generator main control circuit 2 via SRIO. Specifically, motion correction circuit 7 uses an FPGA as its core processor. The internal link cycle within this circuit is controlled to within 10 μs, ensuring a 100 kHz data update cycle. Motion correction circuit 7 performs orthogonal multiplication on the laser interferometer's X, Y, and YAW position data, as well as the height measurement data, to correct any errors and obtain the most accurate position data.

[0078] In a specific embodiment, if Figure 2 As shown, the signal connections between the pattern generator main control circuit 2, CLK & SFP+ adapter circuit 3, pattern generation sub-field and shaping control circuit 4, beam gate control circuit 5, video generation circuit 6, and motion correction circuit 7 all pass through backplane circuit 18. Specifically, the high-speed transmission circuit 1, pattern generator main control circuit 2, CLK & SFP+ adapter circuit 3, pattern generation sub-field and shaping control circuit 4, beam gate control circuit 5, video generation circuit 6, and motion correction circuit 7 are all placed in the same 6U standard VPX chassis, inserted in different slots. The backplane connects the circuit boards. This chassis is named the pattern generator chassis.

[0079] In a specific embodiment, the beam detection circuit 8 is an analog circuit for amplifying a small signal, which is used to amplify the beam current signal collected by the Faraday cup. -8 ~10 -11 A is amplified, then converted into A / D and sent to the FPGA of the pattern generator main control circuit 2 via RS485 for processing. The FPGA determines whether the current beam concentration meets the requirements based on the received beam data and makes corresponding adjustments.

[0080] In a specific embodiment, if Figure 7As shown, the backscattered electron signal detection circuit 9 is also an analog circuit that amplifies tiny signals. This signal has two functions: one is to amplify the backscattered electron signal received by the PN junction, then send it through A / D conversion to the FPGA in the pattern generator main control circuit 2 for processing. The FPGA uses this signal as a scanning imaging signal, which is sent to the video generation circuit 6 to generate a video signal. The other function is to detect a marker signal. In a specific application, the motion correction circuit 7 is used to receive X, Y, and YAW position data from the laser interferometer via SFP+, and simultaneously receive height data from the height detection circuit via TCP / IP. The X, Y, YAW position data and height data are corrected by an algorithm, and the orthogonal correction data is finally sent to the pattern generator main control circuit 2 via SRIO.

[0081] In one specific embodiment, the main field switching circuit 10 is a circuit with an FPGA as its core structure. It connects to the pattern generator main control circuit 2 via two sets of 40-way parallel ports to address long-distance transmission. These parallel ports utilize differential signals and are used for signal conversion. Specifically, the FPGA receives the differential signals from the pattern generator main control circuit 2, which convey the main field information. The FPGA converts the differential signals into single-ended signals, which are then converted into eight sets of 16-bit parallel differential signals that are connected to the eight main field amplifier power circuits of the next-level main field power supply circuit 14. This conversion of the single-ended signals from the FPGA into differential signals ensures stable data transmission.

[0082] In a specific embodiment, the sub-field switching circuit 11 is also a circuit with an FPGA as the core structure, and is connected to the sub-field and shaping control circuit 4 through four groups of 40 parallel ports. The parallel port uses differential signals and is used for signal conversion. Specifically, the differential signal received from the sub-field and shaping control circuit 4 transmits sub-field and shaping information. The FPGA converts the differential signal into a single-ended signal, and the single-ended signal is then converted into a 16-bit parallel differential signal and connected to the sub-field power supply circuit 16 of the next level.

[0083] In one specific embodiment, the shaping switching circuit 12 also utilizes an FPGA as its core structure. To address long-distance transmission issues, the differential data transmitted from the image generation sub-field and shaping control circuit 4 via four 40-way parallel buses is converted by the FPGA into single-ended data. This single-ended data is then converted into eight sets of 16-bit differential data and sent to the eight shaping amplifier power circuits in the shaping field power circuit 17. To ensure data transmission stability, the single-ended signals from the FPGA in the image generation sub-field and shaping control circuit 4 are converted into differential signals before being sent to the eight shaping amplifier power circuits in the shaping power circuit 17.

[0084] In a specific embodiment, the beam gate power supply circuit 13 is a circuit that generates ±100V power supply and requires a very fast switching speed. It and the beam gate control circuit receive signals from the beam gate control circuit through the DB25 header, and finally output two voltages, one positive and one negative, to drive the opening and closing of the beam gate.

[0085] In a specific embodiment, the main field power supply circuit 14 is composed of 8 identical main field amplifier power supply circuits, which are respectively connected to the main field switching circuit through a 16-bit parallel port. The 8 main field amplifier power supply circuits are respectively connected to the main field deflector through SMA connectors. Among the eight main field amplifier power supply circuits, each corresponds to a direction, namely X, -X, Y, -Y, X+Y, -XY, XY, -X+Y. The power supply circuits in the eight directions are respectively transmitted to the main field deflector through SMA connectors to drive the deflection of the main field deflector. Specifically, the eight boards made up of these eight power supply circuits and the dynamic image dispersion power supply circuit are all placed in a 6U-sized main field power supply frame. The assembly diagram is shown in FIG. Figure 3 As shown, due to the large power, water cooling is adopted.

[0086] In a specific embodiment, the dynamic image dispersion power supply circuit 15 is connected to the main field switching circuit 10 via a 16-bit parallel port, and is connected to the image dispersion deflector via an SMA connector.

[0087] In a specific embodiment, the sub-field power supply circuit 16 includes eight identical sub-field amplifying power supply circuits, each of which is connected to the sub-field switching circuit via a 16-bit parallel port. The eight sub-field amplifying power supply circuits are connected to the sub-field deflector via an SMA connector to drive the deflection of the sub-field deflector. The eight boards made up of these eight circuits are all placed in a 6U-sized sub-field power supply frame. Specifically, each of the eight sub-field amplifying power supply circuits corresponds to a direction, namely X, -X, Y, -Y, X+Y, -XY, XY, and -X+Y. The above eight power supply circuits are assembled in the same frame, and the assembly diagram is shown in FIG. Figure 4 As shown, due to the large power, water cooling is adopted.

[0088] In a specific embodiment, the shaping power supply circuit 17 includes eight shaping amplifier power supply circuits. Each of these eight shaping amplifier power supply circuits corresponds to a direction, namely X, -X, Y, -Y, X+Y, -XY, XY, and -X+Y. The power supply circuits for the eight directions are respectively transmitted to the shaping deflector through SMA connectors to drive the deflection of the shaping deflector. Specifically, these eight power supply circuits are assembled in the same machine frame. The assembly diagram is shown in FIG. Figure 5 As shown, due to the large power, water cooling is adopted.

[0089] In a specific embodiment, the backplane circuit 18 is used to route the board in the frame of the pattern generator; the debugging circuit 19 includes two modes, USB and RS232, for debugging the main control circuit 2 of the pattern generator.

[0090] In one embodiment, the debugging circuit 19 is connected to the pattern generator main control circuit 2 via USB and RS232 for system debugging. The height detection circuit 20 is used to detect wafer height information and transmit this information to the motion correction circuit 7 via TCP / IP for orthogonal calculations and calculations on data in the other three axes.

[0091] The present invention introduces multiple groups of 40-way parallel buses, and a single bus is designed at a rate of 100Mbit / s. For a single group of 40-way parallel buses, a rate of 40*100Mbit / s=4000Mbit / s can be achieved. For the main field, two groups are used, and theoretically a rate of 2*4000Mbit / s=8000Mbit / s can be achieved. For the sub-field and forming, the rate can reach 4*4000Mbit / s=16000Mbit / s. For the main field, the transmission bandwidth is required to be no less than 1600Mbit / s, and the transmission bandwidth of the sub-field and forming is required to be no less than 12800Mbit / s. According to the design of the present invention, the transmission bandwidth can meet the requirements, and thus the high-speed transmission requirements can be met. At the same time, the transmission between boards is a differential signal, the transmission is stable, and the error rate is low, thereby obtaining a faster speed, stable data, and a high-accuracy graphics. Figure 6 Shown is the communication timing diagram of the 40-bit parallel bus.

[0092] The present invention utilizes four frames: a pattern generator frame, a main field power supply frame, a sub-field power supply frame, and a shaping power supply frame. The corresponding boards are placed in the correct frames, and communication within the frames is achieved using backplane wiring. The pattern generator frame utilizes fan cooling, while the main field power supply frame, sub-field power supply frame, and shaping power supply frame utilize water cooling due to their high power requirements.

[0093] The present invention can be applied to 50nm or even 28nm electron beam exposure machines, has the characteristics of high speed, high precision, good stability, and can convert CIF, GDSⅡ and DXF exposure files.

[0094] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A pattern generator circuit system for a deformable electron beam exposure machine, characterized in that: The invention comprises a high-speed transmission circuit (1), a pattern generator main control circuit (2), a CLK&SFP+ switching circuit (3), a pattern generator sub-field and shaping control circuit (4), a beam gate control circuit (5), a video generation circuit (6), a motion correction circuit (7), a beam current detection circuit (8), a backscattered electron signal detection circuit (9), a main field switching circuit (10), a sub-field switching circuit (11), a shaping switching circuit (12), a beam gate power supply circuit (13), a main field power supply circuit (14), a dynamic image dispersion power supply circuit (15), a sub-field power supply circuit (16), a shaping power supply circuit (17), a backplane circuit (18), a debugging circuit (19) and a height detection circuit (20); The high-speed transmission circuit (1) is connected to the server and the pattern generator main control circuit (2) respectively; the pattern generator main control circuit (2) is connected to the CLK&SFP+ switching circuit (3), the pattern generator sub-field and shaping control circuit (4), the beam gate control circuit (5), the video generation circuit (6), the motion correction circuit (7), the beam detection circuit (8), the backscattered electron signal detection circuit (9) and the main field switching circuit (10) respectively; the CLK&SFP+ switching circuit (3) is connected to the main field switching circuit (10), the sub-field switching circuit (11), the shaping switching circuit (12) respectively. The image generating sub-field and shaping control circuit (4) is respectively connected to the beam gate control circuit (5), the sub-field switching circuit (11) and the shaping switching circuit (12); the beam gate control circuit (5) is respectively connected to the beam gate power supply circuit (13); the motion correction circuit (7) is connected to the height detection circuit (20); the main field switching circuit (10) is respectively connected to the main field power supply circuit (14) and the dynamic image dispersion power supply circuit (15); the sub-field switching circuit (11) is connected to the sub-field power supply circuit (16); and the shaping switching circuit (12) is connected to the shaping power supply circuit (17).

2. The pattern generator circuit system of the deformable electron beam exposure machine according to claim 1, characterized in that: The pattern generator main control circuit (2) is connected to the high-speed transmission circuit (1) via an SRIO interface; The pattern generator main control circuit (2) is connected to the CLK&SFP+ switching circuit (3) via the SRIO interface; The pattern generator main control circuit (2) is connected to the pattern generator sub-field and shaping control circuit (4) via four groups of 40-way parallel buses and an SRIO interface; The four 40-way parallel buses use single-ended signals; The pattern generator main control circuit (2) is connected to the beam gate control circuit (5), the video generation circuit (6) and the motion correction circuit (7) respectively through the SRIO interface; The pattern generator main control circuit (2) is connected to the beam detection circuit (8) via an RS485 interface; The pattern generator main control circuit (2) is connected to the backscattered electron signal detection circuit (9) via two SMA connectors; The pattern generator main control circuit (2) is connected to the main field switching circuit (10) via two groups of 40-way parallel ports, and the 40-way parallel bus uses differential signals.

3. The pattern generator circuit system of the deformable electron beam exposure machine according to claim 2, characterized in that: The CLK&SFP+ switching circuit (3) is respectively connected to the main field switching circuit (10), the sub-field switching circuit (11) and the forming switching circuit (12) via optical fibers and SMA connectors (for clock signals); The pattern generating sub-field and the shaping control circuit (4) are connected via a set of 40-way parallel buses and a beam gate control circuit (5); The image generating sub-field and shaping control circuit (4) are respectively connected to the sub-field switching circuit (11) and the shaping switching circuit (12) via four groups of 40-way parallel buses; The beam gate control circuit (5) is connected to the beam gate power supply circuit (13) via a DB25 connector; the beam gate power supply circuit (13) connects the converted voltage signal to the beam gate via an SMA connector; The main field switching circuit (10) is connected to the main field power supply circuit (14) via a 16-bit parallel port; The main field switching circuit (10) is connected to the dynamic image dispersion power supply circuit (15) via a 16-bit parallel port; The sub-field switching circuit (11) is connected to the sub-field power supply circuit (16) via a 16-bit parallel port; The shaping switching circuit (12) is connected to the shaping power supply circuit (17) via a 16-bit parallel port.

4. The pattern generator circuit system of the deformable electron beam exposure machine according to claim 1, 2 or 3, characterized in that: The main field power supply circuit (14) is connected to the main field deflector via eight SMA connectors; The dynamic portrait dispersion power supply circuit (15) is connected to the portrait dispersion deflector via an SMA connector; The sub-field power supply circuit (16) is connected to the sub-field deflector via eight SMA connectors; The shaping power supply circuit (17) is connected to the shaping deflector via eight SMA connectors.

5. The pattern generator circuit system of the deformable electron beam exposure machine according to claim 1, 2 or 3, characterized in that: Signal connection lines between the pattern generator main control circuit (2), CLK & SFP+ switching circuit (3), pattern generator sub-field and shaping control circuit (4), beam gate control circuit (5), video generation circuit (6) and motion correction circuit (7) are all routed through the backplane circuit (18).

6. The pattern generator circuit system of the deformable electron beam exposure machine according to claim 1, 2 or 3, characterized in that: The high-speed transmission circuit (1), the pattern generator main control circuit (2), the CLK&SFP+ switching circuit (3), the pattern generator sub-field and shaping control circuit (4), the beam gate control circuit (5), the video generation circuit (6) and the motion correction circuit (7) are all placed in the same 6U standard VPX pattern generator frame and inserted in different slots.

7. The pattern generator circuit system of the deformable electron beam exposure machine according to claim 1, 2 or 3, characterized in that: The pattern generator main control circuit (2) is a circuit with FPGA+DSP as the core architecture. The FPGA and DSP exchange data via SRIO. Its function is to receive data transmitted by the high-speed transmission circuit (1), which is received by the FPGA. The FPGA transmits the data to the DSP, which performs graphic algorithm calculations to generate graphic coordinates required subsequently; at the same time, it receives signals from the beam detection circuit (8), collects beam concentration information, and adjusts the beam concentration in real time according to actual needs; at the same time, it receives backscattered electron signals sent by the backscattered electron signal detection circuit (9). The signal is divided into two parts, one for scanning imaging and the other for mark detection.

8. The pattern generator circuit system of the deformable electron beam exposure machine according to claim 7, characterized in that: The pattern generator main control circuit (2) adopts an address selection method to time-share control the selection of subfield data or shaping data and beam gate control data to be sent to the pattern generator subfield and shaping control circuit (4). The pattern generator subfield and shaping control circuit (4) determines to send the data result to the corresponding subfield switching circuit (11), shaping switching circuit (12) and beam gate control circuit (5) according to the address selection data.

9. The pattern generator circuit system of the deformable electron beam exposure machine according to claim 1, 2 or 3, characterized in that: The main field switching circuit (10) is a circuit with an FPGA as its core structure, and is used to receive the differential signal from the pattern generator main control circuit (2) and convert it into a single-ended signal. The single-ended signal is then converted into a 16-bit parallel differential signal and connected to the main field power supply circuit (14) of the next level.

10. The pattern generator circuit system of the deformable electron beam exposure machine according to claim 1, 2 or 3, characterized in that: The sub-field switching circuit (11) is a circuit with an FPGA as its core structure, and is used to receive the differential signal of the image generating sub-field and the shaping control circuit (4) and convert it into a single-ended signal. The single-ended signal is then converted into a 16-bit parallel differential signal and connected to the sub-field power supply circuit (16) of the next level. The shaping switching circuit (12) is a circuit with an FPGA as its core structure, and is used to receive differential signals from the image generating sub-field and the shaping control circuit (4), and convert them into single-ended signals. The single-ended signals are then converted into 16-bit parallel differential signals and connected to the shaping power supply circuit (17) of the next level.

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