Transistor, method for manufacturing the same and electronic device

Abstract

The transistor, preparation method thereof and electronic device disclosed in the present invention include a substrate; a source electrode located on one side of the substrate; a gate electrode arranged along a first direction on the same side of the substrate as the source electrode, and the gate electrode includes a first boundary away from the substrate side, and both ends of the first boundary are arc-shaped boundaries. The first boundary of the gate disclosed in the present invention is an arc-shaped boundary at both ends away from the substrate side, that is, the gate disclosed in the present invention includes an arc-shaped edge, which has a relatively gentle shape, so that the dielectric layer covering the gate will inherit the smooth shape of the arc-shaped edge without sharp corners, showing good thickness uniformity, and because the dielectric layer has a smooth transition, when the device is reversely resisted and self-heated, there is no local excessive stress and fracture, but it is evenly stressed to avoid disconnection and become a weak point of reliability.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a transistor, a manufacturing method thereof, and an electronic device. Background Art

[0002] In the reliability assessment of silicon carbide devices, the breakdown of the dielectric layer (ILD) at the edge of the gate is a major cause of device failure. Figure 1 This is a schematic diagram of the gate structure formed by dry etching. Figure 2 The schematic diagram of the gate structure formed by wet etching is shown in FIG. Figure 1 and Figure 2 It can be seen that the upper and lower ends of the gate formed by the two methods are sharp corners. The ILD has a minimum thickness at the sharp corner, which is much smaller than the horizontal or vertical thickness. Because the strongest field strength often exists at the sharp corner, the sharp corner becomes one of the points where the device is most likely to be broken down. When the device is in reverse bias, the ILD of the device is required to be thick enough not to be broken down and cause gate-source short circuit. By increasing the thickness of the ILD, its anti-breakdown capability can be enhanced, but the thicker the ILD, the larger the size (pitch) of the device, causing the device's on-current to decrease and the on-resistance to rise rapidly. With the development of power devices, the demand for high current devices is getting higher and higher, and the thickness of the corresponding ILD is gradually decreasing, and the problem of sharp corner breakdown is more prominent. In addition, due to the different thermal expansion coefficients of metal and dielectric, when the device works at high temperature, the ILD at the sharp corner of the gate has the lowest thickness, resulting in fracture at the sharp corner, and the metal contacts the gate along the crack, causing the gate-source short circuit and failure. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a transistor, a method for manufacturing the same, and an electronic device to improve the reliability of the transistor.

[0004] Therefore, the embodiments of the present disclosure provide a transistor, a method for manufacturing the same, and an electronic device, and the specific solutions are as follows:

[0005] In one aspect, an embodiment of the present disclosure provides a transistor, comprising:

[0006] substrate;

[0007] A source electrode, located at one side of the substrate;

[0008] The gate is arranged along a first direction on the same side of the substrate as the source, and the gate includes a first boundary away from one side of the substrate, and both ends of the first boundary are arc-shaped boundaries.

[0009] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, the cross-section of the gate perpendicular to the substrate is a rounded rectangle, and the rounded corners of the rounded rectangle are arranged away from the substrate.

[0010] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, a cross section of the gate perpendicular to the substrate includes a curved boundary that arches in a direction away from the substrate.

[0011] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, it further includes a first conductive type well layer embedded in the substrate, a second conductive type heavily doped layer embedded in the first conductive type well layer, and an ohmic contact layer electrically connected to the source; wherein,

[0012] The first conductive type well layer and the second conductive type heavily doped layer include a plurality of trenches at least partially penetrating the first conductive type well layer and the second conductive type heavily doped layer, and the ohmic contact layer contacts sidewalls and bottoms of the plurality of trenches.

[0013] In some embodiments, in the above-mentioned transistor provided by the embodiments of the present disclosure, the trench is a linear trench arranged along the first direction and extending along a second direction, and the second direction intersects with the first direction.

[0014] In some embodiments, in the above-mentioned transistor provided in the embodiments of the present disclosure, the groove is a strip groove extending along the second direction, and at least two strip grooves are respectively arranged in the first direction and the second direction, and the second direction intersects with the first direction.

[0015] In some embodiments, in the above-mentioned transistor provided by the embodiments of the present disclosure, the trench is an island-shaped trench arranged along the first direction and the second direction, and the second direction intersects with the first direction.

[0016] In some embodiments, the above-mentioned transistor provided by the embodiments of the present disclosure further includes a first conductive type heavily doped layer, and the first conductive type heavily doped layer is located on a side of the ohmic contact layer facing the substrate.

[0017] On the other hand, the present disclosure also provides a method for preparing the above transistor, comprising:

[0018] providing a substrate;

[0019] forming a gate on the substrate, wherein the gate comprises a first boundary away from one side of the substrate, and both ends of the first boundary are arc-shaped boundaries;

[0020] A source electrode is formed and arranged along a first direction with the gate electrode.

[0021] In some embodiments, in the above-mentioned preparation method provided in the embodiments of the present disclosure, forming the gate specifically includes:

[0022] forming a gate by a patterning process;

[0023] The gate is rounded by high temperature or atomic etching, so that two ends of the first boundary of the gate away from the substrate are arc-shaped boundaries.

[0024] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned transistor provided by an embodiment of the present disclosure.

[0025] The beneficial effects of the present disclosure are as follows:

[0026] The transistor, preparation method thereof and electronic device provided by the embodiment of the present disclosure include a substrate; a source electrode, located on one side of the substrate; a gate electrode, arranged along a first direction on the same side of the substrate as the source electrode, and the gate electrode includes a first boundary away from the substrate side, and both ends of the first boundary are arc-shaped boundaries. The first boundary of the gate of the present disclosure is arc-shaped at both ends away from the substrate side, that is, the gate of the present disclosure includes an arc-shaped edge, which has a relatively gentle shape, so that the dielectric layer covered on the gate will inherit the smooth shape of the arc-shaped edge without sharp corners, showing good thickness uniformity, and because the dielectric layer is a smooth transition, when the device is reversely resisted and self-heated, there is no local stress due to excessive stress and fracture, but it is evenly stressed to avoid disconnection and become a weak point of reliability. In addition, thanks to the smooth shape of the dielectric layer, the metal deposition after the dielectric layer is not easy to form voids, and the reliability is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the structure of forming a gate by dry etching;

[0028] Figure 2 A schematic diagram of the structure of forming a gate by wet etching;

[0029] Figure 3 A schematic diagram of a structure of a transistor provided in an embodiment of the present disclosure;

[0030] Figure 4 for Figure 3 A schematic diagram of the structure of the gate in the transistor shown;

[0031] Figure 5 A schematic diagram of another structure of a transistor provided in an embodiment of the present disclosure;

[0032] Figure 6 for Figure 5 A schematic diagram of the structure of the gate in the transistor shown;

[0033] Figure 7 A schematic diagram of a structure of multiple grooves provided in an embodiment of the present disclosure;

[0034] Figure 8 Another schematic diagram of the structure of multiple grooves provided in an embodiment of the present disclosure;

[0035] Fig. 9 Another schematic diagram of the structure of multiple grooves provided in an embodiment of the present disclosure;

[0036] Fig.10 A flowchart of a method for preparing a transistor provided in an embodiment of the present disclosure;

[0037] Fig.11 for Figure 3 A schematic diagram of a structure of a transistor during the preparation process shown;

[0038] Fig.12 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0039] Fig.13 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0040] Fig.14 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0041] Fig.15 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0042] Fig.16 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0043] Fig.17 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0044] Fig.18 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0045] Fig.19 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0046] Fig. 20 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0047] Fig.21 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0048] Fig. 22 for Figure 3 Another schematic diagram of the structure of the transistor during the preparation process shown;

[0049] Fig.23 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that in the drawings, the thickness of the layer, film, panel, area, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shape of the figure as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shape of the area shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes are not intended to illustrate the exact shape of the area, do not reflect the true proportion, and the purpose is only to illustrate the content of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0051] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0052] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] The present disclosure provides a transistor, such as Figures 3 to 6 As shown, this may include:

[0054] The substrate 101 , optionally, is an N-type silicon carbide substrate or a P-type silicon carbide substrate.

[0055] The source 102 is located on one side of the substrate 101. In some embodiments, the source 102 may be made of a conductive metal, such as aluminum Al, or aluminum doped with Si / Cu / Ti or other metals (such as AlSixCuy) to prevent the formation of aluminum nails that damage the stability of the device.

[0056] The gate 103 and the source 102 are arranged on the same side of the substrate 101 along the first direction X. The cross section of the gate 103 perpendicular to the substrate 101 (i.e., the cross section along the Z direction) includes a first boundary away from the side of the substrate 101, and both ends of the first boundary are arc-shaped boundaries. In other words, the gate 103 includes a first surface S1 away from the side of the substrate 101, and the first surface S1 includes an arc-shaped edge S11 extending along the second direction Y. The second direction Y intersects with the first direction X (for example, perpendicular to each other). In some embodiments, the gate 103 can be formed by a patterning process (including but not limited to deposition, photoresist coating, mask template masking, exposure, development, dry etching / wet etching, photoresist stripping) Figure 1 or Figure 2 The gate is then etched by high temperature or atomic etching. Figure 1 or Figure 2 The gate shown is rounded to form Figures 3 to 6 The gate 103 shown has an arc-shaped edge S11;

[0057] In the above transistor provided in the embodiment of the present disclosure, the gate 103 including the arc edge S11 has a relatively gentle shape, so that the dielectric layer 104 covered on the gate 103 will inherit the smooth shape of the arc edge without sharp corners, showing good thickness uniformity. Because the dielectric layer 104 has a smooth transition, when the device is reversely resisted and self-heated, there is no local stress that is too large and breaks, but it is evenly stressed to avoid disconnection and become a weak point of reliability. In addition, thanks to the smooth shape of the dielectric layer 104, the metal deposition after the dielectric layer 104 is not easy to form voids (if there are sharp corners or steep slopes, the metal will be closed in advance at the sharp corners or steep slopes during deposition to form voids), and the reliability is better. Optionally, the metal deposited after the dielectric layer 104 is used to form the source 102 and the lead 105 electrically connected to the gate 103.

[0058] It should be noted that due to the limitations of process conditions or the influence of other factors such as measurement, "uniform thickness" may be completely identical or may have some deviations. Therefore, as long as the relationship of "uniform thickness" satisfies the error allowance, it falls within the scope of protection of the present disclosure.

[0059] In some embodiments, in the above transistors provided in the embodiments of the present disclosure, if Figure 3 and Figure 4 As shown, the cross section of the gate 103 perpendicular to the substrate 101 can be a rounded rectangle, and the rounded corners of the rounded rectangle are set away from the substrate 101, which is equivalent to the present disclosure that only the edge of the first surface S1 of the gate 103 away from the substrate 101 can be set to be an arc shape, and the portion between the arc edges S11 is a plane S12 extending along the second direction Y. The thickness of the gate 103 at the plane S12 is relatively uniform, and the thickness at the arc edge S11 gradually decreases in the direction away from the plane S12. In other embodiments, such as Figure 5 and Figure 6 As shown, the cross section of the gate 103 perpendicular to the substrate 101 may include a curved boundary that arches in the direction Z away from the substrate 101, which is equivalent to the present disclosure also being able to set the first surface S1 of the gate 103 on the side away from the substrate 101 as a curved surface (such as a circular arc surface, an elliptical arc surface, etc.) that arches in the direction Z away from the substrate 101. In this case, the thickness of the gate 103 gradually decreases from the center to both sides along the first direction X. It can be seen that the shape of the gate of the present disclosure can be rounded from only the edge to the whole. Figures 3 to 6 It can be seen that the gate 103 may further include a second surface S2 extending along the second direction Y and connected to the first surface S1. Optionally, the second surface S2 is perpendicular to the substrate 101, or the second surface S2 and the first surface S1 together constitute a curved surface (such as a circular arc surface, an elliptical arc surface, etc.) that is arched away from the substrate 101.

[0060] In some embodiments, in the above transistors provided in the embodiments of the present disclosure, if Figure 3 and Figure 5 As shown, it may also include a first conductive type (e.g., P-type or N-type) well layer 106 embedded in the substrate 101, a second conductive type (e.g., N-type or P-type) heavily doped layer 107 embedded in the first conductive type well layer 106, and an ohmic contact layer 108 electrically connected to the source 102; wherein the first conductive type well layer 106 and the second conductive type heavily doped layer 107 include a plurality of grooves V at least partially penetrating the first conductive type well layer 106 and the second conductive type heavily doped layer 107, that is, the depth of the groove V in the present disclosure may range from the surface of the source 102 to penetrating the first conductive type well layer 106; the ohmic contact layer 108 may contact the sidewalls and bottom of the plurality of grooves V. The groove contact may increase the ohmic contact area of ​​the source region, achieve a better contact effect, and may transform the planar contact into the groove contact, so as to further reduce the size of the planar device, so as to improve the chip utilization area and performance.

[0061] In some embodiments, the first conductive well layer 106 is a P well layer, and the second conductive heavily doped layer 107 is an N+ doped layer, and the P well layer and the N+ doped layer can be formed by ion implantation. The ion source of the P well layer can be a gas or solid containing Al. Specifically, the material used in the present disclosure is AlI with a concentration of 10 17 cm -3 ~10 18 cm -3 , depth is 0.5μm~1μm, injection energy is 5k -1 MeV, the temperature is 500℃. The doping element of the N+ doping layer can be nitrogen or phosphorus. Phosphorus has a higher solid solubility and has a smaller resistance. Specifically, the doping element is phosphorus, and the material can be PH3, P2O5, etc. The doping concentration is 10 19 cm -3 ~10 20 cm -3 , depth is 0.2μm~0.3μm, and injection energy is 200keV~300keV.

[0062] In some embodiments, in the above transistors provided in the embodiments of the present disclosure, if Figure 7 As shown, the groove V may be a linear groove arranged along the first direction X and extending along the second direction Y. Alternatively, as Figure 8 As shown, the groove V may also be a strip groove extending along the second direction Y, and at least two strip grooves are respectively provided in the first direction X and the second direction Y. Alternatively, as Fig. 9As shown, the groove V can also be an island-shaped groove arranged along the first direction X and the second direction Y. In other words, the groove V of the present disclosure can be continuous in the second direction Y, or it can be disconnected and non-continuous. Optionally, the grooves V arranged along the first direction X can be aligned side by side or partially staggered, and the grooves V arranged along the second direction Y can be side by side, aligned, or partially staggered. In addition, in the present disclosure, the gate 103 and the groove V can be combined in any manner, such as an edge arc-shaped gate + island-shaped groove, an overall arc-shaped gate + long strip groove, an overall arc-shaped gate + island-shaped groove, etc.

[0063] In some embodiments, in the above transistors provided in the embodiments of the present disclosure, if Figure 3 and Figure 5 As shown, it may also include a first conductive type heavily doped layer 109, which is located on the side of the ohmic contact layer 108 facing the substrate 101. Taking the first conductive type as P type as an example, a P+ doped layer can be formed by ion implantation after the trench V. Specifically, the material used in the present disclosure is AlI with a concentration of 10 19 cm -3 ~10 20 cm -3 , depth is 0.2μm~0.7μm, injection energy is 200keV~700keV, temperature is 500℃. The existence of P+ doping layer transfers the electric field from the device surface to the body region, there is no strong electric field on the device surface, the self-heating effect is reduced, and the layers above gate oxide 110 will not become premature breakdown points.

[0064] In some embodiments, the parasitic NPN (N+ doped layer-P+ doped layer-N+ doped layer) or PNP (P+ doped layer-N+ doped layer-P+ doped layer) of the transistor are in contact with each other, and a PN junction can be formed at the interface. The present disclosure interrupts the parasitic NPN or PNP through multiple grooves V, thereby removing the parasitic NPN or PNP, avoiding false triggering of the device in high-speed switching, which is beneficial to improving the stability of the application of the switching device; at the same time, the strong electric field strength is moved from the gate oxide 110 to the body region, avoiding the gate from being weak and being broken down, and achieving a stronger gate oxide 110 reliability effect.

[0065] In some embodiments, in the above transistors provided in the embodiments of the present disclosure, if Figure 3 and Figure 5 As shown, it may also include a drain 111, etc. Other essential components of the transistor are well understood by those skilled in the art, and will not be described in detail here, nor should they be used as limitations to the present disclosure.

[0066] Based on the same inventive concept, an embodiment of the present disclosure provides a method for preparing the above-mentioned transistor. Since the principle of solving the problem by the manufacturing method is similar to the principle of solving the problem by the above-mentioned transistor, the implementation of the manufacturing method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned transistor provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0067] In some embodiments, the method for manufacturing a transistor provided by the embodiments of the present disclosure is as follows: Fig.10 As shown, the following steps may be included:

[0068] S1001, providing a substrate;

[0069] S1002, forming a gate on a substrate, wherein the gate includes a first boundary away from a side of the substrate, and two ends of the first boundary are arc-shaped boundaries;

[0070] S1003 , forming a source electrode arranged along a first direction with the gate electrode.

[0071] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, the above-mentioned step S1002, forming a gate, can be specifically implemented in the following manner:

[0072] forming a gate by a patterning process;

[0073] The gate is rounded by high temperature or atomic etching, so that two ends of the first boundary of the gate away from the substrate are arc-shaped boundaries.

[0074] In order to better understand the above preparation method provided by the embodiment of the present disclosure, the present disclosure assumes that the first conductivity type is P type and the second conductivity type is N type. Figure 3 The preparation process of the transistor shown is described in detail.

[0075] In some embodiments, Figure 3 The preparation process of the transistor shown may specifically include the following steps:

[0076] The first step is to grow a substrate 101 (eg, an N-type SiC substrate) and perform epitaxy.

[0077] The second step is to grow a hard mask HM. In some embodiments, HM can be one or more combinations of silicon dioxide, silicon nitride, titanium nitride, and polysilicon. The thickness of HM is determined by software simulation based on the subsequent ion implantation energy and dose of the first conductive well layer 106 (e.g., P-well layer). The greater the ion implantation energy and dose, the thicker the required HM. Specifically, the present disclosure uses PECVD to grow 15K TEOS as a hard mask, using TEOS and O2 as materials, and the temperature is 350°C to 420°C.

[0078] The third step is to apply resist and develop to remove the photoresist in the area where the first conductive type well layer 106 is to be formed.

[0079] The fourth step is to etch the HM not covered by the photoresist. Specifically, the present disclosure uses a dry method to etch the HM, using materials such as CF4, CHF3 and Ar.

[0080] The fifth step is to remove the photoresist. Specifically, the photoresist is etched by dry etching, and the material used is O2.

[0081] Step 6: ion implantation to form a first conductive type well layer 106 (eg, a P well layer, PW), such as Fig.11 The ion source can be a gas or solid containing Al. Specifically, the material used in the present disclosure is AlI with a concentration of 10 17 cm -3 ~10 18 cm -3 , depth is 0.5μm~1μm, injection energy is 5k -1 MeV, and the temperature is 500°C.

[0082] Step 7: Remove HM. Specifically, wet etching is used to remove the hard mask HM, and the material used is DHF.

[0083] Step 8: Growth of HM. PECVD is used to grow TEOS as a hard mask HM. The thickness of the mask is determined by the ion implantation depth of the subsequent second conductive type heavily doped layer 107 (e.g., N+ doped layer). The greater the ion implantation depth, the thicker the required HM. Specifically, 8K TEOS is grown as a hard mask, using TEOS and O2 as materials, and the temperature is 350°C to 420°C.

[0084] The ninth step is to apply resist and develop to remove the photoresist in the area where the second conductive type heavily doped layer 107 (eg, N+ doped layer) is to be fabricated.

[0085] The tenth step is to etch the HM exposed by the photoresist. Specifically, the present disclosure uses a dry method to etch the HM, and the materials used are CF4, CHF3 and Ar.

[0086] Step 11: removing the photoresist. Specifically, the photoresist is etched by dry etching, and the material used is O2.

[0087] In the twelfth step, ion implantation is performed to form a second conductive type heavily doped layer 107 (eg, an N+ doped layer). Fig.12 As shown. Optionally, the doping element of the second conductive type heavily doped layer 107 (eg, N+ doped layer) may be nitrogen or phosphorus. Phosphorus has a higher solid solubility and has a lower resistance. Specifically, the doping element is phosphorus, and the material may be PH3, P2O5, etc., with a doping concentration of 10 19 cm-3 ~10 20 cm -3 , depth is 0.2μm~0.3μm, and injection energy is 200keV~300keV.

[0088] Step 13: Remove HM. Specifically, wet etching is used to remove the hard mask HM, and the material used is DHF.

[0089] Step 14: Growth of HM. PECVD is used to grow TEOS as a hard mask HM. The mask thickness is determined by the ion implantation depth of the subsequent first conductivity type heavily doped layer 109. Specifically, the present disclosure grows 16K TEOS as a hard mask, using TEOS and O2 as materials at a temperature of 350°C to 420°C.

[0090] The fifteenth step is to apply glue and develop the photoresist in the area where the multiple grooves V are to be made.

[0091] Step 16: Etch away the HM not covered by the photoresist. Specifically, the present disclosure uses a dry method to etch the HM, using materials such as CF4, CHF3 and Ar.

[0092] Step 17: removing the photoresist. Specifically, the photoresist is etched by dry etching, and the material used is O2.

[0093] In step 18, the second conductive type heavily doped layer 107 (eg, N+ doped layer) and the first conductive type well layer 106 (eg, P well layer) are etched to form a trench V. Fig.13 Specifically, the materials used are SF6, O2, C4F8 and Ar, dry etching is used, and EDP is used to detect the etching situation. When the first conductive well layer 106 (for example, the P well layer) is completely etched through, that is, the etching stops when the pure SiC layer under the first conductive well layer 106 (for example, the P well layer) is etched.

[0094] In the nineteenth step, ion implantation is performed to form a first conductive type heavily doped layer (eg, a P+ doped layer) 109, such as Fig.14 Specifically, the material used in the present disclosure is AlI, with a concentration of 10 19 cm -3 ~10 20 cm -3 , depth is 0.2μm~0.7μm, injection energy is 200keV~700keV, and temperature is 500℃.

[0095] Step 20: Remove HM. Specifically, use wet etching to remove the hard mask HM, and the material used is DHF.

[0096] Step 21: high temperature annealing to eliminate the lattice damage caused by the P+ ion implantation in step 19. Specifically, the material used is N2, the temperature is 1650°C to 1750°C, and the time is 30 minutes to 3 hours.

[0097] Step 22: grow a sacrificial oxide layer and remove it by wet etching to make the surface smooth, reduce the interface state density, increase the carrier mobility, increase the current, and reduce the resistance. Specifically, the temperature is 1200°C to 1350°C, the thickness of the sacrificial oxide layer is 50nm to 100nm, and the sacrificial oxide layer is removed by wet etching, and the material used is DHF.

[0098] Step 23: growing gate oxide 110, such as Fig.15 As shown. The gate oxide 110 can be grown by LPCVD / thermal oxidation / ALD. Specifically, the gate oxide 110 is deposited by LPCVD at 760°C~800°C, with a thickness of 40 nm~100nm, depending on the device threshold / voltage design, etc. The materials used are DCS and O2. After the gate oxide 110 is deposited, it is annealed in a NO atmosphere at a temperature of 1000°C~1300°C and an annealing time of 30min~3h.

[0099] In the twenty-fourth step, polysilicon 103' is deposited to form the gate 103, such as Fig.16 Specifically, the material used is N-type polysilicon, and the doping element is nitrogen or phosphorus with a concentration of 10 20 cm -3 ~10 21 cm -3 , thickness is equal to the depth of groove V.

[0100] In the twenty-fifth step, the polysilicon 103' is etched to form the gate 103, as shown in FIG. Fig.17 Specifically, the etching can be performed by wet etching or dry etching; wherein, the wet etching can be performed by using solutions such as H2O2 / HF / H2O, and the dry etching can be performed by using fluorine-based and chlorine-based etching solutions such as CF4, Cl2, etc.

[0101] In the 26th step, the gate 103 is smooth, such as Fig.18 As shown. The gate 103 can be rounded by high temperature or atomic etching. For the high temperature method, the gate 103 can be rounded under high temperature conditions by mixing O2 / H2 / N2 in different proportions. For atomic etching, since the reaction area at the sharp corner is larger than that at the flat surface, it has a faster rate. By controlling the progress of the reaction, the gate 103 with an arc-shaped edge can be obtained. The thickness of the gate 103 at the middle plane is relatively uniform, and the thickness at the arc-shaped edges on both sides gradually decreases in the direction away from the middle plane.

[0102] In step 27, a dielectric layer (ILD) 104 is grown, such as Fig.19 As shown. The dielectric layer 104 can be any combination of silicon oxide, borophosphorus glass or silicon nitride. In the present disclosure, the dielectric layer 104 is a double-layer combination of silicon oxide and borophosphorus glass. PECVD can be used for growth, using materials such as TEOS, O2, BH3 and P2O5, and a temperature of 350°C to 420°C.

[0103] Step 28: Apply glue and develop to remove the photoresist at the source contact hole.

[0104] In step 29, the dielectric layer 104 exposed by the photoresist is removed by etching to form a source contact hole penetrating the dielectric layer 104, such as Fig. 20 Specifically, the present disclosure uses dry etching of the dielectric layer 104, and the materials used are CF4, CHF3 and Ar.

[0105] In the 30th step, Ni is deposited and annealed at high temperature to form an ohmic contact layer 108 (such as ohmic contact silicide), such as Fig.21 Specifically, a Ni layer of 50 nm to 200 nm is deposited and rapidly annealed twice in RTP to form Ni2Si. Since the dielectric layer 104 does not react with Ni to form silicide, the unreacted Ni can be removed by wet method.

[0106] In the 31st step, the dielectric layer 104 is etched to form a gate contact hole. Specifically, the dielectric layer 104 is etched by dry etching, and the materials used are CF4, CHF3 and Ar.

[0107] Step 32: deposit a metal interconnection layer MC, such as Fig. 22 As shown. Aluminum doped with Si / Cu / Ti or other metals can be used as the metal interconnection layer MC to prevent the formation of aluminum nails that damage the stability of the device. Specifically, the present disclosure uses PVD to sputter the metal interconnection layer MC of 3μm to 6μm, and the material used is AlSixCuy. The metal interconnection layer MC is patterned to form the source 102 and the lead 105 electrically connected to the gate 103.

[0108] Step 33: Complete the subsequent process steps of depositing and etching metal, forming a passivation layer, and thinning the back gold to form a drain 111. Figure 3 The transistor shown.

[0109] Based on the same inventive concept, the present disclosure provides an electronic device, such as Fig.23 As shown, it includes the transistor 001 provided in the embodiment of the present disclosure. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the transistor, the implementation of the electronic device provided in the embodiment of the present disclosure can refer to the implementation of the transistor provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0110] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, household appliances, etc. Of course, the electronic devices provided by the present disclosure may include other structures in addition to transistors. For example, when the electronic device is a radar, it also includes: transmitters, antennas, receivers, etc.; when the electronic device is a mixer, it also includes: input ports, output ports, etc.

[0111] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A transistor, characterized in that: include: substrate; Two source electrodes, located on one side of the substrate; A gate electrode, arranged along a first direction on the same side of the substrate as the two source electrodes, the gate electrode comprising a first boundary away from one side of the substrate, and both ends of the first boundary are arc-shaped boundaries; A first conductive type well layer embedded in the substrate, a second conductive type heavily doped layer embedded in the first conductive type well layer, and an ohmic contact layer electrically connected to the two source electrodes; wherein, The first conductive well layer and the second conductive heavily doped layer include a plurality of grooves that at least partially penetrate the first conductive well layer and the second conductive heavily doped layer, and the ohmic contact layer electrically connected to the source on one side of the gate contacts the sidewalls and bottoms of the plurality of grooves.

2. The transistor according to claim 1, characterized in that The cross section of the gate perpendicular to the substrate is a rounded rectangle, and the rounded corners of the rounded rectangle are arranged away from the substrate.

3. The transistor according to claim 1, characterized in that A cross section of the gate perpendicular to the substrate includes a curved boundary that arches away from the substrate.

4. The transistor according to claim 3, characterized in that The grooves are linear grooves arranged along the first direction and extending along a second direction, and the second direction intersects with the first direction.

5. The transistor according to claim 3, characterized in that The groove is a strip-shaped groove extending along a second direction, and at least two strip-shaped grooves are respectively arranged in the first direction and the second direction, and the second direction intersects with the first direction.

6. The transistor according to claim 3, characterized in that The grooves are island-shaped grooves arranged along the first direction and the second direction, and the second direction intersects with the first direction.

7. The transistor according to claim 3, characterized in that It also includes a first conductive type heavily doped layer, and the first conductive type heavily doped layer is located on a side of the ohmic contact layer facing the substrate.

8. A method for preparing a transistor according to any one of claims 1 to 7, characterized in that: include: providing a substrate; forming a gate on the substrate, wherein the gate comprises a first boundary away from one side of the substrate, and both ends of the first boundary are arc-shaped boundaries; A source electrode is formed and arranged along a first direction with the gate electrode.

9. The preparation method according to claim 8, characterized in that: Forming the gate specifically includes: forming a gate by a patterning process; The gate is rounded by high temperature or atomic etching, so that two ends of the first boundary of the gate away from the substrate are arc-shaped boundaries.

10. An electronic device, characterized in that: Comprising a transistor as described in any one of claims 1 to 7.

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