Clock driver for time-interleaved digital-to-analog converter

Abstract

In certain aspects, a method for providing first and second drive clock signals to first and second sub-digital-to-analog converters (sub-DACs) includes receiving an input clock signal and dividing the input clock signal to generate first and second divided clock signals. The method also includes gating the input clock signal using the first divided clock signal to generate a first drive clock signal and inputting the first drive clock signal to a clock input of the first sub-DAC. The method also includes gating the input clock signal using the second divided clock signal to generate a second drive clock signal and inputting the second drive clock signal to a clock input of the second sub-DAC.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to non-provisional patent application serial number 17 / 654,916, filed on March 15, 2022, with the United States Patent and Trademark Office, the entire contents of which are as fully set forth herein and incorporated herein for all applicable purposes. background Technical Field

[0004] All aspects of this disclosure relate generally to digital-to-analog converters (DACs), and more specifically to time-interleaved DACs. Background Technology

[0006] High-bandwidth communication systems require high-speed digital-to-analog conversion. One technique for achieving high-speed digital-to-analog conversion is to time-interleave two or more digital-to-analog converters (DACs), in which two or more interleaved DACs alternately convert digital signals into analog signals. Summary of the Invention

[0007] The following is a simplified overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0008] A first aspect relates to a system. The system includes a clock divider circuit having an input terminal, a first output terminal, and a second output terminal, wherein the input terminal of the clock divider circuit is configured to receive an input clock signal. The system also includes a first clock gating circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first clock gating circuit is configured to receive the input clock signal, and the second input terminal of the first clock gating circuit is coupled to the first output terminal of the clock divider circuit. The system further includes a second clock gating circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second clock gating circuit is configured to receive the input clock signal, and the second input terminal of the second clock gating circuit is coupled to the second output terminal of the clock divider circuit. The system also includes a first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gate circuit; and a second sub-DAC having a clock input coupled to the output of the second clock gate circuit.

[0009] A second aspect is directed to a system. The system includes a clock division circuit having an input, a first output, and a second output, where the input of the clock division circuit is configured to receive an input clock signal. The system also includes a first clock gating circuit having a first input, a second input, and an output, where the first input of the first clock gating circuit is configured to receive the input clock signal and the second input of the first clock gating circuit is coupled to the first output of the clock division circuit. The system further includes a multiplexer having a first input, a second input, and an output, where the first input of the multiplexer is coupled to the first output of the clock division circuit and the second input of the multiplexer is coupled to the second output of the clock division circuit. The system also includes a second clock gating circuit having a first input, a second input, and an output, where the first input of the second clock gating circuit is configured to receive the input clock signal and the second input of the second clock gating circuit is coupled to the output of the multiplexer. The system further includes a first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gating circuit and a second sub-DAC having a clock input coupled to the output of the second clock gating circuit.

[0010] A third aspect is directed to a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC. The method includes receiving an input clock signal and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate a first drive clock signal and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate a second drive clock signal and inputting the second drive clock signal to a clock input of the second sub-DAC. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 An example of a time-interleaved digital-to-analog converter (DAC) circuit is shown in accordance with certain aspects of the present disclosure.

[0012] Figure 2 An example of a clock circuit coupled to a time-interleaved DAC circuit is shown in accordance with certain aspects of the present disclosure.

[0013] Figure 3is a timing diagram illustrating an example of a clock signal input to a time-interleaved DAC circuit, in accordance with certain aspects of the present disclosure.

[0014] Figure 4 An example of a clock circuit including a clock gating circuit is shown, in accordance with certain aspects of the present disclosure.

[0015] Figure 5 is a timing diagram illustrating an example of a clock signal in the clock circuit of Figure 4 , in accordance with certain aspects of the present disclosure.

[0016] Figure 6A An example implementation of a clock gating circuit is shown, in accordance with certain aspects of the present disclosure.

[0017] Figure 6B Another example implementation of a clock gating circuit is shown, in accordance with certain aspects of the present disclosure.

[0018] Figure 7A is a timing diagram illustrating an example of signals in a first clock gating circuit and a second clock gating circuit, in which each of the first clock gating circuit and the second clock gating circuit is implemented with an example clock gating circuit of Figure 6A , in accordance with certain aspects of the present disclosure.

[0019] Figure 7B is a timing diagram illustrating an example of signals in a first clock gating circuit and a second clock gating circuit, in which each of the first clock gating circuit and the second clock gating circuit is implemented with an example clock gating circuit of Figure 6B , in accordance with certain aspects of the present disclosure.

[0020] Figure 8 An example of a wireless device including a clock circuit and a DAC circuit is shown, in accordance with certain aspects of the present disclosure.

[0021] Figure 9 An example implementation of a transmitter is shown, in accordance with certain aspects of the present disclosure.

[0022] Figure 10 An example of a clock circuit driving clock inputs of a plurality of sub-DACs is shown, in accordance with certain aspects of the present disclosure.

[0023] Figure 11 An example implementation of a transmitter including an in-phase path and a quadrature path is shown, in accordance with certain aspects of the present disclosure.

[0024] Figure 12 An example of a clock circuit including a plurality of clock gating circuits is shown, in accordance with certain aspects of the present disclosure.

[0025] Figure 13A An example of a programmable clock circuit and a programmable DAC circuit is shown in accordance with certain aspects of the present disclosure.

[0026] Figure 13B An example of a programmable clock circuit in a transmitter coupled to a programmable DAC circuit is shown in accordance with certain aspects of the present disclosure. Figure 13A

[0027] Figure 13C An example of a programmable clock circuit in a transmitter coupled to a programmable DAC circuit is shown in accordance with certain aspects of the present disclosure.

[0028] Figure 14 An example of a clock multiplexer coupled to a clock circuit is shown in accordance with certain aspects of the present disclosure.

[0029] Figure 15 An example of a clock circuit including a bypass switch and a short switch is shown in accordance with certain aspects of the present disclosure.

[0030] Figure 16 An example of a clock division circuit is shown in accordance with certain aspects of the present disclosure.

[0031] Figure 17 is a flowchart illustrating an example method of providing a first drive clock signal and a second drive clock signal to a first sub-DAC and a second sub-DAC in accordance with certain aspects of the present disclosure.

[0032] Figure 18 is a flowchart illustrating another example method of providing a first drive clock signal and a second drive clock signal to a first sub-DAC and a second sub-DAC in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0033] The detailed description set forth below, in connection with the appended drawings and embodiments described herinin, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0034] High bandwidth communication systems require high speed digital to analog conversion. One technique for implementing high speed digital to analog conversion is to time-interleave two or more digital to analog converters (DACs), in which two or more interleaved DACs alternately convert a digital signal to an analog signal. As used herein, a “DAC circuit” is a circuit that includes two or more DACs. Each of the two or more DACs in a DAC circuit can be referred to as a “sub-DAC.”​

[0035] Figure 1 An example of a DAC circuit 110 including a first sub-DAC 120, a second sub-DAC 130, and a combiner 140 is shown in accordance with certain aspects. The DAC circuit 110 has an input 112 configured to receive a digital signal, and an output 114. The first sub-DAC 120 has a data input 122, a clock input 124, and an output 126. The second sub-DAC 130 has a data input 132, a clock input 134, and an output 136. The data input 122 of the first sub-DAC 120 and the data input 132 of the second sub-DAC 130 are coupled to the input 112 of the DAC circuit 110. The combiner 140 has a first input 142 coupled to the output 126 of the first sub-DAC 120, a second input 144 coupled to the output 136 of the second sub-DAC 130, and an output 146 coupled to the output 114 of the DAC circuit 110. Although the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130 are each shown as a single-ended output in Figure 1 some implementations, the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130 can each be a differential output.

[0036] The first sub-DAC 120 receives the digital signal at the data input 122 and a clock signal clkl at the clock input 124. The first sub-DAC 120 is configured to convert the digital signal at the data input 122 to a first analog signal at the output 126. The first sub-DAC 120 is also configured to perform digital-to-analog conversion of the digital signal based on the clock signal clkl. For example, the first sub-DAC 120 can be configured to sample a digital value of the digital signal on an edge (e.g., a rising edge) of the clock signal clkl, and convert the sampled digital value to the first analog signal at the output 126. The clock signal clkl can also be referred to as a first driving clock signal because the clock signal clkl drives the clock input 124 of the first sub-DAC 120.

[0037] The second sub-DAC 130 receives the digital signal at a data input 132 and a clock signal clk2 at a clock input 134. The second sub-DAC 130 is configured to convert the digital signal at the data input 132 to a second analog signal at an output 136. The second sub-DAC 130 is also configured to perform the digital-to-analog conversion of the digital signal based on the clock signal clk2. For example, the second sub-DAC 130 can be configured to sample a digital value of the digital signal on an edge (e.g., a rising edge) of the clock signal clk2 and convert the sampled digital value to the second analog signal at the output 136. The clock signal clk2 can also be referred to as a second driving clock signal because the clock signal clk2 drives the clock input 134 of the second sub-DAC 130.

[0038] The combiner 140 is configured to receive the first analog signal from the first sub-DAC 120 at a first input 142, receive the second analog signal from the second sub-DAC 130 at a second input 144, and combine the first analog signal and the second analog signal into a combined analog signal at an output 146. The combined analog signal is output at the output 114 of the DAC circuit 110. In some implementations, the combiner 140 can be implemented by shorting the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130. Thus, the DAC circuit 110 converts the digital signal at the input 112 to the combined analog signal at the output 114.

[0039] As discussed above, the first sub-DAC 120 performs the digital-to-analog conversion of the digital signal based on the clock signal clk1 and the second sub-DAC 130 performs the digital-to-analog conversion of the digital signal based on the clock signal clk2. In certain aspects, the clock signal clk2 is phase shifted 180 degrees (i.e., half a clock period) with respect to the clock signal clk1. This causes the first sub-DAC 120 and the second sub-DAC 130 to alternately perform the digital-to-analog conversion. In certain aspects, each of the clock signal clk1 and the clock signal clk2 has a frequency F s . Thus, each of the first sub-DAC 120 and the second sub-DAC 130 performs the digital-to-analog conversion at a frequency (i.e., rate) F s . Since the first sub-DAC 120 and the second sub-DAC alternately perform the digital-to-analog conversion, the DAC circuit 110 can convert the digital signal at the input 112 to an analog signal (i.e., the combined analog signal at the output 114) at a frequency 2F s (i.e., twice the frequency of each of the sub-DACs 120 and 130). Thus, the DAC circuit 110 implements a digital-to-analog conversion rate that is twice the digital-to-analog conversion rate of each of the sub-DACs 120 and 130.

[0040] One challenge with using the DAC circuit 110 is the time skew between the sub-DACs 120 and 130, which degrades the image decay and interleaving operations. For example, the time skew can be caused by a phase imbalance in which the clock signal clk2 is not precisely out of phase by 180 degrees from the clock signal clk1. To address this issue, calibration techniques have been developed that measure the image power due to the time skew and use a delay control circuit to reduce the time skew based on the measurement. However, the calibration techniques can be complex, require a long calibration time, and consume a large amount of power and area.

[0041] Figure 2 An existing clock circuit 200 for generating the clock signals clk1 and clk2 is shown. The clock circuit 200 includes a clock divider 210 (also referred to as a frequency divider), a duty cycle correction (DCC) block 220, and clock buffers 230 and 240 coupled in series. The clock circuit 200 is configured to output the clock signal clk1, which is input to the clock input 124 of the first sub-DAC 120. In this example, the second sub-DAC 130 has an inverted clock input 134 (indicated by the circle at the clock input 134), which means that the clock signal clk1 is inverted to provide the clock signal clk2 to the second sub-DAC 130. Note that the data inputs and outputs of the sub-DACs 120 and 130 are not shown in FIG. 2 for ease of illustration. Figure 2

[0042] In this example, the clock circuit 200 receives an input clock clk_in at an input 202 having a frequency of 2F s . The clock divider 210 divides the frequency of the input clock clk_in by two to provide a divided clock signal having a frequency of F s . The DCC block 220 adjusts the duty cycle of the divided clock signal so that the clock signal clk1 at the output 204 has a duty cycle of approximately 50%. This helps to ensure that the clock signal clk1 and the clock signal clk2 are out of phase by approximately 180 degrees, as discussed further below. However, the DCC block 220 increases the complexity, area, and power consumption of the clock circuit 200.

[0043] Figure 3 is a timing diagram illustrating a case in which the duty cycle of the clock signal clk1 is not corrected by the DCC block 220. Ideally, when the duty cycle of the clock signal clk1 is 50%, the rising edge 310 and the falling edge 315 are separated by half a clock period (i.e., 0.5 / F s ), which corresponds to a phase of 180 degrees. However, in this example, the rising edge 310 and the falling edge 315 are separated by 0.6 / F Figure 3 ​In the illustrated example, the clock signal clk1 has a duty cycle less than 50%, which causes the interval between the rising edge 310 and the falling edge 315 to be less than half a clock period. When the clock signal clk1 is inverted to provide the clock signal clk2, the falling edge 315 becomes the rising edge 320 of the clock signal clk2. As Figure 3 In the illustrated example, the duty cycle less than 50% causes the phase difference between the rising edge 310 of the clock signal clk1 and the rising edge 320 of the clock signal clk2 to be less than 180 degrees, resulting in a time skew. Assuming that each of the sub-DACs 120 and 130 performs digital-to-analog conversion on the rising edge of the respective clock signal, the time skew degrades the time-interleaved operation of the DAC circuit 110.

[0044] Aspects of the present disclosure provide clock gating circuits for generating clock signals for sub-DACs with low time skew without the need for DCC blocks or calibration, as discussed further below. In addition, aspects of the present disclosure provide output switches, multiplexers, and internal bypass switches that can be used with the clock gating circuits to handle various phase requirements for different modes (e.g., 4G and 5G modes in a transceiver).

[0045] Figure 4 An example of a clock circuit 400 (also referred to as a clock driver) is shown in accordance with certain aspects of the present disclosure. The clock circuit 400 includes a clock frequency dividing circuit 410 (also referred to as a frequency divider), a first clock gating circuit (CGC) 420, and a second CGC 430. The clock circuit 400 has an input 402, a first output 404, and a second output 406. The input 402 is configured to receive an input clock signal clk_in from a clock source (e.g., a phase-locked loop (PLL)). The first output 404 is coupled to the clock input 124 of the first sub-DAC 120, and the second output 406 is coupled to the clock input 134 of the second sub-DAC 130.

[0046] The clock frequency dividing circuit 410 has an input 412, a first output 414, and a second output 416. The input 412 is coupled to the input 402 of the clock circuit 400 and is configured to receive the input clock signal clk_in. In one example, the input clock signal clk_in has a frequency 2F s . The clock frequency dividing circuit 410 is configured to divide the frequency of the input clock signal clk_in to generate a first divided clock signal and a second divided clock signal. In certain aspects, the second divided clock signal is approximately 180 degrees out of phase with the first divided clock signal, as discussed further below. In one example, the clock frequency dividing circuit 410 is configured to divide the frequency of the input clock signal clk_in by two, where the first divided clock signal and the second divided clock signal each have a frequency Fs However, it should be appreciated that the present disclosure is not limited to this example, and that the clock dividing circuit 410 can divide the frequency of the input clock signal clk_in by another divisor to generate the first and second divided clock signals. The clock dividing circuit 410 outputs the first divided clock signal at the first output 414 and the second divided clock signal at the second output 416.

[0047] The first CGC 420 has a first input 422, a second input 424, and an output 426. The first input 422 is coupled to the input 402 of the clock circuit 400 to receive the input clock signal clk_in, and the second input 424 is coupled to the first output 414 of the clock dividing circuit 410 to receive the first divided clock signal. The output 426 is coupled to the first output 404 of the clock circuit 400, which is coupled to the clock input 124 of the first sub-DAC 120. In operation, the first CGC 420 is configured to gate the input clock signal clk_in using the first divided clock signal, thereby generating the clock signal clk1 for the first sub-DAC 120.

[0048] The second CGC 430 has a first input 432, a second input 434, and an output 436. The first input 432 is coupled to the input 402 of the clock circuit 400 to receive the input clock signal clk_in, and the second input 434 is coupled to the second output 416 of the clock dividing circuit 410 to receive the second divided clock signal. The output 436 is coupled to the second output 406 of the clock circuit 400, which is coupled to the clock input 134 of the second sub-DAC 130. In operation, the second CGC 430 is configured to gate the input clock signal clk_in using the second divided clock signal, thereby generating the clock signal clk2 for the second sub-DAC 130.

[0049] To generate the out-of-phase 180-degree clock signals clk1 and clk2, the first CGC 420 and the second CGC 430 can gate alternate pulses of the input clock signal clk_in. For example, the first CGC 420 can gate even pulses of the input clock signal clk_in using the first divided clock signal to generate the clock signal clk1, and the second CGC 430 can gate odd pulses of the input clock signal clk_in using the second divided clock signal to generate the clock signal clk2, or vice versa.

[0050] Figure 5An example of clock gating is illustrated, showing an exemplary timing diagram of the input clock signal clk_in, the clock signal clk1, and the clock signal clk2. In this example, the first CGC 420 gates even pulses of the input clock signal clk_in to generate the clock signal clk1, and the second CGC 430 gates odd pulses of the input clock signal clk_in to generate the clock signal clk2. As Figure 5 shown, this causes the rising edges 510 and 515 of the clock signals clk1 and clk2 to be spaced apart by one period of the input clock signal clk_in, which is equal to 1 / 2F s , because the input clock signal clk_in has a frequency 2F s . The input clock period 1 / 2F s is equivalent to 0.5 / F s , which is exactly 180 degrees apart for a clock frequency F s that is the frequency of each of the clock signals clk1 and clk2. Thus, the rising edges 510 and 515 of the clock signals clk1 and clk2 are 180 degrees apart. Assuming that each of the sub-DACs 120 and 130 performs digital-to-analog conversion on the rising edge of the respective clock signal, the clock signals clk1 and clk2 cause the sub-DACs 120 and 130 to perform digital-to-analog conversion 180 degrees out of phase with each other. This allows the first sub-DAC 120 and the second sub-DAC 130 to operate in a time-interleaved manner, e.g., in the DAC circuit 110 shown. Figure 1

[0051] The rising edges 510 and 515 of the clock signals clk1 and clk2 are 180 degrees apart even when the duty cycle of the input clock signal clk_in is not 50%. This is because, unlike the example shown in Figure 3 , the clock circuit 400 does not generate the rising edge of the clock signal clk2 by inverting the duty cycle-sensitive falling edge of the clock signal clk1. For example, Figure 5 an example is shown in which the input clock signal clk_in has a duty cycle less than 50%. As Figure 5 shown, the rising edges 510 and 515 of the clock signals clk1 and clk2 are 180 degrees apart even when the input clock signal clk_in has a duty cycle less than 50%. This is equally true for the case in which the input clock signal clk_in has a duty cycle greater than 50%. Thus, the clock circuit 400 is able to generate clock signals clk1 and clk2 that are 180 degrees apart without requiring duty cycle correction by the DCC block 220 in Figure 2

[0052] Note that, in the example shown in Figure 5 ​​In the example, the falling edges of clock signals clk1 and clk2, 520 and 525, are also spaced 180 degrees apart. Therefore, for each of sub-DACs 120 and 130 to perform digital-to-analog conversion on the falling edges of clock signals clk1 and clk2, the corresponding clock signals cause sub-DACs 120 and 130 to perform digital-to-analog conversions 180 degrees out of phase with each other. Thus, clock circuit 400 can be used for cases where each of sub-DACs 120 and 130 performs digital-to-analog conversion on the rising edge of the corresponding clock signal, or where each of sub-DACs 120 and 130 performs digital-to-analog conversion on the falling edge of the corresponding clock signal.

[0053] Figure 6A An exemplary specific implementation of CGC 610 according to certain aspects is shown. The exemplary CGC 610 can be used to implement... Figure 4 Each of the first CGC 420 and the second CGC 430 (i.e., each of the first CGC 420 and the second CGC 430 may be a separate instance of CGC 610).

[0054] In this example, CGC 610 has a first input terminal 612, a second input terminal 614, and an output terminal 616. For the example of CGC 610 implementing a first CGC 420, the first input terminal 612 corresponds to the first input terminal 422, the second input terminal 614 corresponds to the second input terminal 424, and the output terminal 616 corresponds to the output terminal 426. In this example, the first input terminal 612 receives the input clock signal clk_in, and the second input terminal 614 receives a first divided clock signal from the clock divider circuit 410. For the example of CGC 610 implementing a second CGC 430, the first input terminal 612 corresponds to the first input terminal 432, the second input terminal 614 corresponds to the second input terminal 434, and the output terminal 616 corresponds to the output terminal 436. In this example, the first input terminal 612 receives the input clock signal clk_in, and the second input terminal 614 receives a second divided clock signal from the clock divider circuit 410. As discussed above, in some respects, the second divided clock signal is 180 degrees out of phase with the first divided clock signal.

[0055] In this example, CGC 610 includes an NOR gate 620, a delay circuit 630, and an AND gate 640. NOR gate 620 has a first input 622 coupled to the first input 612 of CGC 610, a second input 624 coupled to the second input 614 of CGC 610, and an output 626. AND gate 640 has a first input 642, a second input 644 coupled to the first input 612 of CGC 610, and an output 646 coupled to the output 616 of CGC 610. Delay circuit 630 is coupled between the output 626 of NOR gate 620 and the first input 642 of AND gate 640. It should be appreciated that in some implementations, each of NOR gate 620 and AND gate 640 can be implemented with a combination of logic gates. For example, in some implementations, AND gate 640 can be implemented with a NAND gate and an inverter.

[0056] For the example in which CGC 610 implements first CGC 420, NOR gate 620 receives the input clock signal clk_in and the first divided clock signal from clock division circuit 410. NOR gate 620 then generates an internal clock gating signal (labeled "gate_en") by performing an NOR operation on the first divided clock signal and the input clock signal clk_in. Delay circuit 630 delays the clock gating signal by a time delay, which can be programmable. As discussed further below, the time delay controls the pulse width of clock signal clk1. In Figure 6A In the example in, the delayed clock gating signal is labeled "gate_en_delayed".

[0057] AND gate 640 receives the delayed clock gating signal and the input clock signal clk_in. AND gate 640 then gates the input clock signal clk_in using the delayed clock gating signal to generate clock signal clk1. In this example, AND gate 640 gates the input clock signal clk_in by performing an AND operation on the input clock signal clk_in and the delayed clock gating signal.

[0058] Figure 7A is a timing diagram showing exemplary signals 710 in first CGC 420 for the example in which first CGC 420 is implemented with CGC 610, in accordance with certain aspects. In Figure 7A In the example in, signals 710 include the input clock signal clk_in, the first divided clock signal (labeled "clk_divl"), the clock gating signal (labeled "gate_enl"), the delayed clock gating signal (labeled "gate_en_delayedl"), and clock signal clk1. The pulse width of clock signal clk1 can be adjusted by adjusting the delay of delay circuit 630. The longer the delay, the wider the pulse width.

[0059] In the example of implementing the second CGC 430 using CGC 610, NOR gate 620 receives the input clock signal clk_in and a second divided clock signal from clock divider circuit 410. NOR gate 620 then generates an internal clock gate signal (labeled "gate_en") by performing a NOR operation on the second divided clock signal and the input clock signal clk_in. Delay circuit 630 delays the clock gate signal by a programmable time delay.

[0060] AND gate 640 receives a delayed clock gating signal (labeled "gate_en_delayed") and an input clock signal clk_in. AND gate 640 then uses the delayed clock gating signal to gate the input clock signal clk_in to generate a clock signal clk2. In this example, AND gate 640 gates the input clock signal clk_in by performing a bitwise AND operation on the input clock signal clk_in and the delayed clock gating signal.

[0061] Figure 7A An exemplary signal 720 in a second CGC430, implemented using CGC 610, is also shown according to certain aspects. Figure 7A In the example, signal 720 includes the input clock signal clk_in, the second divided clock signal (labeled "clk_div2"), the clock gating signal (labeled "gate_en2"), the delayed clock gating signal (labeled "gate_en_delayed2"), and the clock signal clk2. Figure 7A In the example, the second divided clock signal is 180 degrees out of phase with the first divided clock signal (i.e., the rising edge of the second divided clock signal is offset by 180 degrees from the rising edge of the first divided clock signal). In this example, the second divided clock signal can be generated by inverting the first divided clock signal or by another technique.

[0062] like Figure 7A As shown, clock signals clk1 and clk2 are spaced one cycle apart from the input clock signal clk_in (labeled "T"). in One clock cycle of the input clock signal clk_in is equivalent to 180 degrees for clock signals clk1 and clk2, because in this example, the input clock signal clk_in has a frequency that is twice the frequency of each of the clock signals clk1 and clk2. Therefore, in this example, clock signals clk1 and clk2 are 180 degrees out of phase.

[0063] It should be understood that the first CGC 420 and the second CGC 430 are not limited to Figure 6AThe exemplary specific implementation shown can be used to implement each of the first CGC 420 and the second CGC 430 using various logic gates and various arrangements of logic gates. In this respect, Figure 6B Another exemplary embodiment of CGC 610 is shown, in which the NOR gate 620 and delay circuit 630 are arranged relative to each other. Figure 6A There are some changes. In this example, the delay circuit 630 is coupled between the first input 612 of CGC 610 and the first input 622 of NOR gate 620, the second input 624 of NOR gate 620 is coupled to the first input 612 of CGC 610, and the output 626 of NOR gate 620 is coupled to the first input 642 of AND gate 640. The second input 644 of AND gate 640 is coupled to the second input 614 of CGC 610.

[0064] In this example, delay circuit 630 delays the input clock signal clk_in to generate a delayed input clock signal (labeled "clk_in_delayed"). NOR gate 620 performs a NOR operation on the input clock signal and the delayed input clock signal to generate clock pulses, the width of which is controlled by the time delay of delay circuit 630. For the example of CGC 610 implementing the first CGC 420, AND gate 640 gates the clock pulses with a first divided clock signal to generate clock signal clk1. For the example of CGC 610 implementing the second CGC 430, AND gate 640 gates the clock pulses with a second divided clock signal to generate clock signal clk2. It should be understood that the operations of NOR gate 620 and AND gate 640 can be performed by other combinations of logic gates.

[0065] Figure 7B It shows that it is aimed at Figure 6B The CGC 610 in the example implements the exemplary signal 750 of the first CGC 420. Figure 7B It also shows the target Figure 6B The CGC 610 in the example implements an exemplary signal 760 of the second CGC 430. (Example...) Figure 7B As shown, the resulting clock signals clk1 and clk2 are offset from each other by one period (labeled "T") of the input clock signal clk_in. in The period corresponds to a 180-degree phase for clock signals clk1 and clk2. The pulse width of each of the clock signals clk1 and clk2 is controlled by the time delay of the corresponding delay circuit.

[0066] In general, it should be appreciated that each of the first CGC 420 and the second CGC 430 can include a logic gate for gating the input clock signal clk in using the first divided clock signal or the second divided clock signal, and can include a delay circuit for adjusting a pulse width of a respective one of the clock signals clk 1 and clk 2.

[0067] Figure 8 An example of a wireless device 805 including the clock circuit 400 and the DAC circuit 110 is shown in accordance with certain aspects. In this example, the wireless device 805 also includes a phase-locked loop (PLL) 820, a baseband processor 810, a transmitter 830, and an antenna 840.

[0068] The PLL 820 has an output 822 coupled to the input 402 of the clock circuit 400. In this example, the PLL 820 is configured to generate the input clock signal clk in and output the input clock signal clk in at the output 822. The clock circuit 400 receives the generated input clock signal clk in via the input 402.

[0069] The clock circuit 400 outputs the clock signal clk 1 to the clock input 124 of the first sub-DAC 120 and outputs the clock signal clk 2 to the clock input 134 of the second sub-DAC 130. As discussed above, the clock signals clk 2 and clk 2 can be 180 degrees out of phase, operating the sub-DACs 120 and 130 in a time-interleaved fashion. This allows the DAC circuit 110 to perform a digital-to-analog conversion at a frequency (i.e., rate) of 2F s performing a digital-to-analog conversion, where F s is a frequency of each of the clock signals clk 1 and clk 2.

[0070] The input 112 of the DAC circuit 110 is coupled to an output 812 of a baseband processor 810 (also referred to as a modem). The baseband processor 810 is configured to receive data (e.g., from another processor) to be transmitted, generate a digital baseband signal including the data, and output the digital baseband signal at the output 812. The DAC circuit 110 receives the digital baseband signal via the input 112 and converts the digital baseband signal to an analog baseband signal at the output 114.

[0071] The transmitter 830 has an input 832 coupled to the output 114 of the DAC circuit 110, and an output 834 coupled to the antenna 840. The transmitter 830 is configured to receive the analog baseband signal, process the analog baseband signal to a radio frequency (RF) signal, and output the RF signal at the output 834 to the antenna 840 for transmission.

[0072] In one example, the processing performed by transmitter 830 may include up-conversion, filtering, power amplification, and / or other processing. In this regard, Figure 9 An exemplary embodiment of transmitter 830 is shown, in which transmitter 830 may include a filter 910, a mixer 920, and a power amplifier 930 chain-coupled. Filter 910 may include a baseband filter and / or a low-pass filter. Mixer 920 may be configured to mix a baseband signal with a local oscillator signal (labeled "LO") to up-convert the baseband signal to an RF signal. Power amplifier 930 is configured to amplify the RF signal for transmission via antenna 840. It should be understood that transmitter 830 may include components not in... Figure 9 One or more additional components are shown in the diagram. Although in Figure 8 An antenna 840 is shown, but it should be understood that the wireless device 805 may include multiple antennas (e.g., arranged in an array) coupled to the transmitter 830.

[0073] It should be understood that the clock circuit 400 is not limited to the two sub-DACs 120 and 130, and the clock circuit 400 can be used to drive the clock inputs of more than two sub-DACs. In this respect, Figure 10 An example of a DAC circuit 110, according to certain aspects, including a third sub-DAC 1020, a fourth sub-DAC 1030, and a second combiner 1040, is shown. In this example, the DAC circuit 110 has a second input 1012 configured to receive digital signals and a second output 1014. The third sub-DAC 1020 has a data input 1022 coupled to the second input 1012, a clock input 1024 coupled to a first output 404 of the clock circuit 400, and an output 1026. The fourth sub-DAC 1030 has a data input 1032 coupled to the second input 1012, a clock input 1034 coupled to a second output 406 of the clock circuit 400, and an output 1036. The combiner 1040 has a first input 1042 coupled to the output 1026 of the third sub-DAC 1020, a second input 1044 coupled to the output 1036 of the fourth sub-DAC 1030, and an output 1046 coupled to the second output 1014.

[0074] The third sub-DAC 1020 receives a digital signal at data input 1022 and a clock signal clk1 from clock circuit 400 at clock input 1024. The third sub-DAC 1020 is configured to convert the digital signal at data input 1022 into a first analog signal at output 1026. The third sub-DAC 1020 is also configured to perform digital-to-analog conversion based on the clock signal clk1.

[0075] The fourth sub-DAC 1030 receives a digital signal at a data input 1032 and a clock signal clk2 from the clock circuit 400 at a clock input 1034. The fourth sub-DAC 1030 is configured to convert the digital signal at the data input 1032 to a second analog signal at an output 1036. The fourth sub-DAC 1030 is further configured to perform the digital-to-analog conversion of the digital signal based on the clock signal clk2.

[0076] The combiner 1040 is configured to receive the first analog signal from the third sub-DAC 1020 at a first input 1042, the second analog signal from the fourth sub-DAC 1030 at a second input 1044, and combine the first analog signal and the second analog signal into a combined analog signal at an output 1046. The combined analog signal is output at the output 1014 of the DAC circuit 110. In some implementations, the combiner 1040 can be implemented by shorting the output 1026 of the third sub-DAC 1020 to the output 1036 of the fourth sub-DAC 1030.

[0077] As discussed above, the clock signal clk2 is phase shifted 180 degrees (i.e., half a clock period) relative to the clock signal clk1. This causes the third sub-DAC 1020 and the fourth sub-DAC 1030 to alternately perform digital-to-analog conversion to provide an effective digital-to-analog conversion rate of 2F s where F s is the frequency of each of the clock signals clk1 and clk2.

[0078] In certain aspects, Figure 10 The example DAC circuit 110 shown can be used in a wireless device that employs in-phase (I) and quadrature (Q) modulation. In this example, the first sub-DAC 120 and the second sub-DAC 130 can be used to generate an analog in-phase (I) signal, and the third sub-DAC 1020 and the fourth sub-DAC 1030 can be used to generate an analog quadrature (Q) signal. In this regard, Figure 11 An example implementation of a transmitter 830 configured to receive the analog I signal and the analog Q signal and convert the analog I signal and the analog Q signal to an RF signal for transmission is shown.

[0079] In Figure 11In the example, transmitter 830 includes an in-phase (I) path comprising a chain-coupled first filter 1110 and a first mixer 1120. The I path is coupled to output 114 of DAC circuit 110 via a first input terminal 832-1. The first filter 1110 may include a baseband filter, a low-pass filter, etc. The first mixer 1120 is configured to mix an analog I signal with a first local oscillator signal (labeled "LO_I") to upconvert the analog I signal into a first RF signal.

[0080] The transmitter 830 also includes a quadrature (Q) path comprising a chain-coupled second filter 1130 and a second mixer 1140. The Q path is coupled to a second output 1014 of the DAC circuit 110 via a second input 832-2. The second filter 1130 may include a baseband filter, a low-pass filter, etc. The second mixer 1140 is configured to mix the analog Q signal with a second local oscillator signal (labeled “LO_Q”) to upconvert the analog Q signal to a second RF signal. The second local oscillator signal may be 90 degrees out of phase with the first local oscillator signal.

[0081] Transmitter 830 also includes a combiner 1150 coupled to the first mixer 1120 and the second mixer 1140, and a power amplifier 1160 coupled to the combiner 1150. The combiner 1150 is configured to combine the first RF signal and the second RF signal into a combined RF signal, and output the combined RF signal to the power amplifier 1160. The power amplifier 1160 amplifies the combined RF signal and outputs the amplified RF signal at output 834. It should be understood that transmitter 830 may include components not included in the first mixer 1120 and the second mixer 1140. Figure 11 One or more additional components are shown in the diagram.

[0082] In some respects, the clock circuit 400 may include one or more additional CGCs for driving the clock inputs 1024 and 1034 of the third sub-DAC 1020 and the fourth sub-DAC 1030, instead of using CGCs 420 and 430. In this respect, Figure 12 An example of a third CGC 1240 and a fourth CGC 1250 is shown, which are used to drive the clock inputs 1024 and 1034 of the third sub-DAC 1020 and the fourth sub-DAC 1030.

[0083] The third CGC 1240 has a first input 1242, a second input 1244, and an output 1246. The first input 1242 is coupled to the input 402 of the clock circuit 400 to receive the input clock signal clk in, and the second input 1244 is coupled to the first output 414 of the clock division circuit 410 to receive the first divided clock signal. The output 1246 is coupled to the third output 1204 of the clock circuit 400, which is coupled to the clock input 1024 of the third sub-DAC 1020. In one example, the third CGC 1240 can be implemented with the exemplary CGC 610 shown in Figure 6A or Figure 6B In operation, the third CGC 1240 is configured to gate the input clock signal clk in using the first divided clock signal, thereby generating the clock signal clk3 for the third sub-DAC 1020.

[0084] The fourth CGC 1250 has a first input 1252, a second input 1254, and an output 1256. The first input 1252 is coupled to the input 402 of the clock circuit 400 to receive the input clock signal clk in, and the second input 1254 is coupled to the second output 416 of the clock division circuit 410 to receive the second divided clock signal. The output 1256 is coupled to the fourth output 1206 of the clock circuit 400, which is coupled to the clock input 1034 of the fourth sub-DAC 1030. In one example, the fourth CGC 1250 can be implemented with the exemplary CGC 610 shown in Figure 6A or Figure 6B In operation, the fourth CGC 1250 is configured to gate the input clock signal clk in using the second divided clock signal, thereby generating the clock signal clk4 for the fourth sub-DAC 1030.

[0085] In certain aspects, the clock signals clk3 and clk4 are 180 degrees out of phase, which causes the third sub-DAC 1020 and the fourth sub-DAC 1030 to alternately perform digital-to-analog conversion to provide an effective digital-to-analog conversion rate of 2F s where F s is the frequency of each of the clock signals clk3 and clk4.

[0086] In certain aspects, the clock circuit 400 and the DAC circuit 110 can be programmable to handle two or more modes. In this regard, Figure 13A An example is shown in which the clock circuit 400 and the DAC circuit 110 can be switched between a first mode and a second mode. In the first mode, the first sub-DAC 120 and the second sub-DAC 130 operate in a time-interleaved manner, as described above with reference to Figure 4discussed. In the second mode, the first sub-DAC 120 and the second sub-DAC 130 perform digital-to-analog conversion on separate channels. In other words, the first sub-DAC 120 and the second sub-DAC 130 are not time-interleaved in the second mode, as further discussed below.

[0087] In this example, the clock circuit 400 includes a multiplexer 1310 having a first input 1312, a second input 1314, a select input 1318, and an output 1316. The first input 1312 is coupled to the first output 414 of the clock division circuit 410, the second input 1314 is coupled to the second output 416 of the clock division circuit 410, and the output 1316 is coupled to the second input 434 of the second CGC 430. In operation, the multiplexer 1310 is configured to receive a selection signal from the controller 1365 via the select input 1318, select the first input 1312 or the second input 1314 based on the selection signal, and couple the selected one of the first input 1312 and the second input 1314 to the output 1316 of the multiplexer 1310. In this example, the first input 1312 receives the first divided clock signal and the second input 1314 receives the second divided clock signal. Thus, the multiplexer 1310 inputs the first divided clock signal to the second input 434 of the second CGC 430 when the first input 1312 is selected and inputs the second divided clock signal to the second input 434 of the second CGC 430 when the second input 1314 is selected.

[0088] In this example, the DAC circuit 110 has a first input 112-1 coupled to the data input 122 of the first sub-DAC 120, a second input 112-2 coupled to the data input 132 of the second sub-DAC 130, and a first output 114-1 coupled to the output 146 of the combiner 140. The DAC circuit 110 also includes a second output 114-2 and a third output 114-3 for the second mode, as further discussed below.

[0089] In this example, the DAC circuit 110 includes a first output switch 1330, a second output switch 1340, a third output switch 1350, and a fourth output switch 1360. The first output switch 1330 is coupled between the output 126 of the first sub-DAC 120 and a first input 142 of the combiner 140. The second output switch 1340 is coupled between the output 136 of the second sub-DAC 130 and a second input 144 of the combiner 140. The third output switch 1350 is coupled between the output 126 of the first sub-DAC 120 and the second output 114-2. The fourth output switch 1360 is coupled between the output 136 of the second sub-DAC 130 and the third output 114-3. The output switches 1330, 1340, 1350, and 1360 are controlled by a controller 1365. For ease of illustration, the individual connections between the controller 1365 and the output switches 1330, 1340, 1350, and 1360 are not explicitly shown in FIG. 13. The first output 114-1, the second output 114-2, and the third output 114-3 can also be referred to as a first DAC output, a second DAC output, and a third DAC output, respectively. Figure 13A

[0090] In the first mode, the controller 1365 causes the multiplexer 1310 to select the second input 1314. Thus, in the first mode, the multiplexer 1310 inputs the second divided clock signal to the second input 434 of the second CGC 430. Thus, the clock signal clk2 is 180 degrees out of phase with the clock signal clk1, which causes the sub-DACs 120 and 130 to perform digital-to-analog conversion in a time-interleaved manner. In this mode, the same digital signal can be input to the first input 112-1 and the second input 112-2.

[0091] Additionally, in the first mode, the controller 1365 closes (i.e., turns on) the first output switch 1330 and the second output switch 1340, and opens (i.e., turns off) the third output switch 1350 and the fourth output switch 1360. Thus, the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130 are coupled to the combiner 140, which combines the analog signals from the sub-DACs 120 into a combined analog signal and outputs the combined analog signal at the first output 114-1. In the first mode, the DAC circuit 110 outputs the combined analog signal at an effective digital-to-analog conversion rate 2F s (also referred to as a sampling rate).

[0092] ​In the second mode, the controller 1365 causes the multiplexer 1310 to select the first input 1312. Thus, in the second mode, the multiplexer 1310 inputs the first divided clock signal to the second input 434 of the second CGC 430. Thus, the clock signal clk2 is approximately in phase with the clock signal clk1, as both CGCs 420 and 430 use the first divided clock signal to gate the input clock signal clk_in. In this mode, a first digital signal can be input to the first input 112-1, and a second digital signal can be input to the second input 112-2. The first sub-DAC 120 converts the first digital signal to a first analog signal, and the second sub-DAC 130 converts the second digital signal to a second analog signal.

[0093] Further, in the second mode, the controller 1365 opens (i.e., turns off) the first output switch 1330 and the second output switch 1340, and closes (i.e., turns on) the third output switch 1350 and the fourth output switch 1360. Thus, the output 126 of the first sub-DAC 120 is coupled to the second output 114-2, and the output 136 of the second sub-DAC 130 is coupled to the third output 114-3. Thus, the first analog signal from the first sub-DAC 120 is output at the second output 114-2, and the second analog signal from the second sub-DAC 130 is output at the third output 114-3. Thus, in the second mode, the sub-DACs 120 and 130 perform digital-to-analog conversion on respective digital signals in parallel. In the second mode, the first analog signal and the second analog signal each have a digital-to-analog conversion rate F s .

[0094] It should be appreciated that the clock circuit 400 is not limited to one multiplexer 1310. In this regard, Figure 13BAn example is shown in which the clock circuit 400 includes a second multiplexer 1320 between the clock division circuit 410 and the first CGC 420 to provide additional programmability. In this example, the second multiplexer 1320 has a first input 1322 coupled to the first output 414 of the clock division circuit 410, a second input 1324 coupled to the second output 416 of the clock division circuit 410, a select input 1328 coupled to the controller 1365, and an output 1326 coupled to the second input 424 of the first CGC 420. In this example, the second multiplexer 1320 allows the controller 1365 to selectively input either the first divided clock signal or the second divided clock signal to the second input 424 of the first CGC 420 (e.g., to support one or more additional modes of operation). The second multiplexer 1320 can also be used to provide a propagation delay that matches the multiplexer 1310. In the first and second modes discussed above, the controller 1365 causes the second multiplexer 1320 to select the first input 1322, which is coupled to the first output 414 of the clock division circuit 410. Thus, in the first and second modes, the second multiplexer 1320 couples the second input 424 of the first CGC 420 to the first output 414 of the clock division circuit 410 to receive the first divided clock signal discussed above.

[0095] For an example in which the clock circuit 400 and the DAC circuit 110 are used in a wireless device, the first input 112-1 and the second input 112-2 of the DAC circuit 110 can be coupled to a baseband processor 810 or another processor. Further, each of the output terminals 114-1, 114-2, and 114-3 of the DAC circuit 110 can be coupled to a respective transmitter. In this regard, Figure 13C An example is shown in which the wireless device includes a first transmitter 1370 having an input 1372 coupled to the first output 114-1, a second transmitter 1380 having an input 1382 coupled to the second output 114-2, and a third transmitter 1390 having an input 1392 coupled to the third output 114-3. Each of the transmitters 1370, 1380, and 1390 can be used to transmit a respective signal to a respective antenna of the wireless device. In this regard, Figure 9 or Figure 11A separate instance of the exemplary transmitter 830 is shown implemented. In a first mode, the combined outputs of the first and second sub-DACs 120 and 130 are coupled to a first transmitter 1370. In a second mode, the output 126 of the first sub-DAC 120 is coupled to a second transmitter 1380, and the output 136 of the second sub-DAC 130 is coupled to a third transmitter 1390. The output 1374 of the first transmitter 1370, the output 1384 of the second transmitter 1380, and the output 1394 of the third transmitter 1390 can be coupled to separate antennas or a common antenna.

[0096] In some implementations, in the second mode, the first sub-DAC 120 can be used to generate an in-phase (I) signal, and the second sub-DAC 130 can be used to generate a quadrature (Q) signal. In this example, the second transmitter 1380 can be used to implement the I signal path of the transmitter 830 shown, and the third transmitter 1390 can be used to implement the Q signal path of the transmitter 830 shown. Figure 11 In this example, the second transmitter 1380 can be used to implement the I signal path of the transmitter 830 shown, and the third transmitter 1390 can be used to implement the Q signal path of the transmitter 830 shown. Figure 11 In this example, the second transmitter 1380 can be used to implement the I signal path of the transmitter 830 shown, and the third transmitter 1390 can be used to implement the Q signal path of the transmitter 830 shown. Figure 11 In this example, the second transmitter 1380 can be used to implement the I signal path of the transmitter 830 shown, and the third transmitter 1390 can be used to implement the Q signal path of the transmitter 830 shown. Figure 11 In this example, the second transmitter 1380 can be used to implement the I signal path of the transmitter 830 shown, and the third transmitter 1390 can be used to implement the Q signal path of the transmitter 830 shown. Figure 14 In this example, the second transmitter 1380 can be used to implement the I signal path of the transmitter 830 shown, and the third transmitter 1390 can be used to implement the Q signal path of the transmitter 830 shown.

[0097] In certain aspects, for different modes, the clock circuit 400 can use different sources for the input clock signal clk_in. In this regard, Figure 15 An example of a system including the clock circuit 400, a clock multiplexer 1410, a first phase-locked loop (PLL) 1420, and a second PLL 1430 is shown. In this example, the first PLL 1420 outputs a first root clock signal having a first frequency, and the second PLL 1430 outputs a second root clock signal having a second frequency.

[0098] The clock multiplexer 1410 has a first input 1412 coupled to an output 1422 of the first PLL 1420, a second input 1414 coupled to an output 1432 of the second PLL 1430, a select input 1418 coupled to the controller 1365, and an output 1416 coupled to the input 402 of the clock circuit 400. The clock multiplexer 1410 is configured to selectively input either the first root clock signal from the first PLL 1420 or the second root clock signal from the second PLL 1430 to the input 402 of the clock circuit 400 under control of the controller 1365. In this example, the selected one of the first root clock signal and the second root clock signal becomes the input clock signal clk_in discussed above.

[0099] The controller 1365 can select either the first root clock signal or the second root clock signal based on the operating mode of the clock circuit 400 and the DAC circuit 110. For example, the controller 1365 can select the first root clock signal in the first mode discussed above and select the second root clock signal in the second mode discussed above. This feature allows the sub-DACs 120 and 130 to operate at different digital-to-analog conversion rates for different modes.

[0100] Figure 13A Another example of a clock circuit 400 is shown in accordance with certain aspects. In this example, the clock circuit 400 can be coupled to Figure 13B and Figure 13A the exemplary DAC circuit 110 shown.

[0101] In this example, the clock circuit 400 can include a shorting switch 1530 coupled between the output 426 of the first CGC 420 and the output 436 of the second CGC 430. The shorting switch 1530 is controlled by the controller 1365 (shown in Figure 13B and Figure 15 In this example, the controller 1365 can selectively close (i.e., turn on) the shorting switch 1530 to short the first output 404 and the second output 406 of the clock circuit 400.

[0102] For example, in the second mode discussed above, the clock signals clkl and clk2 can be approximately in phase because both CGCs 420 and 430 receive the first divided clock signal in the second mode. In this mode, the controller 1365 can close the shorting switch 1530 to reduce any timing skew between the clock signals clkl and clk2. The skew can be caused by small variations (e.g., due to process variations) between the CGCs 420 and 430 and / or small variations in the clock paths of the clock signals clkl and clk2. In Figure 13AIn the example of FIG. 13, closing the shorting switch 1530 in the second mode shorts the clock input 124 of the first sub-DAC 120 with the clock input 134 of the second sub-DAC 130. The controller 1365 can open (i.e., turn off) the shorting switch 1530 in the first mode because the clock signals clkl and clk2 are 180 degrees out of phase with each other to operate the sub-DACs 120 and 130 in a time-interleaved manner in the first mode.

[0103] In this example, the clocking circuit 400 can also include a first bypass switch 1520 and a second bypass switch 1526. The first bypass switch 1520 is coupled between the first input 422 of the first CGC 420 and the output 426 of the first CGC 420. The second bypass switch 1525 is coupled between the first input 432 of the second CGC 430 and the output 436 of the second CGC 430. In this example, the controller 1365 can selectively close (i.e., turn on) the bypass switches 1520 and 1525 to bypass the CGCs 420 and 430. When the bypass switches 1520 and 1525 are on, the controller 1365 can disable the CGCs 420 and 430. The controller 1365 opens (i.e., turns off) the bypass switches 1520 and 1525 in the first and second modes discussed above because the CGCs 420 and 430 are used in these modes.

[0104] For example, in the third mode, the controller 1365 can close (i.e., turn on) the bypass switches 1520 and 1525 to bypass the CGCs 420 and 430. In this mode, the first and second sub-DACs 120 and 130 operate in parallel and in phase with each other. Figure 13B and Figure 13A The clock inputs 124 and 134 of each of the sub-DACs 120 and 130 (shown in FIG. 13) are driven by an input clock signal clkin. Because the input clock signal clkin has a frequency of 2F s , each of the sub-DACs 120 and 130 performs digital-to-analog conversion at a rate of 2F s In the third mode, the controller 1365 closes (i.e., turns on) the first and second output switches 1330 and 1340 and opens (i.e., turns off) the third and fourth output switches 1350 and 1360. Thus, the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130 are coupled to the combiner 140, which combines the analog signals from the sub-DACs 120 into a combined analog signal and outputs the combined analog signal at the first output 114-1. In the third mode, the same digital signal can be input to the sub-DACs 120 and 130, where the sub-DACs 120 and 130 perform digital-to-analog conversion on the digital signal in parallel and in phase with each other at a rate of 2F s .

[0105] Compared to time-interleaved mode, the third mode offers higher performance at the cost of increased power consumption because each sub-DAC 120 and 130 operates at twice the frequency in the third mode. The third mode can be used for applications requiring high performance, for example. In the third mode, the controller 1365 can also close the shorting switch 1530, since both sub-DACs 120 and 130 are driven by the input clock signal clk_in in this mode.

[0106] In another example, in the fourth mode, controller 1365 can close (i.e., turn on) bypass switches 1520 and 1525 to be driven by the input clock signal clk_in. Figure 13B and Figure 16 The clock inputs 124 and 134 of each of the sub-DACs 120 and 130 (shown) are used because the input clock signal clk_in has a frequency of 2F. s Therefore, each of the sub-DACs 120 and 130 operates at a rate of 2F in the fourth mode. s Digital-to-analog conversion is performed. In the fourth mode, controller 1365 disconnects the first output switch 1330 and the second output switch 1340, and closes the third output switch 1350 and the fourth output switch 1360. In this mode, a first digital signal can be input to the first input terminal 112-1, and a second digital signal can be input to the second input terminal 112-2. The first sub-DAC 120 converts the first digital signal into a first analog signal, and the second sub-DAC 130 converts the second digital signal into a second analog signal. The first analog signal is output from the second output terminal 114-2, and the second analog signal is output from the third output terminal 114-3. Since the clock input terminals 124 and 134 of each of sub-DACs 120 and 130 are driven by the input clock signal clk_in, each of sub-DACs 120 and 130 operates at a rate of 2F in the fourth mode. s Perform digital-to-analog conversion.

[0107] It should be understood that the clock circuit 400 and the DAC circuit 110 are not limited to the exemplary modes discussed above. For example, in some specific implementations, the clock circuit 400 and the DAC circuit 110 may use only a subset of the modes discussed above and / or may support one or more additional modes not discussed above.

[0108] Figure 17An example implementation of clock division circuit 410 is shown in accordance with certain aspects of the present disclosure. In this example, clock division circuit 410 includes a frequency divider 1610 and a flip-flop 1620 (e.g., a D-type flip-flop). Frequency divider 1610 has an input 1612 coupled to input 412 of clock division circuit 410, and an output 1614. Flip-flop 1620 has a latch input 1622 (labeled “D”) coupled to output 1614 of frequency divider 1610, a clock input 1624 coupled to input 412 of clock division circuit 410, a first output 1626 (labeled “Q”) coupled to first output 414 of clock division circuit 410, and a second output 1628 (labeled “Qb”) coupled to second output 416 of clock division circuit 410. First output 1626 and second output 1628 can be complementary outputs.

[0109] Frequency divider 1610 is configured to receive an input clock signal clk_in, divide a frequency of input clock signal clk_in (e.g., divide the frequency by two), and output the resulting divided frequency clock signal at output 1614. Flip-flop 1620 is configured to receive the divided frequency clock signal from frequency divider 1610 at latch input 1622, and receive input clock signal clk_in at clock input 1624. Flip-flop 1620 is configured to resample the divided frequency clock signal using input clock signal clk_in. Flip-flop 1620 can do so by latching a logic state of the divided frequency clock signal at latch input 1622 on each triggering edge of input clock signal clk_in, and outputting the latched logic state at first output 1626 and outputting an inversion of the latched logic state at second output 1628. In one example, each triggering edge is a rising edge (also referred to as a positive edge). In another example, each triggering edge is a falling edge (also referred to as a negative edge). Resampling the divided frequency clock signal using input clock signal clk_in helps to synchronize the divided frequency clock signal with input clock signal clk_in to avoid glitching.

[0110] In this example, the resampled divided frequency clock signal at first output 1626 is used for the first divided frequency clock signal, and an inversion of the resampled divided frequency clock signal at second output 1628 is used for the second divided frequency clock signal. In this example, the inversion of the resampled divided frequency clock signal corresponds to the resampled divided frequency clock signal that is offset by 180 degrees in phase.

[0111] Figure 18An exemplary method 1700 for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC is shown. The first sub-DAC can correspond to the first sub-DAC 120, and the second sub-DAC can correspond to the second sub-DAC 130.

[0112] At block 1710, an input clock signal is received. The input clock signal can correspond to the input clock signal clk_in.

[0113] At block 1720, the input clock signal is frequency divided to generate a first divided clock signal and a second divided clock signal. For example, the input clock signal can be frequency divided by the clock division circuit 410. In certain aspects, the second divided clock signal is phase shifted approximately 180 degrees relative to the first divided clock signal. In certain aspects, frequency dividing the input clock signal includes dividing a frequency of the input clock signal (e.g., by two or another divisor) to generate the first divided clock signal and the second divided clock signal.

[0114] At block 1730, the input clock signal is gated using the first divided clock signal to generate a first drive clock signal. For example, the input clock signal can be gated using the first divided clock signal by the first clock gating circuit 420. The first drive clock signal can correspond to the clock signal clk1.

[0115] At block 1740, the first drive clock signal is input to a clock input of the first sub-DAC. For example, the clock input of the first sub-DAC can correspond to the clock input 124.

[0116] At block 1750, the input clock signal is gated using the second divided clock signal to generate a second drive clock signal. For example, the input clock signal can be gated using the second divided clock signal by the second clock gating circuit 430. The second drive clock signal can correspond to the clock signal clk2.

[0117] At block 1760, the second drive clock signal is input to a clock input of the second sub-DAC. For example, the clock input of the second sub-DAC can correspond to the clock input 134.

[0118] In certain aspects, the method 1700 can further include combining an output of the first sub-DAC and an output of the second sub-DAC. For example, the output of the first sub-DAC and the output of the second sub-DAC can be combined by the combiner 140.

[0119] It should be appreciated that the method 1700 is not limited to the particular order of blocks 1710-1760. For example, it should be appreciated that blocks 1710 and 1760 can be performed in various orders without departing from the scope of the present disclosure. It should also be appreciated that two or more of blocks 1710 and 1760 can be performed simultaneously.

[0120] Figure 4 An exemplary method 1800 is shown for providing first and second drive clock signals to first and second sub-digital-to-analog converters (sub-DACs). The first sub-DAC can correspond to the first sub-DAC 120, and the second sub-DAC can correspond to the second sub-DAC 130.

[0121] At block 1810, an input clock signal is received. The input clock signal can correspond to the input clock signal clk_in.

[0122] At block 1820, the input clock signal is frequency divided to generate a first and second frequency divided clock signal. For example, the input clock signal can be frequency divided by the clock frequency division circuit 410. In certain aspects, the second frequency divided clock signal is phase shifted approximately 180 degrees relative to the first frequency divided clock signal. In certain aspects, frequency dividing the input clock signal includes dividing a frequency of the input clock signal (e.g., by two or another divisor) to generate the first and second frequency divided clock signals.

[0123] At block 1830, the input clock signal is gated using the first frequency divided clock signal to generate a first drive clock signal. For example, the input clock signal can be gated using the first frequency divided clock signal by the first clock gating circuit 420. The first drive clock signal can correspond to the clock signal clk1.

[0124] At block 1840, the first drive clock signal is input to a clock input of the first sub-DAC. For example, the clock input of the first sub-DAC can correspond to the clock input 124.

[0125] At block 1850, in a first mode, the input clock signal is gated using the second frequency divided clock signal to generate a second drive clock signal. For example, the input clock signal can be gated using the second frequency divided clock signal by the second clock gating circuit 430. The second drive clock signal can correspond to the clock signal clk2.

[0126] At block 1860, in a second mode, the input clock signal is gated using the first frequency divided clock signal to generate a second drive clock signal. For example, the multiplexer 1310 can select the second input 1314 in the first mode, and the first input 1312 in the second mode.

[0127] At block 1870, a second drive clock signal is input to a clock input of the second sub-DAC. For example, the clock input of the second sub-DAC can correspond to clock input 134.

[0128] It should be appreciated that method 1800 is not limited to the particular order of blocks 1810-1870, and that two or more of these blocks can be performed concurrently.

[0129] Method 1800 can also include combining the output of the first sub-DAC and the output of the second sub-DAC in the first mode. For example, output switches 1330 and 1340 can be closed and output switches 1350 and 1360 can be opened to combine the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130.

[0130] Method 1800 can also include shorting the clock input of the first sub-DAC to the clock input of the second sub-DAC in the second mode. For example, shorting switch 1530 can be closed in the second mode to short the clock input 124 of the first sub-DAC 120 to the clock input 134 of the second sub-DAC 130.

[0131] Method 1800 can also include coupling the output of the first sub-DAC and the output of the second sub-DAC to a first transmitter in the first mode.

[0132] Method 1800 can also include coupling the output of the first sub-DAC to a second transmitter and coupling the output of the second sub-DAC to a third transmitter in the second mode. For example, output switches 1350 and 1360 can be closed to couple the output 126 of the first sub-DAC 120 to the second transmitter 1380 and to couple the output 136 of the second sub-DAC 130 to the third transmitter 1390.

[0133] Although not explicitly shown, it should be appreciated that, Figure 8 , Figures 10 to 15 and ​Any or more of the clock paths shown can include one or more clock buffers. For example, it should be appreciated that the clock path between the output 426 of the first CGC 420 and the clock input 124 of the first sub-DAC 120 can include one or more buffers. In this example, the output 426 of the first CGC 420 is coupled to the clock input 124 of the first sub-DAC 120 via one or more clock buffers. Similarly, the clock path between the output 436 of the second CGC 430 and the clock input 134 of the second sub-DAC 130 can include one or more buffers. In this example, the output 436 of the second CGC 430 is coupled to the clock input 134 of the second sub-DAC 130 via one or more clock buffers. Further, the clock path between each of the PLLs 1420 and 1430 and the clock circuit 400 can include one or more clock buffers.

[0134] Specific implementation examples are described in the following numbered clauses:

[0135] 1. A system comprising:

[0136] a clock division circuit having an input, a first output, and a second output, wherein the input of the clock division circuit is configured to receive an input clock signal;

[0137] a first clock gating circuit having a first input, a second input, and an output, wherein the first input of the first clock gating circuit is configured to receive the input clock signal, and the second input of the first clock gating circuit is coupled to the first output of the clock division circuit;

[0138] a second clock gating circuit having a first input, a second input, and an output, wherein the first input of the second clock gating circuit is configured to receive the input clock signal, and the second input of the second clock gating circuit is coupled to the second output of the clock division circuit;

[0139] a first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gating circuit; and

[0140] a second sub-DAC having a clock input coupled to the output of the second clock gating circuit.

[0141] 2. The system of clause 1, wherein the clock division circuit is configured to:

[0142] frequency-divide the input clock signal to generate a first divided clock signal and a second divided clock signal;

[0143] output the first divided clock signal at the first output of the clock dividing circuit; and

[0144] output the second divided clock signal at the second output of the clock dividing circuit.

[0145] 3. The system of clause 2, wherein the second divided clock signal is phase shifted approximately 180 degrees relative to the first divided clock signal.

[0146] 4. The system of clause 3, wherein the clock dividing circuit is configured to invert the first divided clock signal to generate the second divided clock signal.

[0147] 5. The system of any one of clauses 2-4, wherein the clock dividing circuit is configured to frequency-divide a frequency of the input clock signal to generate the first divided clock signal and the second divided clock signal.

[0148] 6. The system of clause 5, wherein the frequency of the input clock signal is divided by two.

[0149] 7. The system of any one of clauses 2-6, wherein the first clock gating circuit is configured to:

[0150] gate the input clock signal using the first divided clock signal to generate a first drive clock signal; and

[0151] output the first drive clock signal at the output of the first clock gating circuit.

[0152] 8. The system of clause 7, wherein the first clock gating circuit includes a delay circuit having a time delay, and the first clock gating circuit is configured to control a pulse width of the first drive clock signal based on the time delay.

[0153] 9. The system of clause 7 or 8, wherein the second clock gating circuit is configured to:

[0154] gate the input clock signal using the second divided clock signal to generate a second drive clock signal; and

[0155] output the second drive clock signal at the output of the second clock gating circuit.

[0156] 10. The system of clause 9, wherein the second divided clock signal is phase shifted approximately 180 degrees relative to the first divided clock signal.

[0157] 11. The system of clause 9 or 10, wherein:

[0158] the first clock gating circuit is configured to gate even pulses of the input clock signal using the first divided clock signal to generate the first drive clock signal; and

[0159] the second clock gating circuit is configured to gate odd pulses of the input clock signal using the second divided clock signal to generate the second drive clock signal.

[0160] 12. The system of clause 9 or 10, wherein:

[0161] the first clock gating circuit is configured to gate odd pulses of the input clock signal using the first divided clock signal to generate the first drive clock signal; and

[0162] the second clock gating circuit is configured to gate even pulses of the input clock signal using the second divided clock signal to generate the second drive clock signal.

[0163] 13. The system of any one of clauses 1-12, further comprising a combiner coupled to an output of the first sub-DAC and an output of the second sub-DAC.

[0164] 14. The system of clause 13, wherein the combiner is coupled to a transmitter.

[0165] 15. A system comprising:

[0166] a clock dividing circuit having an input, a first output, and a second output, wherein the input of the clock dividing circuit is configured to receive an input clock signal;

[0167] a first clock gating circuit having a first input, a second input, and an output, wherein the first input of the first clock gating circuit is configured to receive the input clock signal, and the second input of the first clock gating circuit is coupled to the first output of the clock dividing circuit;

[0168] a multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the first output of the clock division circuit, and the second input of the multiplexer is coupled to the second output of the clock division circuit;

[0169] a second clock gating circuit having a first input, a second input, and an output, wherein the first input of the second clock gating circuit is configured to receive the input clock signal, and the second input of the second clock gating circuit is coupled to the output of the multiplexer;

[0170] a first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gating circuit; and

[0171] a second sub-DAC having a clock input coupled to the output of the second clock gating circuit.

[0172] 16. The system of clause 15, wherein the clock division circuit is configured to:

[0173] divide the input clock signal to generate a first divided clock signal and a second divided clock signal;

[0174] output the first divided clock signal at the first output of the clock division circuit; and

[0175] output the second divided clock signal at the second output of the clock division circuit.

[0176] 17. The system of clause 16, wherein the clock division circuit is configured to divide a frequency of the input clock signal to generate the first divided clock signal and the second divided clock signal.

[0177] 18. The system of clause 17, wherein the frequency of the input clock signal is divided by two.

[0178] 19. The system of any one of clauses 16-18, wherein the second divided clock signal is phase shifted approximately 180 degrees relative to the first divided clock signal.

[0179] 20. The system of clause 19, wherein the clock division circuit is configured to invert the first divided clock signal to generate the second divided clock signal.

[0180] 21. The system of any of clauses 16-20, further comprising a controller configured to:

[0181] cause the multiplexer to select the second input of the multiplexer in a first mode; and

[0182] cause the multiplexer to select the first input of the multiplexer in a second mode.

[0183] 22. The system of clause 21, further comprising:

[0184] a first output switch coupled between an output of the first sub-DAC and a combiner; and

[0185] a second output switch coupled between an output of the second sub-DAC and the combiner;

[0186] wherein the controller is configured to:

[0187] close the first output switch and the second output switch in the first mode, and

[0188] open the first output switch and the second output switch in the second mode.

[0189] 23. The system of clause 22, further comprising a shorting switch coupled between the output of the first clock gating circuit and the output of the second clock gating circuit, wherein the controller is configured to open the shorting switch in the first mode and close the shorting switch in the second mode.

[0190] 24. The system of clause 22 or 23, wherein an output of the combiner is coupled to a first DAC output, and further comprising:

[0191] a third output switch coupled between the output of the first sub-DAC and a second DAC output; and

[0192] a fourth output switch coupled between the output of the second sub-DAC and a third DAC output;

[0193] wherein the controller is configured to:

[0194] open the third output switch and the fourth output switch in the first mode, and

[0195] close the third output switch and the fourth output switch in the second mode.

[0196] 25. The system of any of Clauses 21-24, further comprising:

[0197] a first bypass switch coupled between the first input of the first clock gating circuit and the output of the first clock gating circuit; and

[0198] a second bypass switch coupled between the first input of the second clock gating circuit and the output of the second clock gating circuit;

[0199] wherein the controller is configured to:

[0200] open the first bypass switch and the second bypass switch in the first mode and the second mode; and

[0201] close the first bypass switch and the second bypass switch in a third mode.

[0202] 26. A method for providing first and second drive clock signals to first and second sub-digital-to-analog converters (sub-DACs), the method comprising:

[0203] receiving an input clock signal;

[0204] frequency dividing the input clock signal to generate first and second frequency divided clock signals;

[0205] gating the input clock signal using the first frequency divided clock signal to generate the first drive clock signal;

[0206] inputting the first drive clock signal to a clock input of the first sub-DAC;

[0207] gating the input clock signal using the second frequency divided clock signal to generate the second drive clock signal; and

[0208] inputting the second drive clock signal to a clock input of the second sub-DAC.

[0209] 27. The method of Clause 26, wherein the second frequency divided clock signal is phase shifted approximately 180 degrees relative to the first frequency divided clock signal.

[0210] 28. The method of Clause 26 or 27, wherein:

[0211] gating the input clock signal using the first divided clock signal includes gating even pulses of the input clock signal using the first divided clock signal; and

[0212] gating the input clock signal using the second divided clock signal includes gating odd pulses of the input clock signal using the second divided clock signal.

[0213] 29. The method of clause 26 or 27, wherein:

[0214] gating the input clock signal using the first divided clock signal includes gating odd pulses of the input clock signal using the first divided clock signal; and

[0215] gating the input clock signal using the second divided clock signal includes gating even pulses of the input clock signal using the second divided clock signal.

[0216] 30. The method of any of clauses 26-29, wherein dividing the input clock signal to generate the first divided clock signal and the second divided clock signal includes dividing a frequency of the input clock signal to generate the first divided clock signal and the second divided clock signal.

[0217] 31. The method of clause 30, wherein dividing the frequency of the input clock signal includes dividing the frequency of the input clock signal by two.

[0218] 32. The method of any of clauses 26-31, further comprising combining an output of the first sub-DAC and an output of the second sub-DAC.

[0219] 33. A method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC, the method comprising:

[0220] receiving an input clock signal;

[0221] dividing the input clock signal to generate a first divided clock signal and a second divided clock signal;

[0222] gating the input clock signal using the first divided clock signal to generate the first drive clock signal;

[0223] inputting the first drive clock signal to a clock input of the first sub-DAC;

[0224] in the first mode, gating the input clock signal using the second divided clock signal to generate the second drive clock signal;

[0225] in the second mode, gating the input clock signal using the first divided clock signal to generate the second drive clock signal;

[0226] inputting the second drive clock signal to a clock input of the second sub-DAC.

[0227] 34. The method of clause 33, wherein the second divided clock signal is phase shifted approximately 180 degrees relative to the first divided clock signal.

[0228] 35. The method of clause 33 or 34, wherein:

[0229] gating the input clock signal using the first divided clock signal comprises gating even pulses of the input clock signal using the first divided clock signal; and

[0230] gating the input clock signal using the second divided clock signal comprises gating odd pulses of the input clock signal using the second divided clock signal.

[0231] 36. The method of clause 33 or 34, wherein:

[0232] gating the input clock signal using the first divided clock signal comprises gating odd pulses of the input clock signal using the first divided clock signal; and

[0233] gating the input clock signal using the second divided clock signal comprises gating even pulses of the input clock signal using the second divided clock signal.

[0234] 37. The method of any one of clauses 33 to 36, wherein dividing the input clock signal to generate the first divided clock signal and the second divided clock signal comprises dividing a frequency of the input clock signal to generate the first divided clock signal and the second divided clock signal.

[0235] 38. The method of clause 37, wherein dividing the frequency of the input clock signal comprises dividing the frequency of the input clock signal by two.

[0236] 39. The method of any one of clauses 33 to 38, further comprising combining an output of the first sub-DAC and an output of the second sub-DAC in the first mode.

[0237] 40. The method of clause 39, further comprising shorting the clock input of the first sub-DAC and the clock input of the second sub-DAC in the second mode.

[0238] 41. The method of clause 39 or 40, further comprising coupling the output of the first sub-DAC and the output of the second sub-DAC to a first transmitter in the first mode.

[0239] 42. The method of clause 41, further comprising in the second mode:

[0240] coupling the output of the first sub-DAC to a second transmitter; and

[0241] coupling the output of the second sub-DAC to a third transmitter.

[0242] Within the present disclosure, the word“exemplary” is used to mean“serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term“aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term“approximately” as used herein with respect to a specified value or property is intended to indicate within 10% of the specified value or property.

[0243] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Modifications to various implementations of the disclosure will be apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: a clock division circuit having an input, a first output, and a second output, wherein the input of the clock division circuit is configured to receive an input clock signal, wherein the clock division circuit is configured to: divide the input clock signal to generate a first divided clock signal and a second divided clock signal, output the first divided clock signal at the first output of the clock division circuit, and output the second divided clock signal at the second output of the clock division circuit, wherein the second divided clock signal is phase shifted 180 degrees relative to the first divided clock signal; a first clock gating circuit having a first input, a second input, and an output, wherein the first input of the first clock gating circuit is configured to receive the input clock signal, and the second input of the first clock gating circuit is coupled to the first output of the clock division circuit; a multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the first output of the clock division circuit, and the second input of the multiplexer is coupled to the second output of the clock division circuit; a second clock gating circuit having a first input, a second input, and an output, wherein the first input of the second clock gating circuit is configured to receive the input clock signal, and the second input of the second clock gating circuit is coupled to the output of the multiplexer; a digital-to-analog converter (DAC) circuit including: a first DAC output, a second DAC output, and a third DAC output; a first sub-DAC having a clock input coupled to the output of the first clock gating circuit; a second sub-DAC having a clock input coupled to the output of the second clock gating circuit; a combiner having an output coupled to the first DAC output; a first output switch coupled between an output of the first sub-DAC and the combiner; a second output switch coupled between an output of the second sub-DAC and the combiner; a third output switch coupled between the output of the first sub-DAC and the second DAC output; and a fourth output switch coupled between the output of the second sub-DAC and the third DAC output; and a controller configured to: in a first mode: cause the multiplexer to select the second input of the multiplexer, close the first output switch and the second output switch, and open the third output switch and the fourth output switch, to output at the first DAC output; and in a second mode: cause the multiplexer to select the first input of the multiplexer, close the third output switch and the fourth output switch, and open the first output switch and the second output switch, to output at the second DAC output. causing the multiplexer to select the first input of the multiplexer, opening the first and second output switches and closing the third and fourth output switches for output at the second and third DAC output terminals.

2. The system of claim 1, wherein the clock dividing circuit is configured to divide a frequency of the input clock signal to generate the first divided clock signal and the second divided clock signal.

3. The system of claim 2, wherein the frequency of the input clock signal is divided by two.

4. The system of claim 1, wherein the first clock gating circuit is configured to: gate the input clock signal using the first divided clock signal to generate a first drive clock signal; and output the first drive clock signal at the output of the first clock gating circuit.

5. The system of claim 4, wherein the first clock gating circuit includes a delay circuit having a time delay, and the first clock gating circuit is configured to control a pulse width of the first drive clock signal based on the time delay.

6. The system of claim 1, wherein the second clock gating circuit is configured to: gate the input clock signal using the second divided clock signal to generate a second drive clock signal; and output the second drive clock signal at the output of the second clock gating circuit.

7. The system of claim 6, wherein the clock dividing circuit is configured to invert the first divided clock signal to generate the second divided clock signal.

8. The system of claim 1, wherein the combiner is coupled to a transmitter.

9. The system of claim 1, wherein: the first clock gating circuit is configured to gate one of even and odd pulses of the input clock signal using the first divided clock signal to generate a first drive clock signal; and the second clock gating circuit is configured to gate the other of the even and odd pulses of the input clock signal using the second divided clock signal to generate a second drive clock signal.

10. The system of claim 1, further comprising a shorting switch coupled between the output of the first clock gating circuit and the output of the second clock gating circuit, wherein the controller is configured to open the shorting switch in the first mode and to close the shorting switch in the second mode.

11. The system of claim 9, further comprising: a first bypass switch coupled between the first input of the first clock gating circuit and the output of the first clock gating circuit; and a second bypass switch coupled between the first input of the second clock gating circuit and the output of the second clock gating circuit; wherein the controller is configured to: ​ opening the first and second bypass switches in the first and second modes; and closing the first and second bypass switches in a third mode.

12. A method for providing first and second drive clock signals to first and second sub- digital-to-analog converters (sub-DACs) using the system of claim 1, the method comprising: receiving an input clock signal; frequency dividing the input clock signal to generate a first and a second frequency divided clock signal, wherein the second frequency divided clock signal is phase shifted 180 degrees relative to the first frequency divided clock signal; gating the input clock signal using the first frequency divided clock signal to generate the first drive clock signal; inputting the first drive clock signal to a clock input of the first sub-DAC to generate a first analog signal; gating the input clock signal using the second frequency divided clock signal to generate the second drive clock signal to generate a second analog signal; inputting the second drive clock signal to a clock input of the second sub-DAC; and based on a signal received from a controller: in a first mode: causing a multiplexer to select the second frequency divided clock signal, combining the first and second analog signals and outputting the combined first and second analog signals; or in a second mode: causing the multiplexer to select the first frequency divided clock signal, and outputting the first and second analog signals, respectively.

13. The method of claim 12, wherein: gating the input clock signal using the first frequency divided clock signal comprises gating even pulses of the input clock signal using the first frequency divided clock signal; and gating the input clock signal using the second frequency divided clock signal comprises gating odd pulses of the input clock signal using the second frequency divided clock signal.

14. The method of claim 12, wherein: gating the input clock signal using the first frequency divided clock signal comprises gating odd pulses of the input clock signal using the first frequency divided clock signal; and gating the input clock signal using the second frequency divided clock signal comprises gating even pulses of the input clock signal using the second frequency divided clock signal.

15. The method of claim 12, wherein frequency dividing the input clock signal to generate the first and second frequency divided clock signals comprises frequency dividing a frequency of the input clock signal to generate the first and second frequency divided clock signals.

16. The method of claim 15, wherein frequency dividing the frequency of the input clock signal comprises dividing the frequency of the input clock signal by two. ​ ​ ​

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