A Subthreshold CMOS Reference Circuit with Temperature Compensation

Abstract

The present invention discloses a subthreshold CMOS reference circuit with temperature compensation, belonging to the technical field of analog integrated circuits. The subthreshold CMOS reference circuit with temperature compensation comprises a startup circuit, a reference core circuit, a low temperature zone compensation circuit and a high temperature zone compensation circuit, wherein the first output terminal and the second output terminal of the startup circuit are respectively connected to the first input terminal and the second input terminal of the reference core circuit. The low temperature zone compensation circuit and the high temperature zone compensation circuit perform segmented compensation in the low temperature zone and the high temperature zone, thereby obtaining a very low temperature drift coefficient, and a negative feedback method is used in the reference core circuit to improve the power supply voltage rejection ratio of the overall circuit.

Description

Technical Field

[0001] The invention relates to the technical field of analog integrated circuits, and in particular to a sub-threshold CMOS reference circuit with temperature compensation. Background Art

[0002] In recent years, the rapid development of wireless IoT devices, especially wireless sensor network nodes, wireless medical electronic devices and wearable devices, has driven the development of SoC (system on chip) chips towards low power consumption and low power supply voltage. The reference source plays an important role in SoC. It provides voltage and current references for other circuit modules, and its design accuracy determines the accuracy of the entire system. However, the output of the reference source will change due to temperature. The temperature drift coefficient (TC) is generally used to measure the accuracy and stability of the reference source. It is the most critical parameter of the reference source. The power supply voltage of the traditional bandgap reference (BGR) circuit is limited by the base-emitter voltage (V BE ), which is difficult to reduce further, and the power consumption of traditional bandgap reference is relatively large, generally above the microwatt level, so it is not applicable in many IoT application scenarios.

[0003] Subthreshold CMOS reference sources are widely used due to their low power consumption, support for low power supply voltage operation, and high compatibility with standard CMOS processes. The generation principle of subthreshold CMOS reference sources is similar to that of bandgap reference sources: it uses two threshold voltages (V TH ) Different NMOS transistors are used to obtain the reference voltage. The expression of the reference voltage includes the negative temperature coefficient term formed by the difference in the threshold voltage of the two transistors and the positive temperature coefficient term formed by adjusting the tube size. Adding the two terms together can obtain a reference voltage with a zero temperature coefficient. But V TH The value of the higher-order term is much larger than the V BE Therefore, the subthreshold CMOS reference source often has a higher temperature drift coefficient or a narrow applicable temperature range.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a sub-threshold CMOS reference circuit with temperature compensation to solve the problem of high temperature drift coefficient or narrow applicable temperature range.

[0006] In order to solve the above technical problems, the present invention provides a subthreshold CMOS reference circuit with temperature compensation, comprising:

[0007] A reference core circuit is used to compensate the temperature coefficient of the output reference voltage through a MOS tube, wherein the first output end of the reference core circuit is used as a reference voltage output end, and the second output end is used to output a reference current. The reference core circuit also includes a zero temperature coefficient resistor and an operational amplifier, wherein the non-inverting input end of the operational amplifier is connected to the first output end of the reference core circuit, and the inverting input end of the operational amplifier is connected to a bias current and is connected to the positive electrode of the zero temperature coefficient resistor to form a virtual short through a negative feedback loop to generate a zero temperature coefficient bias current on the zero temperature coefficient resistor, and the bias current is copied and output through a current mirror;

[0008] A startup circuit, used to make the reference core circuit leave the zero state, wherein the first output terminal and the second output terminal of the startup circuit are respectively connected to the first input terminal and the second input terminal of the reference core circuit;

[0009] A first compensation circuit, used for obtaining a copied bias current and accessing the first output terminal of the reference core circuit through a MOS tube to compensate for the reference voltage;

[0010] The second compensation circuit is used to obtain the copied bias current and compensate the reference voltage by connecting to the first output terminal of the reference core circuit through the MOS tube.

[0011] Preferably, the reference core circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first NMOS transistor MN1, a second NMOS transistor MN2, a zero temperature coefficient resistor, a first capacitor C1, a second capacitor C2 and an operational amplifier A;

[0012] The source of the first NMOS transistor MN1, the negative plate of the first capacitor C1, and the negative electrode of the zero temperature coefficient resistor are connected to GND; the gate of the first NMOS transistor MN1 is connected to the gate and drain of the second NMOS transistor MN2, and the drain of the second PMOS transistor MP2; the source of the first PMOS transistor MP1, the source of the third PMOS transistor MP3, the source of the fifth PMOS transistor MP5, and the positive plate of the second capacitor C2 are all connected to the power supply voltage VDD; the drain of the fourth PMOS transistor MP4 is connected to the bias current input terminal IB of the operational amplifier A; the drain of the sixth PMOS transistor MP6 is connected to the positive electrode of the zero temperature coefficient resistor and the inverting input terminal of the operational amplifier A; the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2; the drain of the third PMOS transistor MP3 is connected to the source of the fourth PMOS transistor MP4; the drain of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6.

[0013] Preferably, the first compensation circuit includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a seventh PMOS transistor MP7 and an eighth PMOS transistor MP8;

[0014] The source of the seventh PMOS tube MP7 is connected to the power supply voltage VDD, the gate and drain of the fourth NMOS tube MN4 are connected to the drain of the eighth PMOS tube MP8 and connected to the gate of the fifth NMOS tube MN5, the source of the fourth NMOS tube MN4 is connected to the drain and gate of the third NMOS tube MN3, the source of the third NMOS tube MN3 and the source of the fifth NMOS tube MN5 are both connected to GND, and the drain of the seventh PMOS tube MP7 is connected to the source of the eighth PMOS tube MP8.

[0015] Preferably, the second compensation circuit includes a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11 and a twelfth PMOS transistor MP12;

[0016] The source of the ninth PMOS transistor MP9 is connected to the power supply voltage VDD, the drain of the ninth PMOS transistor MP9 is connected to the source of the tenth PMOS transistor MP10, the drain of the tenth PMOS transistor MP10 is connected to the gate and drain of the sixth NMOS transistor MN6, and is connected to the gate of the seventh NMOS transistor MN7, and the source of the sixth NMOS transistor MN6 and the source of the seventh NMOS transistor MN7 are both connected to GND;

[0017] The source of the eleventh PMOS transistor MP11 is connected to the power supply voltage VDD, the drain of the eleventh PMOS transistor MP11 is connected to the source of the twelfth PMOS transistor MP12, and the drain of the twelfth PMOS transistor MP12 is a reference current output terminal.

[0018] Preferably, the output end of the operational amplifier A is connected to the gate of the first PMOS tube MP1, the gate of the second PMOS tube MP2, the gate of the third PMOS tube MP3, the gate of the fourth PMOS tube MP4, the gate of the fifth PMOS tube MP5, the gate of the sixth PMOS tube MP6, the gate of the seventh PMOS tube MP7, the gate of the eighth PMOS tube MP8, the gate of the ninth PMOS tube MP9, the gate of the tenth PMOS tube MP10, the gate of the eleventh PMOS tube MP11, the gate of the twelfth PMOS tube MP12, and the negative plate of the second capacitor C2, and serves as the first input end of the reference core circuit; the drain of the first NMOS tube MN1 and the source of the second NMOS tube MN2, the positive plate of the first capacitor C1, the drain of the fifth NMOS tube MN5, the drain of the seventh NMOS tube MN7, the non-inverting input end of the operational amplifier A, and the reference voltage output end, and serves as the second input end of the reference core circuit.

[0019] Preferably, the startup circuit includes a first PMOS transistor MS1, a second NMOS transistor MS2 and a third NMOS transistor MS3, the gate of the first PMOS transistor MS1 is connected to the drain of the second NMOS transistor MS2 and the gate of the third NMOS transistor MS3, the source and drain of the first PMOS transistor MS1 are both connected to the power supply voltage VDD, the drain of the third NMOS transistor MS3 serves as the first output end of the startup circuit, the source of the second NMOS transistor MS2 and the source of the third NMOS transistor MS3 are both connected to GND, and the gate of the second NMOS transistor MS2 serves as the second output end of the startup circuit.

[0020] Preferably, the operational amplifier includes an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, a twelfth NMOS tube MN12, a thirteenth NMOS tube MN13, a fourteenth NMOS tube MN14, a fifteenth NMOS tube MN15, a thirteenth PMOS tube MP13, a fourteenth PMOS tube MP14, a fifteenth PMOS tube MP15, a sixteenth PMOS tube MP16, a seventeenth PMOS tube MP17, an eighteenth PMOS tube MP18, a nineteenth PMOS tube MP19, a twentieth PMOS tube MP20, a twenty-first PMOS tube MP21 and a twenty-second PMOS tube MP22;

[0021] The gate and drain of the eighth NMOS tube MN8 are interconnected, and are connected together with the gate of the ninth NMOS tube MN9, the gate of the twelfth NMOS tube MN12, and the gate of the fourteenth NMOS tube MN14 to serve as the bias current input terminal IB of the operational amplifier A. The source of the eighth NMOS tube MN8, the source of the ninth NMOS tube MN9, the source of the tenth NMOS tube MN10, the source of the twelfth NMOS tube MN12, and the source of the fourteenth NMOS tube MN14 are all connected to GND;

[0022] The drain of the ninth NMOS tube MN9 is connected to the gate of the thirteenth PMOS tube MP13, the gate of the fourteenth PMOS tube MP14, the gate of the fifteenth PMOS tube MP15, the gate of the sixteenth PMOS tube MP16, the gate of the seventeenth PMOS tube MP17, the gate of the eighteenth PMOS tube MP18, and the drain of the fourteenth PMOS tube MP14; the source of the thirteenth PMOS tube MP13, the source of the fifteenth PMOS tube MP15, the source of the seventeenth PMOS tube MP17, the source of the twenty-first PMOS tube MP21, and the source of the twenty-second PMOS tube MP22 are all connected to the power supply voltage VDD; the drain of the thirteenth PMOS tube MP13 is connected to the source of the fourteenth PMOS tube MP14, the drain of the fifteenth PMOS tube MP15 is connected to the source of the sixteenth PMOS tube MP16, and the drain of the seventeenth PMOS tube MP17 is connected to the source of the eighteenth PMOS tube MP18;

[0023] The drain of the sixteenth PMOS tube MP16 is connected to the gate and drain of the eleventh NMOS tube MN11, the gate of the thirteenth NMOS tube MN13, and the gate of the fifteenth NMOS tube MN15. The source of the eleventh NMOS tube MN11 is connected to the gate and drain of the tenth NMOS tube MN10. The drain of the eighteenth PMOS tube MP18 is connected to the source of the nineteenth PMOS tube MP19 and the source of the twentieth PMOS tube MP20. The gate of the nineteenth PMOS tube MP19 is used as the non-inverting input terminal of the operational amplifier A. The drain of the nineteenth PMOS tube MP19 is connected to the gate of the twelfth NMOS tube The gate of the twentieth PMOS tube MP20 is used as the inverting input terminal of the operational amplifier A. The drain of the twentieth PMOS tube MP20 is connected to the drain of the fourteenth NMOS tube MN14 and the source of the fifteenth NMOS tube MN15. The gate and drain of the twenty-first PMOS tube MP21 are interconnected and connected to the gate of the twenty-second PMOS tube MP22 and the drain of the thirteenth NMOS tube MN13. The drain of the twenty-second PMOS tube MP22 is connected to the drain of the fifteenth NMOS tube MN15 and serves as the output terminal of the operational amplifier A.

[0024] Preferably, the zero temperature coefficient resistor comprises a first resistor R1 and a second resistor R2 connected in series, wherein the first resistor R1 has a negative temperature coefficient, and the second resistor R2 has a positive temperature coefficient.

[0025] Preferably, the first resistor R1 is a polysilicon resistor, and the second resistor R2 is an N-well resistor.

[0026] Preferably, the first NMOS transistor MN1, the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 are transistors with a standard voltage of 3.3V, and the remaining MOS transistors are transistors with a standard voltage of 1.5V.

[0027] Preferably, the ratio of the width to length ratios of the fifth PMOS transistor MP5 , the sixth PMOS transistor MP6 , the eleventh PMOS transistor MP11 , and the twelfth PMOS transistor MP12 is λ:λ:1:1.

[0028] Preferably, the width-to-length ratio of the first NMOS transistor MN1 and the width-to-length ratio of the second NMOS transistor MN2 have a certain ratio so as to compensate for the voltage outputted from the reference voltage output terminal.

[0029] In a sub-threshold CMOS reference circuit with temperature compensation provided by the present invention, segmented compensation is performed in a low temperature zone and a high temperature zone by a first compensation circuit and a second compensation circuit, thereby obtaining a very low temperature drift coefficient, and a negative feedback method is used in the reference core circuit to improve the power supply voltage rejection ratio of the overall circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0031] Figure 1 It is a schematic diagram of a sub-threshold CMOS reference circuit with temperature compensation provided by the present invention;

[0032] Figure 2 is a schematic diagram of an operational amplifier circuit according to an embodiment of the present invention;

[0033] Figure 3 This is a simulation result diagram of the variation of the output voltage of a subthreshold CMOS reference circuit with temperature according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0035] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features. The term "proximal end" is usually the end close to the operator, and the term "distal end" is usually the end close to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" usually refer to two corresponding parts, which include not only the endpoints. The terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of the two elements or the interaction relationship between the two elements. In addition, as used in the present invention, an element is arranged on another element, which usually only means that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and it cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] The inventors have found that conventional subthreshold CMOS reference sources widely have V TH The value of the higher-order term is much larger than the V BE In order to solve this problem, it is necessary to design a temperature compensation circuit to expand the operating temperature range and reduce the temperature drift coefficient.

[0037] Based on this, the core idea of ​​the present invention is to obtain a very low temperature drift coefficient by performing segmented compensation in the low temperature zone and the high temperature zone through the first compensation circuit and the second compensation circuit, and use the negative feedback method in the reference core circuit to improve the power supply voltage suppression ratio of the overall circuit.

[0038] For details, please refer to Figure 1-Figure 3 , which is a schematic diagram of an embodiment of the present invention. Figure 1 As shown, a subthreshold CMOS reference circuit with temperature compensation comprises:

[0039] A reference core circuit is used to compensate the temperature coefficient of the output reference voltage through a MOS tube, wherein the first output end of the reference core circuit is used as a reference voltage output end, and the second output end is used to output a reference current. The reference core circuit also includes a zero temperature coefficient resistor and an operational amplifier A, wherein the non-inverting input end of the operational amplifier A is connected to the first output end of the reference core circuit, and the inverting input end of the operational amplifier A is connected to a bias current and is connected to the positive electrode of the zero temperature coefficient resistor to form a virtual short through a negative feedback loop to generate a zero temperature coefficient bias current on the zero temperature coefficient resistor, and the bias current is copied and output through a current mirror;

[0040] A startup circuit, used to make the reference core circuit leave the zero state, wherein the first output terminal and the second output terminal of the startup circuit are respectively connected to the first input terminal and the second input terminal of the reference core circuit;

[0041] A first compensation circuit is used to obtain a copied bias current and access the first output end of the reference core circuit through a MOS tube to compensate for the reference voltage. The first compensation circuit performs low temperature compensation on the reference voltage. The first compensation circuit is also a low temperature zone compensation circuit.

[0042] The second compensation circuit is used to obtain the copied bias current and compensate the reference voltage by connecting to the first output end of the reference core circuit through the MOS tube. The second compensation circuit performs high temperature compensation on the reference voltage. The second compensation circuit is also a high temperature zone compensation circuit.

[0043] The reference core circuit is used to generate a reference voltage and a reference current. For example, two NMOS tubes with different threshold voltages can be stacked and their width-to-length ratios can be adjusted to obtain a reference voltage that eliminates the first-order temperature coefficient. Furthermore, an operational amplifier A and a zero temperature coefficient resistor are introduced. The "virtual short" formed by the deep negative feedback of the operational amplifier generates a zero temperature coefficient current on the zero temperature coefficient resistor, which is then copied and output through a current mirror.

[0044] More preferably, the low temperature zone compensation circuit allows the copied bias current to flow through two MOS tubes connected by diodes to generate a CTAT bias voltage with a lower slope, and the bias voltage is connected to the gate of another MOS tube, and the drain of the MOS tube is connected to the first output end of the reference core circuit to perform low temperature compensation for the reference voltage; the high temperature zone compensation circuit allows the copied bias current to flow through a MOS tube connected by a diode to generate a CTAT bias voltage with a higher slope, and the bias voltage is connected to the gate of another MOS tube, and the drain of the MOS tube is connected to the first output end of the core reference current to perform high temperature compensation for the reference voltage.

[0045] It can be understood that the startup circuit is used to make the reference core circuit out of the zero state during the initialization phase and output the reference voltage VREF It exits operation when a stable state is reached, and at this time, other transistors in the circuit all operate in the subthreshold region.

[0046] In one embodiment, the startup circuit includes a first PMOS transistor MS1, a second NMOS transistor MS2 and a third NMOS transistor MS3, the gate of the first PMOS transistor MS1 is connected to the drain of the second NMOS transistor MS2 and the gate of the third NMOS transistor MS3, the source and drain of the first PMOS transistor MS1 are both connected to the power supply voltage VDD, the drain of the third NMOS transistor MS3 serves as the first output end of the startup circuit, the source of the second NMOS transistor MS2 and the source of the third NMOS transistor MS3 are both connected to GND, and the gate of the second NMOS transistor MS2 serves as the second output end of the startup circuit.

[0047] The startup circuit is composed of a first PMOS transistor MS1, a second NMOS transistor MS2 and a third NMOS transistor MS3. The gate of the first PMOS transistor MS1 is connected to the drain of the second NMOS transistor MS2 and the gate of the third NMOS transistor MS3, and its source and drain are both connected to the power supply voltage VDD. The gate of the second NMOS transistor MS2 is connected to the drain of the first NMOS transistor MN1, the source of the second NMOS transistor MN2, the positive plate of the first capacitor C1, the positive input terminal of the operational amplifier A, the drain of the fifth NMOS transistor MN5, the drain of the seventh NMOS transistor MN7 and the reference voltage output terminal, and the sources of the second NMOS transistor MS2 and the third NMOS transistor MS3 are both connected to GND. The drain of the third NMOS transistor MS3 is connected to the gates of the first PMOS transistor MP1 to the twelfth PMOS transistor MP12, the lower plate of the second capacitor C2, and the output terminal of the operational amplifier A.

[0048] It can be understood that the first PMOS transistor MS1 acts as a capacitor. When the voltage V REF When the gate voltage V GS3 As the power supply increases, V GS3 is greater than the threshold voltage of the third NMOS transistor MS3, and then the gate voltages of the first PMOS transistor MP1 to the twelfth PMOS transistor MP12 are pulled down, so that the reference core circuit is out of the zero state. REFWhen the stable state is reached, the second NMOS transistor MS2 is turned on, pulling down the gate voltage of the third NMOS transistor MS3, and the third NMOS transistor MS3 is turned off. The startup circuit no longer consumes power. To reduce power consumption and power supply voltage, other transistors in the circuit all operate in the subthreshold region.

[0049] The reference core circuit includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first NMOS tube MN1, a second NMOS tube MN2, a zero temperature coefficient resistor, a first capacitor C1, a second capacitor C2 and an operational amplifier A; the source of the first NMOS tube MN1, the negative plate of the first capacitor C1, and the negative electrode of the zero temperature coefficient resistor are connected to GND, the gate of the first NMOS tube MN1 and the gate and drain of the second NMOS tube MN2, and the drain of the second PMOS tube MP2 are connected, and the first PMOS tube MP1 is connected to the gate of the second NMOS tube MN2. The source of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2, the source of the third PMOS tube MP3 is connected to the source of the fourth PMOS tube MP4, the drain of the fifth PMOS tube MP5 is connected to the source of the sixth PMOS tube MP6, and the drain of the sixth PMOS tube MP6 is connected to the positive electrode of the zero temperature coefficient resistor and the inverting input terminal of the operational amplifier A. The drain of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2, the drain of the third PMOS tube MP3 is connected to the source of the fourth PMOS tube MP4, and the drain of the fifth PMOS tube MP5 is connected to the source of the sixth PMOS tube MP6.

[0050] After the reference core circuit is started up by the startup circuit and leaves the zero state, the reference voltage V REF It is generated by the difference between the gate-source voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2, which can be expressed by the following formula (1):

[0051] (1)

[0052] V GS1 is the gate-source voltage of the first NMOS tube MN1, V GS2is the gate-source voltage of the second NMOS transistor MN2. Exemplarily, the first NMOS transistor MN1 is a 3.3V NMOS transistor, and the second NMOS transistor MN2 is a 1.5V NMOS transistor. Both transistors operate in the subthreshold region, but the types of the first NMOS transistor MN1 and the second NMOS transistor MN2 are not limited thereto. The following description is based on the assumption that the first NMOS transistor MN1, the fifth NMOS transistor MN5, and the seventh NMOS transistor MN7 are transistors with a standard voltage of 3.3V, and the remaining MOS transistors are transistors with a standard voltage of 1.5V.

[0053] Obviously, the threshold voltage of the 3.3V NMOS transistor is greater than the threshold voltage of the 1.5V NMOS transistor. DS ≥3V T When the subthreshold current I D It can be expressed as:

[0054] (2)

[0055] μ n is the electron mobility of the NMOS transistor, the subscript n represents the nth NMOS tube, C OX is the gate oxide capacitance, K is the width-to-length ratio (W / L) of the transistor, m is the subthreshold slope factor, V T =k B T / q is the thermal voltage, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, V GS is the gate-source voltage of the NMOS tube, V TH represents the threshold voltage of the NMOS tube. The subthreshold slope factor of any NMOS transistor is equal. Then the reference voltage V REF can be written as:

[0056] (3)

[0057] in,

[0058] (4)

[0059] In formula (3) and formula (4), the subscript numbers represent the subscripts of transistors MNi, V TH1 、V TH2 Represent the threshold voltages of the first NMOS tube and the second NMOS tube respectively, m is the subthreshold slope factor, V T is the thermal voltage, I D1 ,I D2 ,I D5 and I D7represents the subthreshold current of the first NMOS tube, the second NMOS tube, the fifth NMOS tube and the seventh NMOS tube, μ1 and μ2 are the electron mobility of the first NMOS tube and the second NMOS tube respectively, C OX1 , C OX2 are the gate oxide layer capacitances of the first NMOS tube and the second NMOS tube, respectively. K1 and K2 are the width-to-length ratios (W / L) of the first NMOS tube and the second NMOS tube, respectively. Threshold voltage V TH It can be expressed as:

[0060] (5)

[0061] V TH (T0) is the threshold voltage value when T0=300K, T is the absolute temperature, k t The slope is negative, and the absolute value of the threshold voltage slope of the 3.3V NMOS transistor is greater than that of the 1.5V NMOS transistor. Therefore, the first term in equation (3) has a negative temperature coefficient. The width-to-length ratio of the first NMOS transistor MN1 and the width-to-length ratio of the second NMOS transistor MN2 have a certain ratio to the voltage V output from the reference voltage output terminal. REF The positive temperature coefficient term can be compensated by adjusting the width-to-length ratio K1 of the first NMOS transistor MN1 and the width-to-length ratio K2 of the second NMOS transistor MN2. REF The first-order compensation.

[0062] like Figure 2 As shown, the output end of the operational amplifier A is connected to the gate of the first PMOS tube MP1, the gate of the second PMOS tube MP2, the gate of the third PMOS tube MP3, the gate of the fourth PMOS tube MP4, the gate of the fifth PMOS tube MP5, the gate of the sixth PMOS tube MP6, the gate of the seventh PMOS tube MP7, the gate of the eighth PMOS tube MP8, the gate of the ninth PMOS tube MP9, the gate of the tenth PMOS tube MP10, the gate of the eleventh PMOS tube MP11, the gate of the twelfth PMOS tube MP12, and the negative plate of the second capacitor C2, and serves as the first input end of the reference core circuit; the drain of the first NMOS tube MN1 and the source of the second NMOS tube MN2, the positive plate of the first capacitor C1, the drain of the fifth NMOS tube MN5, the drain of the seventh NMOS tube MN7, the non-inverting input end of the operational amplifier A, and the reference voltage output end, and serves as the second input end of the reference core circuit.

[0063] Specifically, the operational amplifier includes an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, a twelfth NMOS tube MN12, a thirteenth NMOS tube MN13, a fourteenth NMOS tube MN14, a fifteenth NMOS tube MN15, a thirteenth PMOS tube MP13, a fourteenth PMOS tube MP14, a fifteenth PMOS tube MP15, a sixteenth PMOS tube MP16, a seventeenth PMOS tube MP17, an eighteenth PMOS tube MP18, a nineteenth PMOS tube MP19, a twentieth PMOS tube MP20, a twenty-first PMOS tube MP21 and a twenty-second PMOS tube MP22.

[0064] The gate and drain of the eighth NMOS tube MN8 are interconnected, and are connected together with the gate of the ninth NMOS tube MN9, the gate of the twelfth NMOS tube MN12, and the gate of the fourteenth NMOS tube MN14 to serve as the bias current input terminal IB of the operational amplifier A. The source of the eighth NMOS tube MN8, the source of the ninth NMOS tube MN9, the source of the tenth NMOS tube MN10, the source of the twelfth NMOS tube MN12, and the source of the fourteenth NMOS tube MN14 are all connected to GND.

[0065] The drain of the ninth NMOS tube MN9 is connected to the gate of the thirteenth PMOS tube MP13, the gate of the fourteenth PMOS tube MP14, the gate of the fifteenth PMOS tube MP15, the gate of the sixteenth PMOS tube MP16, the gate of the seventeenth PMOS tube MP17, the gate of the eighteenth PMOS tube MP18, and the drain of the fourteenth PMOS tube MP14; the source of the thirteenth PMOS tube MP13, the source of the fifteenth PMOS tube MP15, the source of the seventeenth PMOS tube MP17, the source of the twenty-first PMOS tube MP21, and the source of the twenty-second PMOS tube MP22 are all connected to the power supply voltage VDD; the drain of the thirteenth PMOS tube MP13 is connected to the source of the fourteenth PMOS tube MP14, the drain of the fifteenth PMOS tube MP15 is connected to the source of the sixteenth PMOS tube MP16, and the drain of the seventeenth PMOS tube MP17 is connected to the source of the eighteenth PMOS tube MP18.

[0066] The drain of the sixteenth PMOS tube MP16 is connected to the gate and drain of the eleventh NMOS tube MN11, the gate of the thirteenth NMOS tube MN13, and the gate of the fifteenth NMOS tube MN15. The source of the eleventh NMOS tube MN11 is connected to the gate and drain of the tenth NMOS tube MN10. The drain of the eighteenth PMOS tube MP18 is connected to the source of the nineteenth PMOS tube MP19 and the source of the twentieth PMOS tube MP20. The gate of the nineteenth PMOS tube MP19 is used as the non-inverting input terminal VIP of the operational amplifier A. The drain of the nineteenth PMOS tube MP19 is connected to the twelfth NMOS tube M The drain of the 20th PMOS tube MP20 is used as the inverting input terminal VIP of the operational amplifier A. The drain of the 20th PMOS tube MP20 is connected to the drain of the 14th NMOS tube MN14 and the source of the 15th NMOS tube MN15. The gate and drain of the 21st PMOS tube MP21 are interconnected and connected to the gate of the 22nd PMOS tube MP22 and the drain of the 13th NMOS tube MN13. The drain of the 22nd PMOS tube MP22 is connected to the drain of the 15th NMOS tube MN15 and serves as the output terminal VO of the operational amplifier A.

[0067] like Figure 1 and Figure 2 The operational amplifier A and the reference core circuit adopt a folded common source and common gate structure to improve the loop gain, and the first capacitor C1 is connected between the reference voltage output terminal and GND to improve PSRR, and the second capacitor C2 is connected between the operational amplifier and the power supply voltage VDD to compensate for frequency and ensure the stability of the loop. Under the action of the negative feedback loop provided by the operational amplifier A, the inverting input terminal of the operational amplifier A is connected to the reference voltage V REF To accurately approximate, the current flowing through a zero temperature coefficient resistor can be calculated by dividing the current through the zero temperature coefficient resistor and V REF It means that both are independent of temperature, so the current flowing through the zero temperature coefficient resistor is also independent of temperature.

[0068] In one embodiment, the zero temperature coefficient resistor includes a first resistor R1 and a second resistor R2 connected in series, the positive electrode of the first resistor R1 is connected to the inverting input terminal of the operational amplifier A, and the negative electrode is connected to the positive electrode of the second resistor R2, and the negative electrode of the second resistor R2 is connected to GND, wherein the first resistor R1 has a negative temperature coefficient, and the second resistor R2 has a positive temperature coefficient. More preferably, the first resistor R1 is a polysilicon resistor, and the second resistor R2 is an N-well resistor. The types of the first resistor and the second resistor can be swapped, and the zero temperature coefficient resistor can also be formed by combining other types of positive temperature coefficient resistors and negative temperature coefficient resistors. In the case where the first resistor R1 is a polysilicon resistor and the second resistor R2 is an N-well resistor, the bias current flowing through the zero temperature coefficient resistor I BIAS :

[0069] (6)

[0070] R1 and R2 are the resistance values ​​of the first resistor R1 and the second resistor R2 respectively, and the reference voltage V REF R1 is a polysilicon resistor with a negative temperature coefficient, and R2 is an N-well resistor with a positive temperature coefficient. The combination of the two can form a total resistor with a zero temperature coefficient. Since both the numerator and denominator of equation (6) are independent of temperature, then I BIAS It has nothing to do with temperature.

[0071] The first PMOS transistor MP1 to the twelfth PMOS transistor MP12 are current mirror structures of cascade transistors, which are used to accurately replicate the current in proportion. I BIAS Current. The current copied by the first PMOS tube MP1 and the second PMOS tube MP2 is used to bias the first NMOS tube MN1 and the second NMOS tube MN2 to generate a reference voltage; the current copied by the third PMOS tube MP3 and the fourth PMOS tube MP4 is used to bias the operational amplifier A; the current copied by the seventh PMOS tube MP7 and the eighth PMOS tube MP8 is used to bias the low temperature compensation circuit; the current copied by the ninth PMOS tube MP9 and the tenth PMOS tube MP10 is used to bias the high temperature compensation circuit. The current copied by the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12 is the output reference current I REF , I REF It has nothing to do with temperature either.

[0072] Exemplarily, the fifth PMOS tube and the sixth PMOS tube have the same width-to-length ratio, the eleventh PMOS tube and the twelfth PMOS tube have the same width-to-length ratio, and the ratio of the width-to-length ratios of the fifth PMOS tube MP5, the sixth PMOS tube MP6, the eleventh PMOS tube MP11, and the twelfth PMOS tube MP12 is recorded as λ:λ:1:1. Then the reference current I REF It can be expressed as:

[0073] (7)

[0074] R1 and R2 are the resistance values ​​of the first resistor R1 and the second resistor R2 respectively, and the reference voltage V REF。 The low temperature zone compensation circuit includes a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a seventh PMOS tube MP7 and an eighth PMOS tube MP8; the source of the seventh PMOS tube MP7 is connected to the power supply voltage VDD, the gate and drain of the fourth NMOS tube MN4 are connected to the drain of the eighth PMOS tube MP8, and are connected to the gate of the fifth NMOS tube MN5, the source of the fourth NMOS tube MN4 is connected to the drain and gate of the third NMOS tube MN3, the source of the third NMOS tube MN3 and the source of the fifth NMOS tube MN5 are both connected to GND, the drain of the seventh PMOS tube MP7 is connected to the source of the eighth PMOS tube MP8. The fifth NMOS tube MN5 is a 3.3V NMOS transistor, and the gate voltage or gate-source voltage V GS5 It can be expressed by the following formula:

[0075] (8)

[0076] V GS3 is the gate voltage of the third NMOS transistor MN3, V GS4 is the gate voltage of the fourth NMOS transistor MN4. According to formula (2), the subthreshold current I flowing through the fifth NMOS transistor MN5 is D5 can be written as:

[0077] (9)

[0078] Among them, I3 and I4 are the subthreshold currents flowing through the third NMOS tube and the fourth NMOS tube, respectively; μ3, μ4, and μ5 are the electron mobilities of the third NMOS tube, the fourth NMOS tube, and the fifth NMOS tube, respectively; C OX3 , C OX4 , C OX5are the gate oxide capacitances of the third, fourth, and fifth NMOS tubes, respectively. K3, K4, and K5 are the width-to-length ratios of the third, fourth, and fifth NMOS tubes, respectively. m is the subthreshold slope factor. Since the threshold voltage V TH3 The threshold voltage V TH4 The sum is less than the threshold voltage V of the fifth NMOS tube TH5 , and the thermal voltage V T is proportional to temperature, so I D5 In the high temperature area, it is almost zero. TH3 Temperature coefficient vs. V TH4 The sum of the temperature coefficients is less than V TH5 The temperature coefficient in the low temperature zone I D5 Therefore, the temperature performance of the circuit in the low temperature area is compensated.

[0079] The high temperature zone compensation circuit includes a sixth NMOS tube MN6, a seventh NMOS tube MN7, a ninth PMOS tube MP9, a tenth PMOS tube MP10, an eleventh PMOS tube MP11 and a twelfth PMOS tube MP12; the source of the ninth PMOS tube MP9 is connected to the power supply voltage VDD, the drain of the ninth PMOS tube MP9 is connected to the source of the tenth PMOS tube MP10, the drain of the tenth PMOS tube MP10 is connected to the gate and drain of the sixth NMOS tube MN6, and is connected to the gate of the seventh NMOS tube MN7, the source of the sixth NMOS tube MN6 and the source of the seventh NMOS tube MN7 are both connected to GND; the source of the eleventh PMOS tube MP11 is connected to the power supply voltage VDD, the drain of the eleventh PMOS tube MP11 is connected to the source of the twelfth PMOS tube MP12, and the drain of the twelfth PMOS tube MP12 is the reference current output terminal. The seventh NMOS transistor MN7 is a 3.3V NMOS transistor. The drain current or subthreshold current I D7 It can be expressed as:

[0080] (10)

[0081] I6 is the subthreshold current flowing through the sixth NMOS tube, μ6 and μ7 are the electron mobility of the sixth NMOS tube and the seventh NMOS tube respectively, C OX6 , C OX7 are the gate oxide capacitances of the sixth and seventh NMOS tubes, respectively; K6 and K7 are the width-to-length ratios of the sixth and seventh NMOS tubes, respectively; m is the subthreshold slope factor; V T is the thermal voltage, I D7In the low temperature region, it is almost zero. The threshold voltage V TH6 The temperature coefficient is greater than the threshold voltage V TH7 Temperature coefficient, I D7 It cannot be ignored in the high temperature area. Therefore, the temperature performance of the circuit in the high temperature area is compensated.

[0082] In one embodiment, based on the design of Hua Hong Hong Li 110nm standard process library, such as Figure 3 As shown in the simulation diagram of the output reference voltage changing with temperature, the output voltage of the CMOS reference source is compensated in both low and high temperature areas, and the temperature drift coefficient is optimized, achieving a temperature drift coefficient of 10.86ppm / ℃ in the range of -40~125℃.

[0083] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A subthreshold CMOS reference circuit with temperature compensation, characterized in that: include: A reference core circuit is used to compensate the temperature coefficient of the output reference voltage through a MOS tube, wherein the first output end of the reference core circuit is used as a reference voltage output end, and the second output end is used to output a reference current. The reference core circuit also includes a zero temperature coefficient resistor and an operational amplifier, wherein the non-inverting input end of the operational amplifier is connected to the first output end of the reference core circuit, and the inverting input end of the operational amplifier is connected to a bias current and is connected to the positive electrode of the zero temperature coefficient resistor to form a virtual short through a negative feedback loop to generate a zero temperature coefficient bias current on the zero temperature coefficient resistor, and the bias current is copied and output through a current mirror; A startup circuit, used to make the reference core circuit leave the zero state, wherein the first output terminal and the second output terminal of the startup circuit are respectively connected to the first input terminal and the second input terminal of the reference core circuit; a first compensation circuit, used for obtaining a copied bias current and compensating a reference voltage by connecting the first output end of the reference core circuit through a MOS tube, wherein the first compensation circuit comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a seventh PMOS tube and an eighth PMOS tube; The source of the seventh PMOS tube is connected to the power supply voltage, the gate and drain of the fourth NMOS tube are connected to the drain of the eighth PMOS tube and connected to the gate of the fifth NMOS tube, the source of the fourth NMOS tube is connected to the drain and gate of the third NMOS tube, the source of the third NMOS tube and the source of the fifth NMOS tube are both connected to GND, and the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube; The second compensation circuit is used to obtain the copied bias current and compensate the reference voltage by connecting to the first output terminal of the reference core circuit through the MOS tube.

2. The subthreshold CMOS reference circuit with temperature compensation according to claim 1, characterized in that: The reference core circuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a first capacitor, and a second capacitor; The source of the first NMOS tube, the negative plate of the first capacitor, and the negative electrode of the zero temperature coefficient resistor are connected to GND; the gate of the first NMOS tube is connected to the gate and drain of the second NMOS tube, and the drain of the second PMOS tube; the source of the first PMOS tube, the source of the third PMOS tube, the source of the fifth PMOS tube, and the positive plate of the second capacitor are all connected to the power supply voltage; the drain of the fourth PMOS tube is connected to the bias current input terminal of the operational amplifier; the drain of the sixth PMOS tube is connected to the positive electrode of the zero temperature coefficient resistor and the inverting input terminal of the operational amplifier; the drain of the first PMOS tube is connected to the source of the second PMOS tube; the drain of the third PMOS tube is connected to the source of the fourth PMOS tube; and the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube.

3. The subthreshold CMOS reference circuit with temperature compensation according to claim 2, characterized in that: The second compensation circuit includes a sixth NMOS tube, a seventh NMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube and a twelfth PMOS tube; The source of the ninth PMOS tube is connected to the power supply voltage, the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube, the drain of the tenth PMOS tube is connected to the gate and drain of the sixth NMOS tube, and is connected to the gate of the seventh NMOS tube, and the source of the sixth NMOS tube and the source of the seventh NMOS tube are both connected to GND; The source of the eleventh PMOS tube is connected to the power supply voltage, the drain of the eleventh PMOS tube is connected to the source of the twelfth PMOS tube, and the drain of the twelfth PMOS tube is the reference current output terminal.

4. The subthreshold CMOS reference circuit with temperature compensation according to claim 3, characterized in that: The output end of the operational amplifier is connected to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube, the gate of the fourth PMOS tube, the gate of the fifth PMOS tube, the gate of the sixth PMOS tube, the gate of the seventh PMOS tube, the gate of the eighth PMOS tube, the gate of the ninth PMOS tube, the gate of the tenth PMOS tube, the gate of the eleventh PMOS tube, the gate of the twelfth PMOS tube, and the negative plate of the second capacitor, and serves as the first input end of the reference core circuit; the drain of the first NMOS tube and the source of the second NMOS tube, the positive plate of the first capacitor, the drain of the fifth NMOS tube, the drain of the seventh NMOS tube, the non-inverting input end of the operational amplifier, and the reference voltage output end, and serve as the second input end of the reference core circuit.

5. The subthreshold CMOS reference circuit with temperature compensation according to claim 2, characterized in that: The startup circuit includes a first PMOS transistor, a second NMOS transistor and a third NMOS transistor, the gate of the first PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the third NMOS transistor, the source and drain of the first PMOS transistor are both connected to the power supply voltage, the drain of the third NMOS transistor serves as the first output end of the startup circuit, the source of the second NMOS transistor and the source of the third NMOS transistor are both connected to GND, and the gate of the second NMOS transistor serves as the second output end of the startup circuit.

6. The subthreshold CMOS reference circuit with temperature compensation according to claim 1, characterized in that: The operational amplifier includes an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube and a twenty-second PMOS tube; The gate and drain of the eighth NMOS tube are interconnected and connected with the gates of the ninth NMOS tube, the twelfth NMOS tube, and the fourteenth NMOS tube to serve as the bias current input terminal of the operational amplifier, and the source of the eighth NMOS tube, the source of the ninth NMOS tube, the source of the tenth NMOS tube, the source of the twelfth NMOS tube, and the source of the fourteenth NMOS tube are all connected to GND; The drain of the ninth NMOS tube is connected to the gate of the thirteenth PMOS tube, the gate of the fourteenth PMOS tube, the gate of the fifteenth PMOS tube, the gate of the sixteenth PMOS tube, the gate of the seventeenth PMOS tube, the gate of the eighteenth PMOS tube, and the drain of the fourteenth PMOS tube, the source of the thirteenth PMOS tube, the source of the fifteenth PMOS tube, the source of the seventeenth PMOS tube, the source of the twenty-first PMOS tube, and the source of the twenty-second PMOS tube are all connected to the power supply voltage, the drain of the thirteenth PMOS tube is connected to the source of the fourteenth PMOS tube, the drain of the fifteenth PMOS tube is connected to the source of the sixteenth PMOS tube, and the drain of the seventeenth PMOS tube is connected to the source of the eighteenth PMOS tube; The drain of the sixteenth PMOS tube is connected to the gate and drain of the eleventh NMOS tube, the gate of the thirteenth NMOS tube, and the gate of the fifteenth NMOS tube. The source of the eleventh NMOS tube is connected to the gate and drain of the tenth NMOS tube. The drain of the eighteenth PMOS tube is connected to the source of the nineteenth PMOS tube and the source of the twentieth PMOS tube. The gate of the nineteenth PMOS tube is used as the non-inverting input terminal of the operational amplifier. The drain of the nineteenth PMOS tube is connected to the drain of the twelfth NMOS tube and the source of the thirteenth NMOS tube. The gate of the twentieth PMOS tube is used as the inverting input terminal of the operational amplifier. The drain of the twentieth PMOS tube is connected to the drain of the fourteenth NMOS tube and the source of the fifteenth NMOS tube. The gate and drain of the twenty-first PMOS tube are interconnected and connected to the gate of the twenty-second PMOS tube and the drain of the thirteenth NMOS tube. The drain of the twenty-second PMOS tube is connected to the drain of the fifteenth NMOS tube and serves as the output terminal of the operational amplifier.

7. The subthreshold CMOS reference circuit with temperature compensation according to claim 1, characterized in that: The zero temperature coefficient resistor includes a first resistor and a second resistor connected in series, wherein the first resistor has a negative temperature coefficient and the second resistor has a positive temperature coefficient.

8. The subthreshold CMOS reference circuit with temperature compensation according to claim 3, characterized in that: The first NMOS tube, the fifth NMOS tube and the seventh NMOS tube are transistors with a standard voltage of 3.3V, and the remaining MOS tubes are transistors with a standard voltage of 1.5V.

9. The subthreshold CMOS reference circuit with temperature compensation according to claim 4, characterized in that: The fifth PMOS tube and the sixth PMOS tube have the same width-to-length ratio, and the eleventh PMOS tube and the twelfth PMOS tube have the same width-to-length ratio.

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