Method, board, electronic device and storage medium for data transmission between boards

Abstract

The embodiment of the present invention relates to a method, board, electronic device and storage medium for data transmission between boards. The method comprises: sending a write instruction to a first board; in response to receiving the write instruction, the first board writes a predetermined amount of data to a second board; sending a barrier instruction to the first board to block the first board from sending subsequent instructions to the second board until it is determined that the predetermined amount of data is all written to the second board; the first board determines whether the predetermined amount of data is all written to the second board; and in response to the first board determining that the predetermined amount of data is all written to the second board, the first board sends a synchronization signal to the second board to indicate that the predetermined amount of data has been fully synchronized to the second board. The embodiment of the present invention can avoid the second board from remotely polling the first board, improve the performance of data transmission, and ensure the accuracy of data synchronization.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of data transmission, and more specifically, to a method, a board, an electronic device, and a storage medium for data transmission between boards. Background Art

[0002] A multi-card cluster, i.e. a cluster consisting of multiple boards, can achieve large model training, etc. through data interaction between boards. Taking the example of transferring data from a first board to a second board to achieve data synchronization between the first board and the second board, the existing method for data transmission between boards includes: first, writing the data to be transmitted to the first board, and after all the data is written to the first board, writing a synchronization signal to the first board; and, the second board repeatedly remotely polls the first board until the second board reads the synchronization signal, and then the second board reads the data written to the first board from the first board.

[0003] However, in the above existing solutions, the remote polling path is long, the delay is long, and the bandwidth utilization is low, which makes the performance of data transmission between boards poor and it is difficult to ensure data synchronization and order preservation between boards.

[0004] In summary, the existing methods for data transmission between boards have poor performance and lack methods that can ensure data synchronization and order preservation between boards. Summary of the invention

[0005] In view of the above problems, the present invention provides a method, a board, an electronic device and a storage medium for data transmission between boards, so as to improve the performance of data transmission and ensure the data order preservation and synchronization accuracy between boards.

[0006] According to a first aspect of the present invention, a method for data transmission between boards is provided, comprising: sending a write instruction to a first board; in response to receiving the write instruction, the first board writes a predetermined amount of data to a second board; sending a barrier instruction to the first board to block the first board from sending subsequent instructions to the second board until it is determined that the predetermined amount of data is all written to the second board; determining by the first board whether the predetermined amount of data is all written to the second board; and in response to the first board determining that the predetermined amount of data is all written to the second board, sending a synchronization signal by the first board to the second board to indicate that the predetermined amount of data has been all synchronized to the second board.

[0007] In some embodiments, writing a predetermined amount of data by the first board to the second board includes: at least one computing core of the first board converting a write instruction into a corresponding write request so as to count the expected amount of data to be written by the first board to the second board based on the write request.

[0008] In some embodiments, the write request includes information regarding a source of the predetermined amount of data.

[0009] In some embodiments, determining by the first board whether a predetermined amount of data is all written to the second board includes: receiving, by the atomic type accumulator of the first board, a response returned from the second board, the response including information related to the amount of data that has been written to the second board; calculating, based on the response, the amount of data that has been written to the second board; and determining, based on the calculated amount of data that has been written to the second board, whether the predetermined amount of data is all written to the second board.

[0010] In some embodiments, determining whether the predetermined amount of data is all written to the second board includes: at least one computing core of the first board pollingly reads the atomic type accumulator of the first board to calculate the amount of data that has been written to the second board; and in response to the amount of data that has been written to the second board being the same as the expected amount of data to be written to the second board, determining that the predetermined amount of data is all written to the second board.

[0011] In some embodiments, writing a predetermined amount of data by a first board into a second board includes: reading a predetermined amount of data from a high-bandwidth memory of the first board by at least one computing core of the first board; and sending the predetermined amount of data to the second board via an on-chip network and at least one connection port of the first board, so as to be written into the high-bandwidth memory of the second board via at least one connection port of the second board and the on-chip network of the second board.

[0012] In some embodiments, writing a predetermined amount of data by the first board into the second board also includes: in response to at least a portion of the predetermined amount of data being written into the high-bandwidth memory of the second board, generating a write response by the high-bandwidth memory of the second board, and sending the write response to the aggregate response unit of the second board via the on-chip network of the second board; and counting the source and quantity of the data that has been written into the high-bandwidth memory of the second board based on the write response via the aggregate response unit of the second board.

[0013] In some embodiments, the write response includes information related to the source of the data written to the second board. In these embodiments, counting the source and amount of data that has been written to the high-bandwidth memory of the second board includes: determining the source of the data corresponding to the current write response; determining whether the aggregate response unit includes a record entry that is the same as the source of the data corresponding to the current write response; and in response to the aggregate response unit including the record entry that is the same as the source of the data corresponding to the current write response, performing a cumulative operation based on the record entry to facilitate counting the amount of data from the same source.

[0014] In some embodiments, counting the source and quantity of data that has been written to the high-bandwidth memory of the second board also includes: in response to the aggregate response unit not including a record entry with the same source as the data corresponding to the current write response, determining whether the aggregate response unit includes cache space; in response to the aggregate response unit including cache space, generating a new record entry based on the write response to record the source and quantity of the data corresponding to the current write response; and in response to the aggregate response unit not including cache space, generating a new record entry based on the write response to replace an existing record entry according to a least recently used policy, and recording the source and quantity of the data corresponding to the current write response.

[0015] In some embodiments, the aggregate response unit of the second board sends a response to the first board so that the first board determines whether a predetermined amount of data is all written to the second board based on the response, wherein the response includes information about the amount of data that has been written to the second board.

[0016] According to a second aspect of the present invention, a board is provided, comprising: at least one computing core, wherein the at least one computing core is configured to: receive a write instruction so that the board writes a predetermined amount of data to another board based on the write instruction; receive a barrier instruction to block the board from sending subsequent instructions to the other board until it is determined that the predetermined amount of data is all written to the other board; determine whether the predetermined amount of data is all written to the other board; and send a synchronization signal to indicate that the predetermined amount of data has been fully synchronized to the other board.

[0017] In some embodiments, at least one computing core is further configured to: convert the received write instruction into a corresponding write request so as to count the expected amount of data to be written by the board to another board based on the write request.

[0018] In some embodiments, the board also includes: an atomic type accumulator, wherein the atomic type accumulator is configured to: receive a response returned from another board, the response including information related to the amount of data that has been written to the other board; based on the response, calculate the amount of data that has been written to the other board; and based on the calculated amount of data that has been written to the other board, determine whether the predetermined amount of data is all written to the other board.

[0019] In some embodiments, at least one computing core is further configured to: poll and read the number of data that has been written to another board card calculated by an atomic type accumulator; and in response to the number of data that has been written to another board card being the same as the expected number of data to be written to the other board card, determine that a predetermined number of data is all written to the other board card.

[0020] In some embodiments, the board also includes: a high-bandwidth memory configured to store data written to the board and to generate a write response based on the data written to the board; and an aggregation response unit configured to count the source and quantity of data that has been written to the board based on the write response generated by the high-bandwidth memory.

[0021] In some embodiments, the aggregate response unit is further configured to: send a response including information about the amount of data that has been written to the board.

[0022] According to a third aspect of the present invention, a computing device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor so that the at least one processor can execute the method of the first aspect of the present invention.

[0023] According to a fourth aspect of the present invention, there is provided a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method of the first aspect of the present invention.

[0024] According to a fifth aspect of the present invention, there is provided a computer program product, wherein the computer program product is tangibly stored on a non-transitory computer readable medium and comprises machine executable instructions which, when executed, cause a machine to perform the steps in the method of the first aspect of the present invention.

[0025] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features, advantages and aspects of the embodiments of the present invention will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements.

[0027] Figure 1 An exemplary structural diagram of a commonly used board is shown.

[0028] Figure 2 A schematic diagram of the structure of a computing system including a cluster composed of multiple boards according to an embodiment of the present invention is shown.

[0029] Figure 3 A flow chart of a method for inter-board data transmission according to an embodiment of the present invention is shown.

[0030] Figure 4 A schematic structural diagram of a board according to an embodiment of the present invention is shown.

[0031] Figure 5 A schematic principle diagram of data transmission between boards according to an embodiment of the present invention is shown.

[0032] Figure 6 A block diagram of a computing device suitable for implementing embodiments of the present invention is schematically shown. DETAILED DESCRIPTION

[0033] The following is a description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0034] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0035] In a computing system including a cluster consisting of multiple boards, data transmission between boards faces great challenges in data synchronization and order preservation. Common boards may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), etc. Figure 1 An exemplary structural diagram of a commonly used board is shown.

[0036] like Figure 1 As shown, the board 100 may include: at least one computing core 110 , a high bandwidth memory (HBM) 120 , a network-on-chip (NoC) 130 , and at least one connection port 140 .

[0037] Regarding the computing core 110, it can be configured to perform tasks indicated by the received instructions. Specifically, the computing core 110 can be configured to receive, for example, a write instruction, and perform tasks related to writing data indicated by the write instruction, for example, writing data in the current board 100 to other boards to achieve data synchronization between the board 100 and other boards. The computing core 110 can also be configured to read data and / or signals from the high bandwidth memory 120, etc.

[0038] Regarding the high bandwidth memory 120 , it may be configured to store data and signals written to the board 100 .

[0039] Regarding the on-chip network 130 , it may be configured to implement data transmission within the board. For example, data read by the computing core 110 may be transmitted to, for example, the connection port 140 via the on-chip network 130 .

[0040] Regarding the connection port 140, it can be a P2P (peer-to-peer) port, configured to connect multiple boards to achieve data transmission between the boards. For example, the connection port 140 of the current board 100 can be connected to the connection port of another board (not shown), so that the data in the current board 100 is transmitted to the other board via the connection port 140 and the connection port of the other board.

[0041] Generally, the data transmission method between boards may include: writing the data to be transmitted and the synchronization signal into a first board (e.g., a source board); and remote polling (remote polling) of the first board by a second board (e.g., a destination board) to read data from the first board based on the synchronization signal. Specifically, the data may be first written into the high-bandwidth memory of the first board, and after the data is completely written, the synchronization signal may be written into the high-bandwidth memory of the first board. At the same time, the computing unit of the second board may remotely poll the high-bandwidth memory of the first board until the synchronization signal is read, and then the computing unit of the second board performs the operation of reading the data from the high-bandwidth memory of the first board, thereby realizing the data transmission between the first board and the second board. However, in the above scheme, the second board needs to perform remote polling and repeatedly read the synchronization signal in the first board. Due to the long remote polling path, long delay, and low bandwidth utilization, the performance of data transmission between boards will be affected, making it difficult to ensure data synchronization and order preservation between boards.

[0042] In summary, in the prior art, for data transmission between boards, the data transmission performance is poor, and there is a lack of methods that can ensure data synchronization and order preservation between boards.

[0043] In order to at least partially solve one or more of the above problems and other potential problems, an exemplary embodiment of the present invention proposes a scheme for data transmission between boards. In this scheme, a write instruction is sent to a first board; in response to receiving the write instruction, the first board writes a predetermined amount of data to a second board; a barrier instruction is sent to the first board to block the first board from sending subsequent instructions to the second board until it is determined that the predetermined amount of data is all written to the second board; the first board determines whether the predetermined amount of data is all written to the second board; and in response to the first board determining that the predetermined amount of data is all written to the second board, the first board sends a synchronization signal to the second board to indicate that the predetermined amount of data has been fully synchronized to the second board, so that the data to be transmitted is directly sent from the first board to the second board, thereby avoiding the second board from remotely polling the first board, and improving the performance of data transmission. In addition, the above scheme uses barrier instructions to maintain order to ensure that the data to be transmitted is fully sent from the first board to the second board, and then the first board sends a synchronization signal to the second board, thereby ensuring the accuracy of data synchronization.

[0044] The following will be combined Figures 2 to 5 A scheme for data transmission between boards according to an embodiment of the present invention is described in detail.

[0045] Figure 2 The schematic diagram of the structure of a computing system 200 including a cluster of multiple boards according to an embodiment of the present invention is shown. It should be understood that the system 200 may further include additional modules not shown and / or may omit the modules shown, and the scope of the present invention is not limited in this respect.

[0046] like Figure 2 As shown, the computing system 200 includes a processor 205 and a plurality of boards, namely a first board 210a and a second board 210b. It should be understood that according to an embodiment of the present invention, the number of boards that the computing system 200 may include is not limited to two. In some examples, the computing system 200 may include four, eight, sixteen boards, etc., and the present invention is not limited thereto.

[0047] Regarding the processor 205, it can be configured to send instructions to the board to instruct the board to perform corresponding operations. In an embodiment of the present invention, a write instruction such as a write instruction can be sent to the board to instruct the board to perform a write operation, that is, to write data to other boards. In some other embodiments, a fence instruction such as a fence instruction can be sent to the board to instruct the board to perform the operations indicated by all instructions before the barrier instruction, and then perform the operations indicated by the instructions after the barrier instruction.

[0048] Regarding the board, namely the first board 210a and the second board 210b, they can be, for example, a CPU, a GPU, a GPGPU, etc. Figure 3 The following specifically describes how to perform data transmission between the first board 210a and the second board 210b according to an embodiment of the present invention.

[0049] Figure 3 The flowchart of the method 300 for inter-board data transmission according to the embodiment of the present invention is shown. It should be understood that the method 300 may also include additional actions not shown and / or may omit the actions shown, and the scope of the present invention is not limited in this respect.

[0050] In step 301, the processor 205 sends a write instruction to the first board 210a.

[0051] Regarding the write instruction, it may be to instruct the first board 210a to write data to other boards except the first board 210a, such as the second board 210b, which is equivalent to instructing the first board 210a to synchronize the data thereon to the second board 210b.

[0052] In step 302, in response to receiving a write instruction, the first board 210a writes a predetermined amount of data into the second board 210b.

[0053] In step 303, the processor 205 sends a barrier instruction to the first board 210a to block the first board 210a from sending subsequent instructions to the second board 210b until it is determined that the predetermined amount of data is all written into the second board 210b.

[0054] According to an embodiment of the present invention, the barrier instruction here can be used to ensure that the first board 210a writes all the predetermined amount of data into the second board 210b, so as to avoid interference in the process of transmitting the predetermined amount of data. In other words, the barrier instruction can be used to isolate the instructions before and after it, so as to ensure that the first board 210a executes operations corresponding to other instructions after executing the operations corresponding to the write instruction, thereby ensuring the execution order of the operations corresponding to the received instructions.

[0055] In step 304, the first board 210a determines whether the predetermined amount of data is all written into the second board 210b.

[0056] Regarding determining whether all the predetermined amount of data is written into the second board 210b, the number of data actually written into the second board 210b can be compared with the number of data to be written into the second board 210b to determine whether all the data is actually written into the second board 210b. According to an embodiment of the present invention, the number of data already written into the second board 210b can be compared with the expected number of data to be written into the second board 210b by the first board 210a to determine whether all the predetermined amount of data is written into the second board 210b. The specific details will be described in detail below and will not be repeated here.

[0057] In step 305, in response to the first board 210a determining that the predetermined amount of data is all written to the second board 210b, the first board 210a sends a synchronization signal to the second board 210b to indicate that the predetermined amount of data has been all synchronized to the second board 210b.

[0058] The synchronization signal may be a signal for indicating that data synchronization has been completed. According to an embodiment of the present invention, by sending a synchronization signal to the second board 210b, it may be indicated that a predetermined amount of data to be transmitted to the second board 210b for synchronization has been written to the second board 210b.

[0059] From the scheme for data transmission between boards provided by the present invention as described above, it can be seen that the data to be transmitted for synchronization between boards and the synchronization signal to be transmitted are directly sent from the first board 210a to the second board 210b, so that the second board 210b does not need to perform remote polling as in the prior art, thereby improving the performance of data transmission; and, barrier instructions are used to ensure that all data to be transmitted are sent from the first board 210a to the second board 210b, thereby improving the accuracy of data synchronization, thereby ensuring data synchronization and order preservation between boards.

[0060] In order to better implement the scheme for data transmission between boards as described above, the present invention further provides a board, which improves and optimizes the configuration of the board to improve the performance of data transmission between boards, while ensuring data synchronization and order preservation between boards.

[0061] Figure 4 A schematic structural diagram of a board 400 according to an embodiment of the present invention is shown.

[0062] like Figure 4 As shown, the board 400 includes: at least one computing core 410 , a high bandwidth memory 420 , an atomic type accumulator 450 , and an aggregate response unit 460 .

[0063] Regarding the computing core 410, according to an embodiment of the present invention, if it is desired to synchronize the data transmission on the board 400 to another board, the computing core 410 can be configured to: receive a write instruction so that the board writes a predetermined amount of data to another board based on the write instruction; receive a barrier instruction to block the board from sending subsequent instructions to another board until it is determined that the predetermined amount of data is all written to the other board; determine whether the predetermined amount of data is all written to the other board; and send a synchronization signal to indicate that the predetermined amount of data has been fully synchronized to the other board. According to an embodiment of the present invention, the computing core 410 can also be configured to: convert the received write instruction into a corresponding write request so as to count the expected amount of data to be written to the other board by the board based on the write request. According to an embodiment of the present invention, the computing core 410 can also be configured to: poll and read the number of data that has been written to another board calculated by the atomic type accumulator 450; and in response to the number of data that has been written to another board being the same as the expected number of data to be written to another board, determine that the predetermined amount of data is all written to the other board.

[0064] Regarding the atomic type accumulator 450, according to an embodiment of the present invention, if it is desired to synchronize the data transmission on the board 400 to another board, the atomic type accumulator 450 can be configured to: receive a response returned from the other board, the response including information related to the amount of data that has been written to the other board; based on the response, calculate the amount of data that has been written to the other board; and based on the calculated amount of data that has been written to the other board, determine whether the predetermined amount of data is all written to the other board.

[0065] Regarding High Bandwidth Memory 420, similar to Figure 1 The high bandwidth memory 120 of the board 100 shown can be configured to store data and signals written to the board 400. According to an embodiment of the present invention, if it is desired to synchronize data transmission on other boards to the board 400, the high bandwidth memory 420 can be configured to: store the data written to the board 400, and generate a write response based on the data written to the board 400.

[0066] Regarding the aggregate response unit 460, according to an embodiment of the present invention, if it is desired to synchronize data transmission on other boards to the board 400, the aggregate response unit 460 may be configured to: count the source and amount of data that has been written to the board 400 based on the write response generated by the high bandwidth memory 420. Further, the aggregate response unit 460 may also be configured to: send a response to other boards to which data is transmitted, wherein the response generated by the aggregate response unit 460 may include information related to the amount of data that has been written to the board 400.

[0067] Further, similar to Figure 1The board 100 of the board 400 may further include: an on-chip network 430 and at least one connection port 440. The on-chip network 430 may be configured to communicate with Figure 1 Similar to the on-chip network 130, the connection port 440 is configured to Figure 1 The connection port 140 is similar to the connection port 140. For details, please refer to the above description of the on-chip network 130 and the connection port 140, which will not be repeated here.

[0068] It should be understood that the board 400 may further include additional modules not shown and / or the modules shown may be omitted, and the scope of the present invention is not limited in this respect.

[0069] According to an embodiment of the present invention, the computing core 410 may further include a plurality of different units so that the computing core implements all operations configured as above. For example, in some examples of the present invention, the computing core 410 may include: a computing unit and a polling unit, wherein the computing unit may include an instruction processing unit and a load storage cache (LSC) unit, and the polling unit may include an addressing unit and a counting unit.

[0070] Regarding the instruction processing unit, it can be configured to receive and / or send instructions and signals. For example, according to an embodiment of the present invention, the instruction processing unit can be configured to receive write instructions, accept barrier instructions, send synchronization signals, etc.

[0071] Regarding the load-store cache unit, it may be configured to perform instruction conversion. For example, according to an embodiment of the present invention, the load-store cache unit may be configured to: convert a received write instruction into a write request.

[0072] Regarding the addressing unit, it can be configured to poll and read the calculation result from the atomic type accumulator 450 of the board 400. In some embodiments of the present invention, the addressing unit can also be configured to read the write response generated based on the data written thereon from the high bandwidth memory 420 of the board 400. In some other embodiments of the present invention, the addressing unit can also be configured to read the synchronization signal from the high bandwidth memory 420 of the board 400.

[0073] Regarding the counting unit, it can be configured to count. For example, according to an embodiment of the present invention, the counting unit can be configured to count the number of write requests based on the write requests converted by the load storage cache unit. In some other embodiments, the counting unit can also be configured to compare the calculation result read from the atomic type accumulator 450 of the board 400 with the number of write requests counted to determine whether the data transmission between the boards is completed. In some other embodiments, the counting unit can also be configured to record the source of the transmitted data, such as which board the data comes from, which computing core, etc.

[0074] According to an embodiment of the present invention, the aggregate response unit 460 may further include multiple different units so that the aggregate response unit 460 can implement all the operations configured above. For example, in some examples of the present invention, the aggregate response unit 460 may include: an accumulation transmission unit and a response calculation unit.

[0075] Regarding the accumulation transmission unit, it can be configured to send a response to other boards that transmit data to the board 400.

[0076] Regarding the response calculation unit, it may be configured to count the source and amount of data that has been written to the board 400 .

[0077] The following will be combined Figure 5 How to realize data transmission between boards provided by the present invention is described in detail.

[0078] Figure 5 FIG. 4 shows a schematic diagram of data transmission between a first board 500a and a second board 500b, wherein the first board 500a and the second board 500b have Figure 4 The structure of the board 400 is shown in FIG. That is, the first board 500a at least includes: at least one computing core 510a, a high bandwidth memory 520a, an on-chip network 530a, at least one connection port 540a, an atomic type accumulator 550a, and an aggregate response unit 560a. Similarly, the second board 500b at least includes: at least one computing core 510b, a high bandwidth memory 520b, an on-chip network 530b, at least one connection port 540b, an atomic type accumulator 550b, and an aggregate response unit 560b.

[0079] like Figure 5 As shown, the computing core 510a of the first board 500a may further include: a computing unit 512a and a polling unit 514a, wherein the computing unit 512a may include an instruction processing unit 5122a and a load storage cache unit 5124a, and the polling unit 514a may include an addressing unit 5142a and a counting unit 5144a. Similarly, the computing core 510b of the second board 500b may further include: a computing unit 512b and a polling unit 514b, wherein the computing unit 512b may include an instruction processing unit 5122b and a load storage cache unit 5124b, and the polling unit 514b may include an addressing unit 5142b and a counting unit 5144b.

[0080] like Figure 5As shown, the aggregate response unit 560a of the first board 500a may further include: an accumulation transmission unit 562a and a response calculation unit 564a. Similarly, the aggregate response unit 560b of the second board 500b may further include: an accumulation transmission unit 562b and a response calculation unit 564b.

[0081] Taking synchronizing data transmission on the first board 500a to the second board 500b as an example, the method for inter-board data transmission according to an embodiment of the present invention may include the following steps.

[0082] Step 1: The processor sends a write instruction to the first board 500a.

[0083] According to an embodiment of the present invention, a processor may send a write instruction to an instruction processing unit 5122a in a computing unit 512a of at least one computing core 510a of a first board 500a to instruct the first board 500a to remotely send the data to be transmitted to a second board 500b.

[0084] Step 2: In response to receiving the write instruction, the first board 500a writes a predetermined amount of data into the second board 500b.

[0085] In some embodiments, the write instruction may include information related to the storage location of the data to be transmitted, so that the first board 500a can read the data to be transmitted from the appropriate location.

[0086] Regarding writing a predetermined amount of data into the second board 500b, according to an embodiment of the present invention, it may include: reading a predetermined amount of data from the high-bandwidth memory 520a of the first board 500a by at least one computing core 510a of the first board 500a; and sending the predetermined amount of data to the second board 500b via the on-chip network 530a and at least one connection port 540a of the first board 500a by at least one computing core 510a of the first board 500a, so as to write the data into the high-bandwidth memory 520b of the second board 500b via the at least one connection port 540b of the second board 500b and the on-chip network 530b of the second board 500b.

[0087] For example, in response to the instruction processing unit 5122a of the first board 500a receiving a write instruction, the instruction processing unit 5122a of the first board 500a can read a predetermined amount of data from the high-bandwidth memory 520a of the first board 500a, and then write the data into the high-bandwidth memory 520b of the second board 500b via the polling unit 514a, the on-chip network 530a, and the connection port 540a of the first board 500a and the connection port 540b and the on-chip network 530b of the second board 500b.

[0088] In the process of the first board 500a writing a predetermined amount of data into the second board 500b, according to the concept of the present invention, the first board 500a can also count the amount of data to be written into the second board 500b, so as to be used for subsequent determination whether all the data are actually written into the second board 500b.

[0089] Specifically, according to an embodiment of the present invention, regarding writing a predetermined amount of data into the second board 500b, it may also include: at least one computing core 510a of the first board 500a converting a write instruction into a corresponding write request, so as to count the expected amount of data to be written by the first board 500a to the second board 500b based on the write request.

[0090] For example, a load storage cache unit 5124a in a computing unit 512a of at least one computing core 510a of the first board 500a may convert a write instruction such as one received from an instruction processing unit 5122a into a write request, and then send the write request to a polling unit 514a of the at least one computing core 510a to record the source and expected amount of a predetermined amount of data to be written to the second board 500b.

[0091] Regarding the write request, it may be configured to include information regarding the source of the predetermined amount of data.

[0092] Regarding the source of the predetermined amount of data, it may refer to a specific unit on the board that sends the predetermined amount of data.

[0093] According to some embodiments of the present invention, the write request may include at least: an identifier of the computing core, an identifier of the computing unit, and an identifier of the instruction processing unit of the first board 500a, so as to identify which computing core, which computing unit, and which instruction processing unit of the first board 500a the data to be written into the second board 500b is issued by. In the above example, the data to be written into the second board 500b is issued by the instruction processing unit 5122a of the computing unit 512a of the computing core 510a of the first board 500a, then the write request may include at least: information related to the identifier of the computing core 510a, information related to the identifier of the computing unit 512a, and information related to the identifier of the instruction processing unit 5122a.

[0094] On this basis, the counting unit 5144a of the polling unit 514a of at least one computing core 510a of the first board 500a can then record information related to the identifier of the computing core 510a, information related to the identifier of the computing unit 512a, and information related to the identifier of the instruction processing unit 5122a based on the received write request.

[0095] In the above embodiment of the present invention, the counting unit 5144a of the first board 500a may also be configured to record the number of write requests to count the expected number of the predetermined amount of data to be written into the second board 500b.

[0096] In some embodiments, the counting unit 5144a of the first board 500a can record the source and expected number of the predetermined number of data to be written into the second board 500b in a form such as a table. It should be understood that the source and expected number of the predetermined number of data to be written into the second board 500b can also be recorded in the counting unit in other appropriate ways, and the present invention is not limited to this.

[0097] According to the inventive concept of the present invention, when data is transmitted from at least one connection port 540a of the first board 500a to at least one connection port 540b of the second board 500b, a global identifier for identifying the source of the data may be added to each piece of transmitted data.

[0098] Regarding the global identifier, it may be composed of a combination of identifiers such as the identifier of the board that sends data, the identifier of the computing core, the identifier of the computing unit, and the identifier of the instruction processing unit. For example, in some examples, the global identifier may include at least: an identifier of the board 500a, an identifier of the computing core 510a, an identifier of the computing unit 512a, and an identifier of the instruction processing unit 5122a. In some other examples, the board 500a may include multiple processor cores (e.g., a stream processor cluster (SPC)), and the computing core 510a belongs to one of the multiple stream processor clusters. In this case, the global identifier may also include: an identifier of the stream processor cluster (not shown) to which the computing core 510a belongs.

[0099] Further, according to the inventive concept of the present invention, the second board 500b may generate a write response to indicate that the data has been written.

[0100] Specifically, according to an embodiment of the present invention, regarding writing a predetermined amount of data into the second board 500b, it may also include: in response to at least part of the predetermined amount of data being written into the high-bandwidth memory 520b of the second board 500b, generating a write response by the high-bandwidth memory 520b of the second board 500b, and sending the write response to the aggregate response unit 560b of the second board 500b via the on-chip network 530b of the second board 500b; and counting the source and quantity of the data that has been written into the high-bandwidth memory 520b of the second board 500b based on the write response via the aggregate response unit 560b of the second board 500b.

[0101] Regarding the write response, it may include information related to the data source, such as a global identifier for identifying the data source. According to an embodiment of the present invention, the write response may include information related to the source of the data written to the second board 500b, i.e., a global identifier corresponding to the data written to the second board 500b.

[0102] For example, when data is written into the high-bandwidth memory 520b of the second board 500b, a write response may be generated by the high-bandwidth memory 520b to indicate that the current data has actually been written into the high-bandwidth memory 520b of the second board 500b. The write response is then sent to the response calculation unit 564b in the aggregated response unit 560b of the second board 500b via the on-chip network 530b of the second board 500b to be recorded and counted in the response calculation unit 564b based on the global identifier corresponding to the current data included in the write response.

[0103] Regarding statistics on the source and quantity of data that have been written to the high-bandwidth memory 520b of the second board 500b, according to an embodiment of the present invention, it may include: at the response calculation unit 564b in the aggregate response unit 560b, determining the source of the data corresponding to the current write response, and determining whether the response calculation unit 564b includes the same record entry as the source of the data corresponding to the current write response.

[0104] Regarding the record entry, it can be used to record information related to the source and quantity of the data. For example, each record entry can correspond to data from the same source to record the source information (such as a global identifier) ​​and quantity information of the data from the same source. According to an embodiment of the present invention, the aggregate response unit of the board may include multiple record entries. For example, Figure 5 Taking the second board 500b as an example, the response calculation unit 564b of the aggregate response unit 560b may record 32, 64 or 128 record entries, where the number of record entries included may be related to the cache space of the response calculation unit 564b, and the present invention does not impose any limitation on this.

[0105] Regarding determining the source of the data corresponding to the current write response, it can be determined by the global identifier included in the received current write response. For example, the global identifier included in the received current write response includes: the identifier of the board 500a, the identifier of the computing core 510a, the identifier of the computing unit 512a, and the identifier of the instruction processing unit 5122a, which means that the data currently written into the high bandwidth memory 520b of the second board 500b and generating the write response is sent by the instruction processing unit 5122a of the computing unit 512a of the computing core 510a of the board 500a.

[0106] According to an embodiment of the present invention, it is possible to determine whether the aggregate response unit 560b includes a record entry with the same source of data as that corresponding to the current write response by comparing data source information determined based on the global identifier included in the received current write response with data source information already recorded in the response calculation unit 564b of the aggregate response unit 560b.

[0107] If the aggregate response unit 560b includes a record entry with the same source as the data corresponding to the current write response, for example, the same global identifier is recorded in the response calculation unit 564b of the aggregate response unit 560b, it means that the data has been cached (i.e., hit), and then operations can be performed based on the cached data. Specifically, in some embodiments, in response to the aggregate response unit 560b including a record entry with the same source as the data corresponding to the current write response, an accumulation operation can be performed based on the record entry at the response calculation unit 564b of the aggregate response unit 560b to facilitate counting the number of data from the same source. For example, a response statistics counter can be configured at the response calculation unit 564b to count the number of data from the same source.

[0108] If the aggregate response unit 560b does not include a record entry with the same source as the data corresponding to the current write response, for example, the same global identifier is not recorded in the response calculation unit 564b of the aggregate response unit 560b, it means that the data is not in the cache (i.e., a miss). In this case, it is necessary to record the information related to the source of the data corresponding to the current write response in the response calculation unit 564b. According to the inventive concept of the present invention, it can be determined whether the information related to the source of the data corresponding to the current write response can be successfully recorded in the response calculation unit 564b by, for example, determining whether the response calculation unit 564b of the aggregate response unit 560b includes sufficient cache space for storing information related to the data corresponding to the current write response, such as the source and quantity of the data.

[0109] Specifically, in an embodiment of the present invention, in response to the aggregate response unit 560b not including a record entry with the same source as the data corresponding to the current write response, the aggregate response unit 560b further determines whether the response calculation unit 564b of the aggregate response unit 560b includes a cache space. If the response calculation unit 564b includes a cache space, a new record entry can be generated based on the write response at the response calculation unit 564b to record the source and quantity of the data corresponding to the current write response. That is, if the response calculation unit 564b of the aggregate response unit 560b includes a cache space, the newly generated record entry can be directly recorded therein.

[0110] However, in some other embodiments, the response calculation unit 564b does not include a cache space, that is, the current cache space of the response calculation unit 564b is full of record entries. In this case, it is necessary to replace at least one existing record entry in the aggregate response unit 564 with a newly generated record entry. For example, a new record entry can be generated based on the write response at the aggregate response unit 560b according to a least recently used (LRU) strategy to replace an existing record entry in the response calculation unit 564b, thereby recording the source and quantity of the data corresponding to the current write response in the response calculation unit 564b.

[0111] The least recently used strategy refers to eliminating the least recently used data to achieve the elimination of memory data. It should be understood that the present invention can also be based on other appropriate strategies to achieve the replacement of existing record entries with generated new record entries, which is not limited here.

[0112] In the above example, for the existing record entry replaced in the response calculation unit 564b of the second board 500b, according to an embodiment of the present invention, the information in the record entry can be returned to the board that originally sent the data corresponding to the record entry, that is, the location indicated by the data source information included in the record entry. Assuming that the data corresponding to the replaced record entry was also originally sent from the first board 500a to the second board 500b, the information in the record entry can be returned to the first board 500a. Specifically, the information in the record entry (especially the information related to the amount of data) can be sent to the first board 500a by the cumulative transmission unit 562b in the aggregate response unit 560b of the second board 500b, so that the information in the record entry is transferred to the first board 500a.

[0113] According to some other embodiments of the present invention, at predetermined intervals, the accumulative transmission unit 562b in the aggregated response unit 560b of the second board 500b may send information in all record entries in the response calculation unit 564b to the respective corresponding boards, for example, at least information related to the amount of data in all record entries may be sent to the high-bandwidth memory of the corresponding board, and then the information related to the amount of data in the record entries may be cleared.

[0114] Based on the above embodiment, the second board 500b can return the number of data from the first board 500a that has been written into its high bandwidth memory 520b to the first board 500a, so that the first board 500a can subsequently determine whether the predetermined number of data is all written into the second board 500b. In some embodiments, the first board 500a can include an atomic type accumulator 550a, which is used to count the number of data sent by the first board 500a and written into other boards (such as the second board 500b) at the first board 500a, so as to determine whether the predetermined number of data is all written into the second board 500b by the first board 500a based on the calculation result of the atomic type accumulator 550a. This will be described in detail in step 4 below, and will not be repeated here.

[0115] Step 3: The processor sends a barrier instruction to the first board 500a to prevent the first board 500a from sending subsequent instructions to the second board 500b.

[0116] According to an embodiment of the present invention, after all write instructions are sent, the processor may then send a barrier instruction to the instruction processing unit 5122a in the computing unit 512a of at least one computing core 510a of the first board 500a to block the instruction processing unit 5122a of the first board 500a from continuing to send instructions.

[0117] Step 4: The first board 500a determines whether all the predetermined amount of data is written into the second board 500b.

[0118] Regarding determining whether the predetermined amount of data is all written to the second board 500b, as described above, it can be determined by, for example, comparing the amount of data already written to the second board 500b with the expected amount of data to be written from the first board 500a to the second board 500b.

[0119] Specifically, according to some embodiments of the present invention, determining whether a predetermined amount of data is all written into the second board 500b may include: receiving, by the atomic type accumulator 550a of the first board 500a, a response returned from the second board 500b, the response may include information related to the amount of data that has been written into the second board 500b; based on the response, calculating, by the atomic type accumulator 550a of the first board 500a, the amount of data that has been written into the second board 500b; and determining, by the first board 500a, whether the predetermined amount of data is all written into the second board 500a, based on the calculated amount of data that has been written into the second board 500b.

[0120] For example, in an embodiment of the present invention, the atomic type accumulator 550a of the first blade 500a may receive a response returned from the accumulation transmission unit 562b in the aggregate response unit 560b of the second blade 500b. According to the inventive concept of the present invention, the response returned by the second blade 500b may at least include: the information of the record entry related to the data sent from the first blade 500a to the second blade 500b recorded in the response calculation unit 564b of the aggregate response unit 560b of the second blade 500b as described above. That is, the "response" here at least includes information related to the amount of data from the first blade 500a and written to the second blade 500b. In an embodiment of the present invention, based on the received response from the second blade 500b, the atomic type accumulator 550a of the first blade 500a may then calculate the amount of data that has come from the first blade 500a and written to the second blade 500b.

[0121] Further, according to some embodiments of the present invention, the calculation result of the atomic type accumulator 550a of the first board 500a can be polled by at least one computing core 510a of the first board 500a, such as a polling unit 5142a, wherein the calculation result may include the amount of data that has been written to the second board 500b.

[0122] On this basis, the first board 500a can then compare the number of data that has been written into the second board 500b with the expected number of data to be written into the second board 500b recorded in its counting unit 5124a, so as to determine whether the predetermined number of data has been written into the second board 500b. Specifically, according to an embodiment of the present invention, if the number of data that has been written into the second board 500b is the same as the expected number of data to be written into the second board 500b, that is, the value of the number of data that has been written into the second board 500b included in the calculation result of the atomic type accumulator 550a read by the polling unit 512a of the first board 500a is the same as the value of the expected number of data to be written into the second board 500b recorded in the polling unit 512a of the first board 500a, then it can be determined that the predetermined number of data has been written into the second board 500b.

[0123] For example, in some embodiments of the present invention, in response to the instruction processing unit 5122a of the first board 500a receiving the barrier instruction, the addressing unit 5142a of the polling unit 514a of the computing core 510a of the first board 500a can poll the atomic type accumulator 550a of the first board 500a to read the number of data written to the second board 500b calculated therein, and compare the number of data written to the second board 500b read therein with the expected number of data to be written to the second board 500b recorded in the counting unit 5124a of the polling unit 514a of the first board 500a. If the number of data written to the second board 500b read therein is the same as the expected number of data to be written to the second board 500b recorded therein, it can be determined that the predetermined number of data sent by the first board 500a has been written to the second board 500b, so that the second board 500b can subsequently read and consume the data.

[0124] Step 5: In response to the first board 500a determining that the predetermined amount of data is all written to the second board 500b, the first board 500a sends a synchronization signal to the second board 500b to indicate that the predetermined amount of data has been all synchronized to the second board 500b.

[0125] For example, in response to the polling unit 514a of the computing core 510a of the first board 500a determining that the predetermined amount of data is all written to the second board 500b, the polling unit 514a may send an instruction to the computing unit 512a of the computing core 510a, such as the instruction processing unit 5122a in the computing unit 512a, to instruct the instruction processing unit 5122a of the first board 500a to continue processing the instructions after the barrier instruction. In an embodiment of the present invention, the instructions after the barrier instruction may include: an instruction to instruct the first board 500a to send a synchronization signal to the second board 500b.

[0126] According to an embodiment of the present invention, the instruction processing unit 5122a in the computing unit 512a of at least one computing core 510a of the first board 500a can then send a synchronization signal to the high bandwidth memory 520b of the second board 500b to indicate that a predetermined amount of data on the first board 500a has been fully synchronized to the second board 500b.

[0127] In the above embodiment, the polling unit 514b in the second board 500b, such as in the at least one computing core 510b, can poll and read the synchronization signal from the high bandwidth memory 520b of the second board 500b until the synchronization signal is read. In response to the polling unit 514b of the second board 500b reading the synchronization signal, the data written by the first board 500a in the high bandwidth memory 520b can then be read and consumed by the second board 500b, such as in the at least one computing core 510b.

[0128] As can be seen from the above, according to the scheme for data transmission between boards according to the embodiment of the present invention, the predetermined amount of data to be transmitted by the first board 500a to be synchronized to the second board 500b can be directly remotely written by the first board 500a to the second board 500b, and then the second board 500b performs local polling data reading and consumption, thereby avoiding the second board 500b from performing remote polling, thereby improving the performance of data transmission. Secondly, by writing a barrier instruction to the first board 500a, it can be ensured that the operations related to the instruction of writing the predetermined amount of data on the first board 500a to the second board 500b before the barrier instruction are completely completed, and then the operations indicated by the subsequent instructions are performed, such as instructing the first board 500a to send a synchronization signal to the second board 500b, thereby ensuring the accuracy of data synchronization between boards.

[0129] According to the inventive concept of the present invention, the above scheme for data transmission between boards can also be applied to data transmission between multiple boards, including one-to-many, many-to-one, many-to-many, etc. Figure 5 The description is not repeated here.

[0130] Figure 6 The block diagram of a computing device 800 suitable for implementing an embodiment of the present invention is schematically shown. The device 600 may be a computer program product for implementing an embodiment of the present invention. Figure 3 The method 300 is shown in the apparatus. Figure 6 As shown, the device 600 includes a processing unit 601 (e.g., a central processing unit (CPU)), which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 602 or computer program instructions loaded from a storage unit 608 to a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the device 600 can also be stored. The processing unit 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0131] Multiple components in the device 600 are connected to the I / O interface 605, including: an input unit 606, an output unit 607, and a storage unit 608. The processing unit 601 performs the various methods and processes described above, such as performing the method 300. For example, in some embodiments, the method 300 can be implemented as a computer software program, which is stored in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the processing unit 601, one or more operations in the method 300 described above can be performed. Alternatively, in other embodiments, the processing unit 601 can be configured to perform one or more actions of the method 300 in any other appropriate manner (for example, by means of firmware).

[0132] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0133] The computer program instructions for performing the operation of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect through the Internet). In some embodiments, by using the state information of the computer-readable program instructions to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit may execute the computer-readable program instructions, thereby implementing various aspects of the present invention.

[0134] These computer-readable program instructions can be provided to a processor in a voice interaction device, a general-purpose computer, a special-purpose computer, or a processing unit of other programmable data processing devices, thereby producing a machine, so that when these instructions are executed by the processing unit of a computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other device to work in a specific manner.

[0135] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0136] The above are only optional embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for data transmission between boards, characterized in that: include: Sending a write instruction to the first board; In response to receiving the write instruction, the first board writes a predetermined amount of data into the second board, wherein the connection port of the first board is connected to the connection port of the second board so that the predetermined amount of data is written into the second board by the first board via the connection port of the first board and the connection port of the second board; Sending a barrier instruction to the first board to prevent the first board from sending subsequent instructions to the second board until it is determined that the predetermined amount of data is all written to the second board; comparing, at the first board, the amount of data already written into the second board with the amount of data to be written into the second board by the first board, so as to determine, by the first board, whether all of the predetermined amount of data has been written into the second board; and In response to the first board determining that the predetermined amount of data is all written to the second board, the first board directly sends a synchronization signal to the second board to indicate that the predetermined amount of data has been all synchronized to the second board, Wherein, determining by the first board whether all the predetermined amount of data is written into the second board includes: The atomic type accumulator of the first board receives a response returned from the aggregate response unit of the second board, wherein the aggregate response unit is configured to count the source and amount of data that has been written into the high bandwidth memory of the second board, calculating, by the atomic type accumulator of the first board based on the response, the amount of data that has been written to the second board, and The atomic type accumulator of the first board is read by at least one computing core of the first board in a polling manner to determine whether the predetermined amount of data is all written into the second board.

2. The method according to claim 1, characterized in that: Writing a predetermined amount of data into the second board by the first board includes: The write instruction is converted into a corresponding write request by at least one computing core of the first board, so as to count the expected amount of data to be written by the first board to the second board based on the write request.

3. The method according to claim 2, characterized in that The write request includes information about a source of the predetermined amount of data.

4. The method according to claim 2, characterized in that: Determining by the first board whether all of the predetermined amount of data is written into the second board includes: receiving, by the atomic type accumulator of the first blade, a response returned from the second blade, the response including information related to the amount of data that has been written to the second blade; Based on the response, calculating the amount of data that has been written to the second blade; and Based on the calculated amount of data that has been written into the second board, it is determined whether the predetermined amount of data is all written into the second board.

5. The method according to claim 4, characterized in that Determining whether the predetermined amount of data is all written into the second board includes: The number of data written into the second board is calculated by reading the atomic type accumulator of the first board by at least one computing core of the first board in a polling manner; and In response to the amount of data already written to the second board being the same as the expected amount of data to be written to the second board, it is determined that the predetermined amount of data is all written to the second board.

6. The method according to claim 1 or 2, characterized in that Writing a predetermined amount of data into the second board by the first board includes: Reading the predetermined amount of data from the high bandwidth memory of the first board by at least one computing core of the first board; and The predetermined amount of data is sent to the second board via the on-chip network and at least one connection port of the first board, so as to be written into the high-bandwidth memory of the second board via at least one connection port of the second board and the on-chip network of the second board.

7. The method according to claim 6, characterized in that Writing a predetermined amount of data into the second board by the first board also includes: In response to at least part of the predetermined amount of data being written into the high bandwidth memory of the second board, generating a write response by the high bandwidth memory of the second board, and sending the write response to the aggregated response unit of the second board via the on-chip network of the second board; and The aggregate response unit of the second board is used to count the source and quantity of the data written into the high-bandwidth memory of the second board based on the write response.

8. The method according to claim 7, characterized in that The write response includes information about the source of the data written to the second blade, and Counting the sources and quantity of data written into the high bandwidth memory of the second board includes: Determine the source of data corresponding to the current write response; determining whether the aggregate response unit includes a record entry having the same source as data corresponding to the current write response; and In response to the aggregate response unit including a record entry having a same source as the data corresponding to the current write response, an accumulation operation is performed based on the record entry to count the amount of data having the same source.

9. The method according to claim 8, characterized in that Counting the source and quantity of the data written into the high bandwidth memory of the second board also includes: In response to the aggregate response unit not including a record entry having the same source as the data corresponding to the current write response, determining whether the aggregate response unit includes cache space; In response to the aggregate response unit including a cache space, generating a new record entry based on the write response to record the source and amount of data corresponding to the current write response; and In response to the aggregate response unit not including cache space, a new record entry is generated based on the write response according to a least recently used policy to replace an existing record entry, and the source and quantity of data corresponding to the current write response are recorded.

10. The method according to claim 7, characterized in that Also includes: The aggregate response unit of the second blade sends a response to the first blade so that the first blade determines whether the predetermined amount of data is all written to the second blade based on the response, wherein the response includes information related to the amount of data that has been written to the second blade.

11. A board, characterized in that: include: At least one computing core, wherein the at least one computing core is configured to: receiving a write instruction so that the board writes a predetermined amount of data into another board based on the write instruction, wherein a connection port of the board is connected to a connection port of the other board so that the predetermined amount of data is written by the board into the other board via the connection port of the board and the connection port of the other board; receiving a barrier instruction to block the board from sending subsequent instructions to the other board until it is determined that the predetermined amount of data is all written into the other board; comparing the amount of data already written to the other board with the amount of data to be written to the other board to determine whether the predetermined amount of data is all written to the other board; and Sending a synchronization signal to the other board to indicate that the predetermined amount of data has been fully synchronized to the other board; and Atomic accumulators are configured as: receiving a response returned from the aggregate response unit of the other board, wherein the aggregate response unit is configured to count the source and amount of data that has been written into the high bandwidth memory of the other board; and Based on the response, calculating the amount of data that has been written to the other board; Wherein, determining whether the predetermined amount of data is all written into the other board comprises: The at least one computing core reads the atomic type accumulator in a polling manner to determine whether the predetermined amount of data is all written into the other board.

12. The board according to claim 11, characterized in that: The at least one computing core is further configured to: The received write instruction is converted into a corresponding write request, so as to count the expected amount of data to be written by the board to the other board based on the write request.

13. The board according to claim 12, characterized in that: The atomic type accumulator is configured as: receiving a response back from the other blade, the response including information about the amount of data that has been written to the other blade; Based on the response, calculating the amount of data that has been written to the other board; as well as Based on the calculated amount of data that has been written to the other board, it is determined whether the predetermined amount of data is all written to the other board.

14. The board according to claim 13, characterized in that: The at least one computing core is further configured to: polling and reading the amount of data written into the other board calculated by the atomic type accumulator; and In response to the amount of data already written to the other board being the same as the expected amount of data to be written to the other board, it is determined that the predetermined amount of data is all written to the other board.

15. The board according to claim 11, characterized in that: Also includes: a high bandwidth memory configured to store data written to the board and to generate a write response based on the data written to the board; as well as The aggregate response unit is configured to count the source and quantity of the data that has been written to the board based on the write response generated by the high bandwidth memory.

16. The board according to claim 15, characterized in that: The aggregate response unit is further configured to: A reply is sent, the reply comprising information about the amount of data that has been written to the board.

17. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 10.

18. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to make a computer execute the method according to any one of claims 1 to 10.

19. A computer program product, characterized in that The computer program product is tangibly stored on a non-transitory computer readable medium and comprises machine executable instructions which, when executed, cause a machine to perform the steps of the method according to any one of claims 1-10.

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