Expression method, system, electronic device and storage medium of multiplexer

Abstract

The present invention provides a method, system, electronic device and storage medium for expressing a multiplexer, and relates to the field of electronic design technology. The method includes obtaining register transfer level design information of the multiplexer; analyzing the register transfer level design information to obtain signal state information and data channel information of the multiplexer; grouping the data channels of the multiplexer according to the data channel information to obtain priority group information; configuring an operator according to the signal state information and the priority group information, and setting an operator port; connecting an external signal to the operator port to drive the operator to express the multiplexer. The present invention records the selection signal and priority information of the data in the expression operator, effectively saves memory, retains complete multiplexer circuit information, makes the optimization of the multiplexer circuit more flexible in the middle and late stages, and obtains a priority decoding structure that is more suitable for the current timing context.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design, and in particular to an expression method, system, electronic equipment and storage medium of a multiplexer. Background Art

[0002] A MUX (Multiplexer) circuit is an electronic circuit that has multiple data input channels and uses a set of control signals to determine which input channel's data can pass through to a single output line. MUX circuits have a wide range of applications and play an important role in electronic design. By optimizing the design and implementation of MUX circuits, the performance, flexibility, and efficiency of the entire system can be significantly improved.

[0003] The expression of MUX circuit plays a very important role in the quality and efficiency of circuit optimization in the process of logic synthesis. The expression of MUX circuit needs to retain the complete MUX circuit information and should be as concise as possible. At the same time, it should be easy to apply various MUX optimization strategies in the later stage, such as optimization of irrelevant items and adjustment of implementation structure. In the current mainstream electronic design automation (EDA) tools, there are two operators commonly used to express MUX circuits, namely binary multiplexer (Binary MUX) operator and select (SELECT) operator. However, the Binary MUX operator is an internal decoding structure, and there is a large amount of data redundancy when expressing sparse multiplexers (Sparse MUX). The SELECT operator is an external decoding structure, which can effectively solve the data redundancy problem in the Binary MUX operator, but this external decoding structure cannot fully retain the information of the MUX circuit, and the implementation structure is solidified into a decoder-selector (Decoder-Selector) structure, which is difficult to perform structural optimization for timing in the later stage of optimization. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a method, system, electronic device and storage medium for expressing a multiplexer, which effectively solves the problem in the prior art that it is difficult to perform structural optimization on the timing in the later stage of optimization when expressing the multiplexer circuit.

[0005] In a first aspect, the present invention provides a method for expressing a multiplexer, the method comprising:

[0006] Obtain register transfer level design information of the multiplexer;

[0007] Analyzing the register transfer level design information to obtain signal state information and data channel information of the multiplexer;

[0008] Grouping the data channels of the multiplexer according to the data channel information to obtain priority group information;

[0009] configuring an operator according to the signal state information and the priority group information, and setting an operator port;

[0010] An external signal is connected to the operator port to drive the operator to perform the expression of the multiplexer.

[0011] Furthermore, the signal status information includes at least control signal information, output signal information, data signal information of the data channel and selection signal status of the data channel, and the data channel information includes at least the number of data channels, data channel priority relationship and data channel conflict relationship.

[0012] Further, grouping the data channels of the multiplexer according to the data channel information includes:

[0013] Sorting the plurality of data channels of the multiplexer according to the data channel priority relationship;

[0014] The data channels with default branches are divided into the lowest priority group, and the data channels with the highest priority are divided into the highest priority group;

[0015] Traversing the ungrouped data channels in sequence, and determining the data channel conflict relationship between the ungrouped data channels and the data channel with the highest priority;

[0016] If there is at least one first data channel that does not conflict with the data channel with the highest priority, classifying at least one first data channel into the highest priority group;

[0017] If there is at least one second data channel that conflicts with the data channel with the highest priority, at least one second data channel is further divided into priority groups according to the data channel priority relationship and the data channel conflict relationship until all the data channels are divided into different priority groups.

[0018] Further, the operator is a sparse selector operator, and configuring the operator according to the signal state information and the priority group information includes:

[0019] matching the data channels of the multiplexer according to the data ports of the sparse selector operator;

[0020] The selection signal state of the data channel and the priority group information are recorded to the corresponding data port.

[0021] Furthermore, the external signal includes a first control signal and a first data signal, and the step of connecting the external signal to the operator port to drive the operator to perform the expression of the multiplexer includes:

[0022] Inputting the first control signal drives the control port of the sparse selector operator;

[0023] Inputting the first data signal drives the data port of the sparse selector operator;

[0024] The output port of the sparse selector operator is driven to output a target signal.

[0025] Further, the operator is a sparse decoder operator, and configuring the operator according to the signal state information and the priority group information includes:

[0026] matching the data channels of the multiplexer according to the output ports of the sparse decoder operator;

[0027] The selection signal state of the data channel and the priority group information are recorded to the corresponding output port.

[0028] Furthermore, the external signal includes a second control signal and a second data signal, and the step of connecting the external signal to the operator port to drive the operator to perform the expression of the multiplexer includes:

[0029] Creating a selector operator, the selector operator comprising at least a control port, a data port, and an output port;

[0030] Inputting the second data signal drives the data port of the selector operator;

[0031] Inputting the second control signal drives the control port of the sparse decoder operator;

[0032] driving a control port of the selector operator according to an output port of the sparse decoder operator;

[0033] The output port of the selector operator is driven to output a target signal.

[0034] In a second aspect, the present invention provides an expression system of a multiplexer, the system comprising:

[0035] An information acquisition module, used for acquiring register transfer level design information of the multiplexer;

[0036] An information analysis module, used for analyzing the register transfer level design information to obtain the signal state information and data channel information of the multiplexer;

[0037] A channel grouping module, used for grouping the data channels of the multiplexer according to the data channel information to obtain priority group information;

[0038] An operator configuration module, configured to configure an operator according to the signal state information and the priority group information, and to set an operator port;

[0039] The selector expression module is used to connect the external signal to the operator port and drive the operator to express the multiplexer.

[0040] In a third aspect, the present invention provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method for expressing a multiplexer as described in the first aspect of the present invention.

[0041] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method for expressing a multiplexer as described in the first aspect of the present invention.

[0042] The expression method, system, electronic device and storage medium of the multiplexer provided by the present invention do not rely on the full expansion of the control signal or the early decoding of the selection signal, but record the selection signal of the data in the expression operator, so that the design of the multiplexer is more concise and easy to understand, and better performance and resource utilization are obtained during implementation, effectively saving memory. At the same time, the priority information is fully recorded in the expression operator, and the complete multiplexer circuit information is retained, making the optimization of the multiplexer circuit more flexible in the middle and late stages. Based on the goal of timing optimization, the implementation structure of the multiplexer circuit can be freely selected, and the implementation of priority decoding can be postponed to obtain a priority decoding structure that is more suitable for the current timing context. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 This is a first schematic diagram of the expression method flow of a multiplexer provided by an embodiment of the present invention;

[0045] Figure 2 is a second schematic diagram of the expression method flow of the multiplexer provided by an embodiment of the present invention;

[0046] Figure 3 is a third schematic diagram of the expression method flow of a multiplexer provided in an embodiment of the present invention;

[0047] Figure 4 is a fourth schematic diagram of the expression method flow of a multiplexer provided by an embodiment of the present invention;

[0048] Figure 5 is a fifth schematic diagram of a method for expressing a multiplexer provided in an embodiment of the present invention;

[0049] Figure 6 is a sixth schematic diagram of the expression method flow of a multiplexer provided by an embodiment of the present invention;

[0050] Figure 7 is a schematic diagram of the structure of the expression system of the multiplexer provided in an embodiment of the present invention;

[0051] Figure 8 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention.

[0052] Description of main component symbols:

[0053] 700, expression system of multiplexer; 710, information acquisition module; 720, information analysis module; 730, channel grouping module; 740, operator configuration module; 750, selector expression module; 800, electronic device; 810, processor; 820, communication interface; 830, memory; 840, communication bus. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be further clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be noted that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0057] The MUX circuit is closely related to statements such as if else, variable index, case / casex / casez, etc. in register transfer level design. The MUX circuit usually has multiple control signals and multiple data channels. The data channel selected at a certain moment is determined by the state of the control signal. According to the ratio between the number of data channels N and the number of control signals s in the MUX circuit, the MUX can be divided into dense selectors (Dense MUX) and sparse selectors (Sparse MUX). Specifically, the sparsity of MUX is defined as N / 2 s , given a sparsity threshold p less than 1, when the sparsity is less than the sparsity threshold p, the MUX is SparseMUX, otherwise it is Dense MUX. When N=2 s , that is, N / 2 s =1, it can also be called a binary multiplexer Binary MUX, indicating that each state of the control signal corresponds to a data channel. At the same time, depending on whether the control signal has priority, the MUX circuit can be divided into a parallel MUX and a priority MUX. When there is no conflict in the selection signal states of each data path of the MUX circuit, it is a Parallel MUX. When there is a conflict in the control signal states of each data path of the MUX circuit, it is a Priority MUX. Therefore, when the control signal state can match the selection signals of multiple data paths, a data channel with a higher priority should be selected. According to the implementation structure of MUX, the MUX circuit can also be divided into two categories, namely the multiplexer tree structure and the decoder-selector structure.

[0058] The expression of MUX circuit plays a very important role in the quality and efficiency of circuit optimization in the process of logic synthesis. The expression of MUX circuit needs to retain the complete MUX circuit information and should be as concise as possible. At the same time, it should be easy to apply various MUX optimization strategies in the later stage, such as optimization of irrelevant items and adjustment of implementation structure. In the current mainstream electronic design automation (EDA) tools, there are two operators commonly used to express MUX circuits, namely, binary multiplexer (Binary MUX) operator and select (SELECT) operator. However, the Binary MUX operator is an internal decoding structure, and its input port includes the control signal and the data input signal corresponding to its fully expanded state. This expression is suitable for expressing Dense MUX with a small bit width, while the effective data channel of Sparse MUX is often much smaller than the number of fully expanded states of the control signal. The Binary MUX operator has a lot of data redundancy problems when expressing Sparse MUX. The SELECT operator is an external decoding structure. Different from the full decoding of the Binary MUX, the SELECT operator only decodes the selection signal status of the valid data channel, which can effectively solve the data redundancy problem in the Binary MUX operator. However, this external decoding structure cannot completely retain the information of the MUX circuit, and the implementation structure is solidified into a decoder-selector structure, which makes it difficult to perform structural optimization for timing in the later stage of optimization.

[0059] Example 1

[0060] The embodiment of the present invention provides a method for expressing a multiplexer, which effectively solves the problem in the prior art that it is difficult to perform structural optimization on the timing in the later stage of optimization when expressing the multiplexer circuit. Figure 1 is a first schematic diagram of the expression method flow of the multiplexer provided by an embodiment of the present invention, such as Figure 1 As shown, the method comprises the following steps:

[0061] S100. Obtain register transfer level design information of a multiplexer.

[0062] In register transfer level design, multiplexers can selectively read data from multiple registers or write data to specified registers according to control signals. MUX circuits are closely related to statements such as if else, variable index, case / casex / casez, etc. in register transfer level design. These statements are used to describe data selection, branching and conditional logic in register transfer level design, and MUX circuits are an effective way to implement these logics.

[0063] S200, analyzing register transfer level design information to obtain signal state information and data channel information of the multiplexer.

[0064] In an embodiment of the present invention, the signal status information includes at least control signal information, output signal information, data signal information of the data channel and selection signal status of the data channel, and the data channel information includes at least the number of data channels, data channel priority relationship and data channel conflict relationship.

[0065] Exemplarily, if the register transfer level design information of the multiplexer circuit is a casez statement, for example:

[0066]

[0067] According to the analysis of the above casez statement, the control signal of the multiplexer circuit is sel, the output signal is the result signal, the data signal is the data signal assigned to result in each case branch, and the number of output channels is the number of branches of the casez statement. The selection signal status corresponding to the data channel of the casez statement has been written in the casez statement. The default branch indicates that the selection signal of this branch is the fully expanded signal set excluding all selection signals of other branches. The default branch does not need to list the selection signal status.

[0068] Exemplarily, if the register transfer level design information of the multiplexer circuit is an if-else statement, for example:

[0069]

[0070] According to the above if-else statement analysis, the control signals are S0, S1 and S2, the output signal is out, there are four data channels, and the corresponding data signals are a, b, c, and d. The selection signal state of signal a is S0=1, S1 and S2 can be any value, that is, S2S1S0=??1. Similarly, the selection states of signals b, c and d are , and default.

[0071] The data channel priority relationship and the data channel conflict relationship can be obtained by analyzing the selection signal states corresponding to the data signals of the data channels.

[0072] S300 , grouping data channels of the multiplexer according to the data channel information to obtain priority group information.

[0073] The data channels of the multiplexer are grouped according to the data channel priority relationship and data channel conflict relationship in the data channel information. Figure 2is a second schematic diagram of the expression method flow of the multiplexer provided in an embodiment of the present invention, such as Figure 2 As shown, data channel grouping includes the following steps:

[0074] S310 , sorting multiple data channels of the multiplexer according to data channel priority relationships.

[0075] Optionally, if the initial state of the priority group of 5 data channels is [d1, d2, d3, d4, d5], these 5 data channels have not been grouped, and the priorities of d1-d5 are from high to low according to the data channel priority relationship.

[0076] S320: Divide the data channel with the default branch into the lowest priority group, and divide the data channel with the highest priority into the highest priority group.

[0077] In the embodiment of the present invention, the default branch refers to the default branch. If there is a default branch, it is divided into a separate priority group with the lowest priority. For example, if d5 is the default branch, the priority group state becomes [d1, d2, d3, d4, [d5]]. The data channel with the highest priority is divided into the highest priority group, and the priority group state becomes [[d1], d2, d3, d4, [d5]].

[0078] S330 , traverse the ungrouped data channels in sequence, and determine the data channel conflict relationship between the ungrouped data channels and the data channel with the highest priority.

[0079] The remaining ungrouped data channels are traversed in sequence, and searching forward from the position of the current data channel is performed to determine the data channel conflict relationship between data channels d2, d3 and d4 and the data channel d1 with the highest priority.

[0080] S340: If there is at least one first data channel that does not conflict with the data channel with the highest priority, classify the at least one first data channel into the highest priority group.

[0081] Assuming that data channels d2 and d3 conflict with data channel d1, and data channel d4 has no conflict with data channel d1, d2, and d3, data channel d4 can be placed in the highest priority group, and the priority group status of the data channel is updated to [[d1, d4], d2, d3, [d5]].

[0082] S350: If there is at least one second data channel that conflicts with the data channel with the highest priority, the at least one second data channel is further divided into priority groups according to the data channel priority relationship and the data channel conflict relationship until all the data channels are divided into different priority groups.

[0083] Since data channels d2 and d3 conflict with data channel d1, data channels d2 and d3 are further divided into priority groups according to the data channel priority relationship and data channel conflict relationship. If data channels d2 and d3 do not conflict, the priority group status of the data channels is updated to [[d1, d4], [d2, d3], [d5]]; if data channels d2 and d3 conflict, the priority group status of the data channels is updated to [[d1, d4], [d2], [d3], [d5]].

[0084] S400: Configure an operator according to the signal status information and the priority group information, and set the operator port.

[0085] In the embodiment of the present invention, the operator includes a sparse selector operator and a sparse decoder operator. If the sparse selector operator is used to express the multiplexer, Figure 3 3 is a third schematic diagram of the expression method flow of a multi-way selector provided in an embodiment of the present invention. The configuration of the sparse selector operator includes the following steps:

[0086] S401 . Match the data channels of the multiplexer according to the data ports of the sparse selector operator.

[0087] The data ports of the sparse selector operator Sparse MUX are matched with the data channels analyzed in the multiplexer circuit.

[0088] S402: Record the selection signal status and priority group information of the data channel to the corresponding data port.

[0089] The selection signal state refers to the selection signal state required to select the current data channel. For example, in the above casez statement, the selection signal state required to select data0 is 00000. Therefore, this information should be stored in the data port of its corresponding Sparse MUX.

[0090] The priority group information refers to the priority group number corresponding to the current data channel. The smaller the priority group number, the higher the priority. Because the selection signals on different data channels often conflict, suppose the selection signal of data0 is 0000 and the selection signal of data1 is (including 0000 and 0001), at this time, the selection signals of data0 and data1 conflict, and it is necessary to decide which data channel to select based on the priority group. Assuming that the priority group number of data0 is 0 and the priority group number of data1 is 1, then when the selection signal is 0000, data0 with a higher priority should be selected.

[0091] If the multiplexer is expressed using a sparse decoder operator, Figure 4 4 is a schematic diagram of a method for expressing a multiplexer provided by an embodiment of the present invention. The configuration of a sparse decoder operator includes the following steps:

[0092] S410 , matching data channels of a multiplexer according to output ports of the sparse decoder operator.

[0093] The data port of the sparse decoder operator Sparse Decoder is matched with the data channel analyzed in the multiplexer circuit.

[0094] S420, recording the selection signal status and priority group information of the data channel to the corresponding output port.

[0095] In the Sparse Decoder operator, the selection signal state and priority group information are recorded at the output port. Optionally, the selection signal state and priority group information may also be recorded at other places of the operator in other forms, such as in a matrix form in the operator module.

[0096] S500, connecting the external signal to the operator port to drive the operator to express the multiplexer.

[0097] If a sparse selector operator is used to express a multiplexer, the external signal includes a first control signal and a first data signal. Figure 5 5 is a fifth schematic diagram of the expression method flow of the multiplexer provided in an embodiment of the present invention. Figure 5 As shown, driving the sparse selector operator to express a multiplexer includes the following steps:

[0098] S501, input a first control signal to drive a control port of a sparse selector operator;

[0099] S502, input a first data signal to drive a data port of a sparse selector operator;

[0100] S503 , driving the output port of the sparse selector operator to output a target signal.

[0101] If the multiplexer is expressed using a sparse decoder operator, the external signal includes a second control signal and a second data signal, Figure 6 6 is a sixth schematic diagram of the expression method flow of the multiplexer provided in an embodiment of the present invention. Figure 6 As shown, the expression of driving the sparse decoder operator to perform a multiplexer includes the following steps:

[0102] S510, creating a selector operator, where the selector operator at least includes a control port, a data port, and an output port;

[0103] S520, input a second data signal to drive a data port of a selector operator;

[0104] S530, input a second control signal to drive a control port of a sparse decoder operator;

[0105] S540, driving the control port of the selector operator according to the output port of the sparse decoder operator;

[0106] S550, drive the output port of the selector operator to output the target signal.

[0107] In the embodiment of the present invention, the structure of the Sparse MUX operator can be converted to the structure of the Sparse Decoder operator, mainly through the following steps:

[0108] First, disconnect the original structure from the control signal, data signal, and output signal. Then generate a new structure based on the original structure: the Sparse MUX operator is disassembled into the Sparse Decoder operator and the Selector operator, or the Sparse Decoder operator is merged into the Sparse MUX operator. The control port of the Sparse Decoder operator corresponds to the control port of the Sparse MUX operator, the number of output ports of the Sparse Decoder operator, the number of data channels of the Selector operator, and the number of control ports of the Selector operator are the same as the number of data channels of the Sparse MUX operator, and the information stored in the data port of the Sparse MUX operator should be consistent with the information stored on the output port of the Sparse Deocder operator. Finally, connect the ports of the new structure to the control signal, data signal, and output signal in the circuit.

[0109] The expression method of the multiplexer provided in the embodiment of the present invention does not rely on the full expansion of the control signal or the early decoding of the selection signal, but records the selection signal of the data in the expression operator, so that the design of the multiplexer is more concise and easy to understand, and better performance and resource utilization are obtained during implementation, effectively saving memory. At the same time, the priority information is fully recorded in the expression operator, and the complete multiplexer circuit information is retained, making the optimization of the multiplexer circuit more flexible in the middle and later stages.

[0110] Example 2

[0111] Based on the same technical concept as the method embodiment of the above embodiment 1, the embodiment of the present invention provides an expression system of a multiplexer, Figure 7is a schematic diagram of the structure of the expression system of the multiplexer provided in an embodiment of the present invention, such as Figure 7 As shown, the expression system 700 of the multiplexer includes:

[0112] An information acquisition module 710, used to acquire register transfer level design information of a multiplexer;

[0113] An information analysis module 720, used to analyze register transfer level design information to obtain signal state information and data channel information of the multiplexer;

[0114] The channel grouping module 730 is used to group the data channels of the multiplexer according to the data channel information to obtain priority group information;

[0115] An operator configuration module 740, configured to configure an operator according to the signal state information and the priority group information, and to set an operator port;

[0116] The selector expression module 750 is used to connect the external signal to the operator port and drive the operator to express the multiplexer.

[0117] The multiplexer expression system provided by the embodiment of the present invention can freely select the implementation structure of the multiplexer circuit based on the goal of timing optimization, and can also postpone the implementation of priority decoding to obtain a priority decoding structure that is more suitable for the current timing context.

[0118] It can be understood that the implementation method of the expression method of the multiplexer described in the above embodiment 1 is also applicable to this embodiment and can achieve the same technical effect, so it will not be repeated here.

[0119] Example 3

[0120] Based on the same concept, an embodiment of the present invention further provides an electronic device, Figure 8 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention, such as Figure 8 As shown, the electronic device 800 may include: a processor 810, a communication interface 820, a memory 830 and a communication bus 840, wherein the processor 810, the communication interface 820, and the memory 830 communicate with each other through the communication bus 840. The processor 810 may call the logic instructions in the memory 830 to execute the steps of the expression method of the multiplexer as described in the above embodiments. For example, it includes:

[0121] S100. Obtain register transfer level design information of a multiplexer.

[0122] S200, analyzing register transfer level design information to obtain signal state information and data channel information of the multiplexer;

[0123] S300, grouping the data channels of the multiplexer according to the data channel information to obtain priority group information;

[0124] S400, configuring an operator according to the signal state information and the priority group information, and setting the operator port;

[0125] S500, connecting the external signal to the operator port to drive the operator to express the multiplexer.

[0126] The processor 810 may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips.

[0127] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0128] The memory 830 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0129] Example 4

[0130] Based on the same concept, an embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program, and the computer program includes at least one code segment, which can be executed by a main control device to control the main control device to implement the steps of the expression method of the multiplexer described in the above embodiments. For example, it includes:

[0131] S100. Obtain register transfer level design information of a multiplexer.

[0132] S200, analyzing register transfer level design information to obtain signal state information and data channel information of the multiplexer;

[0133] S300, grouping the data channels of the multiplexer according to the data channel information to obtain priority group information;

[0134] S400, configuring an operator according to the signal state information and the priority group information, and setting the operator port;

[0135] S500, connecting the external signal to the operator port to drive the operator to express the multiplexer.

[0136] Based on the same technical concept, an embodiment of the present invention further provides a computer program, which is used to implement the above method embodiment when executed by a main control device.

[0137] The computer program may be stored in whole or in part on a computer-readable storage medium packaged with the processor, or may be stored in whole or in part on a memory not packaged with the processor.

[0138] Based on the same technical concept, an embodiment of the present invention further provides a processor, which is used to implement the above method embodiment. The above processor can be a chip.

[0139] In summary, the expression method, system, electronic device and storage medium of the multiplexer provided by the present invention do not rely on the full expansion of the control signal or the early decoding of the selection signal, but record the selection signal of the data in the expression operator, so that the design of the multiplexer is more concise and easy to understand, and better performance and resource utilization are obtained during implementation, which effectively saves memory. At the same time, the priority information is completely recorded in the expression operator, and the complete multiplexer circuit information is retained, making the optimization of the multiplexer circuit more flexible in the middle and late stages. Based on the goal of timing optimization, the implementation structure of the multiplexer circuit can be freely selected, and the implementation of priority decoding can be postponed to obtain a priority decoding structure that is more suitable for the current timing context.

[0140] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0141] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for expressing a multiplexer, characterized in that: The method comprises: Obtain register transfer level design information of the multiplexer; Analyzing the register transfer level design information to obtain signal state information and data channel information of the multiplexer; Grouping the data channels of the multiplexer according to the data channel information to obtain priority group information; configuring an operator according to the signal state information and the priority group information, and setting an operator port; Connecting an external signal to the operator port to drive the operator to perform the expression of the multiplexer; The signal status information at least includes control signal information, output signal information, data signal information of data channels and selection signal status of data channels, and the data channel information at least includes the number of data channels, data channel priority relationship and data channel conflict relationship; The grouping of the data channels of the multiplexer according to the data channel information includes: Sorting the plurality of data channels of the multiplexer according to the data channel priority relationship; The data channels with default branches are divided into the lowest priority group, and the data channels with the highest priority are divided into the highest priority group; Traversing the ungrouped data channels in sequence, and determining the data channel conflict relationship between the ungrouped data channels and the data channel with the highest priority; If there is at least one first data channel that does not conflict with the data channel with the highest priority, classifying at least one first data channel into the highest priority group; If there is at least one second data channel that conflicts with the data channel with the highest priority, at least one second data channel is further divided into priority groups according to the data channel priority relationship and the data channel conflict relationship until all the data channels are divided into different priority groups.

2. The method for expressing a multiplexer according to claim 1, characterized in that: The operator is a sparse selector operator, and configuring the operator according to the signal state information and the priority group information includes: matching the data channels of the multiplexer according to the data ports of the sparse selector operator; The selection signal state of the data channel and the priority group information are recorded to the corresponding data port.

3. The method for expressing a multiplexer according to claim 2, characterized in that: The external signal includes a first control signal and a first data signal, and the step of connecting the external signal to the operator port to drive the operator to perform the expression of the multiplexer includes: Inputting the first control signal drives the control port of the sparse selector operator; Inputting the first data signal drives the data port of the sparse selector operator; The output port of the sparse selector operator is driven to output a target signal.

4. The method for expressing a multiplexer according to claim 1, characterized in that: The operator is a sparse decoder operator, and configuring the operator according to the signal state information and the priority group information comprises: matching the data channels of the multiplexer according to the output ports of the sparse decoder operator; The selection signal state of the data channel and the priority group information are recorded to the corresponding output port.

5. The method for expressing a multiplexer according to claim 4, characterized in that: The external signal includes a second control signal and a second data signal, and the step of connecting the external signal to the operator port to drive the operator to perform the expression of the multiplexer includes: Creating a selector operator, the selector operator comprising at least a control port, a data port, and an output port; Inputting the second data signal drives the data port of the selector operator; Inputting the second control signal drives the control port of the sparse decoder operator; driving a control port of the selector operator according to an output port of the sparse decoder operator; The output port of the selector operator is driven to output a target signal.

6. A multiplexer expression system, characterized in that: The system comprises: An information acquisition module, used for acquiring register transfer level design information of the multiplexer; An information analysis module, used for analyzing the register transfer level design information to obtain the signal state information and data channel information of the multiplexer; A channel grouping module, used for grouping the data channels of the multiplexer according to the data channel information to obtain priority group information; An operator configuration module, configured to configure an operator according to the signal state information and the priority group information, and to set an operator port; A selector expression module, used for connecting an external signal to the operator port to drive the operator to perform the expression of the multiplexer; The signal status information at least includes control signal information, output signal information, data signal information of data channels and selection signal status of data channels, and the data channel information at least includes the number of data channels, data channel priority relationship and data channel conflict relationship; The grouping of the data channels of the multiplexer according to the data channel information includes: Sorting the plurality of data channels of the multiplexer according to the data channel priority relationship; The data channels with default branches are divided into the lowest priority group, and the data channels with the highest priority are divided into the highest priority group; Traversing the ungrouped data channels in sequence, and determining the data channel conflict relationship between the ungrouped data channels and the data channel with the highest priority; If there is at least one first data channel that does not conflict with the data channel with the highest priority, classifying at least one first data channel into the highest priority group; If there is at least one second data channel that conflicts with the data channel with the highest priority, at least one second data channel is further divided into priority groups according to the data channel priority relationship and the data channel conflict relationship until all the data channels are divided into different priority groups.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor executes the computer program to implement the expression method of the multiplexer according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for expressing a multiplexer according to any one of claims 1 to 5 is implemented.

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