Gate turn-off thyristor chip and its manufacturing method

Abstract

The present disclosure relates to a gate commutated thyristor chip and a manufacturing method thereof, and relates to the field of semiconductor technologies. The manufacturing method of the gate commutated thyristor chip includes the following steps: providing a substrate; performing a first-type doping on the upper surface of the substrate to form a first-type base region, and performing a first-type doping on the lower surface of the substrate to form a first-type anode region; performing a first-type ion implantation on the upper surface of the first-type base region, and by adjusting the implantation angle and / or the opening size of the implantation mask plate, forming a first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration; performing a second-type impurity diffusion on the upper surface of the first-type doped base region to form a second-type doped emitter region; performing a first-type ion implantation on the lower surface of the first-type anode region to form a first-type doped emitter region. The present disclosure can improve the turn-off performance of the device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a gate commutated thyristor chip and a manufacturing method thereof. Background Art

[0002] Integrated Gate Commutated Thyristor (IGCT) is a new type of power semiconductor device. IGCT integrates the gate drive circuit and the Gate Commutated Thyristor (GCT) chip into a whole, combining the advantages of the stable turn-off ability of transistors and the low conduction loss of thyristors. IGCT performs excellently in high-voltage and high-current applications and is suitable for occasions that require frequent switching and high-efficiency energy conversion.

[0003] The GCT chip has a whole-wafer structure and is composed of an active region, a terminal region, and a gate contact ring region. The active region is formed by thousands of cathode comb bars connected in parallel. During conduction, thousands of cathode comb bars conduct, so thousands of amperes of current are distributed on the entire wafer device. Inevitably, a large current redistribution occurs during turn-off, and at this time, the current load of each cathode comb bar is not evenly distributed. The cathode comb bars far from the gate have a greater current density and are more likely to be damaged, reducing the turn-off ability of the device.

[0004] Therefore, how to improve the uniformity of current distribution in the GCT chip during turn-off, so as to improve the turn-off performance of IGCT, is an urgent problem to be solved. Summary of the Invention

[0005] Based on this, the embodiments of the present disclosure provide a gate commutated thyristor chip and a manufacturing method thereof, which can improve the uniformity of current distribution in the GCT chip during turn-off, thereby improving the turn-off performance of IGCT.

[0006] To achieve the above object, on the one hand, the embodiments of the present disclosure provide a manufacturing method of a gate commutated thyristor chip, including the following steps:

[0007] Provide a substrate;

[0008] Perform a first-type doping on the upper surface of the substrate to form a first-type base region;

[0009] Perform a first-type ion implantation on the upper surface of the first-type base region, and by adjusting the implantation angle and / or the opening size of the implantation mask plate, form a first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration;

[0010] Perform a second-type impurity diffusion on the upper surface of the first-type doped base region to form a second-type doped emitter region;

[0011] Form a first-type doped emitter region on the lower surface of the substrate;

[0012] Form a gate electrode on the upper surface of the first-type doped base region;

[0013] Form a cathode on the upper surface of the second-type doped emitter region;

[0014] Form an anode on the lower surface of the first-type doped emitter region.

[0015] In some embodiments, the first-type doped base region that is longitudinally and laterally variably doped and has a preset doping concentration includes: a first-type doped base region with stepwise gradient doping.

[0016] In some embodiments, the mask includes: photoresist or a metal thin film.

[0017] In some embodiments, after forming a first-type base region by performing first-type doping on the upper surface of the substrate, it further includes: performing first-type doping on the lower surface of the substrate to form a first-type anode region.

[0018] Correspondingly, in some embodiments, forming a first-type doped emitter region on the lower surface of the substrate includes: performing first-type ion implantation on the lower surface of the first-type anode region to form a first-type doped emitter region.

[0019] In some other embodiments, after forming a first-type base region by performing first-type doping on the upper surface of the substrate, it further includes: performing second-type doping on the lower surface of the substrate to form a second-type doped buffer region.

[0020] Correspondingly, in some embodiments, forming a first-type doped emitter region on the lower surface of the substrate includes: performing first-type ion implantation on the lower surface of the second-type doped buffer region to form a first-type doped emitter region.

[0021] In some embodiments, the first type includes: p-type; the second type includes n-type.

[0022] Performing first-type ion implantation on the upper surface of the first-type base region includes: performing aluminum ion implantation or boron ion implantation on the upper surface of the first-type base region.

[0023] In some embodiments, performing first-type ion implantation on the upper surface of the first-type base region, and forming a first-type doped base region that is longitudinally and laterally variably doped and has a preset doping concentration by adjusting the implantation angle and / or the opening size of the implantation mask, includes:

[0024] Adopt the method of ion implantation, and adjust the implantation angle and energy of the ion implantation through simulation calculation by numerical simulation software to adjust the doping concentration of the first-type base region;

[0025] After ion implantation, a diffusion process is performed to form a first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration.

[0026] In some embodiments, performing first-type ion implantation on the upper surface of the first-type base region and forming a first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration by adjusting the implantation angle and / or the opening size of the implantation mask includes:

[0027] Adopting the method of ion implantation, controlling the implantation angle to be fixed at a preset angle, and adjusting the doping concentration of the first-type base region by adjusting the opening size of the implantation mask.

[0028] After ion implantation, a diffusion process is performed to form a first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration.

[0029] In some embodiments, performing first-type ion implantation on the upper surface of the first-type base region and forming a first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration by adjusting the implantation angle and / or the opening size of the implantation mask includes:

[0030] Adopting the method of ion implantation, and adjusting the doping concentration of the first-type base region by simultaneously adjusting the implantation angle, energy, and the opening size of the mask.

[0031] After ion implantation, a diffusion process is performed to form a first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration.

[0032] In some embodiments, the first-type doping includes: aluminum ion doping or gallium ion doping.

[0033] In some embodiments, the second-type impurity includes: phosphorus.

[0034] On the other hand, the embodiments of the present disclosure provide a gate-commutated thyristor chip, which is prepared by using the preparation method of the gate-commutated thyristor chip described in the foregoing embodiments.

[0035] The embodiments of the present disclosure may / at least have the following advantages:

[0036] In the embodiments of the present disclosure, when forming the first-type doped base region by first-type ion implantation on the upper surface of the first-type base region, by adjusting the implantation angle and / or the opening size of the implantation mask, the doping concentration of the first-type base region in the longitudinal and transverse directions is adjusted, so as to form a first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration. In this way, by adjusting the doping concentration of the first-type doped base region under the gate electrode, the non-uniformity of the reverse resistance is adjusted, thereby adjusting the non-uniformity of the gate resistance, and further improving the uniformity of the current distribution on the gate-commutated thyristor chip during turn-off, and finally achieving the purpose of improving the turn-off performance of the IGCT.

[0037] In addition, when forming the first-type doped base region with vertical and horizontal variable doping and a preset doping concentration, the embodiments of the present disclosure avoid adjusting the ion implantation energy or implantation time multiple times, and avoid multiple diffusion processes, reducing the heating steps, thereby greatly improving the production efficiency and the overall yield. Further, the mask can be selected from photoresist or metal thin film, and the selection is relatively flexible, avoiding the variations introduced during mask etching, further improving the production efficiency and the overall yield of the device.

[0038] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0040] Figure 1 It is a schematic flowchart of a method for preparing a gate commutated thyristor chip provided in an embodiment of the present disclosure;

[0041] Figure 2 It is a cross-sectional schematic view of the structure obtained in step S100 in a method for preparing a gate commutated thyristor chip provided in an embodiment of the present disclosure;

[0042] Figure 3 It is a cross-sectional schematic view of the structure obtained in step S200 in a method for preparing a gate commutated thyristor chip provided in an embodiment of the present disclosure;

[0043] Figure 4 It is a cross-sectional schematic view of the structure obtained in step S300 in a method for preparing a gate commutated thyristor chip provided in an embodiment of the present disclosure;

[0044] Figure 5 It is a cross-sectional schematic view of the structure obtained when adjusting the implantation angle in step S300 in a method for preparing a gate commutated thyristor chip provided in an embodiment of the present disclosure;

[0045] Figure 6 It is a cross-sectional schematic view of the structure obtained when adjusting the opening size of the implantation mask in step S300 in a method for preparing a gate commutated thyristor chip provided in an embodiment of the present disclosure;

[0046] Figure 7Schematic cross-sectional view of the structure obtained when simultaneously adjusting the implantation angle and the opening size of the implantation mask in step S300 of a method for manufacturing a gate commutated thyristor chip provided in an embodiment of the present disclosure;

[0047] Figure 8 Schematic cross-sectional view of the structure obtained in step S400 of a method for manufacturing a gate commutated thyristor chip provided in an embodiment of the present disclosure;

[0048] Figure 9 Schematic cross-sectional view of the structure obtained in step S500 of a method for manufacturing a gate commutated thyristor chip provided in an embodiment of the present disclosure;

[0049] Figure 10 Schematic cross-sectional view of the structure obtained in step S700 of a method for manufacturing a gate commutated thyristor chip provided in an embodiment of the present disclosure;

[0050] Figure 11 Schematic cross-sectional view of the structure obtained in step S800 of a method for manufacturing a gate commutated thyristor chip provided in an embodiment of the present disclosure.

[0051] Description of reference numerals:

[0052] 1 - Substrate; 11 - First-type base region; 111 - First-type doped base region; 12 - First-type anode; 121 - First-type doped emitter region; 13 - Second-type doped emitter region; 21 - Gate electrode; 22 - Cathode; 23 - Anode; Y - Mask. Detailed implementation manners

[0053] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used in the specification of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0055] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be denoted as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0056] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also assume other orientations (such as, for example, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0057] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be identified, but one or more other features, integers, steps, operations, elements, components, and / or groups thereof are not precluded from existence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0058] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, and it is to be expected that variations in the shapes of the illustrated regions may result, for example, from manufacturing techniques and / or tolerances. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but include shape deviations resulting, for example, from manufacturing techniques.

[0059] Integrated Gate Commutated Thyristor (IGCT) is a new type of power semiconductor device. The IGCT integrates the gate drive circuit and the Gate Commutated Thyristor (GCT) chip into a whole, combining the stable turn-off ability of transistors and the low conduction loss of thyristors. During the conduction stage, the IGCT can fully utilize the characteristics of thyristors to provide low conduction voltage drop and efficient energy transfer. While during the turn-off stage, it exhibits the characteristics of transistors, achieving a fast and reliable turn-off process. This dual characteristic makes the IGCT perform excellently in high-voltage and high-current applications and is suitable for occasions that require frequent switching and high-efficiency energy conversion.

[0060] The GCT chip has a whole-wafer structure and is composed of an active region, a termination region, and a gate contact ring region. The termination region is the edge area of the wafer and is an important part of the GCT structure. It mainly involves the edge design and protection of the chip, which can reduce the electric field concentration at the edge of the active region, broaden the width of the depletion layer, and increase the breakdown voltage of the device. The active region is formed by thousands of cathode comb bars in parallel. The cathode comb bars are usually arranged concentrically in circles, in a rectangular array, an arc array, or evenly distributed radially on the wafer surface. The gate contact ring is located between the active region and the termination region of the chip to realize the connection between the external gate drive signal and the gate of the GCT unit. During the conduction process, thousands of cathode comb bars conduct, so thousands of amperes of current are distributed on the entire wafer device. Inevitably, there will be a large current redistribution during turn-off, and at this time, the current load of each cathode comb bar is not evenly distributed. The cells near the gate ring have a lower inductive current than the comb bars far from the gate ring, resulting in a larger current density in the cathode comb bars far from the gate, so they are more likely to be damaged.

[0061] Based on this, the embodiments of the present disclosure provide a gate commutated thyristor chip and its manufacturing method, which can improve the uniformity of current distribution in the GCT chip during turn-off, thereby improving the turn-off performance of the IGCT.

[0062] In some embodiments of the present disclosure, please refer to Figure 1 , the manufacturing method of the gate commutated thyristor chip includes steps S100 to S800.

[0063] S100, provide a substrate.

[0064] S200, perform a first-type doping on the upper surface of the substrate to form a first-type base region.

[0065] S300, perform a first-type ion implantation on the upper surface of the first-type base region, and by adjusting the implantation angle and / or the opening size of the implantation mask, form a first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration.

[0066] S400, perform a second-type impurity diffusion on the upper surface of the first-type doped base region to form a second-type doped emitter region.

[0067] S500, form a first-type doped emitter region on the lower surface of the substrate.

[0068] S600, form a gate electrode on the upper surface of the first-type doped base region.

[0069] S700, form a cathode on the upper surface of the second-type doped emitter region.

[0070] S800, form an anode on the lower surface of the first-type doped emitter region.

[0071] In the embodiments of the present disclosure, when forming the first-type doped base region by first-type ion implantation on the upper surface of the first-type base region, by adjusting the implantation angle and / or the opening size of the implantation mask, the doping concentration of the first-type base region in the longitudinal and transverse directions is adjusted, so as to form a first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration. Thus, by adjusting the doping concentration of the first-type doped base region under the gate electrode, the non-uniformity of the reverse resistance is adjusted, thereby adjusting the non-uniformity of the gate resistance, and further improving the uniformity of the current distribution on the gate commutated thyristor chip during turn-off, and finally achieving the purpose of improving the turn-off performance of the IGCT.

[0072] In addition, when forming the first-type doped base region with variable doping in the longitudinal and transverse directions and having a preset doping concentration, the embodiments of the present disclosure avoid adjusting the ion implantation energy or implantation time multiple times, and avoid multiple diffusion processes, reducing the heating steps, thereby greatly improving the production efficiency and the overall yield.

[0073] In some embodiments, after step S200 performs a first-type doping on the upper surface of the substrate to form a first-type base region, it further includes step S250: performing a first-type doping on the lower surface of the substrate to form a first-type anode region.

[0074] Correspondingly, in some embodiments, step S500 forms a first-type doped emitter region on the lower surface of the substrate, including: performing a first-type ion implantation on the lower surface of the first-type anode region to form a first-type doped emitter region.

[0075] In other embodiments, after step S200 performs a first-type doping on the upper surface of the substrate to form a first-type base region, it further includes step S250': performing a second-type doping on the lower surface of the substrate to form a second-type doped buffer region.

[0076] Accordingly, in some embodiments, step S500 forms a first-type doped emitter region on the lower surface of the substrate, including: performing first-type ion implantation on the lower surface of the second-type doped buffer region to form the first-type doped emitter region.

[0077] It should be understood that although Figure 1 the steps in the flowchart are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, there is no strict order limit for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 at least a part of the steps in

[0078] may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of the steps or stages in other steps or other steps. Figures 2 to 11 In order to more clearly illustrate the method for manufacturing a gate-commutated thyristor chip provided by the above embodiments, the following will be described in detail with reference to

[0079] In some embodiments, referring to Figure 1 S100 in Figure 2 and

[0080] step S100 provides the substrate 1.

[0081] In some examples, the substrate 1 may be a silicon substrate, and a resist cleaning and stripping (RCA) process is performed on it.

[0082] Exemplarily, the substrate 1 may be an n-type doped silicon substrate. The substrate 1 may be an n-region base region. 11 cm -3 -1e 14 cm -3 . For example, the doping concentration of the substrate 1 may be: 5e 11 cm -3 , 1e 12 cm -3 , 5e 12 cm -3 , 1e 13 cm -3 , 5e 13 cm -3 or 1e 14 cm -3and so on. The thickness range of the substrate 1 includes: 200 µm - 1400 µm. For example, the thickness of the substrate 1 can be: 200 µm, 400 µm, 600 µm, 800 µm, 1000 µm, 1200 µm or 1400 µm.

[0083] Here, the RCA process is a process used to clean integrated circuits and microelectronic devices. Its principle is to remove dirt and residues on the chip surface through chemical reactions and physical and mechanical actions.

[0084] Exemplarily, the specific steps of the RCA cleaning process are as follows: pre-cleaning, using organic solvents (such as acetone, methanol, ethyl acetate, etc.) to clean the organic substances and impurities on the chip surface; acidic cleaning, using acidic solutions (such as hydrochloric acid, sulfuric acid, etc.) to clean the metal oxides and metals on the chip surface; alkaline cleaning, using alkaline solutions (such as sodium hydroxide, potassium hydroxide, etc.) to clean the acidic residues and organic substances on the chip surface; neutralization cleaning, using neutralizing agents (such as ammonium hydroxide, sodium carbonate, etc.) to neutralize the acidic and alkaline residues on the chip surface; water washing, using pure water to clean the chip surface to remove the residues of the neutralizing agent and the cleaning agent; drying, using a dryer to dry the chip to remove moisture.

[0085] In the embodiments of the present disclosure, the RCA process can effectively remove dirt and residues on the surface of the substrate 1, thereby improving the quality and reliability of the substrate 1. However, it should be noted that during the cleaning process, attention should be paid to controlling the concentration and temperature of the cleaning agent to avoid damaging the substrate 1.

[0086] In some embodiments, please refer to Figure 1 S200 in Figure 3 , step 200 performs a first-type doping on the upper surface of the substrate 1 to form a first-type base region 11.

[0087] In some examples, after step S200, there is also step S250: performing a first-type doping on the lower surface of the substrate 1 to form a first-type anode region 12.

[0088] In some examples, the first type includes: p-type. The first-type doping includes p-ion doping, for example: aluminum-ion doping or gallium-ion doping.

[0089] In some examples, performing a first-type doping on the upper surface of the substrate 1 to form a first-type base region 11 includes: performing a first-type ion implantation (such as p-ion implantation) on the upper surface of the substrate 1 to form a first-type base region 11, or, using a pre-deposition plus diffusion process to perform a first-type doping (such as p-ion doping) on the upper surface of the substrate 1 to form a first-type base region 11.

[0090] Correspondingly, in some examples, forming the first-type anode region 12 by performing first-type doping on the lower surface of the substrate 1 includes: forming the first-type anode region 12 by performing first-type ion implantation (such as p ion implantation) on the lower surface of the substrate 1, or forming the first-type anode region 12 by performing first-type doping (such as p ion doping) on the lower surface of the substrate 1 using a pre-deposition plus diffusion process.

[0091] In some examples, the first-type base region 11 can be a p-type base region. The first-type anode region 12 can be a p-type anode region.

[0092] In some embodiments, refer to Figure 1 S300 in Figures 4 to 7 and, in step 300, performing first-type ion implantation on the upper surface of the first-type base region 11, and forming a first-type doped base region 111 with variable doping in the longitudinal direction (such as the Y direction) and the transverse direction (such as the X direction) and having a preset doping concentration by adjusting the implantation angle and / or the opening size of the implantation mask Y.

[0093] In some embodiments, refer to Figure 4 and, the first-type doped base region 111 with variable doping in the longitudinal direction (such as the Y direction) and the transverse direction (such as the X direction) and having a preset doping concentration includes: a first-type doped base region 111 with stepped gradient doping and having a preset doping concentration.

[0094] Here, the preset doping concentration is designed according to the distance from the gate contact ring. The farther away from the gate contact ring, the lower the doping concentration. In this way, according to the different distances of different cathode rings from the gate contact ring, the doping concentration of the p+ base region under the gate is adjusted, so as to adjust the non-uniformity of the reverse resistance to balance the non-uniformity of the gate metal resistance, and further improve the uniformity of the current distribution on the gate-commutated thyristor chip during turn-off, and finally achieve the purpose of improving the turn-off performance of the IGCT.

[0095] In some embodiments, the mask includes: photoresist or metal thin film.

[0096] In the embodiments of the present disclosure, the mask can be selected from photoresist or metal thin film, and the selection is relatively flexible, avoiding the changes introduced during mask etching, improving the production efficiency and the overall yield of the device.

[0097] In some examples, the first-type includes: p-type. The first-type ion implantation includes p-type ion implantation.

[0098] In some examples, the first-type doped base region 111 can be a P-type heavily doped base region.

[0099] In some examples, performing first-type ion implantation on the upper surface of the first-type base region 11 includes: performing aluminum ion implantation or boron ion implantation on the upper surface of the first-type base region 11.

[0100] In some examples, refer to Figure 5 , a first-type ion implantation is performed on the upper surface of the first-type base region 11. By adjusting the implantation angle and / or the opening size of the implantation mask Y, a first-type doped base region 111 with variable doping in the longitudinal direction (e.g., the Y direction) and the transverse direction (e.g., the X direction) and having a preset doping concentration includes:

[0101] Adopt the method of ion implantation. Through simulation calculation by numerical simulation software, adjust the implantation angle and energy of the ion implantation, and regulate the doping concentration of the first-type base region 11; after the ion implantation, perform a diffusion process once to form a first-type doped base region 111 with variable doping in the longitudinal direction (e.g., the Y direction) and the transverse direction (e.g., the X direction) and having a preset doping concentration.

[0102] Among them, the arrow in the figure indicates the direction of ion implantation.

[0103] Here, through simulation calculation by numerical simulation software of the relationship between the implantation angle and energy of the ion implantation and the doping concentration, and then by adjusting the implantation angle and energy of the ion implantation, regulate the doping concentration of the first-type base region 11.

[0104] In other examples, refer to Figure 6 , a first-type ion implantation is performed on the upper surface of the first-type base region 11. By adjusting the implantation angle and / or the opening size of the implantation mask Y, a first-type doped base region 111 with variable doping in the longitudinal direction (e.g., the Y direction) and the transverse direction (e.g., the X direction) and having a preset doping concentration includes:

[0105] Adopt the method of ion implantation, control the implantation angle to be fixed at a preset angle, and regulate the doping concentration of the first-type base region 11 by adjusting the opening size of the implantation mask; after the ion implantation, perform a diffusion process once to form a first-type doped base region 111 with variable doping in the longitudinal direction (e.g., the Y direction) and the transverse direction (e.g., the X direction) and having a preset doping concentration.

[0106] Among them, the arrow in the figure indicates the direction of ion implantation.

[0107] Here, the opening size of the mask Y controls the concentration change: during ion implantation, the entire wafer is implanted, and the dose and energy remain unchanged. More ions will be implanted at the position with a larger opening of the mask Y, and fewer ions will be implanted at the position with a smaller opening of the mask Y. In addition, since there will be a pushing process after ion implantation and there is lateral (e.g., the X direction) diffusion during the pushing process, there will be doped ions diffusing laterally (e.g., the X direction) under the area covered by the mask Y. Thus, the change in doping concentration is smooth, that is, a stepped gradient doping concentration, rather than a wavy shape.

[0108] In still other examples, refer toFigure 7 A first-type ion implantation is performed on the upper surface of the first-type base region 11. By adjusting the implantation angle and / or the size of the opening of the mask Y, a first-type doped base region 111 with variable doping in the longitudinal direction (e.g., the Y direction) and the transverse direction (e.g., the X direction) and having a preset doping concentration is formed, including:

[0109] By means of ion implantation, by simultaneously adjusting the implantation angle, energy, and the size of the opening of the mask Y of the ion implantation, the doping concentration of the first-type base region 11 is adjusted; after the ion implantation, a diffusion process is performed once to form a first-type doped base region 111 with variable doping in the longitudinal direction (e.g., the Y direction) and the transverse direction (e.g., the X direction) and having a preset doping concentration.

[0110] Among them, the arrow in the figure indicates the direction of ion implantation.

[0111] Here, when the ion implantation angle is different, the amount of ions implanted into the first-type base region 11 is different.

[0112] In some embodiments, please refer to Figure 1 S400 in Figure 8 and

[0113] A second-type impurity diffusion is performed on the upper surface of the first-type doped base region 111 to form a second-type doped emitter region 13.

[0114] In some embodiments, the second type includes n-type. Exemplarily, the second-type impurity includes: phosphorus impurity.

[0115] In some examples, the second-type doped emitter region 13 may be an n-type heavily doped emitter region.

[0116] In some embodiments, please refer to Figure 1 S500 in Figure 9 and

[0117] A first-type doped emitter region 121 is formed on the lower surface of the substrate 1.

[0118] In some examples, the first-type doped emitter region 121 may be an anodic heavily doped emitter region.

[0119] In some embodiments, referring to Figure 1 S600 in Figure 10 and

[0120] a gate electrode 21 is formed on the upper surface of the first-type doped base region 111.

[0121] Exemplarily, a chemical vapor deposition (CVD) process may be adopted to form an oxide layer, and a contact window for the cathode electrode and the gate electrode 21 is etched by photolithography. Metal deposition and photolithography are performed by evaporation or sputtering to form the gate electrode 21.

[0122] In some embodiments, referring to Figure 1 S700 in Figure 10 and

[0123] a cathode 22 is formed on the upper surface of the second-type doped emitter region 13.

[0124] Exemplarily, metal deposition and photolithography are performed by evaporation or sputtering to form the gate electrode 21.

[0125] Here, the gate electrode 21 and the cathode 22 may be formed synchronously. That is, metal deposition and photolithography are performed by evaporation or sputtering to form the gate electrode 21 on the upper surface of the first-type doped base region 111 and form the cathode 22 on the upper surface of the second-type doped emitter region 13.

[0126] In some embodiments, referring to Figure 1 S800 in Figure 11 and

[0127] an anode 23 is formed on the lower surface of the first-type doped emitter region 121.

[0128] Exemplarily, metal deposition and photolithography are performed by evaporation or sputtering to form the anode 23.

[0129] In some embodiments, the method for fabricating a gate commutated thyristor chip further includes: terminal region fabrication. Exemplarily, the terminal region is subjected to operations such as scribing, chamfering, etching, passivation, and glue injection to complete the shaping and passivation protection of the terminal region.

[0130] It should be specifically noted that the above embodiments are not only applicable to the symmetric reverse-blocking IGCT shown in the figure, but also applicable to asymmetric IGCTs and reverse-conducting IGCT devices. The substrate material is not limited to silicon, but can also be a third-generation semiconductor material such as silicon carbide or gallium nitride. In addition, the above embodiments are not only applicable to the case where the gate contact ring is at the edge of the chip, but also equally applicable to the case where the gate ring is in the center or a double-gate ring.

[0131] Please refer to Figure 11 , this embodiment of the present disclosure provides a gate-commutated thyristor chip, which is prepared by using the preparation method of the gate-commutated thyristor chip described in the foregoing embodiment. The technical advantages of the foregoing preparation method of the gate-commutated thyristor chip are also possessed by this gate-commutated thyristor chip.

[0132] In the description of this specification, the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0133] The above embodiments only represent several implementation manners of the present disclosure. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A method for preparing a gate-commutated thyristor chip, characterized in that: include: providing a substrate; Performing first-type doping on the upper surface of the substrate to form a first-type base region; Performing first-type ion implantation on the upper surface of the first-type base region, and forming a first-type doped base region with vertical and lateral variable doping and a preset doping concentration by adjusting the implantation angle and / or the size of the implantation mask opening; Diffusion of second type impurities onto the upper surface of the first type doped base region to form a second type doped emitter region; forming a first type doped emitter region on the lower surface of the substrate; forming a gate electrode on the upper surface of the first-type doped base region; forming a cathode on the upper surface of the second-type doped emitter region; forming an anode on the lower surface of the first-type doped emitter region; The farther the distance between the cathode ring and the gate contact ring of the gate-commutated thyristor chip is, the lower the preset doping concentration is, thereby adjusting the non-uniformity of the reverse resistance to balance the non-uniformity of the gate resistance; The first-type doped base region includes a plurality of sub-doped regions with different preset doping concentrations distributed along the lateral direction; and a plurality of second-type doped emitter regions distributed along the lateral direction at intervals are arranged one-to-one with the plurality of sub-doped regions.

2. The method for preparing a gate-commutated thyristor chip according to claim 1, characterized in that: The first-type doped base region with vertically and laterally variable doping and a preset doping concentration comprises: a first-type doped base region with step-shaped gradual doping.

3. The method for preparing a gate-commutated thyristor chip according to claim 2, characterized in that: The mask plate includes: photoresist or metal film.

4. The method for preparing a gate-commutated thyristor chip according to claim 3, characterized in that: After performing first-type doping on the upper surface of the substrate to form a first-type base region, the method further includes: performing first-type doping on the lower surface of the substrate to form a first-type anode region; Forming a first-type doped emitter region on the lower surface of the substrate includes: performing first-type ion implantation on the lower surface of the first-type anode region to form the first-type doped emitter region.

5. The method for preparing a gate-commutated thyristor chip according to claim 3, characterized in that: After performing first-type doping on the upper surface of the substrate to form a first-type base region, the method further includes: performing second-type doping on the lower surface of the substrate to form a second-type doping buffer region; Forming a first-type doped emitter region on the lower surface of the substrate includes: performing first-type ion implantation on the lower surface of the second-type doped buffer region to form the first-type doped emitter region.

6. The method for preparing a gate-commutated thyristor chip according to claim 4 or 5, characterized in that: The first type includes: p-type; the second type includes n-type; The implanting of the first type ions into the upper surface of the first type base region includes implanting aluminum ions or boron ions into the upper surface of the first type base region.

7. The method for preparing a gate-commutated thyristor chip according to claim 6, characterized in that: The step of implanting the first type ions into the upper surface of the first type base region and forming a first type doped base region with vertical and lateral variable doping and a preset doping concentration by adjusting the implantation angle and / or the size of the implantation mask opening comprises: By adopting the method of ion implantation, the angle and energy of the ion implantation are adjusted by numerical simulation software simulation calculation to adjust the doping concentration of the first type base region; After the ion implantation, a diffusion process is performed to form a first-type doped base region with vertical and lateral variable doping and a preset doping concentration.

8. The method for preparing a gate-commutated thyristor chip according to claim 6, characterized in that: The step of implanting the first type ions into the upper surface of the first type base region and forming a first type doped base region with vertical and lateral variable doping and a preset doping concentration by adjusting the implantation angle and / or the size of the implantation mask opening comprises: Using ion implantation, controlling the implantation angle to be fixed to a preset angle, and adjusting the doping concentration of the first type base region by adjusting the size of the implantation mask opening; After the ion implantation, a diffusion process is performed to form a first-type doped base region with vertical and lateral variable doping and a preset doping concentration.

9. The method for preparing a gate-commutated thyristor chip according to claim 6, characterized in that: The step of implanting the first type ions into the upper surface of the first type base region and forming a first type doped base region with vertical and lateral variable doping and a preset doping concentration by adjusting the implantation angle and / or the size of the implantation mask opening comprises: Using ion implantation, by simultaneously adjusting the angle, energy and mask opening size of the ion implantation, the doping concentration of the first type base region is adjusted; After the ion implantation, a diffusion process is performed to form a first-type doped base region with vertical and lateral variable doping and a preset doping concentration.

10. The method for preparing a gate-commutated thyristor chip according to claim 1, characterized in that: The first type doping includes: aluminum ion doping or gallium ion doping.

11. The method for preparing a gate-commutated thyristor chip according to claim 1, characterized in that: The second type impurities include phosphorus.

12. A gate-commutated thyristor chip, characterized in that: The gate-commutated thyristor chip is prepared by the preparation method according to any one of claims 1 to 11.

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