High reliability planar gate SiC MOSFET and method for manufacturing the same

Abstract

The present invention discloses a high-reliability planar gate SiC MOSFET and a manufacturing method thereof. The high-reliability planar gate SiC MOSFET includes a characteristic groove, a substrate, an epitaxial layer and a source region of a first type of doping type, a well region and a body region of a second type of doping type, and a first conductor, a second conductor and a third conductor are formed in the characteristic groove. A well region and a source region are formed on both sides and at the bottom of the characteristic groove, a first type of contact is formed at the bottom of the characteristic groove, and a second type of contact is formed on the surface of the epitaxial layer between adjacent well regions. The present invention significantly improves the short-circuit capability of the device through structural design. The body diode can be prevented from turning on during reverse conduction, thereby avoiding the bipolar degradation effect and significantly improving the application reliability of the device. The present invention also discloses a manufacturing method for the device structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-reliability planar gate SiC MOSFET and a manufacturing method thereof. Background Art

[0002] The development of power electronic systems has put forward higher requirements on the performance of power semiconductor devices. At present, silicon-based power semiconductor devices occupy the main market share of power devices. However, due to the limitations of silicon material properties, the performance of silicon-based power devices has reached its theoretical limit.

[0003] As a representative of the third generation of semiconductor materials, silicon carbide (SiC) has advantages such as a larger bandgap, a higher critical breakdown electric field, and a higher thermal conductivity. Therefore, SiC power devices have obvious advantages in high power, high temperature and other fields. SiC MOSFET power devices with a planar gate structure have been commercialized, and their market share is also expanding. In the 600V~1200V medium and low voltage application field, SiC MOSFET is gradually replacing Si IGBT.

[0004] Compared with Si IGBT, SiC MOSFET can greatly improve the Baliga coefficient of device on-resistance and breakdown voltage, and achieve a significant improvement in static electrical performance. However, the substantial increase in current density damages the application reliability of the device. The short-circuit withstand time of SiIGBT is about 10μs or more, while the short-circuit withstand time of the currently commercially available SiC MOSFET is only about 3μs, and the short-circuit capability of the device has been significantly degraded. In addition, the body diode turn-on voltage of SiC MOSFET is relatively high, resulting in greater device losses, and the bipolar degradation effect caused by the body diode freewheeling will seriously damage the long-term application reliability of the device. Summary of the invention

[0005] Technical purpose: In view of the shortcomings of the above-mentioned planar SiC MOSFET devices, the present invention provides a high-reliability planar gate SiC MOSFET. The purpose of the present invention is to provide a planar SiC MOSFET with significantly improved short-circuit capability, while solving the existing SiC MOSFET bipolar degradation problem.

[0006] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0007] A high reliability planar gate SiC MOSFET, comprising:

[0008] a fourth electrical conductor;

[0009] A substrate, located on the fourth conductor;

[0010] an epitaxial layer, located on the substrate;

[0011] A well region, located in the epitaxial layer;

[0012] a source region, located in the well region, wherein a distance between a left boundary of the source region and a left boundary of the well region is equal to a distance between a right boundary of the source region and a right boundary of the well region, and a depth of the source region is less than a depth of the well region;

[0013] A characteristic groove is located on the epitaxial layer, in the well region, and in the source region. The left and right sidewalls of the characteristic groove are both located in the source region. The distance between the left boundary of the characteristic groove and the left boundary of the source region is equal to the distance between the right boundary of the characteristic groove and the right boundary of the source region. The bottom surface of the characteristic groove is higher than the bottom surface of the source region.

[0014] A body region, located at the bottom of the characteristic trench, wherein the bottom surface of the body region is located above the bottom surface of the well region;

[0015] A first conductor is located in the characteristic groove, on the left side wall and on the surface of the epitaxial layer;

[0016] A second conductor is located in the characteristic groove, on the right side wall and on the surface of the epitaxial layer;

[0017] A first medium is located between the first conductor and the epitaxial layer, the well region, and the source region;

[0018] A second medium is located between the second conductor and the epitaxial layer, the well region, and the source region;

[0019] A first insulator, located on both sides and on the first conductor;

[0020] A second insulator is located on both sides and on the second conductor;

[0021] The third conductor is located between and on the first insulator and the second insulator, forms a first type contact with the body region and the source region, and forms a second type contact with the epitaxial layer.

[0022] A method for manufacturing a high-reliability planar gate SiC MOSFET, used to manufacture the high-reliability planar gate SiC MOSFET described above, comprises the following steps:

[0023] Step 1, forming an epitaxial layer on a substrate;

[0024] Step 2, forming a well region in the epitaxial layer, and forming a source region in the well region;

[0025] Step 3, etching part of the well region and part of the source region to form a characteristic groove; forming a body region at the bottom of the characteristic groove;

[0026] Step 4, forming a first dielectric and a second dielectric on the sidewall and bottom of the characteristic groove and on the epitaxial layer, and forming a first conductor and a second conductor in the characteristic groove and on the surface of the epitaxial layer;

[0027] Step 5: Form a first insulator on both sides and on the first conductor, form a second insulator on both sides and on the second conductor, form a third conductor between and on the first insulator and the second insulator, and form a fourth conductor on the bottom layer of the substrate.

[0028] Beneficial effects:

[0029] (1) The high-reliability planar gate SiC MOSFET proposed in the present invention significantly increases the effective depth of the well region by arranging a first conductor, a second conductor and a third conductor in a characteristic groove, and arranging a well region, a source region and a body region on both sides and at the bottom of the characteristic groove. In the short-circuit state, the pinch-off effect between the well regions is utilized to greatly improve the short-circuit tolerance of the SiC MOSFET.

[0030] (2) The high-reliability planar gate SiC MOSFET proposed in the present invention forms a second-type contact on the surface of the epitaxial layer between adjacent well regions. By utilizing the lower barrier height of the second-type contact, the body diode can be prevented from turning on in the reverse conduction state, thereby reducing device losses and avoiding the bipolar degradation effect, thereby improving the application reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of a high reliability planar gate SiC MOSFET according to Example 1;

[0032] Figure 2 Schematic diagram of a high reliability planar gate SiC MOSFET according to Example 2;

[0033] Figure 3 Schematic diagram of a high reliability planar gate SiC MOSFET according to Example 3;

[0034] Figure 4~Figure 8 Schematic diagram of the preparation process of the high reliability planar gate SiC MOSFET of Example 1;

[0035] Explanation of the accompanying drawings: 1. fourth conductor; 2. substrate; 3. epitaxial layer; 4. well region; 5. body region; 6. source region; 7-1. first conductor; 7-2. second conductor; 8-1. first dielectric; 8-2. second dielectric; 9-1. first insulator; 9-2. second insulator; 10. third conductor; 11. second type contact; 12. current spreading layer; 13. column region; 101. characteristic groove. DETAILED DESCRIPTION

[0036] The present invention is further explained and illustrated below in conjunction with the accompanying drawings and embodiments.

[0037] The embodiments are only used to illustrate the present invention and do not limit the scope of the claims. Other alternative means that can be thought of by those skilled in the art are all within the scope of the claims of the present invention.

[0038] In addition, in the description of the present invention, it should be noted that the terms "central", "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0039] Example 1

[0040] As attached Figure 1 As shown, a high reliability planar gate SiC MOSFET of this embodiment includes:

[0041] a fourth conductor 1;

[0042] A substrate 2 located on the fourth conductor 1, and an epitaxial layer 3 located on the substrate 2; the substrate 2 is a 4H-SiC substrate, and the epitaxial layer 3 is a 4H-SiC epitaxial layer; in some other embodiments of the present invention, the semiconductor material used for the substrate 2 and the epitaxial layer 3 may be 3C-SiC, 6H-SiC or 15R-SiC;

[0043] The well region 4 is located in the epitaxial layer 3. The depth of the well region 4 ranges from 2.0µm to 6.0µm, and the doping concentration is 1e16cm -3 ~ 3e18cm -3 ;

[0044] The source region 6 is located in the well region 4. The depth of the source region 6 ranges from 1.2µm to 5.0µm, and the doping concentration is 1e19cm -3 ~ 3e20cm -3 ; The distance between the left boundary of the source region and the left boundary of the well region is equal to the distance between the right boundary of the source region and the right boundary of the well region, and the distance range is 0.1µm to 0.6µm, and the depth of the source region is less than the depth of the well region, and the difference between the two is 0.2µm to 2.0µm;

[0045] The body region 5 is located in the well region 4. The bottom surface of the body region 5 may be flush with the bottom surface of the source region 6 or not. The doping concentration of the body region 5 is 1e19cm -3 ~ 3e20cm -3 The bottom surface of the body region is located above the bottom surface of the well region, and the distance between the bottom surface of the body region and the bottom surface of the well region is in the range of 0.2µm to 2.0µm;

[0046] A characteristic groove 101 is located in the well region 4, in the source region 6, and on the body region 5, the left and right side walls of the characteristic groove are both located in the source region, the depth of the characteristic groove 101 ranges from 1.0µm to 4.5µm, and the side wall angle of the characteristic groove 101 is not less than 80 degrees; the distance between the left boundary of the characteristic groove and the left boundary of the source region is equal to the distance between the right boundary of the characteristic groove and the right boundary of the source region, and the distance range is 0.3µm to 1.5µm, the bottom surface of the characteristic groove is higher than the bottom surface of the source region, and the distance between the bottom surface of the characteristic groove and the bottom surface of the source region ranges from 0.2µm to 1.0µm;

[0047] A first conductor 7 - 1 located in the characteristic groove 101 and on the left side wall and on the epitaxial layer 3 ; a second conductor 7 - 2 located in the characteristic groove 101 and on the right side wall and on the epitaxial layer 3 ;

[0048] A first dielectric 8-1 located between the first conductor 7-1 and the epitaxial layer 3, the well region 4 and the source region 6; a second dielectric 8-2 located between the second conductor 7-2 and the epitaxial layer 3, the well region 4 and the source region 6;

[0049] A first insulator 9-1 located on both sides and above the first conductor 7-1; a second insulator 9-2 located on both sides and above the second conductor 7-2;

[0050] The third conductor 10 is located between and on the first insulator 9-1 and the second insulator 9-2, and the third conductor 10 forms a first type contact with the source region 6 and the body region 5, and the third conductor 10 forms a second type contact 11 with the epitaxial layer 3. The first type contact is an ohmic contact, and the second type contact is a Schottky contact.

[0051] A high reliability planar gate SiC MOSFET in the present invention shows a cell structure, and the layout of the cell can be a strip, square, hexagon, dodecagon or atomic lattice. The doping type of the substrate, epitaxial layer and source region is a first type, and the doping type of the well region and body region is a second type. The first type can be N-type or P-type, and correspondingly, the second conductivity type can be P-type or N-type.

[0052] As attached Figure 4 To Attachment Figure 8As shown, a method for manufacturing a high-reliability planar gate SiC MOSFET of the present invention comprises the following steps:

[0053] Step 1: forming an epitaxial layer 3 on a substrate 2; Figure 4 As shown, an epitaxial layer 3 is formed on a substrate 2 by epitaxial growth; the depth of the substrate 2 ranges from 80µm to 200µm, and the doping concentration of the substrate 2 is 1e19cm -3 ~ 1e20cm -3 The depth of epitaxial layer 3 ranges from 5µm to 50µm, and the doping concentration of epitaxial layer 3 is 5e15cm -3 ~ 1e17cm -3 .

[0054] Step 2: forming a well region 4 in the epitaxial layer 3, and forming a source region 6 in the well region 4; Figure 5 As shown, a well region 4 is formed in the epitaxial layer 3 by an ion implantation process. The depth of the well region 4 ranges from 2.0µm to 6.0µm, and the doping concentration is 1e16cm -3 ~3e18cm -3 It should be noted that the drawings shown in the present invention are schematic diagrams of a single cell structure in a high-reliability planar gate SiC MOSFET. In adjacent cell structures, the spacing between adjacent well regions 4 ranges from 0.5µm to 2.0µm. Then, a source region 6 is formed in the well region 4 by an ion implantation process. The depth of the source region 6 ranges from 1.2µm to 5.0µm, and the doping concentration is 1e19cm -3 ~3e20cm -3 ; The distance between the left boundary of the source region and the left boundary of the well region is equal to the distance between the right boundary of the source region and the right boundary of the well region, and the distance ranges from 0.1µm to 0.6µm. The depth of the source region is less than the depth of the well region, and the difference between the two ranges from 0.2µm to 2.0µm;

[0055] Step 3, etching part of the well region 4 and part of the source region 6 to form a characteristic groove 101; forming a body region 5 in the well region 4 at the bottom of the characteristic groove 101 and between adjacent source regions 6; Figure 6As shown, a characteristic groove 101 is formed in the well region 4 by an etching process, the depth of the characteristic groove 101 ranges from 1.0µm to 4.5µm, the sidewall angle of the characteristic groove 101 is not less than 80 degrees, the distance between the left boundary of the characteristic groove 101 and the left boundary of the source region 6 is equal to the distance between the right boundary of the characteristic groove 101 and the right boundary of the source region 6, the distance range is 0.3µm to 1.5µm, the bottom surface of the characteristic groove 101 is higher than the bottom surface of the source region 6, and the distance between the bottom surface of the characteristic groove 101 and the bottom surface of the source region 6 ranges from 0.2µm to 1.0µm; step 3 can adopt a reactive ion etching process or an inductively coupled plasma etching process, and the etching gas can be SF 6 、HBr、Cl 2 , O 2 The bottom angle of the characteristic groove 101 may be arc-shaped to reduce the curvature effect of the groove structure. The characteristic groove is in the depth direction of the device, that is, Figure 1 The device structure can be distributed continuously or discontinuously in the direction perpendicular to the paper surface.

[0056] A body region 5 is formed at the bottom of the characteristic groove 101 by ion implantation, wherein the body region 5 is located in the well region 4 at the bottom of the characteristic groove 101 and between adjacent source regions 6; the bottom surface of the body region is located above the bottom surface of the well region, and the spacing between the bottom surface of the body region and the bottom surface of the well region is in the range of 0.2µm to 2.0µm; the bottom surface of the body region 5 may be flush with the bottom surface of the source region 6 or not, and the doping concentration of the body region 5 is 1e19cm -3 ~ 3e20cm -3 ;

[0057] In the present invention, the body region 5, the source region 6, and the characteristic groove 101 are symmetrical in the well region 4 to avoid the phenomenon of uneven flow in cells;

[0058] Step 4, starting from the bottom of the characteristic groove 101, a first dielectric 8-1 and a second dielectric 8-2 are formed which are not connected to each other on the side walls of the characteristic groove 101 and on the epitaxial layer 3, and a first conductor 7-1 and a second conductor 7-2 are formed on the first dielectric 8-1 and the second dielectric 8-2 respectively; Figure 7As shown, a patterned first dielectric 8-1 and a second dielectric 8-2 are formed on the bottom and sidewalls of the characteristic groove 101, the source region 6, the well region 4 and the surface of the epitaxial layer 3 by an LPCVD (Low Pressure Chemical Vapor Deposition) process, wherein the first dielectric 8-1 is located at a portion of the bottom and the left side wall of the characteristic groove 101 and extends to the top of the source region 6, the top of the well region 4 and the top of a portion of the epitaxial layer 3 beside the left side wall of the characteristic groove, and the second dielectric 8-2 is located at a portion of the bottom and the right side wall of the characteristic groove 101 and extends to the top of the source region 6, the top of the well region 4 and the top of a portion of the epitaxial layer 3 beside the right side wall of the characteristic groove. At the bottom of the characteristic groove 101, the first dielectric 8-1 and the second dielectric 8-2 are not connected; A dielectric 8-1 and a second dielectric 8-2 are subjected to high temperature annealing treatment, and then a first conductor 7-1 and a second conductor 7-2 are formed on the dielectric layer, that is, on the first dielectric 8-1 and the second dielectric 8-2, respectively, through an LPCVD process. The first conductor 7-1 and the second conductor 7-2 can only be located on the corresponding first dielectric 8-1 and the second dielectric 8-2, and cannot be in direct contact with the epitaxial layer 3; the material of the first conductor 7-1 and the second conductor 7-2 is polysilicon, and the first conductor 7-1 and the second conductor 7-2 are implanted and activated by annealing; wherein, the first dielectric 8-1 and the second dielectric 8-2 are not connected, and the first conductor 7-1 and the second conductor 7-2 are not connected. The material of the first conductor 7-1 and the second conductor 7-2 can be metal or doped polysilicon; the material of the first dielectric 8-1 and the second dielectric 8-2 can be silicon oxide, silicon nitride, borophosphosilicate glass, aluminum oxide, sapphire or hafnium oxide, and the thickness of the first dielectric and the second dielectric ranges from 40nm to 200nm;

[0059] Step 5: Form a first insulator 9-1 and a second insulator 9-2 on both sides and on the first conductor 7-1 and the second conductor 7-2, respectively, grow a third conductor 10 between and on the first insulator 9-1 and the second insulator 9-2, and grow a fourth conductor 1 on the bottom layer of the substrate 2; Figure 8 As shown, the first insulator 9-1 and the second insulator 9-2 are formed on both sides and on the first conductor 7-1 and the second conductor 7-2 respectively by the LPCVD process, and the first insulator 9-1 and the second insulator 9-2 are also located on the first dielectric 8-1 and the second dielectric 8-2 respectively; the material of the first insulator 9-1 and the second insulator 9-2 is SiO 2A third conductor 10 is grown in the characteristic groove 101, between and on the first insulator 9-1 and the second insulator 9-2, and a fourth conductor 1 is grown on the bottom layer of the substrate 2. In the characteristic groove 101, the third conductor 10 forms a first type contact with the source region 6 and the body region 5, and on both sides of the characteristic groove 101 and on the epitaxial layer 3, the third conductor 10 forms a second type contact 11 with the epitaxial layer 3.

[0060] The materials of the first insulator 9 - 1 and the second insulator 9 - 2 may be silicon dioxide, or nitride, or a composite of silicon dioxide and nitride.

[0061] The material of the third conductor can be one or more combinations of metals such as Ti, Al, Ni, Pt, etc. The material of the fourth conductor can be one or more metals such as Ti, Ni, Ag, etc.

[0062] In this embodiment, the electrode materials of the source, drain, and Schottky electrode are one or more combinations of metals such as Ti, Al, Ni, and Pt; the isolation medium can be silicon dioxide, or nitride, or a composite of silicon dioxide and nitride.

[0063] Example 2

[0064] As attached Figure 2 As shown, a high reliability planar gate SiC MOSFET of this embodiment is different from that of embodiment 1 in that: a current spreading layer 12 is formed on both sides of the well region 4 and near the surface of the epitaxial layer 3, the doping type of the current spreading layer 12 is the first type, the top of the current spreading layer 12 is flush with the top of the epitaxial layer 3, and the current spreading layer 12 is adjacent to the well region 4; the depth of the current spreading layer 12 ranges from 0.2µm to 2.0µm, and the doping concentration is 1e16m -3 ~ 3e17cm -3 , the bottom of the current spreading layer 12 is higher than the bottom of the well region 4; the introduction of the current spreading layer 12 can further reduce the on-resistance of the device.

[0065] The method for manufacturing a high-reliability planar gate SiC MOSFET of this embodiment is different from that of Embodiment 1 in that:

[0066] In step 2 of forming a well region 4 in the epitaxial layer 3 and forming a source region 6 in the well region 4 , an additional step is added: a current spreading layer 12 is formed on both sides of the well region 4 and on the epitaxial layer 3 by ion implantation, and the current spreading layer 12 is adjacent to the well region 4 .

[0067] Example 3

[0068] As attached Figure 3As shown, a high reliability planar gate SiC MOSFET of this embodiment is different from that of embodiment 1 in that the depth of the well region 4 ranges from 2.0µm to 10.0µm, and the doping concentration is 1e16cm -3 ~ 1e18cm -3 , a column region 13 is formed on both sides of the well region 4 and on the epitaxial layer 3. The doping type of the column region 13 is the first type, the depth of the column region 13 ranges from 2.0µm to 10.0µm, and the doping concentration is 1e16m -3 ~ 3e18cm -3 The bottom of the column region 13 is flush with the bottom of the well region 4 , and the column region 13 can form a semi-super junction structure with the well region 4 , which greatly reduces the resistance of the drift region while ensuring that the breakdown voltage is not degraded.

[0069] The method for manufacturing a high-reliability planar gate SiC MOSFET of this embodiment is different from that of Embodiment 1 in that:

[0070] In step 2 of forming a well region 4 in the epitaxial layer 3 and forming a source region 6 in the well region 4, an additional step is added: forming a column region 13 on the epitaxial layer 3 on both sides of the well region 4 by ion implantation, the column region 13 is adjacent to the well region 4, and a semi-super junction structure is formed.

[0071] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A high reliability planar gate SiC MOSFET, characterized in that: include: a fourth electrical conductor; A substrate, located on the fourth conductor; an epitaxial layer, located on the substrate; A well region, located in the epitaxial layer; a source region, located in the well region, wherein a distance between a left boundary of the source region and a left boundary of the well region is equal to a distance between a right boundary of the source region and a right boundary of the well region, and a depth of the source region is less than a depth of the well region; A characteristic groove is located on the epitaxial layer, in the well region, and in the source region. The left and right sidewalls of the characteristic groove are both located in the source region. The distance between the left boundary of the characteristic groove and the left boundary of the source region is equal to the distance between the right boundary of the characteristic groove and the right boundary of the source region. The bottom surface of the characteristic groove is higher than the bottom surface of the source region. A body region, located at the bottom of the characteristic trench, wherein the bottom surface of the body region is located above the bottom surface of the well region; A first conductor is located in the characteristic groove, on the left side wall and on the surface of the epitaxial layer; A second conductor is located in the characteristic groove, on the right side wall and on the surface of the epitaxial layer; A first medium is located between the first conductor and the epitaxial layer, the well region, and the source region; A second medium is located between the second conductor and the epitaxial layer, the well region, and the source region; A first insulator, located on both sides and on the first conductor; A second insulator is located on both sides and on the second conductor; The third conductor is located between and on the first insulator and the second insulator, forms a first type of contact with the body region and the source region, and forms a second type of contact with the epitaxial layer, the first type of contact is an ohmic contact, and the second type of contact is a Schottky contact.

2. A high reliability planar gate SiC MOSFET according to claim 1, characterized in that: When the distance between the left boundary of the source region and the left boundary of the well region is equal to the distance between the right boundary of the source region and the right boundary of the well region, the distance range is 0.1µm to 0.6µm; When the distance between the left boundary of the characteristic groove and the left boundary of the source region is equal to the distance between the right boundary of the characteristic groove and the right boundary of the source region, the distance range is 0.3µm to 1.5µm.

3. A high reliability planar gate SiC MOSFET according to claim 1, characterized in that: The depth of the source region is less than the depth of the well region, and the difference between the two is 0.2µm ~ 2.0µm; the spacing between the bottom surface of the characteristic groove and the bottom surface of the source region is in the range of 0.2µm ~ 1.0µm; the spacing between the bottom surface of the body region and the bottom surface of the well region is in the range of 0.2µm ~ 2.0µm.

4. A high reliability planar gate SiC MOSFET according to claim 1, characterized in that: The invention also includes a current spreading layer located on both sides of the well region and on the epitaxial layer.

5. A high reliability planar gate SiC MOSFET according to claim 1, characterized in that: It also includes column regions located on both sides of the well region and above the epitaxial layer, and the column regions and the well region form a semi-super junction structure.

6. A high reliability planar gate SiC MOSFET according to claim 1, characterized in that: The depth of the well region ranges from 2.0µm to 6.0µm, and the doping concentration is 1e16cm -3 ~ 3e18cm -3 The source region has a depth range of 1.2µm to 5.0µm and a doping concentration of 1e19cm -3 ~ 3e20cm -3 The bottom surface of the body region is flush with or not flush with the bottom surface of the source region, and the doping concentration of the body region is 1e19cm -3 ~ 3e20cm -3 .

7. A high reliability planar gate SiC MOSFET according to claim 1, characterized in that: The depth of the characteristic groove ranges from 1.0µm to 4.5µm, and the sidewall angle of the characteristic groove is not less than 80 degrees.

8. A high reliability planar gate SiC MOSFET according to claim 1, characterized in that: The two bottom corners of the characteristic groove are arc-shaped.

9. A method for manufacturing a high reliability planar gate SiC MOSFET, used to manufacture a high reliability planar gate SiC MOSFET as claimed in any one of claims 1 to 8, characterized in that: The following steps are involved: Step 1, forming an epitaxial layer on a substrate; Step 2, forming a well region in the epitaxial layer, and forming a source region in the well region; Step 3, etching part of the well region and part of the source region to form a characteristic groove; forming a body region at the bottom of the characteristic groove; Step 4, forming a first dielectric and a second dielectric on the sidewall and bottom of the characteristic groove and on the epitaxial layer, and forming a first conductor and a second conductor in the characteristic groove and on the surface of the epitaxial layer; Step 5: Form a first insulator on both sides and on the first conductor, form a second insulator on both sides and on the second conductor, form a third conductor between and on the first insulator and the second insulator, and form a fourth conductor on the bottom layer of the substrate.

10. The method for manufacturing a high reliability planar gate SiC MOSFET according to claim 9, characterized in that: Step 3 adopts a reactive ion etching process or an inductively coupled plasma etching process, and the etching gas is one or more combinations of SF6, HBr, Cl2, O2, and Ar gases.

Images