Power conversion devices and electronic equipment

Abstract

An embodiment of the present invention provides a power conversion device and an electronic device. The power conversion device includes: a power conversion circuit, including a first switching tube, a second switching tube, and an inductor unit, wherein one end of the inductor unit is connected to a first bias voltage, and the other end of the inductor unit is connected to a second bias voltage through the first switching tube; a signal processing circuit, connected to the power conversion circuit, configured to perform pulse width modulation on an input signal to obtain a first PWM signal and a second PWM signal with matching timing, and output the first PWM signal and the second PWM signal to the first switching tube and the second switching tube, respectively, to alternately control the on and off of the first switching tube and the second switching tube; and a power output circuit, connected to the other end of the inductor unit through the second switching tube, configured to output an output conversion signal of the input signal.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of electronic circuits, and in particular to a power conversion device and an electronic device. Background Art

[0002] Power conversion devices, such as power converters, change signal voltage by stepping up or down. Signal processing circuits process the signals to generate a series of PWM (Pulse Width Modulation) signals. These signals are then converted to power amplification and output to drive capacitive loads. These power conversion devices are widely used in applications requiring voltage conversion and power amplification, such as audio amplifiers, power supplies, and motor drivers.

[0003] When performing signal conversion, the power conversion device in the prior art requires a PWM signal to control the on and off of a large number of switching tubes. However, a large number of switching tubes often occupy a large area, which is not conducive to the miniaturization of the power conversion device and the electronic equipment carrying the power conversion device. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a power conversion device and an electronic device to solve the above problems.

[0005] According to a first aspect of an embodiment of the present invention, a power conversion device is provided, comprising: a power conversion circuit, comprising a first switching tube, a second switching tube and an inductor unit, wherein one end of the inductor unit is connected to a first bias voltage, and the other end of the inductor unit is connected to a second bias voltage through the first switching tube; a signal processing circuit, connected to the power conversion circuit, the signal processing circuit being configured to perform pulse width modulation on an input signal to obtain a first PWM signal and a second PWM signal with timing matching, and outputting the first PWM signal and the second PWM signal to the first switching tube and the second switching tube, respectively, to alternately control the on and off of the first switching tube and the second switching tube; and a power output circuit, connected to the other end of the inductor unit through the second switching tube, the power output circuit being configured to output an output conversion signal of the input signal.

[0006] In another implementation of the present invention, the power conversion circuit also includes a third switching tube, and the power output circuit is connected to the other end of the inductor unit through the third switching tube; the signal processing circuit is used to: in the first half of the entire cycle of the input signal, pulse width modulate the input signal to obtain a first PWM signal and a second PWM signal with timing matching, and in the second half of the entire cycle of the input signal, pulse width modulate the input signal to obtain a first PWM signal and a third PWM signal with timing matching, and the first PWM signal and the third PWM signal are respectively used to control the on and off of the first switching tube and the third switching tube.

[0007] In another implementation of the present invention, the signal processing circuit is configured to: perform pulse width modulation on the input signal at sampling points of the first half cycle according to a first preset duty cycle to obtain first and second PWM signals with timing matching in the first half cycle; and perform pulse width modulation at sampling points of the second half cycle according to a second preset duty cycle to obtain first and third PWM signals with timing matching in the second half cycle, wherein the first preset duty cycle and the second preset duty cycle are complementary.

[0008] In another implementation of the present invention, the third PWM signal is used to control the third switch tube to be in a normally off state in the second half cycle, and the second PWM signal is used to control the second switch tube to be in a normally off state in the second half cycle.

[0009] In another implementation of the present invention, the power output circuit includes a first output end and a second output end, the first output end is connected to the other end of the inductor unit through the second switching tube, and the second output end is connected to the other end of the inductor unit through the third switching tube, wherein the power output circuit outputs an output conversion signal of the input signal between the first output end and the second output end.

[0010] In another implementation of the present invention, the power output circuit further includes a fourth switching transistor and a fifth switching transistor, the fourth switching transistor being connected between the first output terminal and the third bias voltage, and the fifth switching transistor being connected between the second output terminal and the third bias voltage. The signal processing circuit is further configured to generate a first commutation signal and a second commutation signal, the first commutation signal being configured to control the fourth switching transistor to be normally off during the first half cycle and normally on during the second half cycle, and the second commutation signal being configured to control the fifth switching transistor to be normally on during the first half cycle and normally off during the second half cycle.

[0011] In another implementation of the present invention, in the in-phase conversion mode, the first output terminal is connected to the positive pole of the capacitive load, and the second output terminal is connected to the negative pole of the capacitive load; in the in-phase conversion mode, the first output terminal is connected to the negative pole of the capacitive load, and the second output terminal is connected to the positive pole of the capacitive load.

[0012] In another implementation of the present invention, the power conversion device further includes a substrate selection circuit, at least one of the second switching transistor and the third switching transistor is a MOS transistor, and the substrate selection circuit is respectively connected to the source, drain, and substrate of the MOS transistor. The substrate selection circuit connects the substrate to the higher voltage between the drain and the source when the MOS transistor is a P-type MOS transistor, and connects the substrate to the lower voltage between the drain and the source when the MOS transistor is an N-type MOS transistor.

[0013] In another implementation of the present invention, in a boost conversion mode, the first bias voltage is greater than the second bias voltage; in a buck conversion mode, the first bias voltage is less than the second bias voltage.

[0014] According to a second aspect of an embodiment of the present invention, an electronic device is provided, comprising: a capacitive load; and the power conversion device according to the first aspect, the power conversion device providing an output conversion signal to the capacitive load.

[0015] In the capacitive load driving scheme of an embodiment of the present invention, the first and second switching transistors are alternately controlled to turn on and off using the converted first and second PWM signals, resulting in a power output circuit obtaining a voltage signal that matches the input signal waveform. Furthermore, when the first and second switching transistors are alternately controlled to turn on and off, the transient current in the inductor unit remains unchanged, generating a reverse electromotive force. Therefore, the power output circuit obtains a voltage signal that is a step-up or step-down of the first bias voltage based on the voltage difference between the second bias voltage and the first bias voltage. Consequently, the aforementioned switching transistors are reused for power conversion and waveform matching, reducing the number of switching transistors used in the power conversion device and facilitating device miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0017] Figure 1Schematic diagram of the structure of a power conversion device according to some embodiments of the present invention.

[0018] Figure 2 for Figure 1 A schematic structural diagram of a power conversion device according to a further example of an embodiment of the present invention.

[0019] Figure 3 for Figure 1 and Figure 2 A circuit diagram of a power conversion device according to an embodiment.

[0020] Figure 4 for Figure 3 Signal timing diagram of each switch tube in the embodiment.

[0021] Figure 5 for Figure 1 A circuit diagram of a substrate selection circuit in a power conversion device according to an embodiment of the present invention.

[0022] Figure 6 for Figure 5 Schematic structural diagram of the substrate selection circuit.

[0023] Figure 7A and Figure 7B This is a structural diagram of other variants of the switch tube.

[0024] Figure 8 Schematic diagram of the structure of electronic devices according to other embodiments of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in the embodiments of the present invention should fall within the scope of protection of the embodiments of the present invention.

[0026] The specific implementation of the embodiment of the present invention is further described below with reference to the accompanying drawings of the embodiment of the present invention.

[0027] Figure 1 Power conversion devices according to some embodiments of the present invention are shown. Figure 1 The power conversion device 100 includes a power conversion circuit 110 , a signal processing circuit 120 and a power output circuit 130 .

[0028] Specifically, the power conversion circuit 110 includes a first switching tube, a second switching tube and an inductor unit, wherein one end of the inductor unit is connected to a first bias voltage, and the other end of the inductor unit is connected to a second bias voltage through the first switching tube.

[0029] It should be understood that transistor M1 may be an example of a first switching transistor, transistor M2 may be an example of a second switching transistor, and inductor L may be an example of an inductor unit. An inductor unit may also include a structure formed by connecting multiple inductors in series or in parallel. In addition, in the boost conversion mode, the first bias voltage is greater than the second bias voltage, for example, the voltage value of VDD (an example of the first bias voltage) is greater than the ground voltage value (an example of the second bias voltage); in the buck conversion mode, the first bias voltage is less than the second bias voltage, for example, the ground voltage value (an example of the first bias voltage) is less than the voltage value of VDD (an example of the second bias voltage).

[0030] Furthermore, the signal processing circuit 120 is connected to the power conversion circuit, and the signal processing circuit 120 is used to perform pulse width modulation on the input signal to obtain a first PWM signal (for example, Figure 1 PWM1 signal in) and a second PWM signal (e.g., Figure 1 The first and second PWM signals are output to the first and second switching tubes, respectively, to alternately control the on and off of the first and second switching tubes, that is, the other end SW (switch) of the inductor unit is switched between a state of being connected to the second bias voltage and a state of being connected to the first output end.

[0031] It should be understood that in some examples, the signal processing circuit can perform pulse width modulation on the sampling points of the input signal according to a first preset duty cycle to obtain a first PWM signal and a second PWM signal with matching timing. For example, the first PWM signal and the second PWM signal are timing-matched to cause the first switching transistor and the second switching transistor to alternately turn on and off, thereby alternatingly outputting high and low voltages at the first output terminal, forming an output conversion signal. That is, the boosted voltage of the first bias voltage is used as the high voltage, and the third bias voltage is used as the low voltage, or the third bias voltage is used as the high point voltage, and the stepped-down voltage of the first bias voltage is used as the low voltage.

[0032] Furthermore, the power output circuit 130 is connected to the other end of the inductor unit through the second switch tube, and the power output circuit 130 is used to output an output conversion signal of the input signal.

[0033] It should be understood that the power output circuit 130 includes a first output terminal (Vout1) and a second output terminal (not shown), and a capacitive load (Capacitive Load) such as a capacitor or a piezoelectric device can be connected between the first output terminal and the second output terminal. Generally speaking, a capacitive load refers to a load that exhibits capacitive characteristics when current passes through, that is, a capacitive load can store electrical energy and release this energy when needed. In some examples, one of the first output terminal and the second output terminal can be connected to the other end of the inductor unit through a second switching tube, and the other is connected to a third bias voltage, and the third bias voltage can have a voltage value independent of the first bias voltage and the second bias voltage.

[0034] exist Figure 1 In the embodiment, the waveform of the input signal may be a periodic waveform, and the periodic waveform may or may not have half-period symmetry.

[0035] In the capacitive load driving scheme of an embodiment of the present invention, the first and second switching transistors are alternately controlled to turn on and off using the converted first and second PWM signals, resulting in a power output circuit obtaining a voltage signal that matches the input signal waveform. Furthermore, when the first and second switching transistors are alternately controlled to turn on and off, the transient current in the inductor unit remains unchanged, generating a reverse electromotive force. Therefore, the power output circuit obtains a voltage signal that is a step-up or step-down of the first bias voltage based on the voltage difference between the second bias voltage and the first bias voltage. Consequently, the aforementioned switching transistors are reused for power conversion and waveform matching, reducing the number of switching transistors used in the power conversion device and facilitating device miniaturization.

[0036] Figure 2 Shown Figure 1 A further example of a power conversion device according to an embodiment of the present invention is provided. Figure 2 As shown, the power conversion circuit 110 further includes a third switch tube, and the power output circuit 130 includes a capacitive load. The two ends of the capacitive load serve as a first output end and a second output end. The first output end is connected to the other end of the inductor unit through the second switch tube, and the second output end is connected to the other end of the inductor unit through the third switch tube (the M3 tube is an example of the third switch tube). In addition, examples of the first PWM signal, the second PWM signal, and the third PWM signal are respectively Figure 2 PWM1 signal, PWM2 signal and PWM3 signal in.

[0037] exist Figure 2In an embodiment, the waveform of the input signal has half-cycle symmetry, that is, the first half-cycle and the second half-cycle are symmetrical about the center of the horizontal axis representing time. More specifically, for a sinusoidal input signal, the first half-cycle can also be a positive half-cycle, and the second half-cycle can be a negative half-cycle. This is because the signal amplitude of the sinusoidal waveform on the vertical axis representing the signal amplitude in the first half-cycle is positive, and the signal amplitude of the sinusoidal waveform on the vertical axis representing the signal amplitude in the second half-cycle is negative. Accordingly, the signal processing circuit 120 is configured to: perform pulse width modulation on the input signal in the first half-cycle of the entire cycle of the input signal to obtain first and second PWM signals with matching timing; and perform pulse width modulation on the input signal in the second half-cycle of the entire cycle of the input signal to obtain first and third PWM signals with matching timing. The first PWM signal and the third PWM signal are used to control the on and off of the first and third switching transistors, respectively.

[0038] That is, in the first half cycle, the other end (SW) of the inductor unit is switched between being connected to the second bias voltage and being connected to the first output terminal by the first and second PWM signals. In the second half cycle, the other end (SW) of the inductor unit is switched between being connected to the second bias voltage and being connected to the second output terminal by the first and third PWM signals.

[0039] In the embodiment of the present invention, the first and third switching transistors are alternately controlled to turn on and off using the converted first and third PWM signals, resulting in a power output circuit obtaining a voltage signal that matches the input signal waveform. Furthermore, when the first and third switching transistors are alternately controlled to turn on and off, the transient current in the inductor unit remains unchanged, generating a reverse electromotive force. Therefore, the power output circuit obtains a voltage signal that is a step-up or step-down of the first bias voltage based on the voltage difference between the second bias voltage and the first bias voltage. Consequently, the aforementioned switching transistors are reused for power conversion and waveform matching, reducing the number of switching transistors used in the power conversion device and facilitating device miniaturization.

[0040] In addition, the first PWM signal and the second PWM signal are time-matched in the first half-cycle, and the first PWM signal and the third PWM signal are time-matched in the second half-cycle, thereby achieving the conversion of reversely symmetrical waveform signals such as sine waveforms or triangular waveforms within the entire cycle. The first PWM signal controls the on and off of the first switching tube within the entire cycle, fully utilizing the waveform conversion capability of the first switching tube, thereby further saving the number of switching tubes used. For waveform signals such as sine waveforms, in some examples, the first half-cycle can be a positive half-cycle and the second half-cycle can be a negative half-cycle; alternatively, the first half-cycle can be a negative half-cycle and the second half-cycle can be a positive half-cycle.

[0041] In addition, in this embodiment, the first output end can be connected to the other end of the inductor unit through the second switch tube, and the second output end can be connected to the other end of the inductor unit through the third switch tube.

[0042] Without loss of generality, when the connection is made through a switch tube, the non-control terminal of the switch tube can be connected. In the example where the switch tube is a MOS tube, the source and drain are non-control terminals, and the gate is the control terminal. When the switch tube is a triode, one of the collector, emitter and base can be the control terminal, and the other two can be non-control terminals (first terminal and second terminal). For example, the first terminal of the second switch tube is connected to the first output terminal, and the second terminal of the second switch tube is connected to the other terminal of the inductor unit. For another example, the first terminal of the third switch tube is connected to the second output terminal, and the second terminal of the third switch tube is connected to the other terminal of the inductor unit.

[0043] That is, the first output end is connected to the other end of the inductor unit through the second switching tube, and the second output end is connected to the other end of the inductor unit through the third switching tube, wherein the power output circuit outputs an output conversion signal of the input signal between the first output end and the second output end.

[0044] In the connection relationship of this embodiment, the signal processing circuit receives an input signal at its input terminal and, after processing the input signal, outputs a first PWM signal, a second PWM signal, and a third PWM signal with timing matching from a first output terminal, a second output terminal, and a third output terminal (not shown). The first output terminal, the second output terminal, and the third output terminal are connected to the control terminal of the first switching transistor, the control terminal of the second switching transistor, and the control terminal of the third switching transistor, respectively.

[0045] In other specific examples, the signal processing circuit is configured to perform pulse width modulation on the input signal at sampling points in the first half cycle according to a first preset duty cycle to generate a first PWM signal and a second PWM signal that are time-matched in the first half cycle. For example, the first PWM signal and the second PWM signal are time-matched in the first half cycle to alternately turn the first switching transistor and the second switching transistor on and off, thereby alternately outputting a high and low voltage at the first output terminal, thereby forming an output conversion signal.

[0046] The signal processing circuit is further configured to perform pulse width modulation at sampling points in the second half of the cycle according to a second preset duty cycle, thereby generating a first PWM signal and a third PWM signal that are time-matched in the second half of the cycle, wherein the first preset duty cycle and the second preset duty cycle are complementary. For example, the first PWM signal and the third PWM signal are time-matched in the second half of the cycle, thereby alternatingly turning the first and third switching transistors on and off, thereby alternatingly outputting high and low voltages at the second output terminal, thereby forming an output conversion signal.

[0047] For another example, as an example of the first preset duty cycle and the second preset duty cycle complementing each other, the sum of the first preset duty cycle and the second preset duty cycle is 1. At this time, the amplitude of the output waveform in the first half cycle and the amplitude of the output waveform in the second half cycle are exactly symmetrical about the time axis.

[0048] In other specific examples, the third PWM signal is used to control the third switch to be in a normally off state during the second half-cycle, and the second PWM signal is used to control the second switch to be in a normally off state during the second half-cycle. Thus, while ensuring continuous output of the PWM signal, the second and third switches are in a normally off state during corresponding half-cycles. Furthermore, in this manner, the effect of the third bias voltage on the output conversion signal can be offset between the first and second output terminals.

[0049] In some other embodiments, the power output circuit further includes a fourth switch and a fifth switch, wherein the fourth switch is connected between the first output terminal and the third bias voltage, and the fifth switch is connected between the second output terminal and the third bias voltage. The signal processing circuit is further configured to generate a first commutation signal and a second commutation signal, wherein the first commutation signal is configured to control the fourth switch to be normally off in the first half cycle and normally on in the second half cycle, and wherein the second commutation signal is configured to control the fifth switch to be normally on in the first half cycle and normally off in the second half cycle. Thus, while ensuring continuous output of the commutation signal, the fourth and fifth switches are in either a normally off or normally on state in corresponding half cycles, thereby preventing the fourth and fifth switches from being simultaneously on or simultaneously off. Furthermore, the normally off and normally on states of the fourth and fifth switches in corresponding half cycles reduce the number of on-off operations of the switches in the power conversion circuit, thereby saving power consumption caused by the on-off operations.

[0050] The following will be combined Figure 3 and Figure 4 The signal conversion process of some embodiments of the present invention is described in detail. Figure 3 The following generally describes a circuit diagram applicable to the signal conversion process of this embodiment. Figure 4 The timing diagrams of the corresponding control signals are shown. Specifically, they will be described and illustrated in conjunction with the positive half cycle and the negative half cycle of the sinusoidal waveform signal.

[0051] It should be understood that Figure 3 In the example, the first switch tube is M1 tube, the second switch tube is M2 tube, the third switch tube is M3 tube, and the inductor unit is exemplarily implemented as an inductor L. In the first half cycle (for example, Figure 4 In the T1 period in the first half cycle, the other end (SW) of the inductor unit is switched between a state of being connected to the second bias voltage and a state of being connected to the first output end by the first PWM signal and the second PWM signal. Figure 4 In the T2 period in the inductor, the other end (SW) of the inductor unit is switched between a state of being connected to the second bias voltage and a state of being connected to the second output end by the first PWM signal and the third PWM signal.

[0052] In addition, the first bias voltage is VDD, and the second bias voltage is ground voltage. Figure 3 As shown, the first output terminal Vout1 outputs the HDP signal, and the second output terminal Vout2 outputs the HDN signal. Figure 3 and Figure 4 In the embodiment, taking a sinusoidal waveform (ie, sin waveform) signal as an example, a full cycle of the sinusoidal waveform can be divided into a first half cycle and a second half cycle, the first half cycle can be a positive half cycle, and the second half cycle can be a negative half cycle. For example, the positive half cycle and the negative half cycle are respectively Figure 4 The first half of each full cycle is continuous in time with the second half of that full cycle, and the second half of each full cycle is continuous in time with the first half of the next full cycle. For a sinusoidal signal, the first half of the cycle is the positive half, and the second half of the cycle is the negative half.

[0053] It should also be understood that in this embodiment, the power conversion device performs signal amplification processing, that is, the first bias voltage is greater than the second bias voltage, for example, the first bias voltage is VDD, and the second bias voltage is the ground voltage.

[0054] It should also be understood that Figure 3 In the example shown, the power output circuit includes a fourth switching tube and a fifth switching tube, M4 tube is an example of the fourth switching tube, and M5 tube is an example of the fifth switching tube. The LS1 signal is an example of a first commutation signal, which is used to control the on and off of M4, and the LS2 signal is an example of a second commutation signal, which is used to control the on and off of M5. The power output circuit also includes a first output terminal and a second output terminal, the first output terminal is used to output a high-voltage positive drive signal (High Side Drive Positive, HDP), and the second output terminal is used to output a high-voltage negative drive signal (High Side Drive Negative, HDN). In addition, the first output terminal and the second output terminal are used to connect a capacitive load such as a capacitor or a piezoelectric device, that is, the input signal is converted by the power conversion device and output from between the first output terminal and the second output terminal.

[0055] It should also be understood that the input signal is used as the signal to be converted. In the boost conversion mode, the voltage difference Vpp between the peak and valley values ​​of the input signal has a small amplitude, and the voltage difference Vpp between the peak and valley values ​​of the output conversion signal has a large amplitude. In addition, the signal processing circuit performs pulse width modulation on the input signal to obtain a first PWM signal, a second PWM signal, and a third PWM signal containing "input signal" information, for example, respectively. Figure 4 In addition, the first PWM signal, the second PWM signal, and the third PWM signal are used to control the M1 tube, the M2 tube, and the M3 tube respectively.

[0056] like Figure 4 As shown, the output conversion signal of the HDP signal during period T1 is a sinusoidal signal with a positive half-cycle, and the signal of the HDN signal during period T2 is a sinusoidal signal with a negative half-cycle. The sinusoidal signals of the positive and negative half-cycles are concatenated to produce a full-cycle sinusoidal signal. It should be understood that the polarity switching between the output conversion signal in the first and second half-cycles is performed by transistors M4 and M5.

[0057] It should be understood that although Figure 4 In the example, a schematic high level indicates that the switch is in the on state, and a schematic low level indicates that the switch is in the off state. For specific implementations of the switch, the on and off states of the switch have actual level states and are not necessarily schematic level states. For another example, in the first half of the cycle, the PWM1 signal and the PWM2 signal have opposite level states, while in the second half of the cycle, the PWM1 signal and the PWM3 signal have opposite level states. However, the above examples are for illustration and explanation purposes only and should not be construed as limiting the embodiments of the present invention.

[0058] Furthermore, during the T1 period, the amplification factor of the power conversion device is determined by the signal processing circuit, and corresponding PWM1 and PWM2 signals are generated. Figure 4As shown, during period T1, transistor M3 is normally off, transistor M4 is normally off via the LS1 signal, and transistor M5 is normally open via the LS2 signal. The signal processing circuit receives the positive half-cycle of a sinusoidal waveform signal as input and pulse-width modulates the sinusoidal waveform signal to generate PWM1 and PWM2 signals containing the input signal information. During period T1, the PWM1 and PWM2 signals control the on and off of transistors M1 and M2, respectively, amplifying the sinusoidal waveform signals to output the HDP signal. The HDN signal output during period T1 is a voltage of VS (an example of a third bias voltage). That is, transistor M5 is normally on during period T1, the HDN signal voltage during period T1 is VS, and the HDP signal during period T1 is an amplified positive half-cycle of the sinusoidal waveform signal. Accordingly, during the T1 period, the voltage difference Vp between the HDP signal and the HDN signal is a sinusoidal waveform signal of the positive half cycle (in the boost conversion mode, VDD is boosted to PVDD), which is loaded onto the capacitive load between the first output end of the HDP signal and the second output end of the HDN signal.

[0059] Without loss of generality, the third PWM signal is used to control the third switching transistor to be in a normally off state during the second half-cycle, and the second PWM signal is used to control the second switching transistor to be in a normally off state during the second half-cycle. Thus, while ensuring continuous output of the PWM signal, the second and third switching transistors are in a normally off state during corresponding half-cycles. Furthermore, in this manner, the effect of the third bias voltage on the output conversion signal can be offset between the first and second output terminals.

[0060] Furthermore, during the T2 period, the amplification factor of the power conversion device is determined by the signal processing circuit, and the corresponding PWM1 signal and PWM3 signal are generated. Figure 4As shown, at time T2, transistor M2 is in a normally closed state, transistor M5 is in a normally closed state controlled by the LS2 signal, and transistor M4 is in a normally open state controlled by the LS1 signal. The signal processing circuit receives the negative half-cycle of a sinusoidal waveform signal as an input signal and pulse-width modulates the sinusoidal waveform signal to generate PWM1 and PWM3 signals containing signal information about the input signal. During time T2, transistors M1 and M3 are controlled on and off by the PWM1 and PWM3 signals, respectively, amplifying the sinusoidal waveform signals to output the HDN signal. At this time, the HDP signal output during time T1 is VS (an example of a third bias voltage). That is, transistor M4 is in a normally open state during time T2, the HDP signal voltage during time T2 is VS, and the HDN signal during time T2 is the amplified negative half-cycle of the sinusoidal waveform signal. Correspondingly, the voltage difference Vp between the HDP signal and the HDN signal is a sinusoidal waveform signal of the negative half cycle (in the boost conversion mode, VDD is boosted to PVDD), which is loaded onto a capacitive load between the first output end of the HDP signal and the second output end of the HDN signal, thereby ensuring that the amplified sinusoidal waveform signal as the output conversion signal is in phase with the sinusoidal waveform signal as the input signal, thereby forming a full-cycle signal output. Exemplarily, the voltage difference Vpp between the peak and valley values ​​of the output conversion signal can reach a maximum of 2PVDD.

[0061] Without loss of generality, the third PWM signal is used to control the third switching transistor to be in a normally off state during the second half-cycle, and the second PWM signal is used to control the second switching transistor to be in a normally off state during the second half-cycle. Thus, while ensuring continuous output of the PWM signal, the second and third switching transistors are in a normally off state during corresponding half-cycles. Furthermore, in this manner, the effect of the third bias voltage on the output conversion signal can be offset between the first and second output terminals.

[0062] It should also be understood that the HDP signal is the output signal of the first output terminal, and the HDN signal is the output signal of the second output terminal. Without loss of generality, the signal processing circuit outputs a first commutation signal (e.g., LS1 signal) and a second commutation signal (e.g., LS2 signal) from the fourth output terminal and the fifth output terminal, respectively, and the first commutation signal and the second commutation signal are output to the control terminal of the fourth switch tube (e.g., M4) and the control terminal of the fifth switch tube (e.g., M5), respectively. For example, the fourth output terminal and the fifth output terminal (not shown) are connected to the control terminal of the fourth switch tube and the control terminal of the fifth switch tube, respectively. It should be understood that the normally closed state and the normally open state of the fourth switch tube and the fifth switch tube in the corresponding half cycle reduce the overall number of on-off operations of each switch tube in the power conversion circuit, saving power consumption caused by the on-off operation.

[0063] Alternatively, in the case of signal commutation, if transistor M3 is in the normally-off state during period T2, transistor M4 is in the normally-off state during period T2 controlled by signal LS1, and transistor M5 is in the normally-on state during period T2 controlled by signal LS2, the signal processing circuit pulse-width modulates the received negative half-cycle sinusoidal waveform signal to generate PWM1 and PWM2 signals, which are used to control transistors M1 and M2, respectively. The sinusoidal waveform signals are simultaneously amplified to HDP signals for output, with the HDN signal output being VS. In this case, the voltage difference between the HDP and HDN signals is equal to the positive half-cycle sinusoidal waveform signal, achieving inversion of the output conversion signal to the input signal in inverse conversion mode.

[0064] Without loss of generality, in the in-phase conversion mode, the first output terminal is connected to the positive terminal of the capacitive load, and the second output terminal is connected to the negative terminal of the capacitive load. In other words, the output terminal connected to the positive terminal of the capacitive load is considered the first output terminal, and the output terminal connected to the negative terminal of the capacitive load is considered the second output terminal.

[0065] Accordingly, in the inverting conversion mode, the first output terminal is connected to the negative terminal of the capacitive load, and the second output terminal is connected to the positive terminal of the capacitive load. In other words, the output terminal connected to the positive terminal of the capacitive load is considered the second output terminal, and the output terminal connected to the negative terminal of the capacitive load is considered the first output terminal.

[0066] In some other embodiments, the power conversion device 100 further includes a substrate selection circuit, at least one of the second switching transistor and the third switching transistor is a MOS transistor, and the substrate selection circuit is connected to the source, drain, and substrate of the MOS transistor, respectively. The substrate selection circuit connects the substrate to the drain or source, whichever has a higher voltage, when the MOS transistor is a P-type MOS transistor, and connects the substrate to the drain or source, whichever has a lower voltage, when the MOS transistor is an N-type MOS transistor. Figure 5 As shown in some examples, the substrate selection circuit is connected to the second switch transistor (e.g., M2) and the third switch transistor (e.g., M3). Without loss of generality, when any of the first, second, third, fourth, and fifth switch transistors is a MOS transistor, the substrate selection circuit can be connected to the source, drain, and substrate of the MOS transistor.

[0067] Specifically, if Figure 6 As shown, in the example where the MOS transistor is used as the M2 transistor or the M3 transistor, the substrate selection circuit includes a comparator. The first input terminal and the second input terminal of the comparator are connected to the drain and the source of the MOS transistor respectively, for example, Figure 6As shown, the comparator's non-inverting input terminal "+" is connected to the drain of the MOS transistor, and the comparator's inverting input terminal "-" is connected to the source of the MOS transistor. The comparator compares the drain voltage and the source voltage. If the MOS transistor is a P-type MOS transistor, the output terminal outputs the higher voltage between the drain and source. The substrate selection circuit connects the substrate to the higher voltage between the drain and source. If the MOS transistor is an N-type MOS transistor, the output terminal outputs the lower voltage between the drain and source. The substrate selection circuit connects the substrate to the lower voltage between the drain and source.

[0068] In other embodiments, any switch tube in the power conversion device (for example, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, and the fifth switch tube) can be implemented by connecting at least two MOS tubes in series. Figure 7A In the example, both M11 and M12 are P-type MOS tubes. The drain of M11 is connected to the drain of M12. The source of M11 and the source of M12 are the two non-control terminals of the switch. The gate of M11 and the gate of M12 can be used as the control terminals of the switch. Figure 7B In the example, both M13 and M14 are P-type MOS tubes. The source of M13 is connected to the source of M14. The drain of M13 and M14 serve as the two non-control terminals of the switch tube, and the gate of M13 and M14 can serve as the control terminals of the switch tube.

[0069] An embodiment of the present invention further provides an electronic device 800, which includes a power conversion device 100 and a capacitive load 810. It should be understood that the specific implementation in the electronic device can refer to the corresponding descriptions in the corresponding steps, modules or units in the embodiment of the power conversion device, and has corresponding beneficial effects, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the power conversion device in the electronic device can refer to the corresponding process description in the embodiment of the power conversion device, which will not be repeated here.

[0070] Thus far, specific embodiments of the present subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing may be advantageous.

[0071] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0072] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0073] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0074] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A power conversion device, characterized in that: include: A power conversion circuit, comprising a first switching tube, a second switching tube and an inductor unit, wherein one end of the inductor unit is connected to a first bias voltage, and the other end of the inductor unit is connected to a second bias voltage through the first switching tube; a signal processing circuit connected to the power conversion circuit, the signal processing circuit being configured to perform pulse width modulation on an input signal to obtain a first PWM signal and a second PWM signal with matching timings, and output the first PWM signal and the second PWM signal to the first switching transistor and the second switching transistor, respectively, to alternately control the on and off of the first switching transistor and the second switching transistor; a power output circuit, connected to the other end of the inductor unit through the second switch tube, the power output circuit being configured to output an output conversion signal of the input signal; The power conversion circuit further includes a third switch tube, and the power output circuit is connected to the other end of the inductor unit through the third switch tube; The signal processing circuit is used to: perform pulse width modulation on the input signal in the first half of the full cycle of the input signal to obtain a first PWM signal and a second PWM signal with timing matching; and perform pulse width modulation on the input signal in the second half of the full cycle of the input signal to obtain a first PWM signal and a third PWM signal with timing matching, wherein the first PWM signal and the third PWM signal are respectively used to control the on and off of the first switching tube and the third switching tube.

2. The power conversion device according to claim 1, wherein: The signal processing circuit is configured to: perform pulse width modulation on the input signal at sampling points of the first half cycle according to a first preset duty cycle to obtain first and second PWM signals that are time-matched in the first half cycle; and perform pulse width modulation at sampling points of the second half cycle according to a second preset duty cycle to obtain first and third PWM signals that are time-matched in the second half cycle, wherein the first preset duty cycle and the second preset duty cycle are complementary.

3. The power conversion device according to claim 1, wherein: The third PWM signal is used to control the third switch tube to be in a normally off state in the second half cycle, and the second PWM signal is used to control the second switch tube to be in a normally off state in the second half cycle.

4. The power conversion device according to claim 3, characterized in that: The power output circuit includes a first output end and a second output end, the first output end is connected to the other end of the inductor unit through the second switching tube, and the second output end is connected to the other end of the inductor unit through the third switching tube, wherein the power output circuit outputs an output conversion signal of the input signal between the first output end and the second output end.

5. The power conversion device according to claim 4, characterized in that: The power output circuit further includes a fourth switch tube and a fifth switch tube, the fourth switch tube is connected between the first output terminal and the third bias voltage, and the fifth switch tube is connected between the second output terminal and the third bias voltage; The signal processing circuit is also used to: generate a first commutation signal and a second commutation signal, the first commutation signal is used to control the fourth switch tube to be normally closed in the first half cycle and normally open in the second half cycle, wherein the second commutation signal is used to control the fifth switch tube to be normally open in the first half cycle and normally closed in the second half cycle.

6. The power conversion device according to claim 4, characterized in that: In the in-phase conversion mode, the first output terminal is connected to the positive pole of the capacitive load, and the second output terminal is connected to the negative pole of the capacitive load; in the in-phase conversion mode, the first output terminal is connected to the negative pole of the capacitive load, and the second output terminal is connected to the positive pole of the capacitive load.

7. The power conversion device according to claim 4, characterized in that: The power conversion device further includes a substrate selection circuit, at least one of the second switching transistor and the third switching transistor is a MOS transistor, and the substrate selection circuit is respectively connected to the source, drain and substrate of the MOS transistor; Among them, the substrate selection circuit connects the substrate to the one with a higher voltage between the drain and the source when the MOS transistor is a P-type MOS transistor, and connects the substrate to the one with a lower voltage between the drain and the source when the MOS transistor is an N-type MOS transistor.

8. The power conversion device according to any one of claims 1 to 7, characterized in that: In the boost conversion mode, the first bias voltage is greater than the second bias voltage.

9. An electronic device, characterized in that: include: Capacitive load; The power conversion device according to any one of claims 1 to 8, wherein the power conversion device provides an output conversion signal to the capacitive load.

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