Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises an array substrate, a dielectric layer, a binding terminal and a color filter layer. The dielectric layer is arranged on the array substrate. The binding terminal is arranged on the array substrate and located in a binding area. The binding terminal comprises a first binding metal layer for binding with external components. The color filter layer is arranged on a side of the dielectric layer away from the array substrate. The color filter layer comprises a black matrix layer and a color resistance layer distributed in the black matrix layer. The dielectric layer or the black matrix layer extends to the binding area and forms an isolation part. The isolation part covers the first binding metal layer. The first opening is arranged on the isolation part, and at least part of the first binding metal layer is exposed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Currently, the PLP (English full name: Pol less Panel, Chinese abbreviation: Polarization Film Free) technology can improve the bending performance of the display panel, and also can reduce power consumption, which is the development direction of display technology. The PLP technology uses a BM (Black Matrix) + CF (Color Filter) scheme to replace the function of the polarization film. In the process of making the touch layer of the PLP product, a binding metal layer is formed in the binding area at the same time, which is used to bind with external components; and the binding metal layer is usually a Ti / Al / Ti laminated metal structure; after the touch layer is made, the BM+CF structure needs to be made on the touch layer, and in the process of patterning the BM+CF, the developing solution will cause side etching to the binding metal layer in the binding area, and usually the Al layer in the binding metal layer is etched away, so that the lower part of the top Ti layer in the binding metal layer has no Al layer support; when passing through the air knife device later, the top Ti layer will peel off and scatter to the position of the external components, thereby causing a short circuit at the binding area, and further causing display function abnormalities and reducing product yield. SUMMARY

[0003] The embodiments of the present application provide a display panel and a display device, which form an isolation part in the binding area to cover the side of the binding terminal without adding additional film layers, thereby solving the problem of side etching of the binding terminal.

[0004] In a first aspect, the embodiments of the present application provide a display panel, comprising:

[0005] an array substrate, the array substrate is formed with a binding area at a position close to a side thereof;

[0006] a dielectric layer, disposed on the array substrate;

[0007] a binding terminal, disposed on the array substrate and located in the binding area, the binding terminal comprising a first binding metal layer for binding with external components; and

[0008] a color filter layer, disposed on a side of the dielectric layer away from the array substrate, the color filter layer comprising a black matrix layer and a color resist layer distributed in the black matrix layer;

[0009] wherein the dielectric layer or the black matrix layer extends to the binding area and forms an isolation part, the isolation part covers the first binding metal layer, and the isolation part is provided with a first opening and at least part of the first binding metal layer is exposed.

[0010] In an embodiment, the array substrate comprises a substrate, and a thin film transistor and a driving metal trace disposed on one side of the substrate, the driving metal trace is located in the binding area and disposed in the same layer as the gate of the thin film transistor, and an insulating layer covering the thin film transistor and the driving metal trace, the insulating layer is provided with a first via hole at a position corresponding to the binding area;

[0011] The first binding metal layer is located on the side of the insulating layer away from the substrate, and the first binding metal layer is electrically connected with the driving metal trace through the first via hole;

[0012] The periphery of the first opening is located outside the periphery of the first via hole, and the periphery of the first opening does not exceed the side edge of the first binding metal layer;

[0013] The dielectric layer is disposed on the side of the insulating layer away from the substrate and covers the thin film transistor.

[0014] In an embodiment, the periphery of the first opening is flush with the side edge of the first binding metal layer.

[0015] In an embodiment, the array substrate comprises a substrate, and a thin film transistor and an insulating layer disposed on one side of the substrate, and the insulating layer covers the thin film transistor;

[0016] The dielectric layer comprises a first flat layer and a second flat layer, the first flat layer is disposed on the side of the insulating layer away from the substrate and covers the thin film transistor, and the second flat layer is disposed on the side of the first flat layer away from the insulating layer;

[0017] The display panel further comprises a touch layer, and the touch layer is disposed between the first flat layer and the second flat layer;

[0018] The color filter layer is disposed on the side of the second flat layer away from the touch layer;

[0019] One of the black matrix layer, the first flat layer and the second flat layer extends to the binding area to form the isolation part.

[0020] In an embodiment, the binding terminal further comprises a second binding metal layer, and the second binding metal layer is disposed in the same layer as the source and drain of the thin film transistor;

[0021] The first binding metal layer is disposed on the side of the second binding metal layer away from the substrate, the first binding metal layer is disposed in the same layer as the touch layer, and the first binding metal layer is electrically connected with the second binding metal layer;

[0022] The black matrix layer extends to the binding area to form the isolation part.

[0023] In an embodiment, the first binding metal layer is arranged in the same layer as the source and drain of the thin film transistor.

[0024] The first planar layer or the second planar layer extends to the binding area to form the isolation part.

[0025] In an embodiment, the first binding metal layer is arranged as a multi-layer metal structure, and the first binding metal layer includes a first sub-layer, a second sub-layer and a third sub-layer arranged in layers, and the first sub-layer is arranged closest to one side of the display panel.

[0026] The first sub-layer and the third sub-layer are made of titanium, and the second sub-layer is made of aluminum.

[0027] In an embodiment, the array substrate includes a substrate, and a thin film transistor and an insulating layer arranged on one side of the substrate, and the insulating layer covers the thin film transistor.

[0028] At the position of the binding area, a groove is formed on the side of the insulating layer away from the substrate, and the groove is located at the periphery of the binding terminal.

[0029] The side edge of the first binding metal layer extends to the groove and forms an extension.

[0030] The isolation part is arranged on the side of the insulating layer away from the substrate.

[0031] The periphery of the first opening on the isolation part is located inside the periphery of the groove.

[0032] In an embodiment, the extension is flush with the periphery of the groove.

[0033] In a second aspect, the embodiments of the present application further provide a display device including the display panel.

[0034] Beneficial effects: the display panel provided by the present application is provided with a dielectric layer on the array substrate, and a binding terminal is arranged at the position corresponding to the binding area, the binding terminal comprising a first binding metal layer electrically connected to an external component; a color filter layer is sequentially arranged on the dielectric layer; the color filter layer comprises a black matrix layer and a color resistance layer; it can be known that in the process of manufacturing the color filter layer, the first binding metal layer will be side etched by the developing solution; the side of the first binding metal layer is coated by the isolation part, so as to avoid the side etching of the first binding metal layer by the developing solution; at the same time, since the isolation part is formed by extending to the binding area through the dielectric layer or the black matrix layer, the process of additional film layer is not needed, and the process difficulty is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0035] The technical solutions and other beneficial effects of the present application will be apparent from the following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

[0036] Figure 1 The first film layer diagram of the display panel provided by the embodiment of the present application;

[0037] Figure 2 The second film layer diagram of the display panel provided by the embodiment of the present application;

[0038] Figure 3 The third film layer diagram of the display panel provided by the embodiment of the present application;

[0039] Figure 4 The fourth film layer diagram of the display panel provided by the embodiment of the present application;

[0040] Figure 5 The fifth film layer diagram of the display panel provided by the embodiment of the present application;

[0041] Figure 6 The schematic diagram of the display device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0043] In the description of the application, it needs to be understood that the terms "upper", "lower", "front", "back", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the application and simplifying the description, and cannot be understood as limiting the application. And, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature only means that the first feature is higher in height than the second feature or the first feature is lower in height than the second feature, and does not mean a direct connection relationship.

[0044] In addition, the terms "first", "second" are only for descriptive purposes, and the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.

[0045] In the description of the application, it needs to be understood that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be broadly understood, and the connection method is not specifically limited. For ordinary skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific situation.

[0046] The following disclosure provides many different embodiments for implementing the different structures of the application. In order to simplify the disclosure of the application, the components and arrangements of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the application. In addition, the application provides various specific examples of processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0047] In the first aspect, referring to Figure 1 and Figure 6 , the embodiments of the application provide a display panel 100, which comprises an array substrate 1, a dielectric layer 2, a binding terminal 3 and a color filter layer 4; the array substrate 1 is formed with a binding area BA at a position close to one side thereof; the dielectric layer 2 is arranged on the array substrate 1; the binding terminal 3 is arranged on the array substrate 1 and located in the binding area BA, and the binding terminal 3 comprises a first binding metal layer 31 for binding with external components; the color filter layer 4 is arranged on the side of the dielectric layer 2 away from the array substrate 1, and the color filter layer 4 comprises a black matrix layer 41 and a color resistance layer 42 distributed in the black matrix layer 41; the dielectric layer 2 or the black matrix layer 41 extends to the binding area BA and forms an isolation part 5, the isolation part 5 covers the first binding metal layer 31, and the first opening 51 is arranged on the isolation part 5 and at least part of the first binding metal layer 31 is exposed.

[0048] The display panel 100 provided in the present application is provided with a dielectric layer 2 on the array substrate 1, and a binding terminal 3 is provided at a position corresponding to the binding area BA, the binding terminal 3 comprising a first binding metal layer 31 electrically connected to an external component; a color filter layer 4 is sequentially provided on the dielectric layer 2; the color filter layer 4 comprises a black matrix layer 41 and a color resist layer 42; it can be known that, in the process of manufacturing the color filter layer 4, the developing solution will cause side etching to the first binding metal layer 31; the side part of the first binding metal layer 31 is covered by the isolation part 5, so as to avoid side etching of the developing solution to the first binding metal layer 31; at the same time, since the isolation part 5 is formed by extending through the dielectric layer 2 or the black matrix layer 41 to the binding area BA, no additional film layer process is needed, and the process difficulty is reduced.

[0049] The display panel 100 is not specifically limited in the present application. The display panel 100 can be an LCD panel, an OLED panel, a Mini-LED panel, a Micro-LED panel, etc. The technical solutions of the present application will be introduced below taking the OLED panel as an example, which should not be understood as a limitation on the type of the display panel 100.

[0050] It can be known that the display panel 100 has a display area AA and a non-display area (not shown in the figure) located outside the display area AA, the binding area BA is provided in the non-display area, and the color filter layer is located in the display area AA.

[0051] In the binding area BA, the array substrate 1 is provided with a binding terminal 3, and the first binding metal layer 31 of the binding terminal 3 is used for binding connection with an external component, so as to realize input of a driving signal or a power supply to a display device. The external component is not specifically limited in the present application, and the external component can be a driving chip, a flexible printed circuit board, etc., as long as it can provide a driving signal or a power supply for the display panel 100. The binding mode of the binding terminal 3 and the external component is not specifically limited in the present application, and the binding terminal 3 can be bound with the external component by using ACF (English full name: Anisotropic Conductive Film, Chinese abbreviation: anisotropic conductive adhesive film), but is not limited thereto.

[0052] The array substrate 1 comprises a substrate 11 and a thin film transistor layer 12 provided on one side of the substrate 11, the thin film transistor layer 12 comprising a thin film transistor 121 located in the display area AA, and an insulating layer covering the thin film transistor 121, the insulating layer being located in the display area AA and the binding area BA.

[0053] In an embodiment of the present application, the array substrate 1 comprises an active layer 1211, a gate insulating layer 122, a first metal layer, an interlayer insulating layer 123 and a second metal layer; the active layer 1211 is disposed on one side of the substrate 11 and located in the display area AA; the gate insulating layer 122 is disposed on one side of the substrate 11, the gate insulating layer 122 is located in the display area AA and the binding area BA, and the gate insulating layer 122 covers the active layer 1211; the first metal layer is disposed on the side of the gate insulating layer 122 away from the substrate 11, and the first metal layer comprises a gate 1212 located in the display area AA and a driving metal wire 1213 located in the binding area BA; the interlayer insulating layer 123 is disposed on the side of the gate insulating layer 122 away from the substrate 11, the interlayer insulating layer 123 is located in the display area AA and the binding area BA, and the interlayer insulating layer 123 covers the gate 1212; the second metal layer is disposed on the side of the interlayer insulating layer 123 away from the gate insulating layer 122, and the second metal layer comprises a source 1214 and a drain 1215 located in the display area AA, and the source 1214 and the drain 1215 are electrically connected to the conductor part of the active layer 1211 through a second via.

[0054] That is, the active layer 1211, the gate 1212, the source 1214 and the drain 1215 constitute the thin film transistor 121; the gate insulating layer 122 and the interlayer insulating layer 123 constitute the insulating layer; the dielectric layer 2 is disposed on the side of the interlayer insulating layer 123 away from the gate insulating layer 122 and covers the second metal layer; and the first binding metal layer 31 is disposed on the side of the interlayer insulating layer 123 away from the gate insulating layer 122.

[0055] In an embodiment of the present application, the dielectric layer 2 comprises a first flat layer 21 and a second flat layer 22, the first flat layer 21 is disposed on the side of the interlayer insulating layer 123 away from the gate insulating layer 122, and the first flat layer 21 covers the thin film transistor 121 for packaging and planarizing the array substrate 1.

[0056] And the display panel 100 further comprises a touch layer 6, the touch layer 6 is arranged on the side of the first flat layer 21 away from the array substrate 1, the touch layer 6 is located in the display area AA; the second flat layer 22 is arranged on the side of the first flat layer 21 away from the array substrate 1, the second flat layer 22 covers the touch layer 6; the color filter layer 4 is arranged on the side of the second flat layer 22 away from the first flat layer 21; the color filter layer 4 is arranged on the dielectric layer 2 to form a COE (English full name: CF on Encapsulation, Chinese abbreviation: color filter on encapsulation) structure, thereby replacing the polarizer, which is conducive to reducing the power consumption of the display panel 100, improving the color gamut, thinning the thickness, and improving the bending performance. One of the black matrix layer 41, the first flat layer 21 and the second flat layer 22 extends to the binding area BA to form the isolation part 5, thereby not increasing the film layer process, reducing the process difficulty.

[0057] The present application does not make specific restrictions on the touch layer 6. The touch layer 6 can be a self-capacitive touch or a mutual-capacitive touch. For example, when the touch layer 6 is set as a mutual-capacitive touch, the touch layer 6 includes a touch driving layer and a touch sensing layer, and a capacitor is formed at the overlapping part of the touch driving layer and the touch sensing layer. In an embodiment, the orthographic projection of the touch layer 6 on the color filter layer 4 is located within the range of the black matrix layer 41, so that the touch layer 6 does not affect the aperture ratio of the display panel 100.

[0058] As mentioned above, the array substrate 1 comprises a plurality of thin film transistors 121; the first flat layer 21 encapsulates the plurality of thin film transistors 121; the display panel 100 further comprises a light emitting functional layer 8, the light emitting functional layer 8 is arranged on the side of the first flat layer 21 away from the array substrate 1, the light emitting functional layer 8 comprises a plurality of light emitting units 81, the plurality of light emitting units 81 can include red light emitting units, green light emitting units, blue light emitting units, the plurality of light emitting units 81 can display corresponding colors, thereby realizing color picture display. The light emitting unit 81 can include a stacked anode layer, a light emitting material layer, and a cathode layer; but not limited thereto. And the thin film transistor 121 corresponds to one of the light emitting units 81, and is electrically connected with the corresponding light emitting unit 81, for driving the light emitting unit 81 to emit light.

[0059] The display panel 100 further comprises a third planar layer 91 and a first insulating layer 92. The third planar layer 91 is located in the display area AA and covers the light-emitting functional layer 8. The first insulating layer 92 is arranged on a side of the third planar layer 91 away from the light-emitting functional layer 8. The touch layer 6 is arranged on a side of the first insulating layer 92 away from the third planar layer 91. The second planar layer 22 is arranged on a side of the first insulating layer 92 away from the third planar layer 91, and covers the touch layer 6. The color filter layer 4 is arranged on a side of the second planar layer 22 away from the first insulating layer 92.

[0060] Please refer to Figures 1 to 4 In the embodiment of the present application, the interlayer insulating layer 123 is provided with a first via hole 124 at a position corresponding to the binding area BA. The first binding metal layer 31 is arranged on a side of the interlayer insulating layer 123 away from the gate insulating layer 122, and is electrically connected to the driving metal trace 1213 through the first via hole 124. The periphery of the first opening 51 is located outside the periphery of the first via hole 124, and the periphery of the first opening 51 does not exceed the side of the first binding metal layer 31.

[0061] It can be understood that, since the first binding metal layer 31 is electrically connected to the driving metal trace 1213 through the first via hole 124, the first binding metal layer 31 will be lowered along the film layer settlement terrain at a position corresponding to the first via hole 124. In order to avoid the first binding metal layer 31 from being difficult to bind with external components due to only the settlement position being exposed, the periphery of the first opening 51 is located outside the periphery of the first via hole 124, which can increase the exposed area of the first binding metal layer 31 from the first opening 51, so that the first binding metal layer 31 is more easily bound with external components. At the same time, the periphery of the first opening 51 does not exceed the side of the first binding metal layer 31, which can ensure that the isolation portion 5 covers the side of the first binding metal layer 31, thereby further avoiding side etching of the first binding metal layer 31.

[0062] The present application does not specifically limit the size of the first opening 51. Please refer to Figure 2 , Figure 2For the second embodiment of the present application, the periphery of the first opening 51 is flush with the side of the first binding metal layer 31. At this time, the area of the exposed region of the first binding metal layer 31 is maximized, making it most convenient for binding with external components; at the same time, the isolation portion 5 is in contact with the side of the first binding metal layer 31, and can also ensure that the isolation portion 5 isolates the side of the first binding metal layer 31, thereby avoiding side etching of the side of the first binding metal layer 31 due to contact with the developer.

[0063] Please refer to Figure 1 , Figure 1 For the first embodiment of the present application, the binding terminal 3 further includes a second binding metal layer 32, which is arranged in the same layer as the source 1214 and the drain 1215 of the thin film transistor 121; the first binding metal layer 31 is arranged on the side of the second binding metal layer 32 away from the substrate 11, and is arranged in the same layer as the touch layer 6; the first binding metal layer 31 is electrically connected to the second binding metal layer 32; and the black matrix layer 41 extends to the binding area BA to form the isolation portion 5.

[0064] In the first embodiment of the present application, the binding terminal 3 includes a first binding metal layer 31 and a second binding metal layer 32, the drive metal trace 1213 is arranged in the same layer as the gate 1212 of the thin film transistor 121, the second binding metal layer 32 is arranged in the same layer as the source 1214 and the drain 1215 of the thin film transistor 121, the second binding metal layer 32 is electrically connected to the drive metal trace 1213 through a first via 124, the array substrate 1 further includes a second insulating layer 33, which is arranged on the side of the interlayer insulating layer 123 away from the gate insulating layer 122, and is arranged in the same layer as the first insulating layer 92; the second insulating layer 33 covers the second binding metal layer 32, and the first insulating layer 92 is provided with a second opening and an exposed part of the second binding metal layer 32; the first binding metal layer 31 is arranged on the side of the first insulating layer 92 away from the interlayer insulating layer 123, and is arranged in the same layer as the touch layer 6; the first binding metal layer 31 is electrically connected to the second binding metal layer 32 from the second opening.

[0065] It can be understood that the arrangement of the second binding metal layer 32 can raise the level of the first binding metal layer 31, facilitating the binding of the first binding metal layer 31 with external components; and the electrical connection of the second binding metal layer 32 to the first binding metal layer 31 can increase the cross-sectional area of the binding terminal 3 and reduce the resistance.

[0066] As described above, the second planar layer 22 is arranged on the side of the first insulating layer 92 away from the third planar layer 91, and covers the touch layer 6; the color filter layer 4 is arranged on the side of the second planar layer 22 away from the first insulating layer 92; when the color filter layer 4 is manufactured: step one, a black photoresist layer is deposited, covering the second planar layer 22 and the second insulating layer 33, and the black photoresist layer is subjected to a patterning process, thereby correspondingly forming the black matrix layer 41 on the second planar layer 22 and the isolation portion 5 on the second insulating layer 33; step two, a color resist layer 42 is manufactured in the pixel area divided by the black matrix layer 41; since in step one, the side portion of the first binding metal layer 31 has already covered the black photoresist pattern, therefore when the color resist layer 42 is manufactured in step two, the black photoresist will isolate the side portion of the first binding metal layer 31, thereby avoiding side etching of the first binding metal layer 31 due to contact with the developing solution.

[0067] Please refer to Figure 3 , Figure 3 In a third embodiment of the present application, the first binding metal layer 31 is arranged in the same layer as the source electrode 1214 and the drain electrode 1215 of the thin film transistor 121; the first planar layer 21 extends to the binding area BA to form the isolation portion 5.

[0068] In the third embodiment of the present application, the difference from the first embodiment is that the first binding metal layer 31 is arranged in the same layer as the source electrode 1214 and the drain electrode 1215 of the thin film transistor 121; that is, the second metal layer is deposited on the side of the interlayer insulating layer 123 away from the gate insulating layer 122, the second metal layer is located in the display area AA and the binding area BA, the second metal layer is subjected to a patterning process, thereby forming the source electrode 1214 and the drain electrode 1215 at the position corresponding to the display area AA, and forming the first binding metal layer 31 at the position corresponding to the binding area BA; the first planar layer 21 is arranged on the side of the interlayer insulating layer 123 away from the gate insulating layer 122, and when the first planar layer 21 is manufactured, the first planar layer 21 is located in the display area AA and the binding area BA, and the isolation portion 5 is formed at the position corresponding to the binding area BA; in this way, not only can the side portion of the first binding metal layer 31 be coated, but also no new film layer is added, and no additional film layer process is needed, thereby reducing the process difficulty.

[0069] Please refer to Figure 4 , Figure 4For the fourth embodiment of the present application, the first binding metal layer 31 is arranged in the same layer as the source 1214 and the drain 1215 of the thin film transistor 121; the second planar layer 22 extends to the binding area BA to form the isolation part 5.

[0070] In the fourth embodiment of the present application, the same as the third embodiment is that the second metal layer is deposited on the side of the interlayer insulating layer 123 away from the gate insulating layer 122, the second metal layer is located in the display area AA and the binding area BA, the second metal layer is patterned to form the source 1214 and the drain 1215 corresponding to the display area AA and the first binding metal layer 31 corresponding to the binding area BA.

[0071] But different from the third embodiment is that the first planar layer 21 is arranged on the side of the interlayer insulating layer 123 away from the gate insulating layer 122; the touch layer 6 is arranged on the first planar layer 21, and the second planar layer 22 is arranged on the first planar layer 21, covering the touch layer 6; the second planar layer 22 is located in the display area AA and the binding area BA when the second planar layer 22 is formed, and the isolation part 5 is formed at the binding area BA; in this way, not only the side of the first binding metal layer 31 can be covered, but also no new film layer is added, and no additional film layer process is needed, reducing the process difficulty.

[0072] The present application does not make specific restrictions on the first binding metal layer 31. The first binding metal layer 31 can be a single-layer metal structure or a multi-layer metal structure, for example, the first binding metal layer 31 can be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0073] In an embodiment, the first binding metal layer 31 is arranged as a multi-layer metal structure, the first binding metal layer 31 includes a first sub-layer 311, a second sub-layer 312 and a third sub-layer 313 arranged in layers, the first sub-layer 311 is arranged closest to one side of the display panel 100; the first sub-layer 311 and the third sub-layer 313 are made of metal titanium, and the second sub-layer 312 is made of metal aluminum.

[0074] Please refer to Figure 5 , Figure 5For the fifth embodiment of the present application, the array substrate 1 comprises a substrate 11, and a thin film transistor 121 and an insulating layer disposed on one side of the substrate 11, the insulating layer covering the thin film transistor 121; at the position of the binding area BA, a groove 7 is formed on the side of the insulating layer away from the substrate 11, the groove 7 being located at the periphery of the binding terminal 3; the side edge of the first binding metal layer 31 extends to stop in the groove 7 and forms an extension 31a; the isolation part 5 is disposed on the side of the insulating layer away from the substrate 11; wherein the periphery of the first opening 51 on the isolation part 5 is located inside the periphery of the groove 7.

[0075] In the fifth embodiment of the present application, the difference from the above embodiments is that the side of the insulating layer away from the substrate 11 is formed with a groove 7, and the side edge of the first binding metal layer 31 extends to stop in the groove 7 and forms an extension 31a; in this way, the position of the side of the first binding metal layer 31 can be lowered, facilitating the formation and covering of the isolation part 5; at the same time, since the periphery of the first opening 51 on the isolation part 5 is located inside the periphery of the groove 7, the isolation part 5 can cover the extension 31a, thereby further ensuring that the isolation part 5 covers the side of the first binding metal layer 31.

[0076] In addition, the extension 31a is flush with the periphery of the groove 7; that is, the first binding metal layer 31 is completely embedded in the groove 7 at the position of the extension 31a, so that the surface of the isolation part 5 is planarized, further facilitating the formation and covering of the isolation part 5.

[0077] In a second aspect, the embodiments of the present application also provide a display device. The display device comprises a display panel 100. It should be noted that the display panel 100 is provided as the above-mentioned display panel 100, that is, the display panel 100 comprises all the technical features of the above-mentioned display panel 100, and the display device comprises all the embodiments of the above-mentioned display panel 100, and thus has all the technical effects of the above-mentioned embodiments, which will not be described here.

[0078] The above has described in detail the display panel and display device provided by the embodiments of the present application. The principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions and core ideas of the present application; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, include: An array substrate, wherein a bonding region is formed near one side thereof; A dielectric layer is disposed on the array substrate; A bonding terminal is disposed on the array substrate and located in the bonding area, the bonding terminal including a first bonding metal layer for bonding with external components; as well as, A color filter layer is disposed on the side of the dielectric layer away from the array substrate, and the color filter layer includes a black matrix layer and a color resist layer distributed within the black matrix layer; The black matrix layer extends to the bonding area and forms an isolation portion. The isolation portion has a first opening and exposes at least a portion of the first bonding metal layer. The isolation portion is attached to the side of the first bonding metal layer, and the periphery of the first opening is flush with the side of the first bonding metal layer.

2. The display panel as described in claim 1, characterized in that, The array substrate includes a substrate, a thin-film transistor, a driving metal line, and an insulating layer disposed on one side of the substrate. The driving metal line is located in the bonding region and is disposed on the same layer as the gate of the thin-film transistor. The insulating layer covers the thin-film transistor and the driving metal line. The insulating layer has a first via at a position corresponding to the bonding region. The first bonding metal layer is located on the side of the insulating layer away from the substrate, and the first bonding metal layer is electrically connected to the driving metal trace through the first via. The periphery of the first opening is located outside the periphery of the first via, and the periphery of the first opening does not extend beyond the side of the first bonding metal layer. The dielectric layer is disposed on the side of the insulating layer away from the substrate and covers the thin-film transistor.

3. The display panel as described in claim 1, characterized in that, The array substrate includes a substrate, a thin-film transistor and an insulating layer disposed on one side of the substrate, wherein the insulating layer covers the thin-film transistor; The dielectric layer includes a first planarization layer and a second planarization layer. The first planarization layer is disposed on the side of the insulating layer away from the substrate and covers the thin-film transistor. The second planarization layer is disposed on the side of the first planarization layer away from the insulating layer. The display panel further includes a touch layer, which is disposed between the first planarization layer and the second planarization layer; The color filter layer is disposed on the side of the second planar layer away from the touch layer; Wherein, one of the black matrix layer, the first flat layer, and the second flat layer extends to the binding region to form the isolation section.

4. The display panel as described in claim 3, characterized in that, The bonding terminal further includes a second bonding metal layer, which is disposed on the same layer as the source and drain of the thin film transistor; The first bonding metal layer is disposed on the side of the second bonding metal layer away from the substrate. The first bonding metal layer is disposed in the same layer as the touch layer, and the first bonding metal layer and the second bonding metal layer are electrically connected. The black matrix layer extends to the binding area to form the isolation section.

5. The display panel as described in claim 3, characterized in that, The first bonding metal layer is disposed on the same layer as the source and drain of the thin-film transistor; The first flat layer or the second flat layer extends to the bonding area to form the isolation portion.

6. The display panel as described in claim 1, characterized in that, The first bonding metal layer is configured as a multi-layer metal structure, and the first bonding metal layer includes a first sub-layer, a second sub-layer and a third sub-layer stacked together, with the first sub-layer disposed on the side closest to the display panel; The first sublayer and the third sublayer are made of titanium, and the second sublayer is made of aluminum.

7. The display panel as described in claim 1, characterized in that, The array substrate includes a substrate, a thin-film transistor and an insulating layer disposed on one side of the substrate, wherein the insulating layer covers the thin-film transistor; At the location of the bonding area, a groove is formed on the side of the insulating layer away from the substrate, and the groove is located around the bonding terminal; The side of the first bonding metal layer extends to stop within the groove and forms an extension segment; The isolation portion is disposed on the side of the insulating layer away from the substrate; The periphery of the first opening on the isolation part is located inside the periphery of the groove opening.

8. The display panel as described in claim 7, characterized in that, The extension section is flush with the periphery of the groove opening.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1-8.

Images