Data processing method, hardware accelerator, integrated circuit, and server

Abstract

The application relates to the technical field of data transmission, and discloses a data processing method, a hardware accelerator, an integrated circuit and a server. The method is applied to a hardware accelerator with a conversion unit, a first arbitration unit, a cache unit and an instruction execution unit. The method comprises the following steps: the conversion unit receives an operation instruction sent by a microprocessor; the first arbitration unit arbitrates the operation instruction; the cache unit caches the operation instruction, and sends the operation instruction to the instruction execution unit based on the arbitration result of the first arbitration unit; the instruction execution unit performs data logic processing on the operation instruction that has passed the arbitration, and obtains completion information; and the first arbitration unit feeds back the completion information to the processor. Therefore, when multiple operation instructions that are simultaneously concurrent are received, the arbitration and buffering and other methods can effectively avoid the problems of long delay between the execution of operation commands of multiple microcontrollers and poor performance caused by unreasonable processing of multiple operation instructions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, in particular to a data processing method, a hardware accelerator, an integrated circuit and a server. BACKGROUND

[0002] An SSD (Solid State Drive) master control chip needs to use some hardware accelerators to assist an MCU (Microcontroller Unit) to complete some data reading, operation, deletion, migration and the like. In the related art, a hardware accelerator design scheme usually adopts a single working engine to process commands issued by multiple MCUs, and cannot realize processing of multiple MCU parallel commands, thereby causing large delay between multiple MCU command executions of the SSD master control chip and poor performance. SUMMARY

[0003] Therefore, the present application provides a data processing method, a hardware accelerator, an integrated circuit and a server to solve the problem that the hardware accelerator design scheme usually adopts a single working engine to process commands issued by multiple MCUs, and cannot realize processing of multiple MCU parallel commands, thereby causing large delay between multiple MCU command executions of the SSD master control unit and poor performance.

[0004] In a first aspect, the present application provides a data processing method applied to a hardware accelerator, the hardware accelerator having a conversion unit, a first arbitration unit, a cache unit and an instruction execution unit, and the method comprises the following steps:

[0005] The conversion unit receives an operation instruction sent by a microprocessor;

[0006] The first arbitration unit arbitrates the operation instruction;

[0007] The cache unit caches the operation instruction, and sends the operation instruction to the instruction execution unit based on an arbitration result of the first arbitration unit;

[0008] The instruction execution unit performs data logic processing on the operation instruction passed through arbitration to obtain completion information;

[0009] The first arbitration unit feeds back the completion information to the processor.

[0010] The data processing method provided in this invention receives operation instructions sent by the microprocessor through a conversion unit of a hardware accelerator configured between the microprocessor and the memory. The first arbitration unit arbitrates the operation instructions, a caching unit caches the operation instructions, and based on the arbitration result of the first arbitration unit, sends the operation instructions to an instruction execution unit. The instruction execution unit of the hardware accelerator performs data logic processing on the arbitrated operation instructions to obtain completion information, which is then fed back to the processor by the first arbitration unit. Therefore, when multiple operation instructions are received concurrently from multiple microcontrollers, arbitration and buffering effectively avoid problems such as large delays and poor performance caused by improper processing of multiple operation instructions, significantly improving the user experience.

[0011] In one optional implementation, the conversion unit receives operation instructions sent by the microprocessor, including:

[0012] The conversion unit receives operation instructions sent by the microprocessor through the first central interconnection unit and performs interface bit-width conversion on the operation instructions;

[0013] The converted operation instructions are sent to the first arbitration unit.

[0014] The data processing method provided in this embodiment of the invention performs bit-width conversion on operation instructions through the conversion unit of a hardware accelerator, converting the operation instructions into data and instructions that conform to the data processing interface protocol of the hardware accelerator, thereby achieving fast and accurate conversion of operation instructions, effectively performing operations such as caching of operation instructions, and realizing parallel processing of multiple operation instructions.

[0015] In one alternative implementation, arbitrating the operation command includes:

[0016] Arbitration is performed on operation instructions issued simultaneously by multiple microprocessors based on pre-determined data transmission rules;

[0017] The cache unit will send the operation instructions to the instruction execution unit through arbitration.

[0018] In one optional implementation, sending the operation instructions via arbitration to the instruction execution unit includes:

[0019] Based on the arbitration result, the cache unit controls the sending of a set of operation instructions to the instruction execution unit every clock cycle.

[0020] The data processing method provided in this invention, based on the arbitration result, controls the sending of a set of operation instructions to the instruction execution unit every clock cycle. Therefore, by achieving reasonable caching of multiple operation instructions, the orderliness of operation instruction execution is effectively improved, and the execution efficiency of multiple operation instructions is increased.

[0021] In one alternative implementation, the hardware accelerator is connected between the microprocessor and the memory, and the instruction execution unit performs data logic processing on the arbitrated operation instructions to obtain completion information, including:

[0022] If the instruction execution unit determines that the operation instruction requires the execution of the first read operation, it sends a first read operation request to the atomic control unit.

[0023] The atomic control unit receives the first read data fed back by the atomic control unit, which obtains the first read data from the memory in response to the first read operation.

[0024] The operation instructions are executed based on the first read data, and the completion information is obtained.

[0025] The data processing method provided in this embodiment of the invention involves an instruction execution unit sending a first read operation request to an atomic control unit when it determines that an operation instruction requires a first read operation. The instruction execution unit then receives first read data from the atomic control unit in response to the first read operation. The atomic control unit retrieves the first read data from memory and executes the operation instruction based on the first read data to obtain completion information. Through the atomic control unit, multiple MCUs can operate simultaneously, cache multiple commands, perform atomic operations on data at a specified address, and return completion information, thus achieving the high-performance data processing requirement of multiple microprocessors simultaneously performing atomic operations on data at a specified address.

[0026] In one alternative implementation, the atomic control unit obtains the first read data from the memory by the following operation:

[0027] Send the first read operation to the second arbitration unit;

[0028] The second arbitration unit polls and arbitrates multiple read operations based on the number of read operations under the current clock.

[0029] The second arbitration unit, based on the successful arbitration of the first read operation, executes the first read operation and retrieves the first read data from the memory;

[0030] The second arbitration unit sends the first read data to the atomic control unit.

[0031] The data processing method provided in this embodiment of the invention effectively achieves atomic control of data operations at an address by controlling multiple first read operations through an atomic control unit, thus avoiding problems such as conflicts between multiple operations.

[0032] In one optional implementation, the instruction execution unit performs data logic processing on the operation instructions through arbitration to obtain completion information, including:

[0033] When the instruction execution unit determines that the operation instruction does not require a read operation or has already received the first read data obtained by performing the first read operation, it performs data logic processing in response to the operation instruction to obtain logic processing data.

[0034] If it is determined that a first write operation needs to be performed on the logically processed data, the first write operation is sent to the atomic control unit.

[0035] Receive the first write result of the first write operation from the atomic control unit, and obtain the completion information based on the first write result.

[0036] The data processing method provided in this embodiment of the invention involves an instruction execution unit performing data logic processing in response to an operation instruction when it determines that an operation instruction does not require a read operation or has already received the first read data obtained from the first read operation. This process yields logically processed data. If it determines that a first write operation needs to be performed on the logically processed data, the instruction execution unit sends the first write operation to the atomic control unit, receives the first write result from the atomic control unit, and obtains completion information based on the first write result. Thus, the instruction execution unit executes multiple operation instructions sent by multiple microcontrollers in an orderly manner, effectively reducing the data processing pressure on the microcontrollers, significantly reducing the latency of the microcontrollers' operation instructions, and effectively improving the performance of the microcontrollers.

[0037] In one alternative implementation, the atomic control unit obtains the first write result through the following operation:

[0038] Send the first write operation to the second arbitration unit;

[0039] The second arbitration unit polls and arbitrates multiple write operations based on the number of write operations under the current clock.

[0040] The second arbitration unit, based on the successful arbitration of the first write operation, executes the first write operation and writes logical processing data into the memory;

[0041] The second arbitration unit sends the first write result back to the atomic control unit;

[0042] The first write result is used to characterize the result of the first write operation.

[0043] In one optional implementation, the first arbitration unit completes the feedback of information to the microprocessor, including:

[0044] The instruction execution unit sends a completion message to the first arbitration unit;

[0045] The first arbitration unit, based on the completion information, arbitrates and adds the completion information to the first-in-first-out queue;

[0046] The microprocessor reads the completed information using a first-in-first-out queue.

[0047] In a second aspect, the present invention provides a hardware accelerator connected between a microprocessor and a memory, for performing data processing in response to operation instructions sent by the microprocessor, the hardware accelerator comprising:

[0048] The conversion unit, connected between the microprocessor and the first arbitration unit, is used to receive operation instructions sent by the microprocessor;

[0049] The first arbitration unit, connected between the conversion unit and the instruction execution unit, is used to arbitrate operation instructions;

[0050] The instruction execution unit, connected between the first arbitration unit and the memory, is used to perform data logic processing on the operation instructions that have passed arbitration to obtain completion information;

[0051] The first arbitration unit is also used to feed back completion information to the microprocessor.

[0052] In one alternative implementation, the hardware accelerator further includes: a first central interconnect unit connected between the microprocessor and the conversion unit, for forwarding operation instructions to the conversion unit according to a preset forwarding rule.

[0053] In one optional implementation, the conversion unit includes a data conversion unit and a protocol conversion unit;

[0054] The data conversion unit includes a first conversion unit and a second conversion unit. The data conversion unit is used to receive operation instructions sent by the microprocessor through the first central interconnection unit, perform interface bit width conversion on the operation instructions, and send the converted operation instructions to the first arbitration unit.

[0055] The protocol conversion unit is used to transmit microprocessor configuration instructions for registers;

[0056] The first conversion unit and the second conversion unit perform different interface bit width conversion operations;

[0057] The register is connected between the protocol conversion unit and the memory.

[0058] In one alternative implementation, the register includes:

[0059] The registration register, connected to the instruction execution unit, is used to view the instruction execution status of the instruction execution unit.

[0060] In one alternative implementation, the register further includes:

[0061] The global register is used to receive and execute configuration information for the microprocessor.

[0062] In one alternative implementation, the hardware accelerator further includes:

[0063] An atomic control unit, connected between the instruction execution unit and the memory, is used to sequentially control the multiple logical operations executed by the instruction execution unit.

[0064] In one alternative implementation, the hardware accelerator further includes:

[0065] The second arbitration unit, connected between the atomic control unit and the memory, is used to arbitrate based on the read or write operations that the instruction execution unit needs to perform.

[0066] In one alternative implementation, the hardware accelerator further includes:

[0067] The read / write transmission channel is connected between the second arbitration unit and the memory, and is used to perform data transmission between the second arbitration unit and the memory.

[0068] In one alternative implementation, the hardware accelerator further includes:

[0069] The second central interconnection unit is connected between the second arbitration unit and the memory, and is used to perform data transmission through the read and write transmission channel based on preset read and write transmission rules.

[0070] Thirdly, embodiments of the present invention also provide an integrated circuit, which includes a hardware accelerator according to the first aspect or any corresponding embodiment described above.

[0071] Fourthly, embodiments of the present invention also provide a server, which includes the aforementioned integrated circuit.

[0072] In the data processing method, hardware accelerator, integrated circuit, and server provided in this invention, the conversion unit of the hardware accelerator, configured between the microprocessor and the memory, receives operation instructions sent by the microprocessor. The first arbitration unit arbitrates the operation instructions, a caching unit caches the operation instructions, and based on the arbitration result of the first arbitration unit, sends the operation instructions to the instruction execution unit. The instruction execution unit of the hardware accelerator performs data logic processing on the arbitrated operation instructions to obtain completion information, which is then fed back to the processor by the first arbitration unit. Therefore, when multiple operation instructions from multiple microcontrollers are received concurrently, arbitration and buffering effectively avoid problems such as large delays and poor performance caused by improper processing of multiple operation instructions, significantly improving the user experience. Attached Figure Description

[0073] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0074] Figure 1 This is a schematic diagram illustrating the composition and application scenarios of a hardware accelerator according to an embodiment of the present invention;

[0075] Figure 2 This is a schematic diagram of the composition structure of a hardware accelerator in a specific application example according to an embodiment of the present invention;

[0076] Figure 3 This diagram illustrates the initialization and actual operation workflow of the hardware accelerator provided in this embodiment of the invention.

[0077] Figure 4 This is a flowchart illustrating a data processing method according to an embodiment of the present invention;

[0078] Figure 5 This is a flowchart illustrating another data processing method according to an embodiment of the present invention;

[0079] Figure 6 This is a flowchart illustrating a specific application example of the data processing method according to an embodiment of the present invention. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0081] This invention provides a data processing method, a hardware accelerator, an integrated circuit, and a server to solve the problems of large latency and poor performance between multiple MCU commands executed by the SSD main control unit, which are caused by the fact that hardware accelerator designs typically use a single working engine to process commands issued by multiple MCUs, making it impossible to process commands in parallel by multiple MCUs.

[0082] To better illustrate the embodiments of the present invention, the hardware accelerator provided in the embodiments of the present invention will be described first.

[0083] According to an embodiment of the present invention, a hardware accelerator is provided, connected between a microprocessor and a memory, for performing data processing in response to operation instructions sent by the microprocessor.

[0084] like Figure 1 The diagram shown illustrates the structural composition and application scenarios of the hardware accelerator provided in this embodiment of the invention. It should be noted that... Figure 1 This is one of the preferred embodiments of the present invention. The various components of the hardware accelerator shown in the figure can be retained or not depending on actual needs.

[0085] refer to Figure 1 The dashed box in the figure shows the complete functional architecture of the hardware accelerator, while the area outside the dashed box represents a schematic diagram of the hardware accelerator's application scenarios. The hardware accelerator provided in this embodiment of the invention has multiple Engine Cores configured in its internal instruction execution unit. Each Engine Core can serve one MCU, therefore, the hardware accelerator can serve multiple MCUs simultaneously.

[0086] During MCU idle periods, multiple operation command slots from the MCU can be written into the hardware accelerator. After the operation instructions are written, the MCU can execute other processes until it becomes idle again, at which point it reads the completion information of the operation command slots stored in the hardware accelerator. This frees the MCU from specific and complex data operations, effectively improving the overall performance of control units such as SSDs. The hardware accelerator provided in this embodiment can cache up to 1024 slots.

[0087] like Figure 1 As shown, the hardware accelerator may include a conversion unit, a first arbitration unit, and an instruction execution unit.

[0088] The system includes a conversion unit connected between the microprocessor and the first arbitration unit, used to receive operation instructions sent by the microprocessor. The first arbitration unit, connected between the conversion unit and the instruction execution unit, is used to arbitrate the operation instructions. The instruction execution unit, connected between the first arbitration unit and the memory, is used to perform data logic processing on the arbitrated operation instructions to obtain completion information. The first arbitration unit also feeds back the completion information to the microprocessor.

[0089] In one alternative implementation, the hardware accelerator further includes a first central interconnect unit connected between the microprocessor and the conversion unit, for forwarding operation instructions to the conversion unit according to a preset forwarding rule.

[0090] In one optional implementation, the conversion unit includes a data conversion unit and a protocol conversion unit. The data conversion unit includes a first conversion unit and a second conversion unit. The data conversion unit receives operation instructions sent by the microprocessor through a first central interconnect unit, performs interface bit-width conversion on the operation instructions, and sends the converted operation instructions to a first arbitration unit. The protocol conversion unit transmits configuration instructions from the microprocessor to registers. The first and second conversion units perform different interface bit-width conversion operations, and the registers are connected between the protocol conversion unit and the memory.

[0091] In one alternative implementation, the register includes a registration register connected to the instruction execution unit for viewing the instruction execution status of the instruction execution unit.

[0092] In one alternative implementation, the register further includes a global register for receiving and executing microprocessor configuration information.

[0093] In one alternative implementation, the hardware accelerator further includes an atomic control unit connected between the instruction execution unit and the memory, for sequential control of multiple logical operations performed by the instruction execution unit.

[0094] In one alternative implementation, the hardware accelerator further includes a second arbitration unit connected between the atomic control unit and the memory, for arbitrating read or write operations that the instruction execution unit needs to perform.

[0095] In one alternative implementation, the hardware accelerator further includes a read / write transmission channel connected between the second arbitration unit and the memory, for performing data transmission between the second arbitration unit and the memory.

[0096] In one alternative implementation, the hardware accelerator further includes: a second central interconnect unit connected between the second arbitration unit and the memory, for performing data transmission through a read / write transmission channel based on preset read / write transmission rules.

[0097] According to embodiments of the present invention, a specific application example of a hardware accelerator is also provided, such as... Figure 2 As shown, the hardware accelerator is connected between the microprocessor and the memory to perform data processing in response to operation instructions sent by the microprocessor. Figure 2 This is a schematic diagram of the composition structure of a hardware accelerator in a specific application example provided in this embodiment of the invention.

[0098] refer to Figure 2The hardware accelerator consists of major functional modules such as NIC, Engine_Axi_arb, Engine_cmdc, Engine_Core, Engine_autoc, Axi_mst_arb, and Engine_CFG (Registers).

[0099] The NIC is the first central interconnect unit mentioned above. Here, the NIC is also called the NIC bridge, which serves as the channel for information exchange between the MCU and the hardware accelerator. The NIC bridge can include three communication channels: Axi2local_128, Axi2local_32, and Axi2 APB. Axi2local_128 and Axi2local_32 are the first and second conversion units mentioned above, respectively. Information exchange can include the MCU sending operation command slots to the hardware accelerator and the MCU reading operation result information from the hardware accelerator.

[0100] Two AXI2local modules, Axi2local_128 and Axi2local_32, are used to connect different MCUs and hardware accelerators. The main difference between the MCUs lies in the master interface bit width. Axi2local_128 is a general-purpose module used to convert the 128-bit Axi4 protocol data width into a local interface. In the entire hardware accelerator, it can be configured as a channel for information exchange between MCU0 and the hardware accelerator. The Axi2local_32 module is basically the same as Axi2local_128, the fundamental difference being that the data width of Axi2local_32 is 32 bits.

[0101] The other AAxi2APB is used for reading and writing registers, which is the protocol conversion unit mentioned above. Specifically, this module is a channel for the MCU configuration registers, used to implement the conversion from AXI to APB protocol.

[0102] Engine_Axi_arb, also known as the first arbitration unit mentioned above, is used to process the operation instruction slots issued by the MCU. A slot is an operation command issued by the MCU to the internal hardware accelerator. A complete slot is 128 bits long and has a specific format, including operation address, operation data, ID, OPC (operation mode), and return completion information bits.

[0103] A complete slot is 128 bits. During the MCU's slot writing process, MCU0 to MCU7 can send slots with full bit width via Axi2local_128. However, each set of operation instruction slots written to the hardware accelerator by MCU8 to MCU9 via Axi2local_32 is only 32 bits, and requires receiving 4 consecutive write operation instructions to form a complete set of operation instruction slots.

[0104] During the operation of the hardware accelerator, data is independently controlled between multiple MCUs, leading to the issue of multiple MCUs simultaneously issuing operation instruction slots to the hardware accelerator. However, the Engine_cmdc module can only receive one operation instruction slot per clock cycle. Therefore, it is necessary to cache the operation instruction slots from the NIC bridge and to arbitrate them. Engine_Axi_arb can handle multiple sets of operation instruction slots issued simultaneously by multiple MCUs. Specifically, multiple sets of operation instruction slots issued simultaneously by multiple MCUs can be cached in the cache module at the current clock cycle. The cached slots are then arbitrated using Round-Robin (RR) arbitration before being issued. In this embodiment of the invention, a set of operation instructions mentioned here and elsewhere can be considered as a set of operation instructions issued by the MCU at one time.

[0105] The process of reading completion information from the hardware accelerator's operation instructions to the MCU is similar to writing multiple operation instructions into a buffer. The MCU's read operations for completion information also need to be queued. For example, when multiple MCUs initiate read operations simultaneously, it can easily lead to two NIC bridges each issuing a set of read commands at the same time. In this case, arbitration is also required through the first arbitration module. After the read command is processed by modules such as Engine_Core, Engine_autoc, and Axi_mst_arb, it will return a 64-bit completion information. Since Axi2local_32 is 32-bit wide, it needs to be read twice to read the 64-bit data. Therefore, the first arbitration module needs to temporarily store part of the completion information, waiting for the MCU to completely read it before releasing the buffer space.

[0106] The completion information refers to the completion status information of a set of commands that the hardware accelerator can return after completing a set of operations, according to the requirements of the completion information bit in the slot. This information includes whether the set of commands is completed, the ID, the operation result, and whether an eRRor exists.

[0107] The Engine_cmdc, mentioned above, is the cache unit used to store and forward operation instruction slots and completion information. Engine_cmdc stores operation instruction slots written from the MCU to the hardware accelerator's internal SRAM (Static Random-Access Memory), and temporarily stores the hardware accelerator's completion information in an internal FIFO (First In, First Out) queue. This Engine_cmdc module has a 1024-bit deep, expandable SRAM. Based on user configuration, this 1024-bit deep, expandable SRAM can be divided into 10 groups with adjustable depth. Each group stores the operation slots of its associated Engine_Core. There are 10 internal FIFOs, each 16 bits deep and expandable. Each FIFO corresponds one-to-one with a Group and stores the completion information for each group of slots.

[0108] Engine_cmdc also distributes multiple operation instruction slots and completion information stored internally by the hardware accelerator. Since Engine_cmdc can only send one set of operation instruction slots to the Engine_Core of the instruction execution unit per clock cycle, when multiple Engine_Cores request operation instruction slots, Engine_cmdc performs RR arbitration on these requests. Based on the arbitration result, one slot group is selected each clock cycle, and a set of operation instruction slots is popped to the corresponding Engine_Core.

[0109] Engine_Core refers to the instruction execution unit mentioned above. A hardware accelerator can be configured with 10 Engine_Cores, for example: Figure 2 Engine0-Engine9. Here, the Engine_Core can also be bound to any Slot Group according to user configuration.

[0110] Each Engine core contains 16 Finite State Machines (FSMs), capable of processing 16 sets of Slot commands simultaneously. When a set of commands is sent to the Engine core, it can be placed in the lowest-numbered idle state machine (FSM0-15) for execution. Once the Engine core has received 16 sets of Slots, it sets the busy signal (indicating the Engine core is currently in a working state) to 1, meaning that the Engine core cannot receive any more operation command Slots. The busy signal of the Engine core will only be pulled low once one or more of the 16 operation command Slots within the Engine core have been completed.

[0111] Engine_Core extracts information from the slots, performs corresponding read and write operations, and performs addition, subtraction, OR, and XOR operations on the read data, as well as comparisons of operands in the operation instruction slots, before writing to the specified address and generating a completion message. During the execution of Engine_Core operation instruction slots, since address operations are required, and the addresses operated on by different slots may be the same, this module simultaneously ensures the atomicity of each operation.

[0112] For example, Engine_Core0 currently contains operation instructions Slot0 and Slot1, and the operation addresses of the two operation instructions Slots are the same.

[0113] Operation instruction Slot0 needs to read the data at the specified address, perform an addition operation, and then write it back to that address. Slot1 needs to write data to that address. If operation instruction Slot1 is executed at the same time, after operation instruction Slot0 has already started executing, then the final data at that address has three possibilities:

[0114] The first type is the result of the operation command Slot0 reading the raw data and performing the calculation;

[0115] The second type is the result of the operation instruction Slot0 reading the data written in by the operation instruction Slot1 and performing the calculation.

[0116] The last type is data written by the operation instruction Slot1. This can lead to the MCU receiving unexpected data, reducing MCU performance or even causing errors. To avoid this error, before executing each operation instruction Slot, it is necessary to check if there is an existing operation instruction Slot within the Engine_Core that operates on the same address. If so, it is necessary to wait for the already executed operation instruction Slot to complete before executing the current operation instruction Slot. This is the so-called atomicity between operations.

[0117] Engine_autoc, as mentioned above, is the atomic control unit used to ensure the atomicity of operations between multiple Engine_Cores. Specifically, within an Engine_Core, atomic operations are implemented for 16 slots. However, due to the existence of multiple Engine_Cores, multiple slot commands may be issued simultaneously from different Engine_Cores. If the addresses of different operation instruction slots are identical, the aforementioned error will occur. Therefore, this module compares the addresses of the current operation instruction slot with those of all currently executing operation instruction slots. If a match is found, and the corresponding operation at the same address includes a write operation, then the operation must wait for completion before that operation instruction slot can continue execution. Here, execution refers to sending the operation command to the Axi master interface to perform read and write operations.

[0118] Axi_mst_arb is the second arbitration unit mentioned above. It is used to arbitrate multiple Axi commands. Axi_mst_arb has two Axi master channels used to implement the Axi read / write operations required in the operation instruction slots. Since multiple Engine_Cores can initiate multiple Axi read / write operations simultaneously, but there are only two Axi master channels, when multiple requests using the Axi master occur at the same time, it is necessary to determine which operation instruction to execute based on the user's configuration and the result of RR arbitration. For example, 10 Engine_Cores can each receive 16 operation instructions, and can execute a maximum of 16 Slots * 10 Engine_Cores = 160 read / write operations simultaneously. When 10 Engine_Cores do indeed execute 160 read / write operations simultaneously, it is necessary to determine which read / write operation to execute first based on the user's configuration. Specifically, the binding relationship between Engine_Cores and Axi masters can be configured.

[0119] Engine_CFG(Registers) refers to the registers mentioned above. Registers can include types such as Engine_Coreregister and Global Register.

[0120] The Engine_Core register is only used to view the current state of the Engine_Core. When using it, you need to configure the Engine_debug_select register (offset=0x024) to select and view the states of Engine0 to Engine9.

[0121] The Global Register includes the Slot Allocation Register, used to configure how many slots each slotgroup can hold; the SlotGroup-Engine Mapping Register, used to bind a slotgroup to an Engine Core; the Engine_master_map register, used to bind a slotgroup to an Axi master; the Engine_debug_select register, used to select the Engine Core to be debugged; the GROUP_BASE_ADDR_register, used to configure the starting address of each group; the Slot Empty register, used to display the remaining space in each slotgroup; and the ERRor code register, used to store error codes and error messages. Examples include: an Engine Core being bound to a slotgroup multiple times; an Engine Core experiencing an addition / subtraction overflow error; and address errors when configuring a slot or reading return information.

[0122] It should be noted that the area outside the dashed box mainly consists of three parts: the MCU used to send operation commands, the memory used to store data, and the NIC interconnect structure between components.

[0123] Furthermore, Figure 2In this context, "Slot Path" refers to the transmission path when the MCU writes operation instructions to the hardware accelerator's write command, which is also the transmission path of the operation instruction Slot in this embodiment of the invention. "Data Path0" and "DataPath1" refer to the paths when the hardware accelerator reads or writes data at a specified address through the axi master interface. "Engine RegCFG Path" refers to the transmission path used by the MCU when configuring the internal registers of the hardware accelerator.

[0124] Before the hardware accelerator can perform data processing operations, it needs to be configured via the MCU. Figure 3 This diagram illustrates the initialization and actual operation workflow of the hardware accelerator provided in an embodiment of the present invention. (Reference) Figure 3 The firmware configuration operation process can include S311-S318, and the corresponding register configuration operation can include S321-S328. Among them, S311-S314 are the operation steps of the firmware initialization process, and S321-S324 are the operation steps of the register configuration initialization process.

[0125] Step S311: Assign a SlotGroup to each MCU.

[0126] This is to determine the correspondence between MCUs and SlotGroups. For example, a hardware accelerator can have a maximum of 10 SlotGroups, meaning the SRAM storing operation instructions can be divided into a maximum of 10 parts. The firmware (FW) must first determine the correspondence between each MCU and SlotGroup.

[0127] Step S312: Assign a base address to SlotGroup.

[0128] Step S313: Assign operation instructions (Slot) to SlotGroup.

[0129] Step S314: Assign the corresponding Engine_core to SlotGroup.

[0130] Step S315: Obtain the number of available operation instruction slots in the SlotGroup.

[0131] It should be noted that step S315 is not a mandatory operation.

[0132] Step S316: Write the Slot(Request) for the operation instruction Slot into the SlotGroup.

[0133] Step S317, the hardware accelerator starts working.

[0134] Step S318: Read the completion information of the operation instruction Slot, which represents information such as returned data and completion status.

[0135] Step S321: No register configuration is required.

[0136] It should be noted that when the firmware executes step S311 to allocate a SlotGroup to each MCU, there is no need to configure the register.

[0137] Step S322, Configure GROUP_BASE_ADDR_register.

[0138] Specifically, you can configure GROUP_BASE_ADDR_register by specifying the base address of each slotgroup.

[0139] Step S323, Config Slot Allocation Register.

[0140] Specifically, the number of operation instruction slots corresponding to each SlotGroup can be configured. The firmware configures the maximum number of slots that each slotgroup can hold by writing to the SlotAllocation Register. When configuring a slot, only the base address of the group needs to be written; the hardware will automatically arrange the slots. If the written address is not the base address and is between two slotgroups, the slot will be written to group0. The two slotgroups are located between group0 and group1.

[0141] Step S324, Config SlotGroup-Engine Mapping Register.

[0142] Specifically, the mapping between SlotGroups and Engine Cores can be specified. The Firewall binds the slotgroups and Engine Cores by writing to the SlotGroup-Engine Mapping Register. Each SlotGroup can be bound to multiple Engine Cores, but each Engine Core can only be bound to one group. If an unbound slotgroup or Engine Core exists, it is considered unused.

[0143] Furthermore, the registers are bound to the Engine and the master via the Config Engine_master_map register instruction. Each Engine_Core can choose to read or write data from either Axi Master0 or Axi Master1.

[0144] Step S315, Read Slot Empty register. The register determines how much space is available for operation instruction slots in each SlotGroup.

[0145] Before writing to a Slot Group, the filesystem controller (FW) can first obtain the Slot status. By reading the Slot_Emptyregister, it can determine how many available Slots are currently in each Slot Group, ensuring that write overflow does not occur. This step does not need to be performed every time a slot is configured. If multiple slots are found to be free, all free slots can be written to before reading this register.

[0146] Step S316, Config SlotGroup.

[0147] Specifically, the register is configured with the corresponding SlotGroup for the operation instruction.

[0148] Step S317, Engine working.

[0149] Step S318: Read data and check status.

[0150] The register reads completion information, which represents the returned data and completion status, through this operation step.

[0151] In order to accurately detect errors during the operation of the hardware accelerator, an error reporting mechanism is also configured for the hardware accelerator, using two methods to jointly implement error indication.

[0152] In the first method, error information is recorded through registers. Specifically, during the operation of the hardware accelerator, errors such as address configuration errors, slot loss due to a full slotgroup being written to, exceeding the maximum limit of slots after allocating available space to a slotgroup, and Engine_Core being bound to multiple slotgroups will all be recorded. Detailed error information can be obtained by reading the contents of the register at the specified address.

[0153] In the first method, error information is promptly fed back via an interrupt signal. When any of the various errors described in the first method occurs, an interrupt is generated. The corresponding error information is then retrieved by reading the aforementioned registers.

[0154] According to an embodiment of the present invention, a data processing method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0155] This embodiment provides a data processing method that can be used in the aforementioned hardware accelerator, etc. The hardware accelerator includes a conversion unit, a first arbitration unit, a cache unit, and an instruction execution unit. Figure 4 This is a flowchart of a data processing method according to an embodiment of the present invention, such as... Figure 4 As shown, the process includes the following steps:

[0156] In step S401, the conversion unit receives the operation instructions sent by the microprocessor.

[0157] Specifically, the operation instruction can be a Slot. A Slot refers to the operation command issued by the MCU to the internal hardware accelerator. A complete Slot is 128 bits. The Slot has a specific format, which includes information such as operation address, operation data, ID, operation mode (OPC), and return completion information bits.

[0158] In step S402, the first arbitration unit arbitrates the operation command.

[0159] In some optional embodiments of the invention, the first arbitration unit may receive multiple sets of operation instructions from the conversion unit at the same time, but each cache unit or each instruction execution unit can only execute one operation instruction under the current clock. In this case, the first arbitration unit is required to arbitrate the operation instructions.

[0160] For example, a complete slot has 128 bits. MCUs 0-7 send slots via Axi2local_128 at full width, while MCUs 8-9 send commands via Axi2local_32 in groups of only 32 bits each. It takes receiving four consecutive commands from these MCUs to form a complete slot. Since multiple MCUs are unaware of each other's operations, there's a possibility of multiple MCUs sending slots simultaneously. The Engine_cmdc module only receives one slot per clock cycle, necessitating buffering of slots from the NIC bridge and arbitration. This module handles the situation where multiple slots are sent simultaneously. If the buffer cannot provide a slot to the Engine_cmdc in the current clock cycle, it performs RR arbitration on the buffered slot before sending it to the buffer unit.

[0161] In step S403, the caching unit caches the operation instructions and sends the operation instructions to the instruction execution unit based on the arbitration result of the first arbitration unit.

[0162] For example, the cache unit is Engine_cmdc. Engine_cmdc can be used to store the operation instruction slots written by the MCU to the hardware accelerator into the hardware accelerator's internal SRAM (Static Random-Access Memory), and simultaneously temporarily store the hardware accelerator's completion information in an internal FIFO (First In, First Out) queue. The Engine_cmdc module has a 1024-bit deep, expandable SRAM. Based on user configuration, this 1024-bit deep, expandable SRAM can be divided into 10 groups with adjustable depths. Each group stores the operation slots of its associated Engine_Core. There are 10 internal FIFOs, each 16 bits deep and expandable. Each FIFO corresponds one-to-one with a Group and is used to store the completion information of each group of slots.

[0163] The Engine_cmdc also distributes multiple operation instruction slots and completion messages stored internally by the hardware accelerator. Since the Engine_cmdc module can only send one set of operation instruction slots to the Engine_Core of the instruction execution unit per clock cycle, when multiple Engine_Cores request operation instruction slots, the Engine_cmdc performs RR arbitration on these requests. Based on the arbitration result, one slot group is selected each clock cycle, and a set of operation instruction slots is popped (released) to the corresponding Engine_Core. The Engine_Core is the instruction execution unit.

[0164] In step S404, the instruction execution unit performs data logic processing on the operation instruction that has been arbitrated to obtain completion information.

[0165] In some optional embodiments of the present invention, the instruction execution unit can determine whether the operation instruction requires a read data operation, and if a read data operation is required, perform the read data operation through a second arbitration unit capable of arbitrating the read data operation to obtain the data required by the operation instruction. In response to the operation instruction, it performs data logic processing based on the obtained data or without requiring data acquisition.

[0166] Furthermore, after completing the data logic processing, it will be determined whether a write operation is needed. If a write operation is required, it will be executed through the second arbitration unit, storing the result of the data logic processing into the memory.

[0167] In step S405, the first arbitration unit will send the completed information back to the processor.

[0168] In some optional embodiments of the present invention, after the instruction execution unit completes the data logic processing and the data processing related to the write operation, it sends the completion information to the first arbitration unit. The first arbitration unit then feeds back the completion information to the processor.

[0169] The data processing method provided in this invention receives operation instructions sent by the microprocessor through a conversion unit of a hardware accelerator configured between the microprocessor and the memory. The first arbitration unit arbitrates the operation instructions, a caching unit caches the operation instructions, and based on the arbitration result of the first arbitration unit, sends the operation instructions to an instruction execution unit. The instruction execution unit of the hardware accelerator performs data logic processing on the arbitrated operation instructions to obtain completion information, which is then fed back to the processor by the first arbitration unit. Therefore, when multiple operation instructions are received concurrently from multiple microcontrollers, arbitration and buffering effectively avoid problems such as large delays and poor performance caused by improper processing of multiple operation instructions, significantly improving the user experience.

[0170] This embodiment provides a data processing method that can be used in the aforementioned hardware accelerators, etc. Figure 5 This is a flowchart of a data processing method according to an embodiment of the present invention, such as... Figure 5 As shown, the process includes the following steps:

[0171] Step S501: The conversion unit receives the operation instructions sent by the microprocessor.

[0172] In an optional implementation, step S501 includes:

[0173] In step S5011, the conversion unit receives the operation instruction sent by the microprocessor through the first central interconnection unit and performs interface bit width conversion on the operation instruction.

[0174] For details, please refer to the above. Figure 2 The MCU writes the operation instruction slot to the hardware accelerator via Axi2local_128 or Axi2local_32.

[0175] Step S5012: Send the converted operation instructions to the first arbitration unit.

[0176] For details, please refer to the above. Figure 2 Axi2local_128 or Axi2local_32 converts the axi_slave interface into a local interface and sends the operation instruction slot to Engine_axi_arb.

[0177] The data processing method provided in this embodiment of the invention performs bit-width conversion on operation instructions through the conversion unit of a hardware accelerator, converting the operation instructions into data and instructions that conform to the data processing interface protocol of the hardware accelerator, thereby achieving fast and accurate conversion of operation instructions, effectively performing operations such as caching of operation instructions, and realizing parallel processing of multiple operation instructions.

[0178] For further details, please refer to Figure 4 Step S401 of the illustrated embodiment will not be described again here.

[0179] In step S502, the first arbitration unit arbitrates the operation command.

[0180] In one alternative implementation, the arbitration of operation instructions can be achieved by arbitrating operation instructions issued simultaneously by multiple microprocessors based on predetermined data transmission rules, and the cache unit will send the arbitrated operation instructions to the instruction execution unit.

[0181] In one alternative implementation, the operation instructions sent to the instruction execution unit through arbitration can be achieved by the following operation: the buffer unit controls the sending of a set of operation instructions to the instruction execution unit every clock cycle according to the arbitration result.

[0182] For example, refer back to the above. Figure 2 Engine_axi_arb can arbitrate the received operation instruction slots and, based on the arbitration result, send the conversion operation instruction slots to Engine_cmdc.

[0183] The data processing method provided in this invention, based on the arbitration result, controls the sending of a set of operation instructions to the instruction execution unit every clock cycle. Therefore, by achieving reasonable caching of multiple operation instructions, the orderliness of operation instruction execution is effectively improved, and the execution efficiency of multiple operation instructions is increased.

[0184] For further details, please refer to Figure 4 Step S403 of the illustrated embodiment will not be described again here.

[0185] In step S503, the caching unit caches the operation instructions and sends the operation instructions to the instruction execution unit based on the arbitration result of the first arbitration unit.

[0186] For further details, please refer to Figure 4 Step S403 of the illustrated embodiment will not be described again here.

[0187] In step S504, the instruction execution unit performs data logic processing on the operation instruction that has been arbitrated to obtain completion information.

[0188] In one optional implementation, the hardware accelerator is connected between the microprocessor and the memory. In step S504, the instruction execution unit performs data logic processing on the operation instructions through arbitration to obtain completion information. Specifically, this can be achieved through the following operations:

[0189] Step S5041: If the instruction execution unit determines that the operation instruction requires the execution of the first read operation, it sends a first read operation request to the atomic control unit.

[0190] Step S5042: Receive the first read data fed back by the atomic control unit. The first read data is obtained from the memory by the atomic control unit in response to the first read operation.

[0191] Step S5043: Execute the operation instruction based on the first read data to obtain completion information.

[0192] The data processing method provided in this embodiment of the invention involves an instruction execution unit sending a first read operation request to an atomic control unit when it determines that an operation instruction requires a first read operation. The instruction execution unit then receives first read data from the atomic control unit in response to the first read operation. The atomic control unit retrieves the first read data from memory and executes the operation instruction based on the first read data to obtain completion information. Through the atomic control unit, multiple MCUs can operate simultaneously, cache multiple commands, perform atomic operations on data at a specified address, and return completion information, thus achieving the high-performance data processing requirement of multiple microprocessors simultaneously performing atomic operations on data at a specified address.

[0193] In one alternative implementation, the atomic control unit obtains the first read data from the memory by the following operation:

[0194] Step a1: Send the first read operation to the second arbitration unit.

[0195] Step a2: The second arbitration unit polls and arbitrates multiple read operations based on the number of read operations under the current clock.

[0196] Step a3: The second arbitration unit, based on the successful arbitration of the first read operation, executes the first read operation and retrieves the first read data from the memory.

[0197] Step a4: The second arbitration unit sends the first read data to the atomic control unit.

[0198] The data processing method provided in this embodiment of the invention effectively achieves atomic control of data operations at an address by controlling multiple first read operations through an atomic control unit, thus avoiding problems such as conflicts between multiple operations.

[0199] In one optional implementation, step S504 includes:

[0200] In step S5044, if the instruction execution unit determines that the operation instruction does not require a read operation or has already received the first read data obtained by performing the first read operation, it performs data logic processing in response to the operation instruction to obtain logic processing data.

[0201] Step S5045: If it is determined that a first write operation needs to be performed on the logical processing data, the first write operation is sent to the atomic control unit.

[0202] Step S5046: Receive the first write result of the first write operation from the atomic control unit, and obtain completion information based on the first write result.

[0203] It should be noted that the above steps S5041-S5043 and steps S5044-S5046 are all conditional operation steps, and are not steps that must be performed in every embodiment.

[0204] The data processing method provided in this embodiment of the invention involves an instruction execution unit performing data logic processing in response to an operation instruction when it determines that an operation instruction does not require a read operation or has already received the first read data obtained from the first read operation. This process yields logically processed data. If it determines that a first write operation needs to be performed on the logically processed data, the instruction execution unit sends the first write operation to the atomic control unit, receives the first write result from the atomic control unit, and obtains completion information based on the first write result. Thus, the instruction execution unit executes multiple operation instructions sent by multiple microcontrollers in an orderly manner, effectively reducing the data processing pressure on the microcontrollers, significantly reducing the latency of the microcontrollers' operation instructions, and effectively improving the performance of the microcontrollers.

[0205] In one alternative implementation, the atomic control unit obtains the first write result through the following operation:

[0206] Step b1: Send the first write operation to the second arbitration unit.

[0207] Step b2: The second arbitration unit polls and arbitrates multiple write operations based on the number of write operations under the current clock.

[0208] In step b3, the second arbitration unit, based on the successful arbitration of the first write operation, executes the first write operation to write logical processing data into the memory.

[0209] Step b4: The second arbitration unit sends the first write result back to the atomic control unit.

[0210] The first write result is used to characterize the result of the first write operation.

[0211] For further details, please refer to Figure 1 Step S404 of the illustrated embodiment will not be described again here.

[0212] In step S505, the first arbitration unit will send the completed information back to the processor.

[0213] In an optional implementation, step S505 may include:

[0214] Step S5051: The instruction execution unit sends completion information to the first arbitration unit.

[0215] In step S5052, the first arbitration unit adds the completion information to the first-in-first-out queue through arbitration based on the completion information.

[0216] In step S5053, the microprocessor reads the completion information through the first-in-first-out queue.

[0217] This embodiment provides a specific application example of a data processing method, which can be used in the aforementioned hardware accelerators, etc. Figure 6 This is a flowchart of a data processing method according to an embodiment of the present invention, such as... Figure 6 As shown, the flow of a specific application example of the data processing method provided in this embodiment of the invention includes the following steps:

[0218] S601, the MCU executes write operation instructions Slot operations through Axi2local_128 or Axi2local_32.

[0219] S602, Axi2local_128 or Axi2local_32 converts the Axi_slave interface into a local interface and assigns the slot to Engine_Axi_arb.

[0220] S603, Engine_Axi_arb arbitrates the received slot and sends the slot to Engine_cmdc.

[0221] S604, Engine_cmdc internal SlotGroup(sram) writes slots to Engine_CORE.

[0222] S605, Engine_CORE determines whether the group of cmds needs an Axi read operation; if yes, execute S606; otherwise, execute S10.

[0223] S606, Engine_CORE initiates an Axi operation request to Engine_autoc, waiting to obtain Axi usage rights.

[0224] S607, Engine_CORE initiates a read operation and sends the read command to Axi_mst_arb.

[0225] S608, after the arbitration of the Axi_mst_arb read command is completed, the Axi_mst read operation is initiated.

[0226] S609, Engine_CORE obtains read data.

[0227] S610, Engine_CORE performs calculations based on OPC (OPC refers to operation or operation mode, which has nine types: read-only, write-only, read-then-write, OR operation, XOR operation, addition operation, subtraction operation, comparison and replacement, calculate bit count, and AND operation) to obtain the calculation result.

[0228] S611, Engine_CORE determines whether the group of cmds needs an Axi write operation. If yes, execute S612; otherwise, execute S614.

[0229] S612, Engine_CORE initiates a write operation based on OPC and sends the operation cmd to Axi_mst_arb.

[0230] S613, after the Axi_mst_arb write command arbitration is completed, the Axi_mst write operation is initiated.

[0231] S614, Engine_CORE returns FB_data to FB_Group.

[0232] Among them, FB_Group is a FIFO that stores completion information.

[0233] S615, the MCU reads FB_Group through AXI_Slave.

[0234] Among them, FB_Group is a FIFO that stores completion information.

[0235] Thirdly, embodiments of the present invention also provide an integrated circuit, which includes a hardware accelerator according to the first aspect or any corresponding embodiment described above.

[0236] For details on the implementation of integrated circuits and their beneficial effects, please refer to the implementation details and beneficial effects of the hardware accelerators mentioned above, which will not be repeated here.

[0237] Fourthly, embodiments of the present invention also provide a server, which includes the aforementioned integrated circuit.

[0238] For specific implementation details and beneficial effects of the server, please refer to the implementation details of the hardware accelerator and data processing methods mentioned above, which will not be repeated here.

[0239] In the data processing method, hardware accelerator, integrated circuit, and server provided in this invention, the conversion unit of the hardware accelerator, configured between the microprocessor and the memory, receives operation instructions sent by the microprocessor. The first arbitration unit arbitrates the operation instructions, a caching unit caches the operation instructions, and based on the arbitration result of the first arbitration unit, sends the operation instructions to the instruction execution unit. The instruction execution unit of the hardware accelerator performs data logic processing on the arbitrated operation instructions to obtain completion information, which is then fed back to the processor by the first arbitration unit. Therefore, when multiple operation instructions from multiple microcontrollers are received concurrently, arbitration and buffering effectively avoid problems such as large delays and poor performance caused by improper processing of multiple operation instructions, significantly improving the user experience.

[0240] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A data processing method, characterized in that, The method is applied to a hardware accelerator, which has a conversion unit, a first arbitration unit, a cache unit, and multiple instruction execution units. The hardware accelerator is connected between a microprocessor and a memory, and simultaneously serves multiple microprocessors, with each instruction execution unit corresponding to one microprocessor. The conversion unit receives the operation instruction sent by the microprocessor through the first central interconnect unit, performs interface bit width conversion on the operation instruction, and sends the converted operation instruction to the first arbitration unit. The first arbitration unit caches multiple sets of operation instructions issued simultaneously by multiple microprocessors at the current clock, and after polling and arbitrating the cached multiple sets of operation instructions, it issues them to the cache unit. The caching unit caches operation instructions. When multiple instruction execution units initiate commands requesting operation instructions, the caching unit arbitrates the requests initiated by the multiple instruction execution units and, based on the arbitration result, sends a set of operation instructions to the instruction execution unit at each clock cycle. The instruction execution unit performs data logic processing on the operation instructions that have been arbitrated, obtains completion information, and sends the completion information to the first arbitration unit; The first arbitration unit feeds back the completion information to the microprocessor; The instruction execution unit performs data logic processing on the operation instructions obtained through arbitration, including: When the instruction execution unit needs to perform a read data operation, it performs a read data operation through the second arbitration unit to obtain the data required by the operation instruction, and responds to the operation instruction by performing data logic processing based on the obtained data. When a write operation is required, the write operation is performed through the second arbitration unit, and the result of the data logic processing is stored in the memory.

2. The method according to claim 1, characterized in that, The hardware accelerator is connected between the microprocessor and the memory. The instruction execution unit performs data logic processing on the arbitrated operation instructions to obtain completion information, including: If the instruction execution unit determines that the operation instruction requires the execution of a first read operation, it sends a first read operation request to the atomic control unit. The atomic control unit receives first read data fed back by the atomic control unit, the first read data being obtained from the memory by the atomic control unit in response to the first read operation; The operation instruction is executed based on the first read data to obtain the completion information.

3. The method according to claim 2, characterized in that, The atomic control unit obtains the first read data from the memory through the following operation: Send the first read operation to the second arbitration unit; The second arbitration unit polls and arbitrates multiple read operations based on the number of read operations under the current clock. The second arbitration unit, based on the successful arbitration of the first read operation, executes the first read operation and retrieves the first read data from the memory; The second arbitration unit sends the first read data to the atomic control unit.

4. The method according to claim 1, characterized in that, The instruction execution unit performs data logic processing on the operation instructions through arbitration to obtain completion information, including: When the instruction execution unit determines that the operation instruction does not require a read operation or has already received the first read data obtained by performing the first read operation, it performs data logic processing in response to the operation instruction to obtain logic processing data. If it is determined that a first write operation needs to be performed on the logically processed data, the first write operation is sent to the atomic control unit; The first write result of the first write operation is received by the atomic control unit, and the completion information is obtained based on the first write result.

5. The method according to claim 4, characterized in that, The atomic control unit obtains the first write result through the following operation: Send the first write operation to the second arbitration unit; The second arbitration unit polls and arbitrates multiple write operations based on the number of write operations under the current clock. The second arbitration unit, based on the successful arbitration of the first write operation, executes the first write operation and writes the logical processing data into the memory; The second arbitration unit sends the first write result back to the atomic control unit; The first write result is used to characterize the result of the first write operation.

6. The method according to claim 1, characterized in that, The first arbitration unit feeds back the completion information to the microprocessor, including: The instruction execution unit sends completion information to the first arbitration unit; The first arbitration unit, based on the completion information, arbitrates and adds the completion information to the first-in-first-out queue; The microprocessor reads the completion information through the first-in-first-out queue.

7. A hardware accelerator, characterized in that, Connected between a microprocessor and a memory, the hardware accelerator simultaneously serves multiple microprocessors and performs data processing in response to operation instructions sent by the microprocessors. The hardware accelerator has a conversion unit, a first arbitration unit, a cache unit, and multiple instruction execution units, each of which corresponds to a microprocessor. The conversion unit is connected between the microprocessor and the first arbitration unit, and is used to receive the operation instructions sent by the microprocessor through the first central interconnection unit, convert the interface bit width of the operation instructions, and send the converted operation instructions to the first arbitration unit. The first arbitration unit is connected between the conversion unit and the instruction execution unit, and is used to cache multiple sets of operation instructions issued simultaneously by multiple microprocessors at the current clock, and to issue the cached multiple sets of operation instructions to the cache unit after polling and arbitrating the cached multiple sets of operation instructions. The cache unit is used to cache operation instructions. When multiple instruction execution units initiate commands requesting operation instructions, the cache unit arbitrates the requests initiated by the multiple instruction execution units, and based on the arbitration result, sends a set of operation instructions to the instruction execution unit at each clock cycle. The instruction execution unit is connected between the first arbitration unit and the memory, and is used to perform data logic processing on the operation instructions that have been arbitrated, and send the completion information to the first arbitration unit; The first arbitration unit is also configured to feed back the completion information to the microprocessor; The instruction execution unit performs data logic processing on the operation instructions obtained through arbitration, including: When the instruction execution unit needs to perform a read data operation, it performs a read data operation through the second arbitration unit to obtain the data required by the operation instruction, and responds to the operation instruction by performing data logic processing based on the obtained data. And when a write operation is required, the write operation is performed through the second arbitration unit to store the result of the data logic processing into the memory.

8. The hardware accelerator according to claim 7, characterized in that, The hardware accelerator further includes: a first central interconnect unit connected between the microprocessor and the conversion unit, used to forward the operation instructions to the conversion unit according to a preset forwarding rule.

9. The hardware accelerator according to claim 8, characterized in that, The conversion unit includes a data conversion unit and a protocol conversion unit; The data conversion unit includes a first conversion unit and a second conversion unit. The data conversion unit is used to receive the operation instructions sent by the microprocessor through the first central interconnect unit, perform interface bit width conversion on the operation instructions, and send the converted operation instructions to the first arbitration unit. The protocol conversion unit is used to transmit the microprocessor's configuration instructions for the registers; The first conversion unit and the second conversion unit perform different interface bit width conversion operations; The register is connected between the protocol conversion unit and the memory.

10. The hardware accelerator according to claim 9, characterized in that, The register includes: A registration register, connected to the instruction execution unit, is used to view the instruction execution status of the instruction execution unit.

11. The hardware accelerator according to claim 10, characterized in that, The register also includes: A global register is used to receive and execute configuration information for the microprocessor.

12. The hardware accelerator according to claim 7, characterized in that, The hardware accelerator also includes: An atomic control unit, connected between the instruction execution unit and the memory, is used to sequentially control multiple logical operations executed by the instruction execution unit.

13. The hardware accelerator according to claim 12, characterized in that, The hardware accelerator also includes: The second arbitration unit, connected between the atomic control unit and the memory, is used to arbitrate based on the read or write operation that the instruction execution unit needs to perform.

14. The hardware accelerator according to claim 13, characterized in that, The hardware accelerator also includes: A read / write transmission channel is connected between the second arbitration unit and the memory, and is used to perform data transmission between the second arbitration unit and the memory.

15. The hardware accelerator according to claim 14, characterized in that, The hardware accelerator also includes: The second central interconnection unit is connected between the second arbitration unit and the memory, and is used to perform data transmission through the read and write transmission channel based on preset read and write transmission rules.

16. An integrated circuit, characterized in that, The integrated circuit includes the hardware accelerator according to any one of claims 7 to 15.

17. A server, characterized in that, The server includes the integrated circuit of claim 16.

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