High-voltage LED chip and preparation method thereof

Abstract

The present invention discloses a high-voltage LED chip and its preparation method, relating to the field of light-emitting diode technology. The preparation method comprises: providing an epitaxial wafer; forming a first hole, a tunnel etch groove, and a bridge etch groove etched into a first semiconductor layer; forming a photoresist layer; exposing to form a first non-exposed area, a tunnel exposed area, a bridge exposed area, a second non-exposed area, and an underexposed area; developing to remove the photoresist layer in the tunnel exposed area and the bridge exposed area, as well as a preset amount of photoresist layer in the underexposed area; baking and curing the remaining photoresist layer; etching to remove the remaining first semiconductor layer in the tunnel etch groove and the bridge etch groove to expose the substrate; removing a preset thickness of the epitaxial layer in the underexposed area to form a slope with an angle of ≤45° in the underexposed area; removing the remaining photoresist layer; and forming a first electrode, a second electrode, and a bridge electrode. Implementing the present invention can simplify the preparation process and reduce costs.

Description

Technical Field

[0001] The present invention relates to the technical field of light emitting diodes, and in particular to a high-voltage LED chip and a preparation method thereof. Background Art

[0002] High-voltage LED chips are constructed by etching deep trenches in the epitaxial layer of a large chip (e.g., 24 mil x 28 mil), dividing it into multiple independent cores (typically 2 to 72). These cores are then connected in series using a "bridge" method using vapor-deposited electrodes. Compared to traditional LED chips, high-voltage LED chips can address the reliability issues of multi-crystal packaging, saving cost and space, and reducing energy losses in voltage conversion. This effectively simplifies LED driver circuit design while increasing light output power, offering broad application prospects.

[0003] For high-voltage LED chips, isolation trenches are provided between adjacent core particles. These isolation trenches include a bridge region and an aisle region located at the electrode connection. The bridge region needs to have a relatively small angle to ensure that the "gold finger" connecting the two small chips overlaps smoothly, without bubbles, holes, and other defects. Otherwise, the voltage and reliability of the entire chip will be affected. As for the aisle region, the larger the etching angle, the smaller the loss of luminous area and the higher the luminous brightness. However, excessively large viewing angles can also cause subsequent passivation film layers to crack, affecting reliability. Generally speaking, in the existing technology, the sidewall angle of the bridge region is controlled to be ≤45°, and the sidewall angle of the aisle region is 60°-70°. For isolation trenches with different angles, the existing technology often requires two photolithography processes to form, that is, first using one photolithography process to form the aisle region or bridge region, and then using another photolithography process to form the other region. This makes the existing high-voltage LED chip manufacturing process complex and costly. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for preparing a high-voltage LED chip, which has simple procedures and low costs.

[0005] Another technical problem to be solved by the present invention is to provide a high-voltage LED chip with high brightness and high reliability.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a high-voltage LED chip, which comprises the following steps:

[0007] S1. Providing an epitaxial wafer; the epitaxial wafer includes a substrate and an epitaxial layer, and the epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate;

[0008] S2. Forming a first hole, an aisle etched groove, and a bridge etched groove on the epitaxial wafer, each etched to the first semiconductor layer; the width of the aisle etched groove is smaller than the width of the bridge etched groove; the aisle etched groove and the bridge etched groove divide the epitaxial wafer into at least two or more light-emitting units;

[0009] S3, forming a photoresist layer on the epitaxial wafer obtained in step S2;

[0010] S4. Exposing the photoresist layer using a photomask to form a first non-exposed area, an aisle exposed area, a bridge exposed area, a second non-exposed area, and an under-exposed area; wherein the aisle exposed area is formed above the aisle etch groove, the bridge exposed area is formed above the bridge etch groove, the non-exposed area and the second under-exposed area are spaced apart on both sides of the bridge exposed area, and the exposure depths of the plurality of under-exposed areas decrease from close to the bridge exposed area to far away from the bridge exposed area;

[0011] S5, developing and removing the photoresist layer in the aisle exposure area, the bridge exposure area, and a preset amount of the photoresist layer in the under-exposure area;

[0012] S6, baking and curing the remaining photoresist layer;

[0013] S7, etching the epitaxial wafer obtained in step S6 to remove the remaining first semiconductor layer in the aisle etch grooves and the bridge etch grooves to expose the substrate; and removing the epitaxial layer of a preset thickness in the underexposed area to form a slope with an inclination angle of ≤45° in the underexposed area;

[0014] S8, removing the remaining photoresist layer;

[0015] S9. Form a first electrode, a second electrode, and a bridge electrode on the epitaxial wafer obtained in step S8 to obtain a finished high-voltage LED chip; wherein the first electrode is connected to the first semiconductor layer through the first hole, and the second electrode is connected to the second semiconductor layer.

[0016] As an improvement to the above technical solution, the mask plate includes a light-blocking area, an aisle light-transmitting area, a bridge light-transmitting area, and underexposed areas distributed on both sides of the bridge light-transmitting area. The underexposed area includes a plurality of light-blocking strips and light-transmitting strips distributed at intervals. The widths of the plurality of light-transmitting strips decrease from the side closest to the bridge light-transmitting area to the side away from the bridge light-transmitting area.

[0017] The light-transmitting widths of the aisle light-transmitting area and the bridge light-transmitting area are greater than the resolution of the light source used for exposure; and the light-transmitting width of the light-transmitting strip is smaller than the resolution of the light source used for exposure.

[0018] As an improvement to the above technical solution, the underexposed area includes 5 to 9 light-transmitting strips, and the width of the plurality of light-transmitting strips decreases from 1.3 μm to 1.8 μm on the side close to the bridge light-transmitting area to 0.5 μm to 0.8 μm on the side away from the bridge light-transmitting area; and / or

[0019] The widths of the plurality of light-blocking strips are all the same, ranging from 1.2 μm to 1.8 μm; and / or

[0020] The width of the light-transmitting area of ​​the aisle is 2.1 μm to 3.5 μm; and / or

[0021] The width of the bridge light-transmitting area is 6 μm to 15 μm.

[0022] As an improvement to the above technical solution, step S3 includes:

[0023] S31, spin-coating photoresist on the epitaxial wafer obtained in step S2, wherein the thickness of the photoresist is 10 μm to 13 μm and the uniformity is ≤ 3%;

[0024] S32, baking at 110°C to 130°C for 110s to 130s to obtain a photoresist layer.

[0025] As an improvement to the above technical solution, in step S4, the photoresist layer is exposed by a step-and-step exposure method, the exposure energy is 1000mJ to 1300mJ, the wavelength of the exposure light source is 320nm to 380nm, and the resolution of the exposure light source is 1.8μm to 3μm; and / or

[0026] In step S5, developing is performed 2 to 4 times, each time for 40 to 50 seconds; and / or

[0027] In step S6, the baking temperature is 100° C. to 160° C., and the baking time is 100 s to 300 s.

[0028] As an improvement of the above technical solution, in step S2, when the photoresist used in the photoresist layer is baked at 120° C. to 160° C. for 20 min to 30 min, its viscosity is 500 cP to 700 cP;

[0029] In step S5, after development, a plurality of second holes with different depths are formed on the photoresist layer in the underexposed area; the depths of the second holes decrease from close to the bridge etching groove to far away from the bridge etching groove;

[0030] In step S6, the baking temperature is 120°C to 160°C, and the baking time is 150s to 300s, so that the photoresist layer on both sides of the second hole is softened to fill the second hole, and a sloped photoresist layer is formed on both sides of the bridge etching groove, and the inclination angle is 25° to 35°.

[0031] As an improvement to the above technical solution, in step S7, when the ICP etching process is used, the etching gases used are Ar, BCl3, and Cl2, and the flow ratio of Ar, BCl3, and Cl2 is 1:1:3 to 1:5:15; preferably, the flow ratio of the three is 1:1:6. The etching time is 1300s to 1500s, the RF power is 1000W to 1200W, the ICP power is 400W to 500W, and the etching pressure is 1 torr to 10 torr.

[0032] As an improvement to the above technical solution, step S8 includes:

[0033] S81, removing the remaining photoresist layer;

[0034] S82, forming a current blocking layer on the epitaxial wafer obtained in step S81;

[0035] S83 , forming a transparent conductive layer on the epitaxial wafer obtained in step S82 .

[0036] As an improvement to the above technical solution, step S9 includes:

[0037] S91, forming a first electrode, a second electrode, a bridge electrode and a current spreading bar on the epitaxial wafer obtained in step S8;

[0038] S92, forming a passivation layer on the epitaxial wafer obtained in step S91, and opening holes to expose the first electrode and the second electrode, thereby obtaining a finished high-voltage LED chip;

[0039] Wherein, the thickness of the passivation layer is

[0040] Correspondingly, the present invention also discloses a high-voltage LED chip, which is prepared by the above-mentioned method for preparing the high-voltage LED chip.

[0041] The implementation of the present invention has the following beneficial effects:

[0042] In the preparation method of the high-voltage LED chip of the present invention, a first non-exposed area, an aisle exposure area, a bridge exposure area, a second non-exposed area and an under-exposed area are formed on the photoresist layer through exposure on a mask plate; wherein the non-exposed area and the second under-exposed area are spaced apart and distributed on both sides of the bridge exposure area, and the exposure depths of the multiple under-exposed areas decrease from close to the bridge exposure area to far away from the bridge exposure area; and then, after etching during the development process, a slope with an inclination angle of ≤45° is formed as the bridge area, and the other parts serve as the aisle area. Side walls with different inclination angles are obtained through a photolithography and etching process, which effectively improves the preparation efficiency and reduces the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1is a flow chart of a method for preparing a high-voltage LED chip in one embodiment of the present invention;

[0044] Figure 2 1 is a schematic cross-sectional structural diagram of an epitaxial wafer after step S2 in one embodiment of the present invention;

[0045] Figure 3 1 is a schematic diagram of a top view of the epitaxial wafer after step S2 in one embodiment of the present invention;

[0046] Figure 4 1 is a schematic top view of the structure of a mask plate in one embodiment of the present invention;

[0047] Figure 5 yes Figure 4 A partial enlarged view of area A in the middle;

[0048] Figure 6 1 is a schematic diagram of a top view of the epitaxial wafer after step S4 in one embodiment of the present invention;

[0049] Figure 7 2 is a schematic diagram of the principle of exposure and development of an underexposed area in one embodiment of the present invention;

[0050] Figure 8 is a scanning electron microscope image of the aisle area after step S7 in one embodiment of the present invention;

[0051] Figure 9 is a scanning electron microscope image of the bridging area after step S7 in one embodiment of the present invention;

[0052] Figure 10 This is a schematic top view of a finished high-voltage LED chip according to an embodiment of the present invention;

[0053] Figure 11 is a scanning electron microscope image of the aisle area after step S9 in one embodiment of the present invention;

[0054] Figure 12 is a scanning electron microscope image of the S9 rear bridging region in one embodiment of the present invention;

[0055] Figure 13 This is a scanning electron microscope image of a finished high-voltage LED chip according to one embodiment of the present invention;

[0056] In the figure, A is the Bragg reflector layer, B is the PR layer, and C is the metal electrode layer; 1 is the epitaxial wafer, 11 is the substrate, 12 is the epitaxial layer, 121 is the first semiconductor layer, 122 is the active layer, 123 is the second semiconductor layer, 13 is the first hole, 14 is the aisle etching groove, 15 is the bridge etching groove, 16 is the light-emitting unit, 2 is the photoresist layer, 21 is the first non-exposed area, 22 is the aisle exposure area, 23 is the bridge exposure area, 24 is the second non-exposed area, 25 is the under-exposed area, 26 is the second hole, 3 is the mask plate, 31 is the light-blocking area, 32 is the aisle light-transmitting area, 33 is the bridge light-transmitting area, 34 is the under-exposed area, 341 is the light-blocking strip, 342 is the light-transmitting strip, 4 is the first electrode, 5 is the second electrode, 6 is the bridge electrode, 7 is the current spreading strip, 71 is the N-electrode current spreading strip, and 72 is the P-electrode current spreading strip. DETAILED DESCRIPTION

[0057] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings. It is hereby stated that any directional terms such as "up," "down," "left," "right," "front," "back," "inside," and "outside" that appear or will appear herein are based solely on the accompanying drawings and are not intended to limit the present invention.

[0058] See also Figure 3 The present invention provides a method for preparing a high-reliability flip-chip LED chip, which comprises the following steps:

[0059] S1: Provide epitaxial wafers;

[0060] Among them, reference Figure 2 The epitaxial wafer 1 includes a substrate 11 and an epitaxial layer 12. The epitaxial layer 12 includes a first semiconductor layer 121, an active layer 122, and a second semiconductor layer 123 stacked in sequence on the substrate 11. The substrate 11 is a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited thereto. The first semiconductor layer 122 may be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto. The active layer 122 may be an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer, or an AlGaN-AlGaN type MQW layer, but is not limited thereto. The second semiconductor layer 123 may be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited thereto.

[0061] Preferably, in one embodiment of the present invention, the epitaxial layer 12 may further include one or more of a buffer layer, an intrinsic semiconductor layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer commonly used in the art, but is not limited thereto.

[0062] S2: forming a first hole, a channel etching groove, and a bridge etching groove etched to the first semiconductor layer on the epitaxial wafer;

[0063] Specifically, refer to Figure 2 、 Figure 3 In one embodiment, the epitaxial layer 12 can be etched using the SiO2 layer as a mask to obtain the first hole 13, the channel etching groove 14, and the bridge etching groove 15 etched into the first semiconductor layer. In another embodiment, the etching can be performed by a photolithography process, but is not limited thereto.

[0064] The first hole 13 is used to later form a first electrode electrically connected to the first semiconductor layer 121. The channel etch groove 14 and the bridge etch groove 15 divide the epitaxial wafer into at least two light-emitting units 16. After the subsequent steps S3 to S8, the multiple light-emitting units 16 are electrically connected only through the bridge electrode, and the other areas are insulated from each other.

[0065] Preferably, in one embodiment, in order to improve the connection stability between the light-emitting units 16, a third hole (not shown in the figure) etched to the first semiconductor layer 121 is also formed on one side of the bridge etching groove 15, which can be used later to form an extended electrode and a current expansion bar connected to the bridge electrode, thereby improving the connection stability and optimizing the current distribution.

[0066] Specifically, the width of the aisle etch groove 14 is smaller than the width of the bridge etch groove 15. Based on this structure, the sidewall angle of the aisle area can be increased and the sidewall angle of the bridge area can be reduced. Preferably, the width of the aisle etch groove is 3 to 8 times the width of the bridge etch groove, and more preferably 3 to 6 times.

[0067] S3: forming a photoresist layer on the epitaxial wafer obtained in step S2;

[0068] Among them, the surface of the epitaxial wafer obtained in step S2 can be entirely coated with a positive photoresist or a negative photoresist commonly used in the art and cured to form a photoresist layer 2, but is not limited thereto. Preferably, in one embodiment, step S3 includes:

[0069] S31: Spin-coating photoresist on the epitaxial wafer obtained in step S2;

[0070] The photoresist may be a common positive photoresist in the art, whose main components are propylene glycol monomethyl ether acetate (75% to 85%) and phenolic resin (5% to 30%). Preferably, in one embodiment, the viscosity of the photoresist is controlled to be 500 cP to 700 cP when baked at 120° C. to 160° C. for 20 to 30 minutes. Based on this type of photoresist, the slope angle of the bridge area can be optimized.

[0071] Specifically, the thickness of the glue after spin coating is 10 μm to 13 μm, and the uniformity of the glue thickness is ≤3%.

[0072] S32, baking at 110°C to 130°C for 110s to 130s to obtain a photoresist layer.

[0073] S4: exposing the photoresist layer using a mask plate to form a first non-exposed area, an aisle exposed area, a bridge exposed area, a second non-exposed area, and an under-exposed area;

[0074] Among them, reference Figure 4 、 Figure 5 The photomask 3 includes a light-blocking area 31, an aisle light-transmitting area 32, a bridge light-transmitting area 33, and under-exposed areas 34 distributed on both sides of the bridge light-transmitting area 33. The under-exposed area 34 includes a plurality of light-blocking strips 341 and light-transmitting strips 342 distributed at intervals. The widths of the plurality of light-transmitting strips 342 decrease from the side close to the bridge light-transmitting area 33 to the side away from the bridge light-transmitting area 33. The light-transmitting widths of the aisle light-transmitting area 32 and the bridge light-transmitting area 33 are greater than the resolution of the light source used for exposure. The light-transmitting widths of the light-transmitting strips 342 are less than the resolution of the light source used for exposure. Based on the above-mentioned structure of the photomask 3, the epitaxial wafer 1 corresponding to the aisle light-transmitting area 32 and the bridge light-transmitting area 33 is fully exposed, and the photoresist layer 2 is completely removed during the development process. However, the epitaxial wafer 1 corresponding to the light-transmitting strips 342 is only under-exposed, and the photoresist layer 2 is partially removed during the development process. Furthermore, by controlling the width of the plurality of light-transmitting strips 342 to decrease from the side close to the bridging light-transmitting area 33 to the side away from the bridging light-transmitting area 33, an under-exposed area with a gradual exposure depth will be formed on the epitaxial wafer 1, and then a hole with a gradual depth will be formed after development, laying a good foundation for the subsequent formation of a small-angle bridging area etching angle.

[0075] Specifically, the width of the aisle light-transmitting area 32 is 2 μm to 4 μm, preferably 2.1 μm to 3.5 μm, and the width of the bridge light-transmitting area 33 is 5 μm to 15 μm, preferably 6 μm to 15 μm.

[0076] Specifically, each under-exposed area 34 includes 5 to 9 light-transmitting strips 342, but is not limited thereto. The width of the light-transmitting strips 342 is within the range of 0.5 μm to 1.9 μm. Preferably, in one embodiment, the width of the plurality of light-transmitting strips 342 decreases from 1.3 μm to 1.8 μm on the side close to the bridge light-transmitting area 33 to 0.5 μm to 0.8 μm on the side away from the bridge light-transmitting area 33. The width of the plurality of light-blocking strips is the same, all of which are 1.2 μm to 1.8 μm. By controlling the width of each component in the mask plate 3, the distribution of energy during the exposure process can be controlled, so that the present invention can form the blocking pattern (photoresist layer) required for etching through a single exposure-development.

[0077] Specifically, in some embodiments of the present invention, the photoresist layer is exposed using a stepper exposure method, with an exposure energy of 1000mJ to 1300mJ, a wavelength of the exposure light source of 320nm to 380nm, and a resolution of 1.8μm to 3μm. Preferably, the exposure energy is 1000mJ to 1200mJ, the wavelength of the exposure light source is 365nm, and the resolution of the exposure light source is 2μm.

[0078] Specifically, after exposure, a first non-exposed area 21, an aisle exposure area 22, a bridge exposure area 23, a second non-exposed area 24, and an under-exposed area 25 are formed on the photoresist layer 2. The first non-exposed area 21 is formed below the light-blocking region 31 of the mask plate 3. The light-blocking region 31 blocks the exposure light, preventing the first non-exposed area 21 from being exposed. The aisle exposure area 22 is formed by irradiating the photoresist layer 2 above the aisle etching groove 14 with exposure light from the aisle light-transmitting region 32. The bridge exposure area 23 is formed by irradiating the photoresist layer 2 above the bridge etching groove 15 with exposure light from the bridge light-transmitting region 33. The second non-exposed area 24 is formed below the light-blocking strips 341 of the mask plate 3. The light-blocking strips 341 block the exposure light, preventing the second non-exposed area 22 from being exposed. The under-exposed area 25 is formed by irradiating the photoresist layer 2 on both sides of the bridge etching groove 15 with exposure light from the light-transmitting strips 342. Based on the shape setting of the mask plate 3, the second non-exposed area 24 and the under-exposed area 25 are spaced apart on both sides of the bridge exposure area 23, and the exposure depth of the multiple under-exposed areas 25 decreases from close to the bridge exposure area 23 to far away from the bridge exposure area 23.

[0079] S5: Developing to remove the photoresist layer in the aisle exposure area, the bridge exposure area, and a preset amount of the photoresist layer in the under-exposure area;

[0080] Specifically, in this step, the exposed epitaxial wafer is immersed in a developer to completely remove the photoresist layer in the aisle exposure area and the bridge exposure area. At the same time, since the photoresist layer in the underexposed area 25 is underexposed, it is partially removed. Figure 7 Since the exposure depths of the multiple under-exposed areas 25 are different, second holes 27 with different depths are formed after development.

[0081] Specifically, since the photoresist layer 2 used in the present invention is relatively thick, development is performed 2 to 4 times, and the development time for each time is controlled to be 40 seconds to 50 seconds.

[0082] S6: baking and curing the remaining photoresist layer;

[0083] After development, the remaining photoresist layer is further solidified by baking to prevent it from peeling off or being etched through during subsequent etching. Specifically, the baking temperature is 120°C to 160°C and the baking time is 150s to 300s.

[0084] Preferably, in one embodiment of the present invention, when a specific photoresist is selected (the viscosity is 500cP~700cP after baking at 120℃~160℃ for 20min~30min), the baking temperature is controlled to be 120℃~160℃, and the baking time is 150s~300s, so that the photoresist layer on both sides of the second hole 26 can be softened and partially fill the second hole 26, thereby forming a sloped photoresist layer on both sides of the bridge etching groove 15, and the inclination angle is 25°~35°, that is, the side wall angle of the bridge area after the later etching is 25°~35°, which greatly optimizes the connection stability of the electrode and improves the reliability of the high-voltage LED chip.

[0085] S7: etching the epitaxial wafer obtained in step S6;

[0086] Specifically, the epitaxial layer 12 can be etched by dry etching (such as RIE, ICP, ECR, etc.) or wet etching. Preferably, dry etching is used, and more preferably, ICP etching is used, which has high etching accuracy.

[0087] Specifically, when using the ICP etching process, the etching gases used are Ar, BCl3, and Cl2, with a flow ratio of Ar, BCl3, and Cl2 of 1:1:3 to 1:5:15; preferably, the flow ratio of the three is 1:1:6. The etching time is 1300s to 1500s, the RF power is 1000W to 1200W, the ICP power is 400W to 500W, and the etching pressure is 1 torr to 10 torr.

[0088] Specifically, after etching, the remaining first semiconductor layer 121 in the aisle etching groove 14 and the bridge etching groove 15 is removed, and then a sidewall with an inclination angle of 60° to 75° is formed on the basis of the aisle etching groove 14 (see FIG. Figure 8 In addition, the epitaxial layer 12 of a predetermined thickness in the under-exposed area can be removed by etching, thereby forming a slope with an inclination angle of ≤45° in the under-exposed area (see Figure 9 ).

[0089] S8: removing the remaining photoresist layer;

[0090] Specifically, the residual photoresist layer may be removed by cleaning with an acidic solution, but the present invention is not limited thereto.

[0091] Preferably, in one embodiment, step S8 includes the following steps:

[0092] S81, removing the remaining photoresist layer;

[0093] S82, forming a current blocking layer on the epitaxial wafer obtained in step S81;

[0094] Among them, the current blocking layer can be a SiO2 layer or SiN layer commonly used in the art. x layer, but not limited to it.

[0095] S83 , forming a transparent conductive layer on the epitaxial wafer obtained in step S82 .

[0096] The transparent conductive layer may be an ITO layer, an IZO layer or an AZO layer commonly used in the art, but is not limited thereto.

[0097] S9: forming a first electrode, a second electrode, and a bridge electrode on the epitaxial wafer obtained in step S8 to obtain a finished high-voltage LED chip;

[0098] The first electrode 4, the second electrode 5 and the bridge electrode 6 can be formed by PVD, evaporation and other processes (see Figure 10 ), but not limited thereto. The first electrode 4, the second electrode 5, and the bridging electrode 6 may have the same or different compositions. Preferably, they are the same, and may be composed of one or more of an Al layer, a Cr layer, a Pt layer, an Ag layer, and an Au layer commonly used in the art.

[0099] Specifically, the first electrode 3 is electrically connected to the first semiconductor layer 121 through the first hole 13. The second electrode 8 is electrically connected to the second semiconductor layer 123 through the transparent conductive layer. After steps S3 to S8 of the present invention, a channel region and a bridge region with different sidewall angles are formed through a single etching process, thereby greatly improving the subsequent electrode coating state, so that there are no defects such as voids and breaks between the bridge electrode layers (see FIG. Figure 12 ), and the aisle area has a large inclination angle, which does not affect the subsequent coverage of the passivation film ( Figure 11 ), thereby greatly improving the reliability of high-voltage LED chips and their luminous efficiency.

[0100] Preferably, in one embodiment of the present invention, step S9 includes the following steps:

[0101] S91, forming a first electrode, a second electrode, a bridge electrode and a current spreading bar on the epitaxial wafer obtained in step S8;

[0102] The current spreading bar 7 includes an N-electrode current spreading bar 71 and a P-electrode current spreading bar 72. The N-electrode current spreading bar 71 is disposed in the third hole and is electrically connected to the first semiconductor layer 121. The P-electrode current spreading bar 72 is disposed on the surface of the transparent conductive layer and is electrically connected to the second semiconductor layer 123.

[0103] S92, forming a passivation layer on the epitaxial wafer obtained in step S91, and opening holes to expose the first electrode and the second electrode, thereby obtaining a finished high-voltage LED chip;

[0104] The passivation layer 8 is a SiO2 layer or a SiNx layer, but is not limited thereto. Its thickness is

[0105] The above is a preferred embodiment of the invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for preparing a high-voltage LED chip, characterized in that: The following steps are involved: S1. Providing an epitaxial wafer; the epitaxial wafer includes a substrate and an epitaxial layer, and the epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate; S2, forming a first hole, a channel etching groove and a bridge etching groove etched to the first semiconductor layer on the epitaxial wafer; The width of the aisle etching groove is smaller than the width of the bridge etching groove; The aisle etching grooves and the bridge etching grooves divide the epitaxial wafer into at least two or more light-emitting units; S3, forming a photoresist layer on the epitaxial wafer obtained in step S2; S4. Exposing the photoresist layer using a photomask to form a first non-exposed area, an aisle exposed area, a bridge exposed area, a second non-exposed area, and an under-exposed area; wherein the aisle exposed area is formed above the aisle etch groove, the bridge exposed area is formed above the bridge etch groove, the non-exposed area and the second under-exposed area are spaced apart on both sides of the bridge exposed area, and the exposure depths of the plurality of under-exposed areas decrease from close to the bridge exposed area to far away from the bridge exposed area; S5, developing and removing the photoresist layer in the aisle exposure area, the bridge exposure area, and a preset amount of the photoresist layer in the under-exposure area; S6, baking and curing the remaining photoresist layer; S7, etching the epitaxial wafer obtained in step S6 to remove the remaining first semiconductor layer in the aisle etch grooves and the bridge etch grooves to expose the substrate; and removing the epitaxial layer of a preset thickness in the underexposed area to form a slope with an inclination angle of ≤45° in the underexposed area; S8, removing the remaining photoresist layer; S9. Form a first electrode, a second electrode, and a bridge electrode on the epitaxial wafer obtained in step S8 to obtain a finished high-voltage LED chip; wherein the first electrode is connected to the first semiconductor layer through the first hole, and the second electrode is connected to the second semiconductor layer.

2. The method for preparing a high-voltage LED chip according to claim 1, wherein: The mask plate includes a light-blocking area, an aisle light-transmitting area, a bridge light-transmitting area, and underexposed areas distributed on both sides of the bridge light-transmitting area. The underexposed area includes a plurality of light-blocking strips and light-transmitting strips distributed at intervals. The widths of the plurality of light-transmitting strips decrease from the side close to the bridge light-transmitting area to the side away from the bridge light-transmitting area. The light-transmitting widths of the aisle light-transmitting area and the bridge light-transmitting area are greater than the resolution of the light source used for exposure; and the light-transmitting width of the light-transmitting strip is smaller than the resolution of the light source used for exposure.

3. The method for preparing a high-voltage LED chip according to claim 2, wherein: The underexposed area includes 5 to 9 light-transmitting strips, and the width of the plurality of light-transmitting strips decreases from 1.3 μm to 1.8 μm on a side close to the bridge light-transmitting area to 0.5 μm to 0.8 μm on a side away from the bridge light-transmitting area; and / or The widths of the plurality of light-blocking strips are all the same, ranging from 1.2 μm to 1.8 μm; and / or The width of the light-transmitting area of ​​the aisle is 2.1 μm to 3.5 μm; and / or The width of the bridge light-transmitting area is 6 μm to 15 μm.

4. The method for preparing a high-voltage LED chip according to claim 1, wherein: Step S3 includes: S31, spin-coating photoresist on the epitaxial wafer obtained in step S2, wherein the thickness of the photoresist is 10 μm to 13 μm and the uniformity is ≤3%; S32. Bake at 110°C~130°C for 110s~130s to obtain a photoresist layer.

5. The method for preparing a high-voltage LED chip according to claim 1, wherein: In step S4, the photoresist layer is exposed by a step-and-step exposure method, the exposure energy is 1000mJ~1300mJ, the wavelength of the exposure light source is 320nm~380nm, and the resolution of the exposure light source is 1.8μm~3μm; and / or In step S5, developing is performed 2 to 4 times, each time for 40 to 50 seconds; and / or In step S6, the baking temperature is 100° C. to 160° C., and the baking time is 100 s to 300 s.

6. The method for preparing a high-voltage LED chip according to claim 1, wherein: In step S2, when the photoresist used in the photoresist layer is baked at 120° C. to 160° C. for 20 min to 30 min, the viscosity thereof is 500 cP to 700 cP; In step S5, after development, a plurality of second holes with different depths are formed on the photoresist layer in the underexposed area; the depths of the second holes decrease from close to the bridge etching groove to far away from the bridge etching groove; In step S6, the baking temperature is 120°C~160°C, and the baking time is 150s~300s, so that the photoresist layer on both sides of the second hole is softened to fill the second hole, and a sloped photoresist layer is formed on both sides of the bridge etching groove, and the inclination angle is 25°~35°.

7. The method for preparing a high-voltage LED chip according to claim 1, wherein: In step S7, when the ICP etching process is adopted, the etching gases used are Ar, BCl3 and Cl2, and the flow ratio of Ar, BCl3 and Cl2 is 1:1:3~1:5:15; the etching time is 1300s~1500s, the RF power is 1000W~1200W, the ICP power is 400W~500W, and the etching pressure is 1torr~10torr.

8. The method for preparing a high-voltage LED chip according to claim 1, wherein: Step S8 includes: S81, removing the remaining photoresist layer; S82, forming a current blocking layer on the epitaxial wafer obtained in step S81; S83 , forming a transparent conductive layer on the epitaxial wafer obtained in step S82 .

9. The method for preparing a high-voltage LED chip according to claim 1, wherein: Step S9 includes: S91, forming a first electrode, a second electrode, a bridge electrode and a current spreading bar on the epitaxial wafer obtained in step S8; S92, forming a passivation layer on the epitaxial wafer obtained in step S91, and opening holes to expose the first electrode and the second electrode, thereby obtaining a finished high-voltage LED chip; Wherein, the thickness of the passivation layer is 2000Å~2500Å.

10. A high-voltage LED chip, characterized in that: The high-voltage LED chip is prepared by the method for preparing the high-voltage LED chip according to any one of claims 1 to 9.

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