A dynamic phase modulation method for ADC sampling clock

Abstract

The present invention provides a dynamic phase modulation method for an ADC sampling clock, comprising: obtaining multiple analog signals; sampling and processing the multiple analog signals respectively through multiple ADC modules to obtain multiple digital signals; multiple ADC modules sending the multiple digital signals to a dynamic phase modulation module; the dynamic phase modulation module performs a first preprocessing based on multiple digital signal cycles until the cycle termination condition is met to obtain a two-dimensional function image; based on the two-dimensional function image, a phase delay parameter is determined; wherein the two-dimensional function image is a function image constructed by a final verification result and a reserved value. By determining the phase stability window, it is possible to select a suitable sampling clock delay time based on the signal acquisition situation, with higher adjustment accuracy and adjustment flexibility, greatly reducing the debugging difficulty of the ADC part, reducing the testing workload of the clock phase stability window, and providing great convenience when multiple ADCs are required for acquisition in the future.

Description

Technical Field

[0001] The present invention relates to the field of dynamic phase modulation, and in particular to a dynamic phase modulation method for an ADC sampling clock. Background Art

[0002] At present, in the prior art, the use of high-speed ADC chips mainly includes two parts, chip configuration and chip high-speed data acquisition, among which the mainstream interfaces of high-speed ADC are divided into LVDS and JESD204B interfaces. For the LVDS interface, during the high-speed data acquisition process, there is often a phase difference between the sampling clock and the high-speed sampling data. It is necessary to fine-tune the phase of the sampling clock input outside the ADC chip to keep it in a relatively stable position to ensure the stability of the ADC data acquisition. At the same time, in order to meet the working stability in high and low temperature environments (the phase may drift under different temperature environments), as the number of ADCs increases, the phase relationship between the sampling clock and all data lines is more stringent, and a flexible and high-precision clock dynamic adjustment method is needed to solve this problem. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0004] To this end, a first aspect of the present invention provides a dynamic phase modulation method for an ADC sampling clock.

[0005] A second aspect of the present invention provides a computer-readable storage medium.

[0006] In view of this, a first aspect of the present invention provides a dynamic phase adjustment method for an ADC sampling clock, comprising: acquiring multiple analog signals; sampling and processing the multiple analog signals respectively through multiple ADC modules to acquire multiple digital signals; the multiple ADC modules send the multiple digital signals to a dynamic phase adjustment module; the dynamic phase adjustment module performs a first preprocessing based on the multiple digital signals in a loop until a loop termination condition is met to acquire a two-dimensional function image; based on the two-dimensional function image, a phase delay parameter is determined; wherein the two-dimensional function image is a function image constructed by a final verification result and a reserved value.

[0007] In addition, the dynamic phase modulation method of the ADC sampling clock in the above technical solution provided by the present invention may also have the following additional technical features:

[0008] In some technical solutions of the present invention, optionally, the dynamic phase modulation module performs a first preprocessing based on multiple digital signal cycles until the cycle termination condition is met, including: the dynamic phase modulation module includes a mixing clock manager and multiple ADC receiving modules; any ADC module sends a zero-phase-delayed associated clock signal to the mixing clock manager; the mixing clock manager sends a first time signal with the same phase as the associated clock signal to the ADC receiving module based on the associated clock signal; the multiple ADC receiving modules respectively extract multiple first sequences from the multiple digital signals based on the first time signal and the duration; the multiple first sequences are subjected to a second preprocessing until the cycle termination condition is met; wherein the multiple ADC modules correspond one-to-one to the multiple ADC receiving modules.

[0009] In some technical solutions of the present invention, optionally, a second preprocessing is performed on multiple first sequences until the loop termination condition is met, including: the dynamic phase adjustment module also includes a receiving verification module; multiple ADC receiving modules send the multiple first sequences to multiple receiving verification modules respectively, and the multiple receiving verification modules respectively perform verification processing on the multiple first sequences to obtain multiple verification results; a third preprocessing is performed on the multiple first sequences until the loop termination condition is met; wherein the multiple ADC receiving modules correspond one-to-one to the multiple receiving verification modules.

[0010] In some technical schemes of the present invention, optionally, a third preprocessing is performed on multiple first sequences until a loop termination condition is met, including: the dynamic phase adjustment module also includes a phase accumulation module, and the reserved value includes an initial reserved value and at least one current reserved value; the phase accumulation module is provided with the initial reserved value, and the initial reserved value is subjected to a phase accumulation processing of a granularity to obtain a current phase accumulation value, and the phase accumulation module sets the current phase accumulation value as the current reserved value; it is determined whether the current phase accumulation value meets the loop termination condition, if the current phase accumulation value meets the loop termination condition, the current phase accumulation value is set as the final phase accumulation value, and the mixing clock manager, multiple ADC receiving modules, multiple receiving verification modules and the phase accumulation module no longer perform the first preprocessing; otherwise, the phase of the first time signal is increased by one granularity to obtain a second time signal, and based on the current reserved value and the second time signal, the dynamic phase adjustment module performs the first preprocessing based on multiple digital signals in a loop until the loop termination condition is met.

[0011] In some technical solutions of the present invention, optionally, the loop termination condition is that the current phase accumulation value exceeds 360°.

[0012] In some technical solutions of the present invention, optionally, multiple receiving verification modules respectively perform verification processing on multiple first sequences to obtain multiple verification results, including: performing FFT processing on multiple first sequences; obtaining the power of multiple first sequences; when multiple powers in the first sequences are greater than a first threshold, the verification result is abnormal, otherwise the verification result is normal; obtain multiple verification results, and when multiple verification results are all normal, the final verification result is true, otherwise the final verification result is false.

[0013] In some technical solutions of the present invention, optionally, obtaining a two-dimensional function image includes: the dynamic phase modulation module also includes a serial port printing module; based on the final verification result and the reserved value, the serial port printing module outputs the two-dimensional function image.

[0014] In some technical solutions of the present invention, optionally, a phase delay parameter is determined based on a two-dimensional function image, including: confirming a maximum stable window based on the two-dimensional function image; taking the midpoint position of the maximum stable window as a phase delay parameter; wherein the horizontal axis of the two-dimensional function image represents a reserved value, and the vertical axis of the phase delay coordinate system represents a final verification result.

[0015] In some technical solutions of the present invention, optionally, the first threshold is -50dBm.

[0016] The second aspect of the present invention provides a computer-readable storage medium on which a program or instruction is stored. When the program or instruction is executed by a processor, a two-way communication method as in any of the above technical solutions is implemented. Therefore, the computer-readable storage medium has all the beneficial effects of the two-way communication method in any of the above technical solutions, which will not be repeated here.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0019] Figure 1 This is one of the flow charts of a method for dynamically adjusting the phase of an ADC sampling clock according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0021] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0022] Refer to the following Figure 1 A method for dynamically adjusting the phase of an ADC sampling clock and a computer-readable storage medium according to some embodiments of the present invention are described.

[0023] like Figure 1 As shown, the first aspect of the present invention provides a dynamic phase adjustment method for an ADC sampling clock, comprising:

[0024] Step 102, obtaining multiple analog signals;

[0025] Step 104, sampling and processing the multiple analog signals respectively through multiple ADC modules to obtain multiple digital signals;

[0026] Step 106, the multiple ADC modules send the multiple digital signals to the dynamic phase modulation module;

[0027] Step 108, the dynamic phase modulation module performs a first preprocessing based on a plurality of digital signal cycles until a cycle termination condition is met, thereby obtaining a two-dimensional function image;

[0028] Step 110, determining a phase delay parameter based on the two-dimensional function image;

[0029] Among them, the two-dimensional function image is a coordinate system constructed by the final verification result and the reserved value.

[0030] The present invention provides a dynamic phase modulation method for an ADC sampling clock, wherein a debugging signal is obtained by an external device, that is, multiple analog signals are obtained, and then the multiple analog signals are sampled by multiple ADC modules. The analog signals are converted into digital signals after sampling, so that the system can perform subsequent processing on the signals.

[0031] The ADC module sends multiple digital signals to the dynamic phase modulation module. After receiving the multiple digital signals, the dynamic phase modulation module performs the first preprocessing in a loop according to the multiple digital signals and preset conditions until the loop termination condition is met, terminates the loop, and obtains a two-dimensional function image; otherwise, the first preprocessing is continued in a loop until the loop termination condition is met. After obtaining the phase delay coordinate system, the phase delay parameter is further determined according to the two-dimensional function image. According to the two-dimensional function image, the delayed phase of the sampling clock of the ADC module can be determined, and then synchronization or timing alignment is achieved according to the delayed phase, so that the system can accurately obtain multi-channel synchronous data.

[0032] By determining the two-dimensional function image, it is possible to select the appropriate sampling clock delay time based on the signal acquisition situation, with higher adjustment accuracy and flexibility, greatly reducing the difficulty of debugging the ADC part and reducing the testing workload of the clock phase stability window. This provides great convenience for subsequent work when multiple ADCs are needed for acquisition, such as sampling satellite-borne GNSS occultation and reflection high-speed AD debugging.

[0033] It should be noted that the number of analog signals, ADC modules and digital signals is equal, and there is a one-to-one correspondence between analog signals and ADC modules, and a one-to-one correspondence between digital signals and ADC modules.

[0034] Preferably, the analog signal is a sine wave signal or a cosine wave signal, and multiple analog signals used for the same dynamic phase modulation are exactly the same, because the sine wave signal or the cosine wave signal is easier to process and is suitable for testing and debugging.

[0035] Preferably, multiple ADC modules are made to work simultaneously through a synchronization signal.

[0036] Further, in some embodiments of the present invention, the dynamic phase modulation module performs a first preprocessing based on a plurality of digital signal cycles until a cycle termination condition is met, including:

[0037] The dynamic phase modulation module includes a mixing clock manager and multiple ADC receiving modules;

[0038] Any ADC module sends a zero-phase-delay accompanying clock signal to the mixer clock manager;

[0039] The mixing clock manager sends a first time signal having the same phase as the accompanying clock signal to the ADC receiving module based on the accompanying clock signal;

[0040] The plurality of ADC receiving modules respectively extract a plurality of first sequences from the plurality of digital signals based on the first time signal and the duration;

[0041] Performing second preprocessing on the plurality of first sequences until a loop termination condition is met;

[0042] Among them, the multiple ADC modules correspond one-to-one to the multiple ADC receiving modules.

[0043] In this embodiment, the dynamic phase adjustment module includes a mixing clock manager and a plurality of ADC receiving modules.

[0044] Among them, when the dynamic phase modulation module works for the first time, the dynamic phase modulation module is first initialized, and any ADC module first sends the accompanying clock signal with zero phase delay to the mixing clock manager. After the mixing clock manager obtains the accompanying clock signal, it understands the situation of the accompanying clocks of multiple ADC modules. On this basis, the mixing clock manager sends a first time signal with the same phase as the accompanying clock signal to the ADC receiving module. According to the first time signal, multiple ADC receiving modules determine the time point that needs to be intercepted in the digital signal, and according to the preset duration, multiple ADC receiving modules respectively intercept multiple first sequences from multiple digital signals. Then, the dynamic phase modulation module performs a second preprocessing on the multiple first sequences until the loop termination condition is met.

[0045] Through the first time signal and duration, the required time series is intercepted for processing, which helps to improve the efficiency of data collection, optimize the data processing process, and improve the quality and efficiency of data processing.

[0046] Specifically, the number of ADC modules is the same as the number of ADC receiving modules, and multiple ADC modules correspond one-to-one to multiple ADC receiving modules, thereby receiving multi-channel parallel signals of the ADC in the clock domain and converting the multi-channel parallel signals into a single continuous serial signal, thereby facilitating subsequent transmission.

[0047] It should be noted that, because multiple ADC modules are operated simultaneously through synchronization signals, only one ADC module needs to send an accompanying clock signal to obtain the accompanying clocks of all ADC modules.

[0048] It should be noted that the mixed-mode clock manager, MMCM (Mixed-Mode Clock Manager), is a key module for clock generation and management in FPGA (field programmable gate array), and is widely used in Xilinx FPGAs in particular.

[0049] Preferably, the duration is greater than or equal to 8 ms.

[0050] Furthermore, in some embodiments of the present invention, performing a second preprocessing on the plurality of first sequences until a loop termination condition is met includes:

[0051] The dynamic phase modulation module also includes a receiving verification module;

[0052] The multiple ADC receiving modules send the multiple first sequences to the multiple receiving verification modules respectively, and the multiple receiving verification modules perform verification processing on the multiple first sequences respectively to obtain multiple verification results;

[0053] Performing third preprocessing on the plurality of first sequences until a loop termination condition is met;

[0054] Among them, the multiple ADC receiving modules correspond one to one to the multiple receiving verification modules.

[0055] In this embodiment, the dynamic phase adjustment module further includes a receiving and verifying module, wherein the multiple ADC receiving modules correspond one to one to the multiple receiving and verifying modules.

[0056] The ADC receiving module sends the multiple first sequences to the receiving verification module based on the corresponding relationship. The receiving verification module verifies the first sequence received by itself and takes the verification situation as the verification result. Then, the multiple first sequences are subjected to the third preprocessing until the loop termination condition is met. By verifying the first sequence, it is convenient to take corresponding processing measures in the subsequent processing, thereby obtaining more accurate and reliable results and making it easier to find the phase stability window.

[0057] It should be noted that the number of receiving and verifying modules is the same as the number of ADC receiving modules, and multiple receiving and verifying modules correspond one-to-one to multiple ADC receiving modules, thereby facilitating the transmission of serial signals from the ADC receiving modules to the receiving and verifying modules.

[0058] Furthermore, in some embodiments of the present invention, performing a third preprocessing on the plurality of first sequences until a loop termination condition is met includes:

[0059] The dynamic phase modulation module further includes a phase accumulation module, and the reserved value includes an initial reserved value and at least one current reserved value;

[0060] An initial reserved value is provided in the phase accumulation module, and the initial reserved value is subjected to a phase accumulation process of a granularity to obtain a current phase accumulation value, and the phase accumulation module sets the current phase accumulation value as the current reserved value;

[0061] Determine whether the current phase accumulation value meets the loop termination condition.

[0062] If the current phase accumulation value meets the loop termination condition, the current phase accumulation value is set as the final phase accumulation value, and the mixing clock manager, the multiple ADC receiving modules, the multiple receiving verification modules and the phase accumulation module no longer perform the first preprocessing;

[0063] Otherwise, the phase of the first time signal is increased by one granularity, and the second time signal is obtained. Based on the current reserved value and the second time signal, the dynamic phase adjustment module performs the first preprocessing based on multiple digital signal cycles until the cycle termination condition is met.

[0064] In this embodiment, the dynamic phase modulation module also includes a phase accumulation module, and the reserved value includes an initial reserved value and at least one current reserved value. After the verification process, the multiple first sequences send an accumulation enable signal to the phase accumulation module. The phase accumulation signal performs a phase accumulation with a phase granularity on the basis of the preset value reserved in the phase accumulation module, and sets the accumulated phase accumulation value as the current phase accumulation value, and sets the current phase accumulation value as the current reserved value of the phase accumulation module. Among them, the phase accumulation module stores the initial reserved value. If the dynamic phase modulation module is working for the first time, the initial reserved value is 0°. On this basis, the initial reserved value is subjected to a granularity phase accumulation process, and the accumulated value is set as the current phase accumulation value, and the current phase accumulation value is set as the current reserved value, which is stored in the phase accumulation module.

[0065] Then, according to the current phase accumulation value, it is determined whether the loop termination condition is met and whether to continue the loop operation or stop the loop to execute the next instruction. If the current phase accumulation value meets the loop termination condition, the current phase accumulation value is set as the final phase accumulation value, the instruction jumps out of the loop, and the mixer clock manager, multiple ADC receiving modules, multiple receiving verification modules and phase accumulation module do not need to continue to operate.

[0066] On the contrary, if the current phase accumulation value does not meet the loop termination condition, the phase accumulation module enables the mixer clock manager to adjust the MMCM output clock phase, that is, the phase of the first time signal increases by one granularity, and the new signal is set as the second time signal. The dynamic phase adjustment module performs the first preprocessing on the multiple digital signal cycles again according to the two new parameters of the current reserved value and the second time signal, that is, executes all the above operations until the loop termination condition is met.

[0067] It should be noted that when the dynamic phase modulation module performs initial processing, it is processed based on the reserved value, the first time signal and the duration. When entering the loop again, the phase of the first time signal is adjusted to obtain the second time signal. The second time signal is used as a new parameter to replace the first time signal as the parameter of the dynamic phase modulation module, and the current reserved value replaces the initial reserved value as the parameter of the dynamic phase modulation module, thereby intercepting the time series of the remaining positions in the digital signal and processing based on this sequence until the loop is exited.

[0068] By obtaining the current phase accumulation value and judging whether to continue the first preprocessing cycle based on the current phase accumulation value, the flexibility and controllability of signal processing are ensured, making it easy to obtain a complete phase window so that adjustments can be made based on complete data, which is crucial for subsequent signal analysis and processing.

[0069] Specifically, the granularity is 1 / 56 of the VCO clock period of the MMCM. It should be noted that the VCO (Voltage-Controlled Oscillator) clock is a key component for the MMCM to implement clock management and frequency synthesis.

[0070] Furthermore, in some embodiments of the present invention, the loop termination condition is that the current phase accumulation value exceeds 360°.

[0071] In this embodiment, the loop termination condition is that the current phase accumulation value exceeds 360°, so that the phase window of the signal of a whole cycle will inevitably be obtained. By ensuring that the current phase accumulation value exceeds 360°, the system can capture the complete phase change information of the signal from 0° to 360°. This is crucial for analyzing the periodicity, phase difference, phase modulation and other characteristics of the signal. The acquisition of the complete phase window enables the system to process and analyze based on more comprehensive data, thereby improving the accuracy of signal processing.

[0072] Furthermore, in some embodiments of the present invention, multiple receiving verification modules respectively perform verification processing on multiple first sequences to obtain multiple verification results, including:

[0073] Performing FFT processing on the multiple first sequences;

[0074] obtaining powers of a plurality of first sequences;

[0075] When multiple powers in the first sequence are greater than the first threshold, the verification result is abnormal, otherwise the verification result is normal;

[0076] Get multiple verification results. When multiple verification results are normal, the final verification result is true, otherwise the final verification result is false.

[0077] In this embodiment, the verification process is as follows: first, the first sequence is subjected to FFT processing, the first sequence is converted from a time domain signal to a frequency domain signal, and then the power of the first sequence is obtained, and the power of the first sequence is detected. When multiple powers in the first sequence are greater than the first threshold, the verification result is abnormal, otherwise the verification result is normal. On this basis, multiple verification results are obtained, and when multiple verification results are all normal, the final verification result is true, otherwise the final verification result is false.

[0078] It can be understood that the process of obtaining the final verification result is an "AND" relationship in a digital circuit. Only when multiple verification results are normal, the final verification result is true.

[0079] By detecting the power of the first sequence and obtaining the verification result, the burrs in the sequence can be effectively identified, and then the abnormal signal can be specially processed when the phase window is printed later, so that the characteristics of the signal can be analyzed more accurately and the processing efficiency and accuracy can be improved.

[0080] What needs to be understood is that FFT, the full name of which is Fast Fourier Transform, is fast Fourier transform.

[0081] Furthermore, in some embodiments of the present invention, obtaining a two-dimensional function image includes:

[0082] The dynamic phase modulation module also includes a serial port printing module;

[0083] Based on the final verification result and the reserved value, the serial port printing module outputs a two-dimensional function image.

[0084] In this embodiment, the dynamic phase modulation module also includes a serial port printing module. Based on the final verification result and the reserved value, the serial port printing module outputs a two-dimensional function image. According to the printing result, a complete cycle can be obtained, so that the sampling clock delay phase window of all ADCs can be normally collected, and then a suitable phase delay can be selected according to the output phase window.

[0085] By outputting the phase window to the serial port printing module based on the verification results, it is convenient to quickly select a window with stable phase and high signal quality for subsequent processing, reducing processing errors and retries caused by unstable phase. The system can process signals more efficiently and optimize overall performance.

[0086] Furthermore, in some embodiments of the present invention, determining the phase delay parameter based on the two-dimensional function image includes:

[0087] Based on the two-dimensional function graph, the maximum stable window is confirmed;

[0088] The midpoint position of the maximum stable window is taken as the phase delay parameter;

[0089] The horizontal axis of the two-dimensional function graph represents the reserved value, and the vertical axis of the phase delay coordinate system represents the final verification result.

[0090] In this embodiment, the vertical axis of the two-dimensional function image is actually composed of "true" and "false", that is, "1" and "0", and the horizontal axis of the two-dimensional function image is composed of reserved values ​​corresponding to the final verification results, that is, the two-dimensional function image is a function image constructed by the final verification results and the reserved values. For example, if the final verification result of the accompanying clock signal with zero phase delay is "true" (i.e., the final verification result corresponding to the reserved value and the reserved value), then at the origin of the coordinate, it will be printed out by the serial port printing module; if the final verification result of the second time signal with a reserved value accumulated by one granularity is "false" (i.e., the current reserved value), then no point will be printed out, that is, the point is "0". After all points are printed out, based on the two-dimensional function image, find the window with the most consecutive points where the final verification result is "true", confirm this window as the maximum stable window, and select the midpoint position of the maximum stable window. Because the reserved value represented by the horizontal axis of the coordinate system of the two-dimensional function image is actually the phase delay, the midpoint position is selected as the phase delay parameter of the ADC clock, and then the two-dimensional function image minimizes the impact of phase fluctuations on subsequent processing, thereby ensuring the stability and reliability of signal processing.

[0091] Further, in some embodiments of the present invention, the first threshold is -50dBm.

[0092] In this embodiment, the first threshold is -50dBm, wherein the threshold setting needs to be set according to the actual debugged ADC background noise index, and it is necessary to ensure that all normal background noises cannot be abnormally triggered. Based on the currently commonly used ADC models, the background noise index is lower than -60dBm, and a 10dB margin is reserved, and -50dBm is set as the threshold.

[0093] By setting the first threshold appropriately, it is ensured that all normal background noise (including system noise, environmental noise, etc.) will not trigger the abnormal detection mechanism. This helps to maintain the stability of signal transmission and avoid signal interruption or erroneous processing due to misjudgment.

[0094] Furthermore, in some embodiments of the present invention, a computer-readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, the dynamic phase modulation method of the ADC sampling clock in any of the above technical solutions is implemented, thereby having all the beneficial technical effects of the dynamic phase modulation method of the ADC sampling clock in any of the above embodiments.

[0095] The computer readable storage medium includes a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0096] A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device, and may be an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above devices, but is not limited thereto. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer floppy disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories, static random access memories, portable compact disc read-only memories, digital versatile disks, memory cards, floppy disks, encoding mechanical devices (such as punched cards or grooves with raised structures with recorded instructions), and any suitable combination of the above devices. The computer-readable storage medium used herein should not be understood as a transmission signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media, or electrical signals transmitted through wires, etc.

[0097] In the claims, specification and drawings of the present invention, the term "multiple" refers to two or more than two. Unless otherwise clearly defined, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the drawings, which is only for the purpose of more conveniently describing the present invention and making the description process simpler, rather than indicating or implying that the device or element referred to must have the specific orientation described, be constructed and operated in a specific orientation, so these descriptions cannot be understood as limiting the present invention; the terms "connect", "install", "fix" and the like should be understood in a broad sense. For example, "connection" can be a fixed connection between multiple objects, or a detachable connection between multiple objects, or an integral connection; it can be a direct connection between multiple objects, or an indirect connection between multiple objects through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood based on the specific circumstances of the above data.

[0098] In the claims, specification and drawings of the present invention, the description of the terms "one embodiment", "some embodiments", "specific embodiments" and the like means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In the claims, specification and drawings of the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0099] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A dynamic phase modulation method for an ADC sampling clock, characterized in that: include: Acquire multiple analog signals; Sampling the multiple analog signals respectively through multiple ADC modules to obtain multiple digital signals; The multiple ADC modules send the multiple digital signals to the dynamic phase modulation module; The dynamic phase modulation module performs a first preprocessing based on the plurality of digital signals in a cycle until a cycle termination condition is met to obtain a two-dimensional function image; Based on the two-dimensional function image, determining a phase delay parameter; Wherein, the two-dimensional function image is a function image constructed by the final verification result and the reserved value; The dynamic phase adjustment module performs a first preprocessing based on the plurality of digital signals in a cycle until a cycle termination condition is met, including: Performing second preprocessing on the plurality of first sequences until the loop termination condition is met; The performing second preprocessing on the plurality of first sequences until the loop termination condition is met includes: The multiple ADC receiving modules send the multiple first sequences to the multiple receiving verification modules respectively, and the multiple receiving verification modules perform verification processing on the multiple first sequences respectively to obtain multiple verification results; The multiple receiving verification modules respectively perform verification processing on the multiple first sequences to obtain multiple verification results, including: Performing FFT processing on the multiple first sequences; Acquiring powers of the plurality of first sequences; When multiple powers in the first sequence are greater than a first threshold, the verification result is abnormal; otherwise, the verification result is normal; The multiple verification results are obtained, and when the multiple verification results are all normal, the final verification result is true, otherwise the final verification result is false.

2. The dynamic phase modulation method of the ADC sampling clock according to claim 1, characterized in that: The dynamic phase adjustment module performs first preprocessing based on the plurality of digital signals in a cycle until a cycle termination condition is met, and further includes: The dynamic phase modulation module includes a mixing clock manager and the plurality of ADC receiving modules; Any one of the ADC modules sends a zero-phase-delayed associated clock signal to the mixing clock manager; The mixing clock manager sends a first time signal having the same phase as the associated clock signal to the ADC receiving module based on the associated clock signal; The multiple ADC receiving modules respectively extract the multiple first sequences from the multiple digital signals based on the first time signal and the duration; The multiple ADC modules correspond one-to-one to the multiple ADC receiving modules.

3. The dynamic phase modulation method of the ADC sampling clock according to claim 2, characterized in that: The performing second preprocessing on the plurality of first sequences until the loop termination condition is met further includes: The dynamic phase modulation module also includes a receiving verification module; Performing a third preprocessing on the plurality of first sequences until the loop termination condition is met; Among them, the multiple ADC receiving modules correspond one-to-one to the multiple receiving verification modules.

4. The method for dynamic phase modulation of ADC sampling clock according to claim 3, characterized in that: The performing third preprocessing on the plurality of first sequences until the loop termination condition is met includes: The dynamic phase adjustment module further includes a phase accumulation module, and the reserved value includes an initial reserved value and at least one current reserved value; The phase accumulation module is provided with the initial reserved value, the initial reserved value is subjected to a phase accumulation process of a granularity to obtain a current phase accumulation value, and the phase accumulation module sets the current phase accumulation value as the current reserved value; Determine whether the current phase accumulation value meets the loop termination condition, If the current phase accumulation value meets the loop termination condition, the current phase accumulation value is set as the final phase accumulation value, and the mixing clock manager, the multiple ADC receiving modules, the multiple receiving verification modules and the phase accumulation module no longer perform the first preprocessing; Otherwise, the phase of the first time signal is increased by one granularity to obtain a second time signal, and based on the current reserved value and the second time signal, the dynamic phase adjustment module performs the first preprocessing based on the multiple digital signals in a loop until the loop termination condition is met.

5. The method for dynamic phase modulation of ADC sampling clock according to claim 4, characterized in that: The loop termination condition is that the current phase accumulation value exceeds 360°.

6. The method for dynamic phase modulation of ADC sampling clock according to claim 1, characterized in that: The step of obtaining a two-dimensional function image comprises: The dynamic phase modulation module also includes a serial port printing module; Based on the final verification result and the reserved value, the serial port printing module outputs the two-dimensional function image.

7. The method for dynamic phase modulation of ADC sampling clock according to claim 6, characterized in that: The determining of the phase delay parameter based on the two-dimensional function image comprises: Based on the two-dimensional function image, confirming the maximum stable window; Using the midpoint position of the maximum stable window as the phase delay parameter; The horizontal coordinate of the two-dimensional function image represents the reserved value, and the vertical coordinate of the phase delay coordinate system represents the final verification result.

8. The method for dynamic phase modulation of ADC sampling clock according to claim 7, characterized in that: The first threshold is -50dBm.

9. A computer-readable storage medium storing a program or instruction, characterized in that: When the program or the instruction is executed by a processor, the dynamic phase adjustment method of the ADC sampling clock according to any one of claims 1 to 8 is implemented.

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