Readout circuit of infrared detector and infrared detection device

Abstract

The invention discloses a readout circuit of an infrared detector and an infrared detection device, and relates to the field of circuit design. A current signal detected by a pixel of the infrared detector needs to be first converted into a voltage signal by a capacitive transimpedance integration circuit, and then the voltage signal is read out by cooperation of a sampling circuit and an output circuit. A capacitive transimpedance integration circuit with a CTIA structure is used to obtain the current signal output by the pixel. The input end of the capacitive transimpedance integration circuit can be connected to power tubes of two polarities, p-on-n and n-on-p, and can receive bipolar input signals, thereby solving the problem that the infrared detector needs to redesign readout circuits of different structures when inputted with different polarities, and has a wide range of applications. The readout circuit is applicable to infrared detectors of two polarity arrays at the same time, thereby reducing the process of designing the readout circuit, saving design time and cost, and improving the use efficiency of the entire infrared detection device.

Description

Technical Field

[0001] The invention relates to the field of circuit design, and in particular to a readout circuit of an infrared detector and an infrared detection device. Background Art

[0002] With the continuous development of infrared systems, infrared detectors have been widely used in various scenarios, and the application of infrared detectors will become more and more extensive in the future. Infrared detectors are detection devices that respond to infrared radiation and convert it into electrical signals by using the charge, heat and other effects generated by the movement of electrons caused by the intrinsic material or external electromagnetic field. In infrared detectors, readout circuits are required to collect, process and read out the converted electrical signals, which is an important part of electrical signal reception and processing. At present, the electrical signals output by infrared detectors include two polarities, n on p and p on n. The readout circuits need to be designed differently to process the electrical signals of the two polarities respectively. Therefore, for different infrared detectors, the corresponding readout circuits need to be redesigned when they are used to receive and process electrical signals, which increases the design cost and affects the efficiency of the infrared detector. Summary of the invention

[0003] The purpose of the present invention is to provide a readout circuit of an infrared detector and an infrared detection device. The input end of the capacitive transimpedance integration circuit can be connected to power tubes of two polarities, p-on-n and n-on-p, and can receive bipolar input signals, thereby solving the problem that the infrared detector needs to redesign readout circuits with different structures when different polarity inputs are used, and the application range is wide. The readout circuit is suitable for infrared detectors of two polarity arrays at the same time, which reduces the process of designing the readout circuit, saves design time and cost, and improves the use efficiency of the entire infrared detection device.

[0004] In order to solve the above technical problems, the present invention provides a readout circuit of an infrared detector, comprising:

[0005] A plurality of capacitive transimpedance integration circuits corresponding one-to-one to the pixels of the infrared detector, the input ends of which are connected one-to-one to the pixels of the infrared detector, and are used to convert the current signals detected by the pixels into voltage signals;

[0006] A sampling circuit, whose input end is connected to the output end of the capacitive transimpedance integration circuit, and is used to sample the voltage signal output by the capacitive transimpedance integration circuit;

[0007] An output circuit, whose input end is connected to the output end of the sampling circuit, is used to read out the voltage signal output by the corresponding sampling circuit according to the requirements of the pixel signal;

[0008] The control circuit has an output end respectively connected to the control end of the capacitive transimpedance integration circuit, the control end of the sampling circuit and the control end of the output circuit, and is used to control the corresponding capacitive transimpedance integration circuit and the sampling circuit to be turned on to realize the collection of the required pixel signal, and control the output circuit to be turned on to realize the reading of the required pixel signal.

[0009] Optionally, the sampling circuit is a column-level circuit, the input end of the column-level circuit is respectively connected to the output end of each capacitive transimpedance integration circuit corresponding to the pixel in the same column, and the output end is connected to the input end of the output circuit, for centralized sampling of voltage signals output by each capacitive transimpedance integration circuit corresponding to the pixel in the same column.

[0010] Optionally, the column-level circuit includes:

[0011] A first sampling switch, configured to be turned on based on the control of the control circuit;

[0012] A first sampling capacitor, a first end of which is grounded;

[0013] A second sampling switch, a first end of which is respectively connected to the output end of the corresponding capacitive transimpedance integration circuit and the first end of the first sampling switch, and is used for being turned on based on the control of the control circuit;

[0014] The second sampling capacitor has a first end grounded and a second end respectively connected to the second end of the second sampling switch, the second end of the first sampling switch and the second end of the first sampling capacitor, and serves as an output end of the column stage circuit.

[0015] Optionally, the output circuit includes:

[0016] A signal input module, a first input end of which is connected to the output end of the sampling circuit, and is used to receive a voltage signal output by the sampling circuit;

[0017] an amplifier stage, a first input end connected to the first output end of the signal input module, a second input end connected to the second output end of the signal input module, and used to amplify the voltage signal;

[0018] The output stage has an input end connected to the output end of the amplifier stage, and an output end serving as the output end of the output circuit and connected to the second input end of the signal input module.

[0019] Optionally, the signal input module includes:

[0020] A first power device, a control end of which serves as a first input end of the signal input module;

[0021] A second power device, a control end of which serves as a second input end of the signal input module;

[0022] a third power device, a control end of which is connected to the control end of the first power device;

[0023] a fourth power device, a control end of which is connected to the control end of the second power device;

[0024] a fifth power device, wherein a first end is respectively connected to the first end of the second power device and the first end of the first power device, a second end is used as a first output end of the signal input module, and a control end is connected to a preset bias voltage;

[0025] A sixth power device has a first end connected to the first end of the fourth power device and the first end of the third power device respectively, a second end serving as a second output end of the signal input module, and a control end connected to the preset bias voltage.

[0026] Optionally, the amplifier stage includes a seventh power device, an eighth power device, a ninth power device, a tenth power device, an eleventh power device, a twelfth power device, a thirteenth power device, a fourteenth power device, a fifteenth power device, a sixteenth power device, a seventeenth power device and an eighteenth power device;

[0027] The first end of the seventh power device is respectively connected to the second end of the fifth power device and the first end of the thirteenth power device, and the second end is respectively connected to the second end of the first power device and the first end of the eighth power device, the second end of the eighth power device is respectively connected to the first end of the ninth power device and the first end of the tenth power device, the second end of the ninth power device is respectively connected to the second end of the tenth power device and the first end of the eleventh power device, the second end of the eleventh power device is respectively connected to the second end of the third power device and the first end of the twelfth power device, and the second end of the twelfth power device is respectively connected to the second end of the sixth power device and the first end of the eighteenth power device;

[0028] The second end of the thirteenth power device is respectively connected to the second end of the second power device and the first end of the fourteenth power device, the second end of the fourteenth power device is respectively connected to the first end of the fifteenth power device and the first end of the sixteenth power device, the second end of the fifteenth power device is respectively connected to the second end of the sixteenth power device and the first end of the seventeenth power device, and the second end of the seventeenth power device is respectively connected to the second end of the fourth power device and the second end of the eighteenth power device;

[0029] The control end of the seventh power device, the control end of the eighth power device, the control end of the ninth power device, the control end of the tenth power device, the control end of the eleventh power device, the control end of the twelfth power device, the control end of the thirteenth power device, the control end of the fourteenth power device, the control end of the fifteenth power device, the control end of the sixteenth power device, the control end of the seventeenth power device and the control end of the eighteenth power device are all connected to the preset bias voltage.

[0030] Optionally, the output stage comprises:

[0031] A nineteenth power device, a first end of which is connected to the first end of the seventh power device, and a controller is connected to the second end of the fourteenth power device;

[0032] The twentieth power device has a first end connected to the second end of the nineteenth power device, a control end connected to the first end of the seventeenth power device, and a second end connected to the first end of the eighteenth power device.

[0033] Optionally, the control circuit includes a controller and a timing circuit, the output end of the controller is connected to the input end of the timing circuit, and the output end of the timing circuit is respectively connected to the control end of the capacitive transimpedance integration circuit, the control end of the sampling circuit, and the control end of the output circuit;

[0034] The controller is used to output different control instructions based on the required pixel signals;

[0035] The timing circuit is used to generate a corresponding timing signal based on the control instruction to control the conduction of the capacitive transimpedance integration circuit, the sampling circuit and the output circuit.

[0036] Optionally, the integration circuit includes:

[0037] An operational amplifier, wherein a first input terminal is connected to a reference voltage, a second input terminal is connected to a pixel of a corresponding infrared detector, and an output terminal serves as an output terminal of the integration circuit;

[0038] Integral capacitor;

[0039] A reset switch, wherein the first end is respectively connected to the first end of the integrating capacitor and the second input end of the operational amplifier, and the second end is respectively connected to the second end of the integrating capacitor and the output end of the operational amplifier. A controller is connected to the output end of the control circuit, and is used to turn on or off based on the control of the control circuit.

[0040] In order to solve the above technical problems, the present invention further provides an infrared detection device, comprising a pixel array and a readout circuit of the infrared detector as described above.

[0041] The present invention provides a readout circuit of an infrared detector, comprising a capacitive transimpedance integration circuit, a sampling circuit, an output circuit and a control circuit. The current signal detected by the infrared detector using a pixel needs to be first converted into a voltage signal by the capacitive transimpedance integration circuit, and then the sampling circuit and the output circuit cooperate to realize the readout of the voltage signal; a capacitive transimpedance integration circuit with a CTIA type structure is used to obtain the current signal output by the pixel, and the input end of the capacitive transimpedance integration circuit can be connected to power tubes of two polarities, p-on-n and n-on-p, and can receive bipolar input signals, thereby solving the problem that the infrared detector needs to redesign a readout circuit with a different structure when inputting different polarities, and has a wide range of applications; the readout circuit is applicable to infrared detectors of two polarity arrays at the same time, reducing the process of designing the readout circuit, saving design time and cost, and improving the use efficiency of the entire infrared detection device.

[0042] The present invention also provides an infrared detection device having the same beneficial effects as the readout circuit of the infrared detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A schematic diagram of the structure of a readout circuit of an infrared detector provided by the present invention;

[0045] Figure 2 A schematic diagram of the structure of another readout circuit of an infrared detector provided by the present invention;

[0046] Figure 3 A schematic structural diagram of a pixel array of an infrared detector provided by the present invention;

[0047] Figure 4 A schematic diagram of the structure of an output circuit provided by the present invention;

[0048] Figure 5 A schematic diagram of an output signal waveform of an integration circuit provided by the present invention;

[0049] Figure 6 A schematic diagram of the arrangement structure of an infrared detection device provided by the present invention;

[0050] Figure 7 A schematic diagram of a signal processing flow of an infrared detection device provided by the present invention. DETAILED DESCRIPTION

[0051] The core of the present invention is to provide a readout circuit of an infrared detector and an infrared detection device. The input end of the capacitive transimpedance integration circuit can be connected to power tubes of two polarities, p-on-n and n-on-p, and can receive bipolar input signals, thereby solving the problem that the infrared detector needs to redesign readout circuits with different structures when inputting different polarities, and has a wide range of applications. The readout circuit is suitable for infrared detectors of two polarity arrays at the same time, which reduces the process of designing the readout circuit, saves design time and cost, and improves the utilization efficiency of the entire infrared detection device.

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a readout circuit of an infrared detector provided by the present invention; please refer to Figure 2 , Figure 2 This is a structural diagram of another readout circuit of an infrared detector provided by the present invention; please refer to Figure 3 , Figure 3 A schematic diagram of the structure of a pixel array of an infrared detector provided by the present invention; To solve the above technical problems, the present invention provides a readout circuit of an infrared detector, comprising:

[0054] A plurality of capacitive transimpedance integration circuits 1 corresponding one to one with the pixels of the infrared detector, the input ends of which are connected one to one with the pixels of the infrared detector, and are used to convert the current signals detected by the pixels into voltage signals;

[0055] A sampling circuit 2, whose input end is connected to the output end of the capacitive transimpedance integration circuit 1, and is used to sample the voltage signal output by the capacitive transimpedance integration circuit 1;

[0056] An output circuit 3, whose input end is connected to the output end of the sampling circuit 2, is used to read out the voltage signal output by the corresponding sampling circuit 2 according to the requirements of the pixel signal;

[0057] The control circuit 4, whose output end is respectively connected to the control end of the capacitive transimpedance integration circuit 1, the control end of the sampling circuit 2 and the control end of the output circuit 3, is used to control the corresponding capacitive transimpedance integration circuit 1 and the sampling circuit 2 to be turned on to realize the collection of the required pixel signal, and control the output circuit 3 to be turned on to realize the reading of the required pixel signal.

[0058] Specifically, the infrared detector mainly scans and samples through the internal pixels. The built-in sensor of the pixel can detect, identify and analyze the infrared information of the target object, and convert the scanned information into a current signal. The current signal is output after receiving and processing by the readout circuit to complete the entire infrared detection process. A capacitive transimpedance integration circuit 1 is configured for each pixel in the readout circuit. The capacitive transimpedance integration circuit 1 can amplify the weak photocurrent signal received from the pixel into a voltage signal, which plays the role of signal amplification and signal conversion. The current signal corresponding to each pixel is integrated by the capacitive transimpedance integration circuit 1, and the current signal is amplified into a voltage signal. Then it is necessary to perform signal processing on the amplified voltage signal, which mainly plays the role of sampling and holding by setting a sampling circuit 2, and the analog voltage signal can be output steadily in a very short time. Finally, the signal output is realized through the output circuit 3.

[0059] It should be noted that each pixel may have an output pixel signal during the application process, so it is necessary to set a capacitive transimpedance integration circuit 1 corresponding to each pixel one by one. For each pixel in the infrared detector, there is a corresponding capacitive transimpedance integration circuit 1; and there are multiple options for the number and setting method of the sampling circuit 2 and the output circuit 3, and the present application does not make any special restrictions here; each pixel has a corresponding sampling circuit 2, but the sampling circuit 2 can be set to multiple sampling circuits 2 corresponding to each pixel one by one, or it can be set to a sampling circuit 2 connected to a pixel group one by one, so as to realize the centralized sampling of the voltage signals of multiple pixels; generally, the output circuit 3 will accumulate multiple voltage signals to one port for reading, and the output circuit 3 acts as a buffer circuit, which can further amplify the received pixel signal; at this time, all pixels can be divided into several pixel groups according to the specific setting of the pixel array, and each pixel group corresponds to an output circuit 3, so as to realize the centralized reading of multiple pixel signals, and improve the charge processing capability of the entire readout circuit by superposition of multiple pixel signals. It may also mean setting the number of output circuits 3 according to the number of signals or the number of signal groups required by the application.

[0060] In practical applications, the pixel signal required for each infrared detection process may be different, and the pixels participating in the detection process may also be different pixels each time. Therefore, the readout circuit does not need to read the pixel signals corresponding to all pixels every time. Therefore, the readout circuit is usually configured with a control circuit 4, and the control circuit 4 will turn on the capacitive transimpedance integration circuit 1 and the sampling circuit 2 corresponding to the currently working pixel according to the specific situation of the current detection process. The capacitive transimpedance integration circuit 1 and the sampling circuit 2 will only process the current signal output by the pixel when they are turned on, so that the output circuit 3 finally outputs only the currently working pixel, and obtains the pixel signal required for the current detection process. Other pixel signals that do not participate in the current detection process do not need to be acquired and processed. By configuring the corresponding control circuit 4 for the pixel array, the corresponding working timing can be configured for the capacitive transimpedance integration circuit 1 and the sampling circuit 2 according to the required working mode. A timing circuit module can also be further set to realize the timing control of the signal receiving from the pixel, the signal processing by the capacitive transimpedance integration circuit 1, and the signal accumulation to the output circuit 3 signal output, so as to realize different signal readout methods.

[0061] It is not difficult to understand that a pixel array is generally used in an infrared detector; the input of each pixel is connected to an n-on-p type photodiode or a p-on-n type photodiode according to the application requirements, so the output of the pixel has two polarity current signals. In order for the readout circuit to be applicable to input signals of two polarities at the same time, the integration circuit 1 as the input module adopts a CTIA (Capacitive Transimpedance Amplifier) ​​type structure, and this type of integration circuit can receive bipolar input signals. Furthermore, the output circuit 3 can also adopt a rail-to-rail input structure to receive the voltage signal of the bipolar input signal.

[0062] It should be noted that the specific arrangement of the pixels in the infrared detector is not particularly limited in this application, and can be specifically expanded from a*a pixel modules, such as Figure 3As shown, the pixel array is composed of a plurality of a*a pixel modules, and the entire N*M pixel matrix is ​​formed by using n*m pixel modules of a*a size, and all the same input bias signals are connected as a whole using n*m identical pixels. At the same time, the size, parameters, ports, etc. of each pixel can be kept consistent. The IN port of each pixel is connected to a photodiode, and the light signal is output to the IN port of the pixel in the form of a current signal using the photosensitivity of the photodiode, and enters the N*M pixel array to realize the process of infrared detection. For the specific implementation of the capacitive transimpedance integration circuit 1, the sampling circuit 2 and the output circuit 3, the present application does not make any special restrictions here. In order to facilitate the acquisition of the current signal corresponding to the pixel, the capacitive transimpedance integration circuit 1 can be directly set in the corresponding pixel. The specific circuit embodiments of the capacitive transimpedance integration circuit 1, the sampling circuit 2 and the output circuit 3 given in this application are only for illustration, and can be designed based on the process conditions, index requirements and input signals when specifically applied. The present application does not impose any particular limitation on the specific size of the pixel module. For example, a 2*2 pixel module can be used to implement a pixel array.

[0063] It is not difficult to understand that other circuits can be set in the readout circuit. In the process of processing the pixel signal, not only can a capacitive transimpedance integration circuit 1 be set to convert the weak current signal waveform into a voltage signal, that is, to convert the picoampere or nanoampere level current signal into a voltage signal to achieve signal amplification; other types of signal processing modules can be further set to perform signal processing processes such as filtering the voltage signal; and a sampling circuit 2 is set to output the processed voltage signal stably. The control circuit 4 may include a main timing control, a window module and a conversion module. The main timing control is used to generate the timing signal required for the control process, the window module is used to provide the timing signal under different windowing modes, and the conversion module is used to convert the timing signal generated by the main timing control into the timing control signal of the capacitive transimpedance integration circuit 1 and each sampling circuit 2 corresponding to each pixel. The specific type and implementation method of the control circuit 4 are not particularly limited in this application.

[0064] The present invention provides a design method for a readout circuit supporting bipolar input, which is used for preparing a readout circuit. The readout circuit can be applicable to two polar array infrared detectors, and there is no need to redesign the readout circuit according to the signal polarity, which reduces the process of designing the readout circuit and saves design time and cost. The invention can solve the problem that different readout circuits need to be designed for different polarity inputs of infrared detectors, and by adopting a CITA type integration circuit 1 to receive a bipolar input signal, a cascode (common source and common gate) two-stage operational amplifier circuit with rail to rail (rail to rail input) class AB (class AB) output can be further adopted as an output circuit 3 to realize the output of a bidirectional output signal.

[0065] The present invention provides a readout circuit of an infrared detector, comprising a capacitive transimpedance integration circuit 1, a sampling circuit 2, an output circuit 3 and a control circuit 4. The current signal detected by the infrared detector using a pixel needs to be first converted into a voltage signal by the capacitive transimpedance integration circuit 1, and then the sampling circuit 2 and the output circuit 3 cooperate to realize the readout of the voltage signal; the capacitive transimpedance integration circuit 1 with a CTIA type structure is used to obtain the current signal output by the pixel, the input end of the capacitive transimpedance integration circuit 1 can be connected to power tubes of two polarities, p-on-n and n-on-p, and can receive bipolar input signals, thereby solving the problem that the infrared detector needs to redesign a readout circuit with a different structure when inputting different polarities, and has a wide range of applications; the readout circuit is applicable to infrared detectors of two polarity arrays at the same time, reducing the process of designing the readout circuit, saving design time and cost, and improving the use efficiency of the entire infrared detection device.

[0066] Based on the above embodiments:

[0067] As an optional embodiment, the sampling circuit 2 is a column-level circuit, the input end of the column-level circuit is respectively connected to the output end of each capacitive transimpedance integration circuit 1 corresponding to the pixel in the same column, and the output end is connected to the input end of the output circuit 3, and is used for centralized sampling of the voltage signals output by each capacitive transimpedance integration circuit 1 corresponding to the pixel in the same column.

[0068] It is not difficult to understand that in an infrared detector, the signal readout process is usually carried out in units of a column of pixels. Therefore, the sampling circuit 2 can be implemented by a column-level circuit. The input end of the column-level circuit is simultaneously connected to multiple capacitive transimpedance integrating circuits 1 corresponding to the pixels in the same column, which can achieve centralized sampling of the signals output by the pixels in the same column. The specific type and implementation method of the column-level circuit are not particularly limited in this application. As a specific embodiment, taking an N*M (row*column) pixel array that finally satisfies L outputs, and the sampling circuit 2 is a column-level circuit as an example, the control circuit 4 determines which L columns (L<M) in the M columns need to be output according to the application requirements, that is, selects L column signals in the M columns corresponding to the current requirements for output. At this time, a total of M sampling circuits 2 are provided in the readout circuit, which correspond to the M columns of pixels one by one. After the control circuit 4 determines the L column signals that finally need to be output, it controls the L column-level circuits corresponding to the L column signals to conduct, and conducts the capacitive transimpedance integrating circuits 1 corresponding to all the pixels in the L columns. When the column-level circuit and the capacitive transimpedance integrating circuit 1 conduct, the pixel signals output by the pixel array are centrally read out through the L column-level circuits, and then the L pixel signals are read out in sequence through the L output buffer circuits, realizing the signal readout of the N*M pixel array. The column-level circuit sampled in this embodiment is only a specific implementation method of the sampling circuit 2. In actual applications, the pixels in the same row can also be used as a pixel group for centralized readout, or the entire pixel array can be divided into several sub-arrays for centralized readout, and the number of sampling circuits 2 provided also changes adaptively.

[0069] Specifically, for the convenience of application, the sampling circuit 2 can be implemented by a column-level circuit. The column-level circuit can achieve centralized sampling of the signals output by the pixels in the same column, accumulate the signals output by the pixels and then output them, improving the readout speed, saving the design cost and volume of the sampling circuit 2, and facilitating the simple implementation of the entire readout circuit.

[0070] As an alternative embodiment, the column-level circuit includes:

[0071] The first sampling switch S1, which is used to conduct based on the control of the control circuit 4;

[0072] The first sampling capacitor C1, with the first end grounded;

[0073] The second sampling switch S2, with the first end respectively connected to the output end of the corresponding capacitive transimpedance integrating circuit 1 and the first end of the first sampling switch S1, and is used to conduct based on the control of the control circuit 4;

[0074] The second sampling capacitor C2, with the first end grounded and the second end respectively connected to the second end of the second sampling switch S2, the second end of the first sampling switch S1, and the second end of the first sampling capacitor C1, and serves as the output end of the column-level circuit.

[0075] It can be understood that the column-level circuit may include but is not limited to the first sampling switch S1, the first sampling capacitor C1, the second sampling switch S2 and the second sampling capacitor C2, so as to realize the stable transmission of the signal to the output buffer circuit of the next level. The first sampling switch S1 and the first sampling capacitor C1 are used as one sampling path, and the second sampling switch S2 and the second sampling capacitor C2 are used as one sampling path. The entire column-level circuit is implemented by using a CDS structure (correlated double sampling). The first sampling switch S1 and the second sampling switch S2 are turned on under the action of the control circuit 4, thereby realizing the conduction of the entire sampling circuit 2. When it is necessary to read the signal, the control circuit 4 controls the first sampling switch S1 and / or the second sampling switch S2 to be turned on, ensuring that there must be a path in the sampling and holding circuit path to sample the signal, and the signal is output to the next level circuit in a centralized manner. The control ends of the first sampling switch S1 and the second sampling switch S2 are connected to the control circuit 4. When the control circuit 4 gives a high level to the control end of the first sampling switch S1 and / or the control end of the second sampling switch S2, the sampling circuit 2 samples the signal output by the previous circuit, charges the corresponding sampling capacitor, and stores the signal in the corresponding sampling capacitor. At the same time, the voltage signal stored in the sampling capacitor is retrieved and accumulated in the output circuit 3 to realize the reading of a column signal. The specific types and implementation methods of the first sampling switch S1, the first sampling capacitor C1, the second sampling switch S2, and the second sampling capacitor C2 are not particularly limited in this application. The first sampling switch S1 and the second sampling switch S2 can be implemented by switching devices such as transmission gates.

[0076] Specifically, the structure of a sampling switch plus a sampling capacitor can be used to sample the signal output by the capacitive transimpedance integration circuit 1, and the energy storage process of the sampling capacitor can be used to implement the sampling and holding process of the signal; at the same time, the column-level circuit adopts a CDS structure, which can suppress noise interference and improve the readout accuracy of the pixel output signal.

[0077] Please refer to Figure 4 , Figure 4 A schematic diagram of the structure of an output circuit provided by the present invention; as an optional embodiment, the output circuit 3 includes:

[0078] A signal input module, wherein a first input terminal is connected to an output terminal of the sampling circuit 2 and is used to receive a voltage signal output by the sampling circuit 2;

[0079] an amplifier stage, a first input end connected to a first output end of a signal input module, a second input end connected to a second output end of the signal input module, and used to amplify a voltage signal;

[0080] The output stage has an input end connected to the output end of the amplifier stage, and the output end serves as the output end of the output circuit 3 and is connected to the second input end of the signal input module.

[0081] It is not difficult to understand that the output buffer circuit can adopt a two-stage operational amplifier structure, in which the first stage mainly plays an amplification role. As an amplification stage, a common source and common gate amplifier circuit with a translinear ring structure can be used to implement it. The second stage mainly plays a role of stabilizing the output. As an output stage, a translinear ring structure can be used on the basis of the amplification stage. Specifically, a translinear ring structure of a class AB (class A and B output stage) structure can be used to provide a stable current source for the entire output circuit 3, so that the output signal is not controlled by the power supply voltage and has a lower power consumption; at the same time, a signal input module that receives the output signal of the previous stage circuit needs to be set to receive the signal output by the sampling circuit 2. Specifically, a rail-to-rail input structure can be used to achieve the full output swing within the power supply voltage range and can receive input within the power supply voltage range. The specific types and implementation methods of the signal input module, the amplification stage and the output stage are not particularly limited in this application. The output end of the output stage is connected to the second input end of the signal input module, and the entire output circuit 3 is implemented in the form of an operational amplifier follower U2 to achieve stable output of the signal.

[0082] Specifically, the output circuit 3 can adopt a two-stage operational amplifier structure to achieve a large gain and ensure good stability; the amplifier stage and the output stage cooperate with each other to realize the structure of a push-pull source follower output stage, which can avoid cross distortion and achieve a larger output swing. At the same time, the signal input module is implemented with a rail-to-rail structure, which can meet the input signal range of two polarities.

[0083] As an optional embodiment, the signal input module includes:

[0084] The first power device M1, the control end of which serves as the first input end of the signal input module;

[0085] The second power device M2, the control end of which serves as the second input end of the signal input module;

[0086] A third power device M3, a control end of which is connected to the control end of the first power device M1;

[0087] A fourth power device M4, a control end of which is connected to the control end of the second power device M2;

[0088] A fifth power device M5, a first end of which is respectively connected to the first end of the second power device M2 and the first end of the first power device M1, a second end of which serves as a first output end of the signal input module, and a control end of which is connected to a preset bias voltage;

[0089] The sixth power device M6 has a first end connected to the first end of the fourth power device M4 and the first end of the third power device M3 respectively, a second end serving as a second output end of the signal input module, and a control end connected to a preset bias voltage.

[0090] It is not difficult to understand that the signal input module can be implemented with a rail-to-rail input structure, with the control end of the first power device M1 serving as one input end and the input end of the second power device M2 serving as another input end, thereby realizing a rail-to-rail structure; when the sampling circuit 2 connected to the output circuit 3 is turned on, the control circuit 4 controls the first power device M1 to be turned on, and the control end of the first power device M1 receives the signal output by the previous circuit, and then outputs the received signal to the amplifier stage, and the controller of the second power device M2 is connected to the total output end of the output circuit 3 through a peripheral circuit, and will be turned on when there is a signal output from the output circuit 3; the third power device M3, the fourth power device M4, the fifth power device M5 and the sixth power device M6 all remain in a normally on state under the action of a preset bias voltage. The present application does not specifically limit the specific types and implementation methods of the first power device M1, the second power device M2, the third power device M3, the fourth power device M4, the fifth power device M5 and the sixth power device M6, and they can be implemented using MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transistor) and other methods.

[0091] Specifically, a signal input module with rail-to-rail input is implemented through power devices, thereby achieving a large swing output of the signal, avoiding signal distortion, and improving the accuracy and reliability of the entire signal readout process.

[0092] As an optional embodiment, the amplifier stage includes a seventh power device M7, an eighth power device M8, a ninth power device M9, a tenth power device M10, an eleventh power device M11, a twelfth power device M12, a thirteenth power device M13, a fourteenth power device M14, a fifteenth power device M15, a sixteenth power device M16, a seventeenth power device M17 and an eighteenth power device M18;

[0093] The first end of the seventh power device M7 is respectively connected to the second end of the fifth power device M5 and the first end of the thirteenth power device M13, and the second end is respectively connected to the second end of the first power device M1 and the first end of the eighth power device M8. The second end of the eighth power device M8 is respectively connected to the first end of the ninth power device M9 and the first end of the tenth power device M10. The second end of the ninth power device M9 is respectively connected to the second end of the tenth power device M10 and the first end of the eleventh power device M11. The second end of the eleventh power device M11 is respectively connected to the second end of the third power device M3 and the first end of the twelfth power device M12. The second end of the twelfth power device M12 is respectively connected to the second end of the sixth power device M6 and the first end of the eighteenth power device M18.

[0094] The second end of the thirteenth power device M13 is respectively connected to the second end of the second power device M2 and the first end of the fourteenth power device M14, the second end of the fourteenth power device M14 is respectively connected to the first end of the fifteenth power device M15 and the first end of the sixteenth power device M16, the second end of the fifteenth power device M15 is respectively connected to the second end of the sixteenth power device M16 and the first end of the seventeenth power device M17, and the second end of the seventeenth power device M17 is respectively connected to the second end of the fourth power device M4 and the second end of the eighteenth power device M18;

[0095] The control end of the seventh power device M7, the control end of the eighth power device M8, the control end of the ninth power device M9, the control end of the tenth power device M10, the control end of the eleventh power device M11, the control end of the twelfth power device M12, the control end of the thirteenth power device M13, the control end of the fourteenth power device M14, the control end of the fifteenth power device M15, the control end of the sixteenth power device M16, the control end of the seventeenth power device M17 and the control end of the eighteenth power device M18 are all connected to the preset bias voltage.

[0096] It is not difficult to understand that the amplification stage can be implemented by a common-source common-gate amplifier composed of a seventh power device M7, an eighth power device M8, a ninth power device M9, a tenth power device M10, an eleventh power device M11, a twelfth power device M12, a thirteenth power device M13, a fourteenth power device M14, a fifteenth power device M15, a sixteenth power device M16, a seventeenth power device M17 and an eighteenth power device M18. The specific types and implementation methods of the fourth power device M14, the fifteenth power device M15, the sixteenth power device M16, the seventeenth power device M17 and the eighteenth power device M18 are not particularly limited in this application. The seventh power device M7, the eighth power device M8, the ninth power device M9, the tenth power device M10, the eleventh power device M11, the twelfth power device M12, the thirteenth power device M13, the fourteenth power device M14, the fifteenth power device M15, the sixteenth power device M16, the seventeenth power device M17 and the eighteenth power device M18 are all in a normally on state under the action of a preset bias voltage during operation.

[0097] Specifically, the common-source and common-gate amplifier can provide higher output impedance, drive larger loads, achieve small noise and offset, output stable signals, realize a stable readout process of pixel signals, and improve the accuracy and reliability of the signal readout process; the entire circuit structure is simple and easy to implement.

[0098] As an optional embodiment, the output stage includes:

[0099] A nineteenth power device M19, a first end of which is connected to the first end of the seventh power device M7, and a controller is connected to the second end of the fourteenth power device M14;

[0100] The twentieth power device M20 has a first end connected to the second end of the nineteenth power device M19 , a control end connected to the first end of the seventeenth power device M17 , and a second end connected to the first end of the eighteenth power device M18 .

[0101] It is not difficult to understand that the output stage is provided with a nineteenth power device M19 and a twentieth power device M20, and the common connection end of the two serves as the output end of the entire output circuit 3, and together with the amplifier stage circuit constitutes a translinear ring structure to achieve a stabilization process of the static current in the circuit; the specific type and implementation method of the nineteenth power device M19 and the twentieth power device M20 are not particularly limited in this application, and can be implemented by MOS tubes and the like.

[0102] Specifically, the output stage of the output circuit 3 adopts a translinear loop structure to implement a class AB bias structure. The output signal is not affected by the power supply voltage and can stably output a voltage signal corresponding to the received input signal. The entire circuit structure is simple and easy to implement.

[0103] As an optional embodiment, the control circuit 4 includes a controller and a timing circuit, the output end of the controller is connected to the input end of the timing circuit, and the output end of the timing circuit is respectively connected to the control end of the capacitive transimpedance integration circuit 1, the control end of the sampling circuit 2, and the control end of the output circuit 3;

[0104] The controller is used to output different control instructions based on the required pixel signals;

[0105] The timing circuit is used to generate corresponding timing signals based on the control instructions to control the conduction of the capacitive transimpedance integration circuit 1 , the sampling circuit 2 and the output circuit 3 .

[0106] It is not difficult to understand that, considering that the pixel array includes multiple pixels, multiple pixels have corresponding capacitive transimpedance integration circuits 1 and sampling circuits 2, and the number of capacitive transimpedance integration circuits 1 and sampling circuits 2 that need to be controlled in the entire infrared detector is relatively large, so the control circuit 4 can realize accurate control of each capacitive transimpedance integration circuit 1 and sampling circuit 2 through a timing signal; therefore, a controller and a timing circuit can be set in the control circuit 4, the controller receives the user's operation instruction, determines the required pixel signal, and issues a control instruction according to the specific situation of the required pixel to characterize the specific conduction situation of the capacitive transimpedance integration circuit 1 and the sampling circuit 2 corresponding to the pixel at each position, and the timing circuit generates a corresponding timing signal according to the control instruction, and uniformly controls each capacitive transimpedance integration circuit 1 and the sampling circuit 2 through the timing signal. The specific type and implementation method of the controller and the timing circuit are not particularly limited in this application, and the timing circuit can be implemented by a decoder or a counter.

[0107] On the other hand, considering that the power device in the output circuit 3 needs a preset bias voltage to maintain conduction, the capacitive transimpedance integration circuit 1 needs to set a reference voltage, and the sampling circuit 2 also needs a reference current or reference voltage in some cases, a bias module can be further set in the readout circuit. The bias module can specifically include a main bias module, a column bias module and an output stage bias. The main bias module includes the bias provided for different functions and the reference current or voltage required for the column bias module and the output stage bias. The column bias module is used to provide the bias current or voltage required by the column-level circuit, and the output stage bias is used to provide the bias current or voltage required by the output circuit 3. The specific type and implementation method of the bias module are not specifically limited in this application, and can be selected and set according to the circuit structure of the readout circuit in actual applications. The specific values ​​of the preset bias voltage and the reference voltage are not specifically limited in this application.

[0108] Specifically, the control process of the control circuit 4 over the entire readout circuit can be implemented by means of timing control. The operation efficiency of the timing control instructions is high, and accurate control of a large number of capacitive transimpedance integration circuits 1 and sampling circuits 2 can also be achieved, thereby improving the accuracy and reliability of the working process of the readout circuit.

[0109] Please refer to Figure 5 , Figure 5 A schematic diagram of an output signal waveform of an integration circuit provided by the present invention; as an optional embodiment, the integration circuit 1 includes:

[0110] Operational amplifier U1, a first input terminal connected to a reference voltage, a second input terminal connected to a corresponding pixel of an infrared detector, and an output terminal serving as an output terminal of an integration circuit 1;

[0111] Integral capacitor C0;

[0112] The reset switch K1 has a first end connected to the first end of the integrating capacitor C0 and the second input end of the operational amplifier U1, and a second end connected to the second end of the integrating capacitor C0 and the output end of the operational amplifier U1. The controller is connected to the output end of the control circuit 4, and is used to turn on or off based on the control of the control circuit 4.

[0113] It is not difficult to understand that the integration circuit 1 can be implemented in the form of a capacitive transimpedance amplifier, specifically including an integration capacitor C0, a reset switch K1, a reference voltage VREF and an operational amplifier U1. The integration circuit 1 is used as the input stage of the readout circuit, and can receive the current signal generated by a p-on-n type or n-on-p type photodiode to achieve bipolar input. The current signal enters the integration circuit 1 through the second input terminal of the operational amplifier U1. When the control circuit 4 gives a high level to the reset switch K1 of the integration circuit 1, the reset switch K1 is closed, the integration circuit 1 is in a reset state, the charge of the integration capacitor C0 is released, and the output level Vout is restored to the level value VREF of the reference voltage; when the control circuit 4 gives a low level to the reset switch K1 of the integration circuit 1, the reset switch K1 is disconnected, the integration circuit 1 is in an integration state, the current signal is converted into a voltage signal, and the voltage signal is stored on the integration capacitor C0. At this time, the specific value of the output level Vout is determined by the integration time and the integration capacitor C0.

[0114] It should be noted that each pixel transmits its own signal to the corresponding integration circuit 1, and all integration circuits 1 can integrate the current signal transmitted by the pixel at the same time, convert it into a voltage signal, and control the voltage signal of any required integration circuit 1 to be regularly transmitted to the next level circuit through the row timing circuit. The specific type and implementation method of the integration capacitor C0, the reset switch K1 and the operational amplifier U1 are not particularly limited in this application. Specifically, Figure 5 As shown, Figure 5 The ordinate is the voltage V, and the abscissa is the input signal IN of the integration circuit 1. When the pixel input is connected to the n-on-p tube, the pixel will receive a weak inward current signal. The integration circuit 1 integrates the inward current signal and outputs a voltage signal from the reference voltage upward, as shown in Curve 1; when the pixel input is connected to the p-on-n tube, the pixel will receive a weak outward current signal. The integration circuit 1 integrates the outward current signal and outputs a voltage signal from the reference voltage downward, as shown in Curve 2.

[0115] Specifically, by adopting the integration circuit 1, the amplification and conversion process of the current signal output by the pixel can be effectively realized. At the same time, the CTIA structure adopted by the integration circuit 1 can realize the reception of photocurrent signals of two polarities, thereby realizing a readout circuit suitable for two polarity situations and reducing the design cost.

[0116] As a specific embodiment, please refer to Figure 6 , Figure 6A schematic diagram of the layout structure of an infrared detection device provided by the present invention; the readout circuit may include but is not limited to three parts, the first part is composed of a pixel array, the second part is composed of a control circuit 4 implemented by a digital circuit, and the third part is composed of a column-level circuit as a sampling circuit 2 and an output circuit 3, and a capacitive transimpedance integration circuit 1 is arranged in the corresponding pixel. The pixel array 100 is arranged in the center, with the pixel array as the center, connected to the sampling circuit 2 of the column-level processing downward, and connected to the row selection timing circuit 101 to the left; the column-level processing unit circuit is connected to the output circuit 3 to the right, and connected to the column selection timing circuit 103 downward; the output circuit 3 is connected to the output timing circuit 104 downward; other circuit parts, such as the bias circuit, can be arranged on the right side of the pixel array according to the principle of circuit correlation, and connected to each circuit to provide a bias current or voltage to each circuit; the timing control circuit 102 is connected to each circuit on the left to provide a timing control signal to each circuit. The row selection timing circuit is used to generate a row selection timing signal, the column selection timing circuit is used to generate a column selection timing signal, and the output timing circuit is used to generate an output timing signal. The controller can determine the specific position of the pixel that currently needs to output the signal according to application requirements, and send the pixel position determination result to the row selection timing circuit, the column selection timing circuit and the output timing circuit. The pixel position is determined by the row selection timing signal and the column selection timing signal, and whether the pixel needs to output the signal is determined by the output timing. Finally, the timing control circuit 4 controls whether the capacitive transimpedance integration circuit 1 corresponding to each pixel is turned on according to the timing signal generation results of the row selection timing circuit, the column selection timing circuit and the output timing circuit, and controls whether the column-level circuit as the sampling circuit 2 is turned on, thereby realizing the process of selecting pixels for signal reading.

[0117] It should be noted that the Rst end of each pixel is also connected to the control circuit 4, and the control circuit 4 controls the reset of the signal in each pixel by outputting a control signal to the Rst end. The control end of the sampling switch in the column-level circuit is connected to the column selection timing circuit in the control circuit 4 to control the column readout timing. VREF is used as the reference voltage of the capacitive transimpedance integration circuit 1 and is input by an external signal. Specifically, the conduction process of the capacitive transimpedance integration circuit 1 corresponding to the pixel can be controlled by the row timing signal output by the row selection timing circuit, and the conduction process of the column-level circuit corresponding to the pixel can be controlled by the column selection timing signal output by the column selection timing circuit.

[0118] For details, please refer to Figure 7 , Figure 7A signal processing flow diagram of an infrared detection device provided by the present invention. A capacitive transimpedance integration circuit 1 is arranged in a pixel, and is used as a signal input module to receive a signal. The signal is converted from a current signal to a voltage signal through the integration circuit 1, and enters the signal processing module of the readout circuit. The signal processing module is composed of a column-level circuit. The voltage signal passes through the column-level circuit, samples the signal, and transmits it to the signal output module. The signal output module is composed of an output buffer circuit, and finally the output buffer circuit outputs the sampled voltage signal. The control circuit 4 includes a row selection timing circuit 101, a timing control circuit 102, a column selection timing circuit 103, and an output timing circuit 104. The timing control circuit 102 is used as a control, and the speed of the capacitive transimpedance integration circuit 1 converting the signal and outputting the signal to the next level circuit, the speed of the column-level circuit sampling the signal and outputting the signal to the output module, the speed and logical relationship of the output signal of the output circuit 3, etc. are controlled through the row selection timing circuit 101, the column selection timing circuit 103, and the output timing circuit 104.

[0119] In order to solve the above technical problems, the present invention further provides an infrared detection device, including a pixel array and a readout circuit of the infrared detector as described above.

[0120] For an introduction to an infrared detection device provided by the present invention, please refer to the embodiment of the readout circuit of the infrared detector mentioned above, and the present invention will not be described in detail here.

[0121] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0122] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0123] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A readout circuit for an infrared detector, characterized in that: include: A plurality of capacitive transimpedance integration circuits corresponding one-to-one to the pixels of the infrared detector, the input ends of which are connected one-to-one to the pixels of the infrared detector, and are used to convert the current signals detected by the pixels into voltage signals; A sampling circuit, whose input end is connected to the output end of the capacitive transimpedance integration circuit, and is used to sample the voltage signal output by the capacitive transimpedance integration circuit; An output circuit, whose input end is connected to the output end of the sampling circuit, is used to read out the voltage signal output by the corresponding sampling circuit according to the requirements of the pixel signal; A control circuit, the output end of which is respectively connected to the control end of the capacitive transimpedance integration circuit, the control end of the sampling circuit and the control end of the output circuit, and is used to control the corresponding capacitive transimpedance integration circuit and the sampling circuit to be turned on to collect the required pixel signal, and control the output circuit to be turned on to read the required pixel signal; The sampling circuit is a column-level circuit, the input end of the column-level circuit is respectively connected to the output end of each capacitive transimpedance integration circuit corresponding to the pixel in the same column, and the output end is connected to the input end of the output circuit, and is used for centralized sampling of the voltage signals output by each capacitive transimpedance integration circuit corresponding to the pixel in the same column; The column-level circuit comprises: A first sampling switch, configured to be turned on based on the control of the control circuit; A first sampling capacitor, a first end of which is grounded; A second sampling switch, a first end of which is respectively connected to the output end of the corresponding capacitive transimpedance integration circuit and the first end of the first sampling switch, and is used for being turned on based on the control of the control circuit; A second sampling capacitor, a first end of which is grounded, and a second end of which is respectively connected to the second end of the second sampling switch, the second end of the first sampling switch, and the second end of the first sampling capacitor, and serves as an output end of the column-level circuit; The output circuit comprises: A signal input module, a first input end of which is connected to the output end of the sampling circuit, and is used to receive a voltage signal output by the sampling circuit; an amplifier stage, a first input end connected to the first output end of the signal input module, a second input end connected to the second output end of the signal input module, and used to amplify the voltage signal; An output stage, the input end of which is connected to the output end of the amplifier stage, the output end of which serves as the output end of the output circuit and is connected to the second input end of the signal input module; The signal input module comprises: A first power device, a control end of which serves as a first input end of the signal input module; A second power device, a control end of which serves as a second input end of the signal input module; a third power device, a control end of which is connected to the control end of the first power device; a fourth power device, a control end of which is connected to the control end of the second power device; a fifth power device, wherein a first end is respectively connected to the first end of the second power device and the first end of the first power device, a second end is used as a first output end of the signal input module, and a control end is connected to a preset bias voltage; A sixth power device has a first end connected to the first end of the fourth power device and the first end of the third power device respectively, a second end serving as a second output end of the signal input module, and a control end connected to the preset bias voltage.

2. The readout circuit of the infrared detector according to claim 1, characterized in that: The amplifier stage includes a seventh power device, an eighth power device, a ninth power device, a tenth power device, an eleventh power device, a twelfth power device, a thirteenth power device, a fourteenth power device, a fifteenth power device, a sixteenth power device, a seventeenth power device and an eighteenth power device; The first end of the seventh power device is respectively connected to the second end of the fifth power device and the first end of the thirteenth power device, and the second end is respectively connected to the second end of the first power device and the first end of the eighth power device, the second end of the eighth power device is respectively connected to the first end of the ninth power device and the first end of the tenth power device, the second end of the ninth power device is respectively connected to the second end of the tenth power device and the first end of the eleventh power device, the second end of the eleventh power device is respectively connected to the second end of the third power device and the first end of the twelfth power device, and the second end of the twelfth power device is respectively connected to the second end of the sixth power device and the first end of the eighteenth power device; The second end of the thirteenth power device is respectively connected to the second end of the second power device and the first end of the fourteenth power device, the second end of the fourteenth power device is respectively connected to the first end of the fifteenth power device and the first end of the sixteenth power device, the second end of the fifteenth power device is respectively connected to the second end of the sixteenth power device and the first end of the seventeenth power device, and the second end of the seventeenth power device is respectively connected to the second end of the fourth power device and the second end of the eighteenth power device; The control end of the seventh power device, the control end of the eighth power device, the control end of the ninth power device, the control end of the tenth power device, the control end of the eleventh power device, the control end of the twelfth power device, the control end of the thirteenth power device, the control end of the fourteenth power device, the control end of the fifteenth power device, the control end of the sixteenth power device, the control end of the seventeenth power device and the control end of the eighteenth power device are all connected to the preset bias voltage.

3. The readout circuit of the infrared detector as claimed in claim 2, characterized in that: The output stage comprises: A nineteenth power device, a first end of which is connected to the first end of the seventh power device, and a controller is connected to the second end of the fourteenth power device; The twentieth power device has a first end connected to the second end of the nineteenth power device, a control end connected to the first end of the seventeenth power device, and a second end connected to the first end of the eighteenth power device.

4. The readout circuit of the infrared detector according to claim 1, characterized in that: The control circuit includes a controller and a timing circuit, the output end of the controller is connected to the input end of the timing circuit, and the output end of the timing circuit is respectively connected to the control end of the capacitive transimpedance integration circuit, the control end of the sampling circuit and the control end of the output circuit; The controller is used to output different control instructions based on the required pixel signals; The timing circuit is used to generate a corresponding timing signal based on the control instruction to control the conduction of the capacitive transimpedance integration circuit, the sampling circuit and the output circuit.

5. The readout circuit of the infrared detector according to any one of claims 1 to 4, characterized in that: The integration circuit comprises: An operational amplifier, wherein a first input terminal is connected to a reference voltage, a second input terminal is connected to a pixel of a corresponding infrared detector, and an output terminal serves as an output terminal of the integration circuit; Integral capacitor; A reset switch, wherein the first end is respectively connected to the first end of the integrating capacitor and the second input end of the operational amplifier, and the second end is respectively connected to the second end of the integrating capacitor and the output end of the operational amplifier. A controller is connected to the output end of the control circuit, and is used to turn on or off based on the control of the control circuit.

6. An infrared detection device, characterized in that: The invention comprises a pixel array and a readout circuit of the infrared detector as claimed in any one of claims 1 to 5.

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