A load type detection circuit

Abstract

The present invention relates to the technical field of detection circuits, and specifically discloses a load type detection circuit. In the circuit, a startup module and a detection module are included; after the circuit is powered on, a target current is generated in the current generation branch of the startup module; the target current is transmitted to the load connection end through the fourth switch tube and the fifth switch tube in sequence; the detection module includes a first target circuit, a second target circuit, a third target circuit and a D trigger; the input end of the first target circuit is connected to the output end of the fourth switch tube; the output end of the third target circuit is connected to the first input end of the D trigger; the output end of the D trigger is connected to the control module to control the working state of the power circuit; the second input end of the D trigger, the control end of the fourth switch tube and the control end of the fifth switch tube are respectively connected to the control voltage. The above scheme provides a reliable load type detection circuit, so that the integrated circuit control chip can be miniaturized or multifunctional.

Description

Technical Field

[0001] The present invention relates to the technical field of detection circuits, and in particular to a load type detection circuit. Background Art

[0002] Miniaturization and multifunctionality are the development trends in the existing integrated circuit field, that is, the existing integrated circuit control chip usually has multiple working modes, so that the power circuit controlled by it can usually be applied to different types of circuit loads, thereby achieving multifunctionality. Therefore, at this time, it is necessary to detect the type of circuit load connected to the power circuit to adjust the working mode of the chip. At the same time, the existing integrated circuit control chip also needs to minimize the chip pins to achieve miniaturization. Therefore, at this time, it is necessary to detect the type of pin load connected to the chip to achieve chip pin reuse.

[0003] Therefore, how to obtain a reliable load type detection circuit is a problem that needs to be solved urgently in this field. Summary of the invention

[0004] In view of this, the present invention provides a load type detection circuit, which, when applied to an integrated circuit control chip, enables the integrated circuit control chip to be miniaturized or multifunctional. The technical solution is as follows:

[0005] In one aspect, the present application provides a load type detection circuit, wherein the load type detection circuit includes a startup module and a detection module;

[0006] After the load type detection circuit is powered on, a target current is generated in the current generation branch of the startup module; the current generation branch includes a fourth switch tube and a fifth switch tube; the target current is transmitted to the load connection end through the fourth switch tube and the fifth switch tube in sequence;

[0007] The detection module includes a first target circuit, a second target circuit, a third target circuit and a D trigger; the input end of the first target circuit is connected to the output end of the fourth switch tube; the output end of the first target circuit is connected to the input end of the second target circuit; the output end of the second target circuit is connected to the input end of the third target circuit; the output end of the third target circuit is connected to the first input end of the D trigger; the output end of the D trigger is connected to the control module to control the working state of the external circuit;

[0008] The second input terminal of the D trigger, the control terminal of the fourth switch tube and the control terminal of the fifth switch tube are respectively connected to the control voltage.

[0009] In an optional implementation, after the load type detection circuit is powered on, the control voltage is at a high level and becomes a low level after a target time period.

[0010] In an optional embodiment, the first target circuit includes a second operational amplifier; the non-inverting input terminal of the second operational amplifier is connected to the output terminal of the fourth switching tube; and the inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier.

[0011] In an optional embodiment, the second target circuit includes a first capacitor, a third operational amplifier and a fourth resistor, the input terminal of the second target circuit is connected to the inverting input terminal of the third operational amplifier through the first capacitor; the inverting input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier through the fourth resistor; and the non-inverting input terminal of the third operational amplifier is grounded.

[0012] In an optional embodiment, the third target circuit includes a fifth resistor, a sixth resistor and a fourth operational amplifier; the input terminal of the third target circuit is connected to the inverting input terminal of the fourth operational amplifier through the fifth resistor; the inverting input terminal of the fourth operational amplifier is connected to the output terminal of the fourth operational amplifier through the sixth resistor; and the non-inverting input terminal of the fourth operational amplifier is grounded.

[0013] In an optional implementation, the resistance value of the fifth resistor is equal to the resistance value of the sixth resistor.

[0014] In an optional implementation, the startup module includes a first current mirror; the first current mirror includes a first branch, a second branch and the current generating branch;

[0015] The first branch of the first current mirror is connected to a first node; the first node is connected to the non-inverting input terminal of the first operational amplifier; the first node is also connected to ground through a first resistor and a first transistor in sequence; the first node is also connected to ground through a second resistor;

[0016] The second branch of the first current mirror is connected to a second node; the second node is connected to the inverting input terminal of the first operational amplifier; the second node is grounded through a second transistor; the second node is also grounded through a third resistor;

[0017] The output end of the first operational amplifier is used to control the working state of the first current mirror.

[0018] In an optional implementation, the resistance value of the second resistor is equal to the resistance value of the third resistor.

[0019] In an optional implementation, the control end of the first transistor is grounded; the control end of the second transistor is grounded; and the ratio of the number of the first transistor to the number of the second transistor is N:1.

[0020] In an optional embodiment, the first branch of the first current mirror includes a first switch tube; the second branch of the first current mirror includes a second switch tube; the current generating branch includes a third switch tube; the output end of the first operational amplifier is respectively connected to the control end of the first switch tube, the control end of the second switch tube, and the control end of the third switch tube.

[0021] In an optional implementation, the output end of the third switch tube is connected to the input end of the fourth switch tube.

[0022] On the other hand, the present application provides an integrated circuit control chip, which includes the above-mentioned load type detection circuit and control module.

[0023] In an optional implementation, the integrated circuit control chip has a load pin; the load pin is connected to a load connection terminal in a load type detection circuit inside the integrated circuit control chip;

[0024] When the integrated circuit control chip is used to detect the type of circuit load connected to the power circuit, the load pin is connected to the circuit load; the control module in the integrated circuit control chip controls the working state of the power circuit according to the circuit load type of the power circuit.

[0025] In an optional implementation, the integrated circuit control chip further includes a pin switching circuit;

[0026] When the integrated circuit control chip is used to detect the pin load type, the load pin of the integrated circuit control chip is connected to the external pin load;

[0027] The control module is connected to the pin switching circuit to control the function of the pin switching circuit to switch the load pin according to the load type of the external pin load.

[0028] The technical solution provided by this application may have the following beneficial effects:

[0029] The present application provides a load type detection circuit. When a resistive load is connected to the load type detection circuit, the load type detection circuit outputs a low level. When a capacitive load is connected to the load type detection circuit, the load type detection circuit outputs a high level, thereby detecting the load type of the connected load. When the load type detection circuit and the control module are applied to an integrated circuit control chip, the control module adjusts the working mode or pin of the chip according to the level output by the load type detection circuit, thereby realizing the multifunctionality or miniaturization of the integrated circuit control chip.

[0030] A load type detection circuit provided in the present application can generate a target current with a zero temperature coefficient, thereby ensuring that the load type detection circuit can reliably output a low level or a high level, greatly improving the safety and reliability of the load type detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 is a structural schematic diagram of a load type detection circuit according to an embodiment of the present invention;

[0033] Figure 2 shows a waveform diagram of a control voltage involved in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of the structure of a load type detection circuit when a resistive load is connected according to an embodiment of the present application is shown;

[0035] Figure 4 A schematic diagram of the structure of a load type detection circuit when a capacitive load is connected according to an embodiment of the present application is shown;

[0036] Figure 5 is a schematic diagram of a circuit structure when detecting the type of circuit load connected to a power circuit according to an embodiment of the present invention;

[0037] Figure 6 It is a schematic diagram of a circuit structure when detecting the type of load on a pin connected to an integrated circuit control chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0040] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0041] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0042] Figure 1 is a schematic diagram of the structure of a load type detection circuit according to an embodiment of the present invention. Figure 1 As shown, the load type detection circuit includes a starting module and a detection module;

[0043] After the load type detection circuit is powered on, a target current is generated in the current generating branch of the startup module; the current generating branch includes a fourth switch tube M4 and a fifth switch tube M5; the target current is sequentially transmitted to the load connection terminal VL through the fourth switch tube M4 and the fifth switch tube M5;

[0044] The detection module includes a first target circuit, a second target circuit, a third target circuit and a D trigger; the input end of the first target circuit is connected to the output end of the fourth switch tube M4; the output end of the first target circuit is connected to the input end of the second target circuit; the output end of the second target circuit is connected to the input end of the third target circuit; the output end of the third target circuit is connected to the first input end of the D trigger; the output end of the D trigger is connected to the control module to control the working state of the external circuit;

[0045] The second input terminal of the D trigger, the control terminal of the fourth switch tube M4 and the control terminal of the fifth switch tube M5 are respectively connected to the control voltage.

[0046] In an optional implementation, after the load type detection circuit is powered on, the control voltage is at a high level and becomes a low level after a target time period.

[0047] In an optional implementation, when the control voltage is at a high level, the fourth switch tube M4, the fifth switch tube M5 and the D trigger are turned on; when the control voltage is at a low level, the fourth switch tube M4, the fifth switch tube M5 and the D trigger are turned off.

[0048] In an optional embodiment, the first target circuit includes a second operational amplifier A2; the non-inverting input terminal of the second operational amplifier A2 is connected to the output terminal of the fourth switch tube M4; the inverting input terminal of the second operational amplifier A2 is connected to the output terminal of the second operational amplifier A2.

[0049] In an optional embodiment, the second target circuit includes a first capacitor C1, a third operational amplifier A3 and a fourth resistor R4, the input end of the second target circuit is connected to the inverting input end of the third operational amplifier A3 through the first capacitor C1; the inverting input end of the third operational amplifier A3 is connected to the output end of the third operational amplifier A3 through the fourth resistor R4; the non-inverting input end of the third operational amplifier A3 is grounded.

[0050] In an optional embodiment, the third target circuit includes a fifth resistor R5, a sixth resistor R6 and a fourth operational amplifier A4; the input end of the third target circuit is connected to the inverting input end of the fourth operational amplifier A4 through the fifth resistor R5; the inverting input end of the fourth operational amplifier A4 is connected to the output end of the fourth operational amplifier A4 through the sixth resistor R6; and the non-inverting input end of the fourth operational amplifier A4 is grounded.

[0051] In an optional implementation, the resistance value of the fifth resistor R5 is equal to the resistance value of the sixth resistor R6.

[0052] In an optional implementation, the startup module includes a first current mirror; the first current mirror includes a first branch, a second branch, and the current generating branch;

[0053] The first branch of the first current mirror is connected to the first node; the first node is connected to the non-inverting input terminal of the first operational amplifier A1; the first node is also connected to the ground through the first resistor R1 and the first transistor Q1 in sequence; the first node is also connected to the ground through the second resistor R2;

[0054] The second branch of the first current mirror is connected to a second node; the second node is connected to the inverting input terminal of the first operational amplifier A1; the second node is grounded through a second transistor Q2; the second node is also grounded through a third resistor R3;

[0055] The output terminal of the first operational amplifier A1 is used to control the working state of the first current mirror.

[0056] In an optional implementation, the resistance value of the second resistor R2 is equal to the resistance value of the third resistor R3.

[0057] In an optional implementation, the control end of the first transistor Q1 is grounded; the control end of the second transistor Q2 is grounded; and the ratio of the number of the first transistor Q1 to the number of the second transistor Q2 is N:1.

[0058] In an optional embodiment, the first branch of the first current mirror includes a first switch tube M1; the second branch of the first current mirror includes a second switch tube M2; the current generating branch includes a third switch tube M3; the output end of the first operational amplifier A1 is respectively connected to the control end of the first switch tube M1, the control end of the second switch tube M2, and the control end of the third switch tube M3.

[0059] In an optional implementation, the output end of the third switch tube M3 is connected to the input end of the fourth switch tube M4.

[0060] In an optional implementation, the first switch tube M1 , the second switch tube M2 , and the third switch tube M3 form a 1:1:1 current mirror.

[0061] In an optional implementation, the first switch tube M1, the second switch tube M2, and the third switch tube M3 are PMOS tubes; and the fourth switch tube M4 and the fifth switch tube M5 are NMOS tubes.

[0062] In an optional implementation, the first transistor Q1 and the second transistor Q2 are PNP transistors.

[0063] Figure 1 The load type detection circuit shown works as follows:

[0064] After the load type detection circuit is powered on, the non-inverting input terminal and the inverting input terminal of the first operational amplifier A1 are both grounded through a resistor, so the first operational amplifier A1 outputs a low level, that is, the output terminal of the first operational amplifier is a low level, and the low level pulls down the voltage of the control terminal of the first switch tube M1, the control terminal of the second switch tube M2, and the control terminal of the third switch tube M3, and the first switch tube M1, the second switch tube M2, and the third switch tube M3 are all turned on. At the same time, the control terminal of the first triode Q1 is grounded, the control terminal of the second triode Q2 is grounded, and the first triode Q1 and the second triode Q2 are all turned on. At this time, the load type detection circuit generates a first current with a current value of i1 flowing through the first switch tube M1, a second current with a current value of i2 flowing through the second switch tube M2, a third current with a current value of i3 flowing through the second resistor R2, a fourth current with a current value of i4 flowing through the first resistor R1 and the first transistor Q1, a fifth current with a current value of i5 flowing through the second transistor Q2, a sixth current with a current value of i6 flowing through the third resistor R3, and a target current with a current value of i7 flowing through the current generation branch.

[0065] At this time, the load type detection circuit is adjusted by the first operational amplifier A1 so that the voltage value v1 of the first node is equal to the voltage value v2 of the second node. Figure 1 From the circuit structure in, we can see that , , where VEB1 is the voltage difference between the emitter and base of the first transistor Q1, VR1 is the voltage on the first resistor R1, is is the reverse saturation current of the second transistor Q2, VEB2 is the voltage difference between the emitter and base of the second transistor Q2, , k is the Boltzmann constant, T is the absolute temperature, and q is the unit charge. At the same time, since the first switch tube M1, the second switch tube M2 and the third switch tube M3 form a 1:1:1 current mirror structure, i1=i2=i7. And because v1=v2, R2=R3, i3=i6. At this time, since no current flows through the input end of the first operational amplifier A1, i1=i3+i4, i2=i6+i5, and then i4= i5. From the above records, it can be seen that ,therefore .Depend on Figure 1 It can be seen that ,therefore, , where vt is a positive temperature coefficient parameter and VEB2 is a negative temperature coefficient parameter.

[0066] Therefore, at this time, the resistance value of the first resistor R1, the resistance value of the third resistor R3 and the value of N can be adjusted so that the positive and negative temperature coefficients in the calculation formulas of the current value i1 of the first current, the current value i2 of the second current and the current value i7 of the target current are offset. At this time, when the control voltage is at a high level, the fourth switch tube M4 and the fifth switch tube M5 are turned on, and the target current with a current value of i7 having a zero temperature coefficient flows into the fourth switch tube M4 and the fifth switch tube M5.

[0067] Figure 2 2 shows a waveform diagram of the control voltage involved in the embodiment of the present application, such as Figure 2 As shown, when the load type detection circuit is just powered on, the voltage value vx of the control voltage is high level, and automatically switches to low level after maintaining the target time period. The target time period can be set according to actual needs.

[0068] In an optional implementation, the load type detection circuit further includes a load pin, which is connected to the load connection terminal VL and is used to connect to an external load. The load type detection circuit can perform load type detection on the connected external load.

[0069] Figure 3 The schematic diagram of the structure of the load type detection circuit when the resistive load is connected to the embodiment of the present application is shown. When the resistive load is connected to the load pin, the fourth switch tube M4 and the fifth switch tube M5 are turned on because the control voltage is at a high level, and the target current with a zero temperature coefficient flows to the resistive load through the fourth switch tube M4 and the fifth switch tube M5. At this time, the voltage value v3 at the in-phase input terminal of the second operational amplifier A2 is i7×RL, where RL is the resistance value of the resistive load. By Figure 3It can be seen from the circuit structure that, finally, the second operational amplifier A2 adjusts the voltage value v4 of its output terminal to be equal to the voltage value v3 of its in-phase input terminal. Moreover, since the target current is a zero temperature coefficient current, the current value i7 of the target current is not affected by temperature and is a reliable fixed value. Therefore, at this time, the voltage value v4 of the output terminal of the second operational amplifier A2 and the voltage value v3 of the in-phase input terminal of the second operational amplifier A2 are both reliable fixed values. Since the in-phase input terminal of the third operational amplifier A3 and the in-phase input terminal of the fourth operational amplifier A4 are both grounded, it can be obtained from the virtual short characteristic of the operational amplifier that the voltage value v5 of the inverting input terminal of the third operational amplifier A3 and the voltage value v7 of the inverting input terminal of the fourth operational amplifier A4 are both 0V, and then according to the virtual disconnection characteristic of the operational amplifier, the current values ​​of the current flowing through the first capacitor C1 and the fourth resistor R4 are equal, both of which are the current value i8 of the eighth current, and the current values ​​of the current flowing through the fifth resistor R5 and the sixth resistor R6 are equal, both of which are the current value i9 of the ninth current. At the same time, since the voltage value v4 at the output terminal of the second operational amplifier A2 is a fixed value, and a first capacitor C1 is provided between the output terminal of the second operational amplifier A2 and the inverting input terminal of the third operational amplifier A3, at this time, the first capacitor C1 can be regarded as an open circuit, and the voltage value v5 at the inverting input terminal of the third operational amplifier A3 is always 0V. Therefore, i8=i9=0A, and the voltage value v7 at the inverting input terminal of the fourth operational amplifier A4 is also always 0V. Therefore, at this time, it can be obtained that the voltage value v8 at the output terminal of the fourth operational amplifier A4 is 0V, that is, the fourth operational amplifier A4 outputs a low level.

[0070] Therefore, after the load type detection circuit is powered on, when the resistive load is connected to the load pin, the high-level control voltage and the low-level output voltage of the fourth operational amplifier A4 are input into the D flip-flop, and the voltage value v9 of the output voltage of the D flip-flop follows the low-level output voltage of the fourth operational amplifier A4 and switches to a low level. Afterwards, when the control voltage switches from a high level to a low level, the state of the voltage value v9 of the output voltage of the D flip-flop is locked and does not change with the voltage value v8 of the output voltage of the fourth operational amplifier A4. Therefore, it can be obtained that when the resistive load is connected to the load pin, the load type detection circuit outputs a low level.

[0071] Figure 4 The schematic diagram of the structure of the load type detection circuit when the capacitive load is connected to the embodiment of the present application is shown. When the capacitive load is connected to the load pin, since the control voltage is at a high level, the fourth switch tube M4 and the fifth switch tube M5 are turned on, and the target current with a zero temperature coefficient flows to the capacitive load through the fourth switch tube M4 and the fifth switch tube M5. At this time, the target current charges the capacitive load, and the voltage value v3 at the non-inverting input terminal of the second operational amplifier A2 gradually increases. It can be seen from the capacitor charging formula that, , where t is the time variable and CL is the capacitance value of the capacitive load. Figure 4 From the circuit structure, it can be seen that, finally, the second operational amplifier A2 adjusts the voltage value v4 at its output terminal to be equal to the voltage value v3 at its non-inverting input terminal, and because the target current is a zero temperature coefficient current, the current value i7 of the target current is a reliable current that is not affected by temperature. Also, because the non-inverting input terminal of the third operational amplifier A3 and the non-inverting input terminal of the fourth operational amplifier A4 are both grounded, it can be obtained from the virtual short characteristic of the operational amplifier that the voltage value v5 at the inverting input terminal of the third operational amplifier A3 and the voltage value v7 at the inverting input terminal of the fourth operational amplifier A4 are both 0V, and according to the virtual open characteristic of the operational amplifier, the current values ​​of the current flowing through the first capacitor C1 and the fourth resistor R4 are equal, both are the current value i8 of the eighth current, and the current values ​​of the current flowing through the fifth resistor R5 and the sixth resistor R6 are equal, both are the current value i9 of the ninth current. At the same time, since the voltage value at the output terminal of the second operational amplifier A2 , and the voltage value v4 is a gradually increasing voltage, so at this time, the eighth current is generated in the first capacitor C1, and since the voltage value v5 of the inverting input terminal of the third operational amplifier A3 is 0V, the current value of the eighth current can be obtained. , the voltage value at the output of the third operational amplifier A3 , and since the voltage value v7 of the inverting input terminal of the fourth operational amplifier A4 is also 0V, the current value of the ninth current is , thus we can get At this time, since the resistance value of the sixth resistor R6 is equal to the resistance value of the fifth resistor R5, it can be obtained that , and because ,therefore, , thus we can get Therefore, the voltage value v8 at the output end of the fourth operational amplifier A4 can be ensured to be a higher value by adjusting the resistance value of the fourth resistor R4, the capacitance value of the first capacitor C1 and the current value i7 of the target current, and since the target current is a reliable current that is not affected by temperature, the fourth operational amplifier A4 can reliably output a high level.

[0072] Therefore, after the load type detection circuit is powered on, when the capacitive load is connected to the load pin, the high-level control voltage and the high-level output voltage of the fourth operational amplifier A4 are input to the D flip-flop. At this time, the voltage value v9 of the output voltage of the D flip-flop follows the high-level output voltage of the fourth operational amplifier A4 to switch to a high level. Afterwards, when the control voltage switches from a high level to a low level, the state of the voltage value v9 of the output voltage of the D flip-flop is locked and does not change with the voltage value v8 of the output terminal of the fourth operational amplifier A4. Therefore, when the capacitive load is connected to the load pin, the load type detection circuit outputs a high level.

[0073] It can be seen that when a resistive load is connected to the load pin in the load type detection circuit, the load type detection circuit outputs a low level; when a capacitive load is connected to the load pin in the load type detection circuit, the load type detection circuit outputs a high level. At the same time, a current with a zero temperature coefficient is generated in the load type detection circuit, thereby ensuring that the load type detection circuit reliably outputs a low level or a high level.

[0074] Figure 5 1 is a schematic diagram of a circuit structure for detecting the type of circuit load connected to a power circuit according to an embodiment of the present invention. Figure 5 As shown, the integrated circuit control chip U1 includes the aforementioned load type detection circuit and control module. The integrated circuit control chip U1 has a load pin, which is connected to the load connection terminal VL in the load type detection circuit inside the integrated circuit control chip.

[0075] When the integrated circuit control chip U1 is used to detect the type of circuit load connected to the power circuit, the load pin is connected to the circuit load. The control module in the integrated circuit control chip controls the working state of the power circuit according to the circuit load type of the power circuit.

[0076] Specifically, the load type detection circuit and the control module are located inside the integrated circuit control chip U1, the power circuit and the circuit load are located outside the integrated circuit control chip U1, and the circuit load is connected to the load pin of the integrated circuit control chip U1. When the circuit load is a resistive load, the load type detection circuit outputs a low level, and the low-level output voltage is input into the control module, and the control module controls the power circuit to work in a corresponding working mode; when the circuit load is a capacitive load, the load type detection circuit outputs a high level, and the high-level output voltage is input into the control module, and the control module controls the power circuit to work in a corresponding working mode.

[0077] Figure 6 It is a schematic diagram of the circuit structure when detecting the type of load of the pin connected to the integrated circuit control chip according to an embodiment of the present invention. The integrated circuit control chip U1 also includes a pin switching circuit.

[0078] When the integrated circuit control chip U1 is used to detect the pin load type, the load pin of the integrated circuit control chip is connected to the external pin load, and the control module is connected to the pin switching circuit to control the pin switching circuit to switch the load pin according to the load type of the external pin load.

[0079] Specifically, the load type detection circuit, the control module and the pin switching circuit are located inside the integrated circuit control chip U1, the pin load is located outside the integrated circuit control chip U1, and the pin load is connected to the load pin of the integrated circuit control chip U1. When the pin load is a resistive load, the load type detection circuit outputs a low level, and the low-level output voltage is input into the control module, and the control module controls the pin switching circuit to switch the load pin to achieve the function; when the pin load is a capacitive load, the load type detection circuit outputs a high level, and the high-level output voltage is input into the control module, and the control module controls the pin switching circuit to switch the load pin to achieve the function.

[0080] In summary, when a resistive load is connected to the load type detection circuit, the load type detection circuit outputs a low level, and when a capacitive load is connected to the load type detection circuit, the load type detection circuit outputs a high level, thereby realizing detection of the load type of the connected load. When the load type detection circuit and the control module are applied to an integrated circuit control chip, the control module adjusts the working mode or pin of the chip according to the level output by the load type detection circuit, thereby realizing multifunctionality or miniaturization of the integrated circuit control chip.

[0081] Furthermore, the load type detection circuit can generate a target current with a zero temperature coefficient, thereby ensuring that the load type detection circuit reliably outputs a low level or a high level, greatly improving the safety and reliability of the load type detection circuit.

[0082] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A load type detection circuit, characterized in that: The load type detection circuit includes a starting module and a detection module; After the load type detection circuit is powered on, a target current is generated in the current generation branch of the startup module; the current generation branch includes a fourth switch tube and a fifth switch tube; the target current is transmitted to the load connection end through the fourth switch tube and the fifth switch tube in sequence; The detection module includes a first target circuit, a second target circuit, a third target circuit and a D trigger; the input end of the first target circuit is connected to the output end of the fourth switch tube; the output end of the first target circuit is connected to the input end of the second target circuit; the output end of the second target circuit is connected to the input end of the third target circuit; the output end of the third target circuit is connected to the first input end of the D trigger; the output end of the D trigger is connected to the control module to control the working state of the external circuit; The second input terminal of the D flip-flop, the control terminal of the fourth switch tube, and the control terminal of the fifth switch tube are respectively connected to the control voltage; wherein, after the load type detection circuit is powered on, the control voltage is at a high level, and becomes a low level after a target time period; After the load type detection circuit is powered on, when the resistive load is connected to the load connection terminal, the output terminal voltage of the third target circuit is at a low level, the output voltage of the D trigger is at a low level, and after the target time period, the control voltage is switched from a high level to a low level, the output voltage of the D trigger is locked at a low level; when the capacitive load is connected to the load connection terminal, the output terminal voltage of the third target circuit is at a high level, the output voltage of the D trigger is at a high level, and after the target time period, the control voltage is switched from a high level to a low level, the output voltage of the D trigger is locked at a high level.

2. The load type detection circuit according to claim 1, characterized in that: The first target circuit includes a second operational amplifier; the non-inverting input terminal of the second operational amplifier is connected to the output terminal of the fourth switch tube; and the inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier.

3. The load type detection circuit according to claim 1, characterized in that: The second target circuit includes a first capacitor, a third operational amplifier and a fourth resistor, the input end of the second target circuit is connected to the inverting input end of the third operational amplifier through the first capacitor; the inverting input end of the third operational amplifier is connected to the output end of the third operational amplifier through the fourth resistor; the non-inverting input end of the third operational amplifier is grounded.

4. The load type detection circuit according to claim 1, characterized in that: The third target circuit includes a fifth resistor, a sixth resistor and a fourth operational amplifier; the input end of the third target circuit is connected to the inverting input end of the fourth operational amplifier through the fifth resistor; the inverting input end of the fourth operational amplifier is connected to the output end of the fourth operational amplifier through the sixth resistor; and the non-inverting input end of the fourth operational amplifier is grounded.

5. The load type detection circuit according to claim 4, characterized in that: The resistance value of the fifth resistor is equal to the resistance value of the sixth resistor.

6. The load type detection circuit according to any one of claims 1 to 5, characterized in that: The startup module includes a first current mirror; the first current mirror includes a first branch, a second branch and the current generating branch; The first branch of the first current mirror is connected to a first node; the first node is connected to the non-inverting input terminal of the first operational amplifier; the first node is also connected to ground through a first resistor and a first transistor in sequence; the first node is also connected to ground through a second resistor; The second branch of the first current mirror is connected to a second node; the second node is connected to the inverting input terminal of the first operational amplifier; the second node is grounded through a second transistor; the second node is also grounded through a third resistor; The output end of the first operational amplifier is used to control the working state of the first current mirror.

7. The load type detection circuit according to claim 6, characterized in that: The resistance value of the second resistor is equal to the resistance value of the third resistor.

8. The load type detection circuit according to claim 6, characterized in that: The control end of the first transistor is grounded; the control end of the second transistor is grounded; and the ratio of the number of the first transistor to the number of the second transistor is N:

1.

9. The load type detection circuit according to claim 6, characterized in that: The first branch of the first current mirror includes a first switch tube; the second branch of the first current mirror includes a second switch tube; the current generating branch includes a third switch tube; the output end of the first operational amplifier is respectively connected to the control end of the first switch tube, the control end of the second switch tube and the control end of the third switch tube.

10. The load type detection circuit according to claim 9, characterized in that: The output end of the third switch tube is connected to the input end of the fourth switch tube.

11. An integrated circuit control chip, characterized in that: The integrated circuit control chip includes the load type detection circuit and control module as described in any one of claims 1 to 10.

12. The integrated circuit control chip according to claim 11, characterized in that: The integrated circuit control chip has a load pin; the load pin is connected to a load connection terminal in a load type detection circuit inside the integrated circuit control chip; When the integrated circuit control chip is used to detect the type of circuit load connected to the power circuit, the load pin is connected to the circuit load; the control module in the integrated circuit control chip controls the working state of the power circuit according to the circuit load type of the power circuit.

13. The integrated circuit control chip according to claim 11, characterized in that: The integrated circuit control chip also includes a pin switching circuit; When the integrated circuit control chip is used to detect the pin load type, the load pin of the integrated circuit control chip is connected to the external pin load; The control module is connected to the pin switching circuit to control the function of the pin switching circuit to switch the load pin according to the load type of the external pin load.

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