Gate polysilicon short-circuit test structure and generation method, device and storage medium thereof

Abstract

The present application relates to a gate polysilicon short-circuit test structure and a generation method, device and storage medium thereof. The method comprises the following steps: determining at least one target area in a standard cell area of ​​a layout; obtaining a first auxiliary graphic and a second auxiliary graphic in the target area; generating a first metal line and a second metal line based on the first auxiliary graphic and the second auxiliary graphic respectively; defining a first target gate polysilicon and a second target gate polysilicon from gate polysilicon in the target area; setting a gate through hole in an area where the first metal line overlaps with the first target gate polysilicon, and setting a gate through hole in an area where the second metal line overlaps with the second target gate polysilicon; connecting the first metal line / the second metal line to the first target gate polysilicon / the second target gate polysilicon respectively through the gate through hole to obtain a gate polysilicon short-circuit test structure, thereby solving the problems of low test structure generation efficiency and yield, realizing automatic generation of test results, and improving efficiency and accuracy.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to a gate polysilicon short-circuit test structure and a generation method, device and storage medium thereof. Background Art

[0002] As the process node of integrated circuits continues to shrink to 14nm or below, the distance between gate polysilicon is getting shorter and shorter. Due to the optical proximity effect in the photolithography process, there is a risk of short circuit between gate polysilicon after actual photolithography. Therefore, it is necessary to build a test structure to test the relevant properties of transistors in the standard cell area to quantify the above risks.

[0003] The traditional way to build a test structure is to do it manually in EDA software, which is more suitable for building a test structure for a small layout. If the layout area is too large, the manual processing method is time-consuming and cumbersome. In addition, manual drawing is more prone to human errors, resulting in structural errors, and the functions required by the test cannot be achieved.

[0004] Therefore, the existing manual drawing method for generating a gate polysilicon short test structure cannot meet the requirements in terms of efficiency and functionality. Summary of the invention

[0005] In this embodiment, a gate polysilicon short test structure and a generation method, device and storage medium thereof are provided to solve the problems of test structure generation efficiency and functional requirements in related technologies.

[0006] In a first aspect, a method for generating a gate polysilicon short test structure is provided in this embodiment, the method comprising:

[0007] Acquire a layout, determine a test area in a standard cell area of ​​the layout, and divide the test area into at least one target area;

[0008] In the target area, auxiliary lines are arranged based on power line areas of different doped active areas, and the auxiliary lines are moved and extended to obtain a first auxiliary pattern and a second auxiliary pattern; and a first metal line and a second metal line are generated based on the first auxiliary pattern and the second auxiliary pattern respectively;

[0009] After selecting effective gate polysilicon from the gate polysilicon in the target area, the effective gate polysilicon at the first position is used as the first target gate polysilicon, and the effective gate polysilicon at the second position is used as the second target gate polysilicon;

[0010] A gate through hole is set in the area where the first metal line overlaps with the first target gate polysilicon, and a gate through hole is set in the area where the second metal line overlaps with the second target gate polysilicon; the first metal line is connected to the first target gate polysilicon through the gate through hole, and the second metal line is connected to the second target gate polysilicon through the gate through hole, thereby completing the generation of the gate polysilicon short-circuit test structure.

[0011] In some embodiments, dividing the test area into at least one target area comprises:

[0012] Acquire a body pole region in the test region, and divide the test region into at least one sub-region based on the body pole region;

[0013] After shrinking the sub-areas to a first preset size, a target area is obtained.

[0014] In some embodiments, in the target region, auxiliary lines are arranged in power line regions of different doped active regions, and the auxiliary lines are moved and extended to obtain first auxiliary patterns and second auxiliary patterns, including:

[0015] Acquire a power line region in the target region, and set auxiliary lines based on the power line region in different doped active regions; the doped active regions include N-type doped active regions and P-type doped active regions;

[0016] The auxiliary line is subjected to a first movement process and a second movement process respectively; the first movement process comprises: translating a third preset distance along a first direction; the second movement process comprises: translating a third preset distance along a second direction; the first direction and the second direction are opposite;

[0017] Extending the plurality of auxiliary lines that have undergone the first movement processing, and connecting one ends of the plurality of auxiliary lines together and merging them into a first auxiliary pattern;

[0018] The plurality of auxiliary lines that have undergone the second movement process are extended, and one ends of the plurality of auxiliary lines are connected together and then merged to form a second auxiliary graphic.

[0019] In some of the embodiments, the auxiliary lines are provided based on the power line regions in the differently doped active regions, further comprising:

[0020] Based on the second preset size, the width of the auxiliary line is adjusted.

[0021] In some embodiments, the plurality of auxiliary lines subjected to the first movement processing are extended, and one ends of the plurality of auxiliary lines are connected together and then merged as a first auxiliary pattern; the plurality of auxiliary lines subjected to the second movement processing are extended, and one ends of the plurality of auxiliary lines are connected together and then merged as a first auxiliary pattern, including:

[0022] The plurality of auxiliary lines that have undergone the first movement processing are extended in a third direction, one ends of the plurality of auxiliary lines are connected together through a first longitudinal connection line, and then combined into a first auxiliary pattern;

[0023] The plurality of auxiliary lines subjected to the second movement processing are extended in a fourth direction, one ends of the plurality of auxiliary lines are connected together through a second longitudinal connection line, and then combined into a second auxiliary pattern;

[0024] Wherein, the third direction is opposite to the fourth direction.

[0025] In some of the embodiments, when there are at least two target areas, the first auxiliary pattern further includes a first parallel line to connect one end of the first longitudinal line in each of the target areas to the first parallel line;

[0026] The second auxiliary pattern further includes a second parallel line to connect one end of the second longitudinal line in each of the target areas to the second parallel line.

[0027] In some embodiments, after selecting effective gate polysilicon from the gate polysilicon in the target area, the effective gate polysilicon at the first position is used as the first target gate polysilicon, and the effective gate polysilicon at the second position is used as the second target gate polysilicon, and the above also includes:

[0028] The gate polysilicon in the target area is obtained, and positions of two adjacent gate polysilicon are defined as a first position and a second position along a source-drain direction.

[0029] In some embodiments, selecting effective gate polysilicon from gate polysilicon in the target region includes:

[0030] Screening out initial effective gate polysilicon from the gate polysilicon in the target area; the initial effective gate polysilicon refers to the gate polysilicon area remaining after excluding the area overlapping with the gate cut-off pattern of the gate cut-off layer in the gate polysilicon that is not in contact with the single diffusion interrupt isolation;

[0031] In the initial effective gate polysilicon, after excluding the preset invalid area, the remaining initial effective gate polysilicon is used as the effective gate polysilicon;

[0032] Wherein, the preset invalid region includes: a first invalid gate polysilicon, a second invalid gate polysilicon and a third invalid gate polysilicon;

[0033] The first ineffective gate polysilicon contacts a gate interconnection line spanning across a plurality of the gate polysilicons;

[0034] Two adjacent gate polysilicon layers of the second ineffective gate polysilicon layer are in contact with the single diffusion interrupt isolation;

[0035] The third ineffective gate polysilicon contacts a floating gate cutoff pattern that cuts off at least two of the gate polysilicons; the floating gate cutoff pattern is a gate cutoff pattern on the gate cutoff layer that does not contact the power line region.

[0036] In a second aspect, an embodiment of the present application further provides a device for generating a gate polysilicon short test structure, the device comprising:

[0037] A target area determination module, used to obtain a layout, determine a test area in a standard cell area of ​​the layout, and divide the test area into at least one target area;

[0038] An auxiliary pattern generation module is used to set auxiliary lines in the target area based on the power line area of ​​the different doped active areas, move and extend the auxiliary lines to obtain a first auxiliary pattern and a second auxiliary pattern; and generate a first metal line and a second metal line based on the first auxiliary pattern and the second auxiliary pattern respectively;

[0039] a target gate polysilicon screening module, configured to screen out effective gate polysilicon from the gate polysilicon in the target area, and use the effective gate polysilicon at the first position as the first target gate polysilicon, and use the effective gate polysilicon at the second position as the second target gate polysilicon;

[0040] A test structure generation module is used to set a gate through hole in the area where the first metal line overlaps with the first target gate polysilicon, and set a gate through hole in the area where the second metal line overlaps with the second target gate polysilicon; the first metal line is connected to the first target gate polysilicon through the gate through hole, and the second metal line is connected to the second target gate polysilicon through the gate through hole, thereby completing the generation of the gate polysilicon short-circuit test structure.

[0041] In a third aspect, an embodiment of the present application further provides a gate polysilicon short test structure, the test structure comprising: the test structure is generated based on the method described in any one of the first aspects above;

[0042] The test structure includes: a first target gate polysilicon, a second target gate polysilicon, a first metal line, a second metal line and a gate through hole; the first metal line is connected to the first target gate polysilicon through the gate through hole, and the second metal line is connected to the second target gate polysilicon through the gate through hole; the first metal line and the second metal line serve as test pins of the gate polysilicon short-circuit test structure. The test structure uses the first metal line and the second metal line to be connected to the test pads respectively, so as to connect to an external tester through the test pads to perform a gate polysilicon short-circuit test.

[0043] In a fourth aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method for generating a gate polysilicon short test structure as described in the first aspect is implemented.

[0044] In a fifth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method for generating a gate polysilicon short-circuit test structure in the first aspect is implemented.

[0045] Compared with the related art, the gate polysilicon short test structure and its generation method, device and storage medium provided in this embodiment obtain a layout, determine a test area in the standard cell area of ​​the layout, and divide the test area into at least one target area; in the target area, auxiliary lines are set based on the power line area of ​​different doped active areas, and the auxiliary lines are moved and extended to obtain a first auxiliary pattern and a second auxiliary pattern; based on the first auxiliary pattern and the second auxiliary pattern, a first metal line and a second metal line are generated respectively; after screening out effective gate polysilicon from the gate polysilicon in the target area, the gate polysilicon located in the target area is moved and extended to obtain a first auxiliary pattern and a second auxiliary pattern; The effective gate polysilicon at the first position is used as the first target gate polysilicon, and the effective gate polysilicon at the second position is used as the second target gate polysilicon; a gate through hole is set in the area where the first metal line overlaps with the first target gate polysilicon, and a gate through hole is set in the area where the second metal line overlaps with the second target gate polysilicon; the first metal line / the second metal line are connected to the first target gate polysilicon / the second target gate polysilicon through the gate through hole respectively, to obtain a gate polysilicon short-circuit test structure, which solves the problems of low efficiency and high error rate of test structure generation, realizes automatic generation of test results, and improves efficiency and accuracy. In the standard cell area, the present application distinguishes the left and right adjacent gate polysilicon (distinguishing the first position and the second position, and in the embodiment, all gates are distinguished by adding Masks in advance), and then removes the gate polysilicon that is invalid for the test, so that the gatevia (gate through hole) on the adjacent gate polysilicon can be on different pins, achieving the scenario required by the test object. The present application generates the area required for the test structure by obtaining the information of the layer in the original layout, automatically completes the screening and metal wiring of the target gate polysilicon, and realizes the automatic generation of the test structure.

[0046] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0048] Figure 1 A hardware structure block diagram of a terminal of a method for generating a gate polysilicon short-circuit test structure in one embodiment;

[0049] Figure 2 It is a schematic flow chart of a method for generating a gate polysilicon short-circuit test structure in one embodiment;

[0050] Figure 3A schematic diagram of a target area in a preferred embodiment;

[0051] Figure 4 A schematic diagram of a gate polysilicon pattern for distinguishing a first position and a second position in a preferred embodiment;

[0052] Figure 5 A schematic diagram of an initial effective gate polysilicon in a preferred embodiment;

[0053] Figure 6 A schematic diagram of an invalid area in a preferred embodiment;

[0054] Figure 7 A schematic diagram of a first auxiliary graphic and a second auxiliary graphic in a preferred embodiment;

[0055] Figure 8 A schematic diagram of a gate through hole in a preferred embodiment;

[0056] Fig. 9 It is a practical layout effect diagram of a gate polysilicon short-circuit test structure in a preferred embodiment;

[0057] Fig.10 for Fig. 9 A partial enlarged view of

[0058] Fig.11 for Fig.10 A partial enlarged view of

[0059] Fig.12 FIG. 4 is a structural block diagram of a device for generating a gate polysilicon short-circuit test structure in an embodiment. DETAILED DESCRIPTION

[0060] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0061] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0062] The method embodiment provided in this embodiment can be executed in a terminal, a computer or a similar computing device. For example, running on a terminal, Figure 1 1 is a hardware structure block diagram of a terminal of the method for generating a gate polysilicon short circuit test structure of this embodiment. Figure 1 As shown, the terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 and a memory 104 for storing data, wherein the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA. The above terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0063] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for generating the gate polysilicon short-circuit test structure in the present embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0064] The transmission device 106 is used to receive or send data via a network. The above network includes a wireless network provided by a communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is used to communicate with the Internet wirelessly.

[0065] In this embodiment, a method for generating a gate polysilicon short-circuit test structure is provided. Figure 2 FIG. 1 is a flow chart of a method for generating a gate polysilicon short circuit test structure according to the present embodiment. Figure 2 As shown, the process includes the following steps:

[0066] Step S210 , acquiring a layout, determining a test area in a standard cell area of ​​the layout, and dividing the test area into at least one target area.

[0067] Specifically, layout information is obtained from the original layout, including: active area, gate, single diffusion break isolation SDB (single diffusion break) used to disconnect the active area, polycut used to disconnect the gate, local interconnection line on the gate, power line area, and standard cell area. Standard cells are used extensively in the layout design of integrated circuits to form circuits. Since the layout in the standard cell area is arranged according to certain rules, all operations in this example are performed in the standard cell area. A test area is selected in the standard cell area of ​​the layout. In this embodiment, a rectangular test area is selected, but in some embodiments, other regular or irregular test areas can also be selected. In this embodiment, the test area is divided into at least one target area based on the body area of ​​the standard cell area. If there are N body areas (pickup areas) in the test area, the entire test rectangular area is divided into N+1 rectangles, and each rectangular area is reduced and defined as the target area VLDZONE_BNY; but in other embodiments, the test area can be divided based on other structural graphics in the standard cell according to the specific application scenario requirements to obtain multiple target areas, and even in some embodiments, manual division can be performed to obtain a target area that better meets the test requirements.

[0068] Step S220, in the target area, auxiliary lines are set based on the power line areas in the different doped active areas, and the auxiliary lines are moved and extended to obtain the first auxiliary graphics and the second auxiliary graphics; based on the first auxiliary graphics and the second auxiliary graphics, the first metal wire and the second metal wire are generated respectively.

[0069] Specifically, because the power line area power line is highly consistent in the standard cell area and arranged in a regular manner, in this example, the power line area power line is selected to set the auxiliary line conn_bar_tar. Since the layout in the standard cell area is composed of small standard cells arranged and combined, the power line is generally arranged from top to bottom in N-type doping and P-type doping.

[0070] Step S230 , after selecting effective gate polysilicon from the gate polysilicon in the target area, the effective gate polysilicon at the first position is used as the first target gate polysilicon, and the effective gate polysilicon at the second position is used as the second target gate polysilicon.

[0071] Specifically, the first position and the second position are adjacent positions. In this embodiment, the gate is divided into two types along the source-drain direction by adding a mask to distinguish adjacent gates in preparation for testing the left and right gate polysilicon.

[0072] Step S240, setting a gate through hole in the area where the first metal line overlaps with the first target gate polysilicon, and setting a gate through hole in the area where the second metal line overlaps with the second target gate polysilicon; the first metal line is connected to the first target gate polysilicon through the gate through hole, and the second metal line is connected to the second target gate polysilicon through the gate through hole, completing the generation of the gate polysilicon short-circuit test structure.

[0073] Specifically, the first metal wire and the second metal wire are respectively used as test pins of the gate polysilicon short-circuit test structure, and the first metal wire and the second metal wire are respectively connected to the test pad, so as to connect to an external test machine through the test pad to perform a gate polysilicon short-circuit test; if the test structure is short-circuited after the current test is connected, it means that there is a short circuit between some adjacent gate polysilicons in the selected test area, and the short-circuit position can be continuously approached by continuously reducing the connected test area.

[0074] In this embodiment, by acquiring a layout, a test area is determined in a standard cell area of ​​the layout, and the test area is divided into at least one target area based on the body area of ​​the standard cell area; in the target area, auxiliary lines are set based on power line areas in different doped active areas, and the auxiliary lines are moved and extended in different directions to obtain a first auxiliary pattern and a second auxiliary pattern; a first metal line and a second metal line are generated based on the first auxiliary pattern and the second auxiliary pattern, respectively; after selecting effective gate polysilicon from gate polysilicon in the target area, the effective gate polysilicon located at the first position is used as the first target gate polysilicon, and the effective gate polysilicon located at the second position is used as the second target gate polysilicon; a gate through hole is set in an area where the first metal line overlaps with the first target gate polysilicon, and a gate through hole is set in an area where the second metal line overlaps with the second target gate polysilicon; the first metal line / the second metal line are connected to the first target gate polysilicon / the second target gate polysilicon through the gate through hole, respectively, to complete the generation of a gate polysilicon short-circuit test structure, thereby solving the problems of low efficiency and high error rate of manually hand-drawn test structures and improving the generation efficiency and accuracy of test structures.

[0075] In some embodiments, dividing the test area into at least one target area based on the body area of ​​the standard cell area includes:

[0076] Step S211, obtaining a body pole region in the test region, and dividing the test region into at least one sub-region based on the body pole region.

[0077] In some of the embodiments, the test area may be divided into a plurality of sub-areas of the same size.

[0078] Step S212, shrinking the sub-regions to a first preset size to obtain a target region.

[0079] This leaves space for routing around the target area.

[0080] In some of the embodiments, in the target area, auxiliary lines are set in power line areas of different doped active areas, and the auxiliary lines are moved and extended in different directions to obtain the first auxiliary pattern and the second auxiliary pattern, including:

[0081] Step S221 , acquiring a power line region in a target region, and setting auxiliary lines based on the power line region in different doped active regions; the doped active regions include N-type doped active regions and P-type doped active regions.

[0082] Step S222, performing a first movement process and a second movement process on the auxiliary line respectively; the first movement process includes: translating a third preset distance along a first direction; the second movement process includes: translating a third preset distance along a second direction; the first direction and the second direction are opposite.

[0083] Step S223, extending the multiple auxiliary lines that have undergone the first movement processing, connecting one end of the multiple auxiliary lines together and merging them into a first auxiliary graphic; extending the multiple auxiliary lines that have undergone the second movement processing, connecting one end of the multiple auxiliary lines together and merging them into a second auxiliary graphic.

[0084] In this embodiment, the first auxiliary pattern and the second auxiliary pattern each include a plurality of auxiliary lines connected together at one end, so as to cover more gate polysilicon in the test region.

[0085] In some embodiments, the auxiliary lines are arranged based on the power line regions in the differently doped active regions, and further include: adjusting the width of the auxiliary lines based on a second preset size. Specifically, the second preset size is the metal line width of the metal layer required by the test structure.

[0086] In some embodiments, the plurality of auxiliary lines subjected to the first movement processing are extended, and one ends of the plurality of auxiliary lines are connected together and then merged as a first auxiliary pattern; the plurality of auxiliary lines subjected to the second movement processing are extended, and one ends of the plurality of auxiliary lines are connected together and then merged as a first auxiliary pattern, including:

[0087] Step S223-A, extending the plurality of auxiliary lines that have undergone the first moving process in a third direction, connecting one ends of the plurality of auxiliary lines together through a first longitudinal connecting line, and then merging them into a first auxiliary graphic.

[0088] Step S223-B, the plurality of auxiliary lines that have undergone the second movement processing are extended to a fourth direction, and then one ends of the plurality of auxiliary lines are connected together through a second longitudinal line and then merged into a second auxiliary graphic; wherein the third direction is opposite to the fourth direction.

[0089] In this embodiment, the first auxiliary pattern and the second auxiliary pattern are staggered in opposite extending directions to avoid mutual interference, thereby testing the left and right gate polysilicon separately.

[0090] In some of the embodiments, when there are at least two target areas, the first auxiliary graphic also includes a first parallel line to connect one end of the first longitudinal line in each target area to the first parallel line; the second auxiliary graphic also includes a second parallel line to connect one end of the second longitudinal line in each target area to the second parallel line.

[0091] In this embodiment, the test structures in a plurality of target areas are connected in parallel through the first parallel line and the second parallel line, thereby covering more test areas.

[0092] In some of the embodiments, after selecting effective gate polysilicon from gate polysilicon in the target region, the effective gate polysilicon at the first position is used as the first target gate polysilicon, and the effective gate polysilicon at the second position is used as the second target gate polysilicon, and the process further includes:

[0093] Step S250 , obtaining gate polysilicon in the target area, and defining positions of two adjacent gate polysilicon as a first position and a second position along a source-drain direction.

[0094] Specifically, in this example, all gates are divided into two types along the source-drain direction by adding masks, namely, the gate PO_all_mask1 under the first mask and the gate PO_all_mask2 under the second mask. This is done to distinguish adjacent gates and prepare for testing left and right gate polysilicon.

[0095] In some embodiments, selecting effective gate polysilicon from gate polysilicon in a target region includes:

[0096] Step S241, screening out the initial effective gate polysilicon from the gate polysilicon in the target area; the initial effective gate polysilicon refers to the remaining gate polysilicon area after excluding the area overlapping with the gate cut-off pattern of the gate cut-off layer in the gate polysilicon area that is not in contact with the single diffusion interrupt isolation.

[0097] Step S242 , after excluding the preset invalid area from the initial effective gate polysilicon, the remaining initial effective gate polysilicon is used as the effective gate polysilicon.

[0098] In this embodiment, gate polysilicon that cannot play a testing role is removed in different ways to obtain effective gate polysilicon.

[0099] In some embodiments, the preset ineffective region includes: a first ineffective gate polysilicon, a second ineffective gate polysilicon, and a third ineffective gate polysilicon.

[0100] The first ineffective gate polysilicon contacts the gate interconnection line spanning across the plurality of gate polysilicons.

[0101] Two adjacent gate polysilicons of the second ineffective gate polysilicon both contact the single diffusion interrupt isolation.

[0102] The third ineffective gate polysilicon contacts the floating gate cutoff pattern that cuts off at least two gate polysilicons; the floating gate cutoff pattern is a gate cutoff pattern on the gate cutoff layer that does not contact the power line region, that is, a short Polycut.

[0103] In this embodiment, different invalid situations are defined by different reference objects, so as to facilitate the rapid removal of invalid gate polysilicon.

[0104] The present embodiment is illustrated and described below through preferred embodiments.

[0105] Step S1, obtain layout information from the original layout, including: active area AA, gate Poly, SDB used to disconnect the active area, gate cut-off area polycut used to disconnect the gate, local interconnect line M0 on the gate, power line area, standard cell area. All operations in this example are performed in the standard cell area. Select a rectangular area range for testing in the layout. If there are N pick-up areas in the test area, divide the entire test rectangular area into N+1 rectangles, and reduce each rectangular area to define it as the target area VLDZONE_BNY, such as Figure 3 As shown, the purpose of shrinking is to leave space for routing.

[0106] Step S2: Extend the left and right edges of each VLDZONE_BNY area by the distance of barwidth+barspace to obtain the vertical auxiliary line conn_pin_pre. Take the two vertical edges of conn_pin_pre and extend them inward by the distance of barwidth, such as Figure 3 As shown, the vertical connection conn_pin area is obtained. Among them, barwidth and barspace are the sizes of auxiliary graphics designed for subsequent metal line generation.

[0107] It should be noted that in this embodiment, barwidth, barspace, pinspace, pinwidth, and the so-called metal line pitch, etc., are all pre-set based on design rules, application scenarios and test requirements. This application does not make specific setting limitations. In different embodiments, without violating the design rules, they can be set according to different application scenarios and test requirements.

[0108] Step S3, such as Figure 4 As shown, in this example, all gates are divided into two types along the source-drain direction by adding masks, namely the gate PO_all_mask1 under the first mask and the gate PO_all_mask2 under the second mask. The purpose of this is to distinguish adjacent gates and prepare for testing the left and right gate polysilicon.

[0109] Step S4, because the power lines are highly consistent in the standard cell area and arranged in a regular manner, in this example, the power lines are selected to be used as lateral connections after a series of transformations. The specific method is: in the VLDZONE_BNY area, the width of the power lines is first shortened to the metal line width barwidth required by the test structure, which is defined as the auxiliary line conn_bar_tar.

[0110] Step S5, such as Figure 5 As shown, the initial effective gate polysilicon PO_valid_all is defined. The initial effective gate polysilicon PO_valid_all is the area of ​​the gate polysilicon minus the area overlapping with the gate cut-off pattern polycut of the gate cut-off layer and the area in contact with the single diffusion interrupt isolation SDB. Figure 6As shown, invalid areas are defined. The first type: the gate interconnection line of the gate polysilicon crosses multiple gate polysilicons, which is defined as the first invalid area PO_invalid1; the second type: two adjacent gate polysilicons of the gate polysilicon are in contact with the single diffusion interrupt isolation, which is defined as the second invalid area PO_invalid2; the third type: the gate polysilicon contacts at least two floating gate cut-off patterns of the gate polysilicon, and the floating gate cut-off pattern is a gate cut-off pattern on the gate cut-off layer that does not contact the power line area, which is defined as the third invalid area PO_invalid3. Take the overlapping area of ​​PO_all_mask1 and PO_valid_all, and remove all invalid areas (i.e. PO_invalid1, PO_invalid2 and PO_invalid3), and obtain the gate polysilicon to be tested with Mask1, which is defined as the first target gate polysilicon PO_vldzone1; take the overlapping area of ​​PO_all_mask2 and PO_valid_all, and remove all invalid areas (i.e. PO_invalid1, PO_invalid2 and PO_invalid3), and obtain the gate polysilicon to be tested with Mask2, which is defined as the second target gate polysilicon PO_vldzone2.

[0111] Step S6, as Figure 7 As shown in the layout information extracted in step S1, it can be known that the power line is arranged alternately in N-type doping and P-type doping, so the conn_bar_tar in N-type doping generated in step S4 is translated upward by a metal line pitch and defined as POseed0_C1pin1, and then the conn_bar_tar in N-type doping is translated downward by a metal line pitch and defined as POseed0_C1pin2. Similarly, the conn_bar_tar in P-type doping is translated and defined as POseed0_C2pin1 and POseed0_C2pin2 respectively. POseed0_C1pin2 and POseed0_C2pin2 are merged and defined as POseed0_C1pin, and the barspace is extended to the left as the first auxiliary line net1. POseed0_C1pin1 and POseed0_C2pin1 are merged and defined as POseed0_C2pin1, and the barspace is grown to the right as the second auxiliary line net2.

[0112] Step S7, Figure 7As shown, the area in the vertical connection conn_pin that contacts the first auxiliary line net1 is extended upward by pinspace, which is defined as the first vertical connection conn_pin1; the area in the vertical connection conn_pin that contacts the second auxiliary line net2 is extended downward by pinspace, which is defined as the second vertical connection conn_pin2. A top connection conn_pin_top with a height of pinwidth is generated at the top of conn_pin1, and a bottom connection conn_pin_bottom with a height of pinwidth is generated at the bottom of conn_pin2. The figure composed of net1, conn_pin1, and conn_pin_top is the first auxiliary figure POPin1, and the figure composed of net2, conn_pin2, and conn_pin_bottom is the second auxiliary figure POPin2.

[0113] Step S8, Figure 8 As shown, the overlapping area of ​​PO_vldzone1 and net1 obtained in step S5 is defined as the first overlapping area netpin1_pre, and the overlapping area of ​​PO_vldzone2 and net2 is defined as the second overlapping area netpin2_pre. Then, the size of netpin1_pre and netpin2_pre is modified to the size of the gate via gatevia specified by the design rules, and the gate vias netpin1_vg and netpin2_vg can be obtained.

[0114] Step S9, based on POPin1 / POPin2 / netpin1_vg / netpin2_vg, the test structure is constructed, and PO_vldzone1 / PO_vldzone2 is the test object. POPin1 and POPin2 are connected to two test terminals respectively. If there is a short circuit between the two pins after the current test, it means that there is a short circuit between some adjacent gate polysilicon in the test structure range. The actual effect is as follows Fig. 9 , Fig.10 and Fig.11 shown.

[0115] In this preferred embodiment, the area required for the test structure is generated by obtaining information of each layer in the original layout, and the left and right adjacent gate polysilicon Poly are distinguished by adding masks to all gates in advance, and then the Poly that is invalid for the test is removed. In this way, the gate vias on adjacent Poly can be on different nets (pins), achieving the scenario required by the test object, thereby enabling the gate polysilicon short-circuit test structure to be constructed quickly and accurately.

[0116] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0117] In the present embodiment, a gate polysilicon short test structure is also provided, and the test structure includes: the test structure is generated based on the method for generating a gate polysilicon short test structure described in any of the above embodiments. The test structure includes: a first target gate polysilicon, a second target gate polysilicon, a first metal wire, a second metal wire and a gate through hole; the first metal wire is connected to the first target gate polysilicon through the gate through hole, and the second metal wire is connected to the second target gate polysilicon through the gate through hole. Wherein, the first metal wire and the second metal wire serve as test pins of the gate polysilicon short test structure, and are used to connect the test end.

[0118] In this embodiment, the area required for the test structure is generated by obtaining information of each layer in the original layout, and the left and right adjacent Polys are distinguished by adding masks to all gates in advance, and then the Polys that are invalid for the test are removed. In this way, the gate vias on adjacent Polys can be on different nets, achieving the scenario required by the test object and improving the yield of the gate polysilicon short-circuit test structure.

[0119] In this embodiment, a device for generating a gate polysilicon short test structure is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. The terms "module", "unit", "subunit", etc. used below can implement a combination of software and / or hardware of predetermined functions. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0120] Fig.12 is a structural block diagram of a device for generating a gate polysilicon short circuit test structure according to this embodiment, such as Fig.12 As shown, the device includes: a target area determination module 10, an auxiliary pattern generation module 20, a target gate polysilicon screening module 30, and a test structure generation module 40.

[0121] A target region determination module 10 is used to obtain a layout, determine a test region in a standard cell region of the layout, and divide the test region into at least one target region based on a body region of the standard cell region;

[0122] The auxiliary pattern generation module 20 is used to set auxiliary lines in the target area based on the power line area of ​​the different doped active areas, move and extend the auxiliary lines to obtain a first auxiliary pattern and a second auxiliary pattern; and generate a first metal line and a second metal line based on the first auxiliary pattern and the second auxiliary pattern respectively;

[0123] a target gate polysilicon screening module 30, configured to screen out effective gate polysilicon from the gate polysilicon in the target area, and use the effective gate polysilicon at the first position as the first target gate polysilicon, and use the effective gate polysilicon at the second position as the second target gate polysilicon;

[0124] The test structure generation module 40 is used to set a gate through hole in the area where the first metal line overlaps with the first target gate polysilicon, and set a gate through hole in the area where the second metal line overlaps with the second target gate polysilicon; the first metal line is connected to the first target gate polysilicon through the gate through hole, and the second metal line is connected to the second target gate polysilicon through the gate through hole, thereby completing the generation of the gate polysilicon short-circuit test structure.

[0125] In some of the embodiments, the test area is divided into at least one target area based on the body region of the standard cell area, including: obtaining the body region in the test area, dividing the test area into at least one sub-area based on the body region; and shrinking the sub-areas by a first preset size to obtain the target area.

[0126] In some of the embodiments, in the target area, based on setting auxiliary lines in power line areas of different doped active areas, the auxiliary lines are moved and extended in different directions to obtain a first auxiliary graphic and a second auxiliary graphic, including: obtaining a power line area in the target area, and setting auxiliary lines based on the power line areas in different doped active areas; the doped active area includes an N-type doped active area and a P-type doped active area; performing a first movement process and a second movement process on the auxiliary lines respectively; the first movement process includes: translating a third preset distance along a first direction; the second movement process includes: translating a third preset distance along a second direction; the first direction is opposite to the second direction; extending multiple auxiliary lines subjected to the first movement process, and connecting one end of the multiple auxiliary lines together and merging them as a first auxiliary graphic; extending multiple auxiliary lines subjected to the second movement process, and connecting one end of the multiple auxiliary lines together and merging them as a second auxiliary graphic.

[0127] In some of the embodiments, the setting of auxiliary lines based on the power line regions in the differently doped active regions further includes: adjusting the width of the auxiliary lines based on a second preset size.

[0128] In some of the embodiments, the plurality of auxiliary lines that undergo the first movement processing are extended, and one ends of the plurality of auxiliary lines are connected together and then merged as a first auxiliary graphic; the plurality of auxiliary lines that undergo the second movement processing are extended, and one ends of the plurality of auxiliary lines are connected together and then merged as a first auxiliary graphic, including: the plurality of auxiliary lines that undergo the first movement processing are extended to a third direction, and one ends of the plurality of auxiliary lines are connected together through a first longitudinal connection line and then merged as a first auxiliary graphic; the plurality of auxiliary lines that undergo the second movement processing are extended to a fourth direction, and one ends of the plurality of auxiliary lines are connected together through a second longitudinal connection line and then merged as a second auxiliary graphic; wherein the third direction is opposite to the fourth direction.

[0129] In some embodiments, when there are at least two target areas, the first auxiliary graphic also includes a first parallel line to connect one end of the first longitudinal line in each of the target areas to the first parallel line; the second auxiliary graphic also includes a second parallel line to connect one end of the second longitudinal line in each of the target areas to the second parallel line.

[0130] In some of the embodiments, after selecting effective gate polysilicon from the gate polysilicon in the target area, the effective gate polysilicon located at the first position is used as the first target gate polysilicon, and the effective gate polysilicon located at the second position is used as the second target gate polysilicon, and the process also includes: obtaining the gate polysilicon in the target area, and defining the positions of two adjacent gate polysilicon along the source-drain direction as the first position and the second position.

[0131] In some of the embodiments, selecting effective gate polysilicon from the gate polysilicon in the target area includes: selecting initial effective gate polysilicon from the gate polysilicon in the target area; the initial effective gate polysilicon refers to the gate polysilicon area remaining after excluding the area overlapping with the gate cut-off pattern of the gate cut-off layer in the gate polysilicon that is not in contact with the single diffusion interrupt isolation; in the initial effective gate polysilicon, after excluding the preset invalid area, the remaining initial effective gate polysilicon serves as the effective gate polysilicon.

[0132] In some embodiments, the preset invalid area includes: a first invalid gate polysilicon, a second invalid gate polysilicon and a third invalid gate polysilicon; the first invalid gate polysilicon contacts a gate interconnection line spanning a plurality of the gate polysilicons; two adjacent gate polysilicons of the second invalid gate polysilicon both contact a single diffusion interrupt isolation; the third invalid gate polysilicon contacts a floating gate cutoff pattern that cuts off at least two of the gate polysilicons; the floating gate cutoff pattern is a gate cutoff pattern on the gate cutoff layer that does not contact the power line area.

[0133] It should be noted that the above modules can be functional modules or program modules, and can be implemented by software or hardware. For modules implemented by hardware, the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0134] In this embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0135] Optionally, the computer device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0136] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0137] In addition, in combination with the method for generating a gate polysilicon short test structure provided in the above embodiment, a storage medium can also be provided in this embodiment to implement the method. The storage medium stores a computer program; when the computer program is executed by a processor, any method for generating a gate polysilicon short test structure in the above embodiment is implemented.

[0138] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0139] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0140] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0141] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A method for generating a gate polysilicon short-circuit test structure, characterized in that: The method comprises: Acquire a layout, determine a test area in a standard cell area of ​​the layout, and divide the test area into at least one target area; In the target area, auxiliary lines are arranged based on power line areas of different doped active areas, and the auxiliary lines are moved and extended to obtain a first auxiliary pattern and a second auxiliary pattern; and a first metal line and a second metal line are generated based on the first auxiliary pattern and the second auxiliary pattern respectively; The step of moving and extending the auxiliary lines to obtain the first auxiliary graphics and the second auxiliary graphics comprises: performing a first moving process and a second moving process on the auxiliary lines respectively, wherein the first moving process and the second moving process are in opposite directions; extending the auxiliary lines subjected to the first moving process to obtain the first auxiliary graphics; and extending the auxiliary lines subjected to the second moving process to obtain the second auxiliary graphics; After selecting effective gate polysilicon from the gate polysilicon in the target area, the effective gate polysilicon at the first position is used as the first target gate polysilicon, and the effective gate polysilicon at the second position is used as the second target gate polysilicon; A gate through hole is set in the area where the first metal line overlaps with the first target gate polysilicon, and a gate through hole is set in the area where the second metal line overlaps with the second target gate polysilicon; the first metal line is connected to the first target gate polysilicon through the gate through hole, and the second metal line is connected to the second target gate polysilicon through the gate through hole, thereby completing the generation of the gate polysilicon short-circuit test structure.

2. The method for generating a gate polysilicon short-circuit test structure according to claim 1, characterized in that: Dividing the test area into at least one target area comprises: Acquire a body pole region in the test region, and divide the test region into at least one sub-region based on the body pole region; After shrinking the sub-areas to a first preset size, a target area is obtained.

3. The method for generating a gate polysilicon short-circuit test structure according to claim 1, characterized in that: In the target area, auxiliary lines are arranged in power line areas of different doped active areas, and the auxiliary lines are moved and extended to obtain first auxiliary patterns and second auxiliary patterns, including: Acquire a power line region in the target region, and set auxiliary lines based on the power line region in different doped active regions; the doped active regions include N-type doped active regions and P-type doped active regions; The first movement process includes: translating a third preset distance along a first direction; the second movement process includes: translating a third preset distance along a second direction; the first direction and the second direction are opposite; Extending the plurality of auxiliary lines that have undergone the first movement processing, and connecting one ends of the plurality of auxiliary lines together and merging them into a first auxiliary pattern; The plurality of auxiliary lines that have undergone the second movement process are extended, and one ends of the plurality of auxiliary lines are connected together and then merged to form a second auxiliary graphic.

4. The method for generating a gate polysilicon short-circuit test structure according to claim 3, characterized in that: Extending the plurality of auxiliary lines that have undergone the first movement processing, and connecting one ends of the plurality of auxiliary lines together and merging them into a first auxiliary pattern; Extending the plurality of auxiliary lines that have undergone the second movement processing, and connecting one ends of the plurality of auxiliary lines together and merging them into a first auxiliary graphic, comprising: The plurality of auxiliary lines that have undergone the first movement processing are extended in a third direction, one ends of the plurality of auxiliary lines are connected together through a first longitudinal connection line, and then combined into a first auxiliary pattern; The plurality of auxiliary lines subjected to the second movement processing are extended in a fourth direction, one ends of the plurality of auxiliary lines are connected together through a second longitudinal connection line, and then combined into a second auxiliary pattern; Wherein, the third direction is opposite to the fourth direction.

5. The method for generating a gate polysilicon short-circuit test structure according to claim 4, characterized in that: When there are at least two target areas, the first auxiliary pattern further includes a first parallel line to connect one end of the first longitudinal line in each of the target areas to the first parallel line; The second auxiliary pattern further includes a second parallel line to connect one end of the second longitudinal line in each of the target areas to the second parallel line.

6. The method for generating a gate polysilicon short-circuit test structure according to claim 1, characterized in that: After selecting effective gate polysilicon from the gate polysilicon in the target area, the effective gate polysilicon at the first position is used as the first target gate polysilicon, and the effective gate polysilicon at the second position is used as the second target gate polysilicon, and the method further includes: The gate polysilicon in the target area is obtained, and positions of two adjacent gate polysilicon are defined as a first position and a second position along a source-drain direction.

7. The method for generating a gate polysilicon short-circuit test structure according to claim 1, characterized in that: Screening out effective gate polysilicon from the gate polysilicon in the target area includes: Screening out initial effective gate polysilicon from the gate polysilicon in the target area; the initial effective gate polysilicon refers to the gate polysilicon area remaining after excluding the area overlapping with the gate cut-off pattern of the gate cut-off layer in the gate polysilicon that is not in contact with the single diffusion interrupt isolation; In the initial effective gate polysilicon, after excluding the preset invalid area, the remaining initial effective gate polysilicon is used as the effective gate polysilicon; Wherein, the preset invalid region includes: a first invalid gate polysilicon, a second invalid gate polysilicon and a third invalid gate polysilicon; The first ineffective gate polysilicon contacts a gate interconnection line spanning across a plurality of the gate polysilicons; Two adjacent gate polysilicon layers of the second ineffective gate polysilicon layer are in contact with the single diffusion interrupt isolation; The third ineffective gate polysilicon contacts a floating gate cutoff pattern that cuts off at least two of the gate polysilicons; the floating gate cutoff pattern is a gate cutoff pattern on the gate cutoff layer that does not contact the power line region.

8. A device for generating a gate polysilicon short-circuit test structure, characterized in that: The device comprises: A target area determination module, used to obtain a layout, determine a test area in a standard cell area of ​​the layout, and divide the test area into at least one target area; An auxiliary pattern generation module is used for setting auxiliary lines in the target area based on the power line area of ​​the different doped active areas, moving and extending the auxiliary lines to obtain a first auxiliary pattern and a second auxiliary pattern; generating a first metal line and a second metal line based on the first auxiliary pattern and the second auxiliary pattern respectively; wherein, moving and extending the auxiliary lines to obtain the first auxiliary pattern and the second auxiliary pattern comprises: performing a first moving process and a second moving process on the auxiliary lines respectively, the first moving process and the second moving process are in opposite directions; extending the auxiliary lines subjected to the first moving process to obtain the first auxiliary pattern; and extending the auxiliary lines subjected to the second moving process to obtain the second auxiliary pattern; a target gate polysilicon screening module, configured to screen out effective gate polysilicon from the gate polysilicon in the target area, and use the effective gate polysilicon at the first position as the first target gate polysilicon, and use the effective gate polysilicon at the second position as the second target gate polysilicon; A test structure generation module is used to set a gate through hole in the area where the first metal line overlaps with the first target gate polysilicon, and set a gate through hole in the area where the second metal line overlaps with the second target gate polysilicon; the first metal line is connected to the first target gate polysilicon through the gate through hole, and the second metal line is connected to the second target gate polysilicon through the gate through hole, thereby completing the generation of the gate polysilicon short-circuit test structure.

9. A gate polysilicon short-circuit test structure, characterized in that: The test structure comprises: the test structure is obtained based on the method for generating a gate polysilicon short test structure according to any one of claims 1 to 7; The test structure includes: a first target gate polysilicon, a second target gate polysilicon, a first metal wire, a second metal wire and a gate through hole; the first metal wire is connected to the first target gate polysilicon through the gate through hole, and the second metal wire is connected to the second target gate polysilicon through the gate through hole; the first metal wire and the second metal wire serve as test pins of the gate polysilicon short-circuit test structure.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for generating a gate polysilicon disconnect test structure according to any one of claims 1 to 7 are implemented.

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