Memory system and operating method thereof, memory controller and readable storage medium

Abstract

This disclosure provides a memory system and its operating method, a memory controller, and a readable storage medium. The memory system includes at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device. The memory controller is configured to: determine whether the data mapped to the logical address of a received read command belongs to a first type table or a second type table; confirm the "hotness" of the data corresponding to the logical address of the received read command; determine the level of the threshold voltage drift of the memory cell corresponding to the logical address based on the "hotness" of the data corresponding to the logical address; and determine different read voltages sent to the memory cell corresponding to the logical address based on different levels of drift.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory system and its operation method, a memory controller, and a readable storage medium. Background Technology

[0002] The threshold voltage of the storage cells in non-volatile storage devices drifts over time. The drift time range of the threshold voltage is very large, making it difficult to track the drift level of the threshold voltage of the storage cells corresponding to the logical addresses of all data. As a result, it is difficult to guarantee the reliability of the read voltage, which may lead to errors in reading data and cannot guarantee the reliability of the read data. Summary of the Invention

[0003] In view of the above, this disclosure provides a memory system and its operation method, a memory controller and a readable storage medium to solve at least one technical problem existing in the prior art.

[0004] According to a first aspect of the present disclosure, a memory system is provided, the memory system comprising: at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller being configured to:

[0005] Using a first type of table and a second type of table, the "heat" of the data corresponding to the logical address of the received read command is determined; the "heat" of the data characterizes the length of the average time difference between data writing and reading; the first type of table includes at least one, and at least one first type of table is used to store the data of logical address mapping for each first time interval within a first preset time period after writing; the second type of table includes multiple, and multiple second type of tables are used to alternately store the data of logical address mapping for each second time interval within a second preset time period after writing; the first preset time period is less than the second preset time period, and the first time interval is less than the second time interval;

[0006] Based on the popularity of the data corresponding to the logical address, the level of drift corresponding to the logical address is determined; different levels of drift correspond to different read voltages sent to the non-volatile memory device.

[0007] In the above scheme, the first type of table is obtained through a hash table; the second type of table is obtained through a Bloom filter, a Cuckoo filter, an XOR filter, or a vacuum filter.

[0008] In the above scheme, the data heat includes: hot data, warm data, and cold data; the average time difference for writing and reading corresponding to the hot data, warm data, and cold data increases sequentially; the memory controller is specifically configured as follows:

[0009] When the data mapped by the logical address is in the first type of table, it is determined that the data corresponding to the logical address is hot data or warm data;

[0010] When the data mapped by the logical address is not in the first type of table but is in the second type of table, the data corresponding to the logical address is determined to be warm data or cold data.

[0011] When the data mapped by the logical address is not in the first type of table and not in the second type of table, the data corresponding to the logical address is determined to be cold data.

[0012] In the above scheme, there are two tables of the first type and two tables of the second type;

[0013] The memory controller is specifically configured as follows:

[0014] When the data mapped by the logical address is in the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data.

[0015] When the data mapped by the logical address is not in the first type table of the previous first time interval, but is in the first type table of the current first time interval, the data corresponding to the logical address is determined to be hot data or warm data.

[0016] When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, but is in the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data.

[0017] When the data mapped by the logical address is not in the first type table of the current first time interval, the first type table of the previous first time interval, or the second type table of the previous second time interval, but is in the second type table of the current second time interval, the data corresponding to the logical address is determined to be warm data or cold data.

[0018] When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

[0019] In the above scheme, there are two tables of the first type and two tables of the second type;

[0020] The memory controller is specifically configured as follows:

[0021] When the data mapped by the logical address is in the first type table of the current first time interval or the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data.

[0022] When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, but is in the second type table of the current second time interval or the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data.

[0023] When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

[0024] In the above scheme, the memory controller is further configured as follows:

[0025] When the data corresponding to the logical address is the hot data, the drift amount corresponding to the logical address is determined to be the first-level drift amount;

[0026] When the data corresponding to the logical address is the temperature data, the drift amount corresponding to the logical address is determined to be the second-level drift amount;

[0027] When the data corresponding to the logical address is the cold data, the drift amount corresponding to the logical address is determined to be the third-level drift amount;

[0028] Wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

[0029] In the above scheme, the memory controller is specifically configured as follows:

[0030] When the data corresponding to the logical address is determined to be warm data using the first type of table and the second type of table, and a read failure occurs when reading the data of the storage unit corresponding to the logical address using the read voltage corresponding to the warm data, the data of the storage unit corresponding to the logical address is reread using the read voltage corresponding to the cold data.

[0031] In the above scheme, the memory controller is further configured as follows:

[0032] Check whether the logical address corresponding to the received read command is stored in the write buffer;

[0033] When the logical address is not stored in the write buffer, determine the level of the drift amount corresponding to the logical address;

[0034] A read command is sent to the non-volatile memory device according to the level of drift corresponding to the logical address; wherein at least two processes are executed in parallel during the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command.

[0035] In the above scheme, the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command are all executed in parallel; the memory controller includes: a first processor, a second processor, a third processor, a first on-chip memory, and a second on-chip memory; wherein,

[0036] The first processor is configured to: check whether the logical address corresponding to the received read command is stored in the write buffer, and submit the logical address not stored in the write buffer to the first submission queue;

[0037] The first on-chip memory is configured to store the first submission queue;

[0038] The second processor is configured to: determine the level of drift corresponding to each logical address in the first submission queue, and submit the level of drift corresponding to each logical address to the second submission queue;

[0039] The second on-chip memory is configured to store the second submission queue;

[0040] The third processor is configured to send a read command to the non-volatile memory device according to the level of drift corresponding to each logical address in the second submission queue;

[0041] At any given time, the logical addresses corresponding to the first submission queue, the second submission queue, and the read command are different.

[0042] In the above scheme, the third processor is specifically configured as follows:

[0043] Based on the level of drift corresponding to each logical address in the second submission queue, determine the read voltage for performing a read command operation on the non-volatile memory device;

[0044] A read command is sent to the non-volatile memory device based on the read voltage used to perform the read command operation.

[0045] In the above scheme, both the first on-chip memory and the second on-chip memory include dynamic random access memory or static random access memory.

[0046] In the above scheme, the memory system includes storage-level memory; the non-volatile storage device includes phase-change memory.

[0047] According to a second aspect of the present disclosure, a memory controller is provided, coupled to at least one non-volatile memory device, the memory controller being configured to:

[0048] Using a first type of table and a second type of table, the "heat" of the data corresponding to the logical address of the received read command is determined; the "heat" of the data characterizes the length of the average time difference between data writing and reading; the first type of table includes at least one, and at least one first type of table is used to store the data of logical address mapping for each first time interval within a first preset time period after writing; the second type of table includes multiple, and multiple second type of tables are used to alternately store the data of logical address mapping for each second time interval within a second preset time period after writing; the first preset time period is less than the second preset time period, and the first time interval is less than the second time interval;

[0049] Based on the popularity of the data corresponding to the logical address, the level of drift corresponding to the logical address is determined; different levels of drift correspond to different read voltages sent to the non-volatile memory device.

[0050] According to a third aspect of the present disclosure, a method of operating a memory system is provided, the memory system comprising: at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device; the method of operating the memory system comprising:

[0051] Using a first type of table and a second type of table, the "heat" of the data corresponding to the logical address of the received read command is determined; the "heat" of the data characterizes the length of the average time difference between data writing and reading; the first type of table includes at least one, and at least one first type of table is used to store the data of logical address mapping for each first time interval within a first preset time period after writing; the second type of table includes multiple, and multiple second type of tables are used to alternately store the data of logical address mapping for each second time interval within a second preset time period after writing; the first preset time period is less than the second preset time period, and the first time interval is less than the second time interval;

[0052] Based on the popularity of the data corresponding to the logical address, the level of drift corresponding to the logical address is determined; different levels of drift correspond to different read voltages sent to the non-volatile memory device.

[0053] In the above scheme, the method further includes: forming the first type of table and the second type of table;

[0054] The formation of the first type of table and the second type of table includes:

[0055] The data mapped by the hash table mapping function for each first time interval within the first preset time period after writing is stored in the first type of table;

[0056] The logical addresses of each second time interval within the second preset time period after writing are mapped by mapping functions in Bloom filter, Cuckoo filter, XOR filter or vacuum filter and stored in the second type table.

[0057] In the above scheme, the data heat includes: hot data, warm data, and cold data; the average time difference for writing and reading the hot data, warm data, and cold data increases sequentially.

[0058] The step of using the first type of table and the second type of table to determine the popularity of the data corresponding to the logical address of the received read command includes:

[0059] When the data group mapped by the logical address is in the first type of table, it is determined that the data corresponding to the logical address is hot data or warm data.

[0060] When the data group mapped by the logical address is not in the first type of table but is in the second type of table, the data corresponding to the logical address is determined to be warm data or cold data.

[0061] When the data group mapped by the logical address is not in the first type of table and not in the second type of table, the data corresponding to the logical address is determined to be cold data.

[0062] In the above scheme, there are two tables of the first type and two tables of the second type;

[0063] The step of using the first type of table and the second type of table to determine the popularity of the data corresponding to the logical address of the received read command includes:

[0064] When the data mapped by the logical address is in the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data.

[0065] When the data mapped by the logical address is not in the first type table of the previous first time interval, but is in the first type table of the current first time interval, the data corresponding to the logical address is determined to be hot data or warm data.

[0066] When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, but is in the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data.

[0067] When the data mapped by the logical address is not in the first type table of the current first time interval, the first type table of the previous first time interval, or the second type table of the previous second time interval, but is in the second type table of the current second time interval, the data corresponding to the logical address is determined to be warm data or cold data.

[0068] When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

[0069] In the above scheme, there are two tables of the first type and two tables of the second type;

[0070] The step of using the first type of table and the second type of table to determine the popularity of the data corresponding to the logical address of the received read command includes:

[0071] When the array data mapped by the logical address is in the first type table of the current first time interval or the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data.

[0072] When the array data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, but is in the second type table of the current second time interval or the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data.

[0073] When the array data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

[0074] In the above scheme, determining the level of drift corresponding to the logical address based on the popularity of the data corresponding to the logical address includes:

[0075] When the data corresponding to the logical address is the hot data, the drift amount corresponding to the logical address is determined to be the first-level drift amount;

[0076] When the data corresponding to the logical address is the temperature data, the drift amount corresponding to the logical address is determined to be the second-level drift amount;

[0077] When the data corresponding to the logical address is the cold data, the drift amount corresponding to the logical address is determined to be the third-level drift amount;

[0078] Wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

[0079] The method in the above scheme further includes:

[0080] When the data corresponding to the logical address is determined to be warm data using the first type of table and the second type of table, and a read failure occurs when reading the data of the storage unit corresponding to the logical address using the read voltage corresponding to the warm data, the data of the storage unit corresponding to the logical address is reread using the read voltage corresponding to the cold data.

[0081] The method in the above scheme further includes:

[0082] Check whether the logical address corresponding to the received read command is stored in the write buffer;

[0083] When the logical address is not stored in the write buffer, determine the level of the drift amount corresponding to the logical address;

[0084] A read command is sent to the non-volatile memory device according to the level of drift corresponding to the logical address; wherein the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command are executed in parallel.

[0085] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program, which, when executed, can implement the operation method of the memory system as described in any of the above embodiments.

[0086] This disclosure provides a memory system and its operating method, a memory controller, and a readable storage medium. The memory system includes at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device. The memory controller is configured to: determine whether the data mapped to the logical address of a received read command belongs to a first type table or a second type table, and determine the "hotness" of the data corresponding to the logical address of the received read command based on the determination result; determine the level of drift corresponding to the logical address based on the "hotness" of the data corresponding to the logical address; and apply different read voltages to the non-volatile memory device depending on the level of drift corresponding to the logical address of the received read command. In other words, this disclosure allows for the determination of the level of logical address drift, enabling targeted delivery of read voltages to the non-volatile memory device, thereby ensuring the correctness of the read command operation and improving the reliability of the memory system. Furthermore, the alternating use of multiple second type tables is more flexible and saves more space compared to using a single table. Attached Figure Description

[0087] Figure 1 A block diagram of a memory system provided in an embodiment of this disclosure;

[0088] Figure 2A and Figure 2B A block diagram illustrating the structure of a first type of table and a second type of table in a memory system provided in an embodiment of this disclosure;

[0089] Figure 3A and Figure 3B A flowchart and a data heat map of an operation method for a memory system provided in this disclosure embodiment;

[0090] Figure 4A and Figure 4B A flowchart and a data heat map of another memory system operation method provided in this disclosure embodiment;

[0091] Figure 5A and Figure 5B A flowchart and a data heat map of another method for operating a memory system provided in this disclosure embodiment;

[0092] Figure 6 A block diagram of another memory system provided in an embodiment of this disclosure;

[0093] Figure 7 A flowchart illustrating the operation method of the memory system provided in this embodiment of the disclosure;

[0094] Figure 8 A flowchart illustrating an operation method for a memory system provided in an embodiment of this disclosure;

[0095] Figure 9 A schematic diagram showing the logical addresses corresponding to the first processor, the second processor, and the third processor during the nth time interval of the operation method of the memory system provided in this embodiment of the present disclosure;

[0096] Figure 10 A block diagram of a memory controller provided in an embodiment of this disclosure;

[0097] Figure 11 A block diagram of a readable storage medium provided in embodiments of this disclosure;

[0098] Figure 12 A block diagram of a system provided in an embodiment of this disclosure. Detailed Implementation

[0099] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0100] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0101] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0102] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0103] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0104] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0105] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0106] Figure 1 A block diagram of a memory system provided for an embodiment of this disclosure. (See diagram below.) Figure 1 As shown, according to a first aspect of the present disclosure, a memory system 100 is provided, the memory system 100 including: at least one non-volatile memory device 110 and a memory controller 120 coupled to the non-volatile memory device; the memory controller 120 is configured to perform the following steps:

[0107] Step S1001: Using the first type of table and the second type of table, determine the heat of the data corresponding to the logical address of the received read command; the heat of the data characterizes the length of the average time difference between data writing and reading; the first type of table includes at least one, and at least one first type of table is used to store the data of logical address mapping for each first time interval within a first preset time period after writing; the second type of table includes multiple, and multiple second type of tables are used to alternately store the data of logical address mapping for each second time interval within a second preset time period after writing; the first preset time period is less than the second preset time period, and the first time interval is less than the second time interval;

[0108] Step S1002: Determine the level of drift corresponding to the logical address based on the popularity of the data corresponding to the logical address; different levels of drift correspond to different read voltages sent to the non-volatile memory device.

[0109] The memory system 100 includes at least one memory and a memory controller connected to the at least one memory. The memory may include non-volatile memory devices and volatile memory devices.

[0110] The memory controller 120 controls the overall operation of the memory system 100. The memory controller 120 can store data in a non-volatile memory device or read data stored in a non-volatile memory device.

[0111] The non-volatile storage device 110 may include one of phase change memory (PCM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and carbon nanotube random access memory (NRAM).

[0112] The memory controller 120 can also store various information required for the operation of the memory system 100 (e.g., metadata information and mapping tables) in the volatile storage device, and can access the non-volatile storage device based on the information stored in the volatile storage device.

[0113] Volatile storage devices may include memory devices of dynamic random-access memory (DRAM), static random-access memory (SRAM), synchronous dynamic random-access memory (SDRAM), or double-data-rate fourth-generation synchronous dynamic random-access memory (DDR4SDRAM).

[0114] The first and second type tables can be mapping tables (TBLs) that provide fast and efficient insertion and lookup operations for the memory system. The first and second preset durations can be duration intervals consisting of at least one first time interval trigger and at least one second time interval trigger, respectively, corresponding to different data hotness levels. The first and second time intervals can correspond to different time intervals triggered by the time interval trigger. For example, within the first preset duration, the first type table stores the logical address mapping data obtained from the first time interval trigger; within the second preset duration, the second type table stores the logical address mapping data obtained from the second time interval trigger; the first time interval is shorter than the second time interval.

[0115] In some embodiments, the second time interval includes the first time interval; wherein, within the second time interval, the logical address mapping data obtained by the second time interval includes the logical address mapping data obtained by the first time interval, and the second type of table includes the first type of table.

[0116] Data popularity characterizes the average time lag between writing and reading data from non-volatile storage (hereinafter referred to as average write and read time lag). In some embodiments, data can be categorized into hot data, warm data, and cold data based on the length of the write and read time lag. Hot data has the shortest write and read time lag, followed by warm data, and cold data has the longest write and read time lag; the write and read time lags increase sequentially from hot data to warm data to cold data.

[0117] For example, the average time difference between writing and reading hot data can be defined as 1 μs to 2 ms, and can be simply referred to as hot data (1 μs to 2 ms); the average time difference between writing and reading warm data can be defined as 1 ms to 2 s, and can be simply referred to as warm data (1 ms to 2 s); the average time difference between writing and reading cold data can be defined as 1 s to several hours, and can be simply referred to as cold data (1 s to several hours).

[0118] It should be noted that the write and read time differences for hot, warm, and cold data can overlap. For data whose write and read time differences are not overlapping, the determination of its "hotness" is unique. For example, data with a write and read time difference between 1 microsecond and 1 millisecond can be identified as hot data; data with a write and read time difference between 2 milliseconds and 1 second can be identified as warm data; and data with a write and read time difference exceeding 2 seconds can be identified as cold data. However, for data with overlapping write and read time differences, the determination of its "hotness" is not unique. For example, data with a write and read time difference between 1 millisecond and 2 milliseconds can be identified as either hot or warm data. Data with a write and read time difference between 1 second and 2 seconds can be identified as either warm or cold data. Therefore, the "hotness" of data characterizes the length of the average write and read time difference.

[0119] It is understandable that when there is an overlapping area between the write and read time differences of hot data, warm data, and cold data, these overlapping areas are all located at the boundary between the two types of data. The read voltage actually has a certain window; for data in the overlapping area, both drift levels corresponding to the two types of data can be applied, and therefore, the read voltage corresponding to both drift levels can also be applied.

[0120] Here and below, the logical addresses (LBAs) corresponding to hot data, warm data, and cold data are referred to as hot logical address, warm logical address, and cold logical address, respectively.

[0121] It should be noted that, here and below, the data mapped by the logical address refers to the data representing the logical address. This can be the logical data itself or the data used to represent the logical address after logical operations (or mapping function operations).

[0122] In step S1001, the memory controller can use at least one first type table to store hot logical address mapping data and use multiple second type tables to alternately store warm logical address mapping data.

[0123] It determines whether the data mapped to the logical address of the received read command belongs to either the first type of table or the second type of table, and confirms the "hotness" of the data corresponding to the logical address of the received read command based on the determination result. For example, if the data mapped to the logical address of the received read command belongs to the first type of table, the data corresponding to the logical address of the received read command is confirmed as "hot," meaning the data corresponding to the logical address of the received read command is confirmed as "hot data," or the logical address of the received read command is confirmed as a "hot logical address."

[0124] The memory controller uses at least one type-1 table to store data for hot logical address mapping, which can improve or solve the problem that the read window margin (RWM) of non-volatile memory devices is very small at time 0.

[0125] Warm and cold data have considerable RWM (Read-Write-Time). The memory controller uses multiple Class II tables to alternately store data with warm logical address mappings, enabling low-latency differentiation between massive amounts of warm and cold data with considerable RWM.

[0126] Because the threshold voltage of the storage cells in a non-volatile storage device drifts over time, the level of threshold voltage drift can be classified into different levels based on the different heat levels of the data (e.g., hot, mild, cold).

[0127] In step S1002, the memory controller determines the level of the threshold voltage drift of the memory cell corresponding to the logical address based on the data's activity level at the logical address of the received read command. Based on different drift levels, it determines different read voltages to be sent to the non-volatile memory device 110 corresponding to the logical address. In other words, the different activity levels of the data in the memory cell corresponding to the logical address of the received read command determine the appropriate read voltage. Each drift level of the corresponding read voltage provides a promised raw bit error rate (RBER), ensuring the reliability of the read data.

[0128] In this embodiment of the present disclosure, the memory controller is configured to determine whether the data mapped to the logical address of the received read command belongs to a first type table or a second type table, and to confirm the popularity of the data corresponding to the logical address based on the determination result; to determine the level of the drift amount corresponding to the logical address based on the data popularity of the logical address; and to determine the read voltage applied when reading the data corresponding to the corresponding logical address in the non-volatile memory device based on the level of the drift amount, so as to offset the drift of the threshold voltage of the memory cell over time, thereby ensuring the reliability of reading data from the non-volatile memory device.

[0129] The following will be based on the above references. Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B This section details how the memory controller uses the first and second type tables to determine the "hotness" of the data corresponding to the logical address of a received read command. In the following text and accompanying diagrams, "hot data" can be understood as data mapped to a hot logical address, "warm data" as data mapped to a warm logical address, and "cold data" as data mapped to a cold logical address.

[0130] It should be noted that the following explanation uses hot data (1μs–2ms), warm data (1ms–2s), and cold data (1s–several hours) as the criteria for classifying data heat. It is understood that this criterion for classifying data heat is for simplification only and does not limit the criteria used in this disclosure. In other embodiments, other criteria may be used to classify data heat.

[0131] Figure 2A and Figure 2B This is a block diagram illustrating the structure of a first type of table and a second type of table in a memory system provided in an embodiment of this disclosure. (See diagram below.) Figure 2A and Figure 2B As shown, in some embodiments, the first type of table is obtained through a hash table; the second type of table is obtained through a Bloom filter, a Cuckoo filter, an XOR filter, or a Vacuum filter.

[0132] Here, the hash table may include a first mapping function and a first type of table, and Bloom filters, etc., may include a second mapping function and a second type of table. Data whose logical addresses are mapped by the first mapping function within a first preset time period after being written by the host is stored in the first type of table. Data whose logical addresses are mapped by the second mapping function within a second preset time period after being written by the host is stored in the second type of table.

[0133] In some embodiments, a first type of table is used to store data of logical address mappings obtained by triggering a first time interval, and a second type of table is used to store data of logical address mappings obtained by triggering a second time interval; the first time interval is less than the second time interval; wherein, within the second time interval, the data of logical address mappings obtained by triggering the second time interval includes the data of logical address mappings obtained by triggering the first time interval, and the second type of table includes the first type of table.

[0134] In this embodiment, the first type of table is part of the second type of table, and the storage space of one first type of table triggered by a first time interval corresponds to one unit of storage space of one second type of table triggered by a second time interval. The storage spaces of multiple first type of tables constitute the storage space of one second type of table. For example, the storage spaces of 1000 second type of tables triggered by 1ms time intervals correspond to the storage space of one second type of table triggered by a 1sec time interval.

[0135] In some specific embodiments, a first type of table can be obtained through a hash table, and a second type of table can be obtained through a Bloom filter. For example, the data obtained after a logical address is processed by a hash function is stored in the first type of table, which is used to store data mapped to hot logical addresses; the data obtained after a logical address is processed by multiple unbiased hash functions is stored in the second type of table, which is used to store data mapped to warm logical addresses.

[0136] like Figure 2A As shown, the first type of table is used to store data for hot logical address mapping.

[0137] In some embodiments, the first type of table may include N mapping tables, where N is a positive integer and has a maximum value of 5. Here, the value of N depends on the insertion delay of the Bloom filter.

[0138] For example, the first type of table may include two mapping tables: the current first type of table and the previous first type of table. The current first type of table is a first type of table that stores some logical address mapping data and still has some unused storage space, or it is a first type of table that has just been emptied and all storage space is unused. The previous first type of table is a first type of table that is currently full of logical address mapping data and has no remaining storage space.

[0139] It's important to note that the current and previous Class 1 tables store data alternately over time. These two tables are not physically fixed; the concepts of "current" and "previous" change over time. Specifically, at a given moment, the previous Class 1 table may be full of logically mapped data. At a given moment, the current Class 1 table continues to store logically mapped data. When it becomes full, the previous Class 1 table is cleared. The cleared previous Class 1 table becomes the current Class 1 table at the next moment, and the current Class 1 table that was full before a certain moment becomes the previous Class 1 table at the next moment.

[0140] The data used to complete the logical address mapping of the queue can be part of the input logical address mapping data, or the logical address mapping data that will be inserted into the first or second type of table. For the definition and application of the input logical address mapping data, please refer to the following text. Figures 6 to 8 The relevant explanations will not be repeated here.

[0141] In some embodiments, each mapping table can be obtained using a time interval trigger. For example, a time interval trigger that fires every 1ms forms multiple storage spaces with a width of 31 bits.

[0142] like Figure 2B As shown, the second type of table is used to store data mapped to warm logical addresses.

[0143] In some embodiments, the second type of table may include multiple mapping tables.

[0144] For example, the second type of table may include two mapping tables: the current second type of table and the previous second type of table. The method of inserting data with completed queue logical address mappings into the current and previous second type of tables, and the specific details of how the current and previous second type of tables store data in a time-shifting manner, are similar to the aforementioned case of the current and previous first type of tables, and will not be repeated here. The difference is that the storage space of the second type of table is larger than that of the first type of table, and the triggering time interval of the second type of table is larger than that of the first type of table. For example, the storage space of a second type of table triggered by a second time interval is larger than the storage space of a first type of table triggered by a first time interval.

[0145] In some embodiments, each mapping table can be obtained by a time interval trigger. For example, a time interval trigger of 1 Sec is used to form multiple storage spaces with a bit width of 31 bits.

[0146] In this case, the storage space of one unit in the second type of table is equivalent to the storage space of one unit in the first type of table. For example, such as... Figure 2B The storage space of one unit in the current second-class table shown is equivalent to, for example: Figure 2A The storage space for a first-class table is shown.

[0147] The first type of table can be used to store data mapping hot logical addresses where the RWM is very small at time zero. By using a hash table to store hot logical addresses, it can improve or solve the problem that the RWM of non-volatile memory devices is very small at time zero.

[0148] The second type of table can be used to store massive amounts of warm logical address mapping data and cold logical address mapping data. By using a Bloom filter to store massive amounts of warm logical addresses and cold logical addresses, massive amounts of warm data and cold data can be distinguished with low latency, so that the warm data and cold data have a large RWM.

[0149] Since the space required to store these warm and cold data addresses is enormous, it is impossible to use a hash table to completely store the data mapped to these logical addresses. For example, querying a massive amount of warm logical address mapping data on a hash table takes a long time, resulting in a large read latency and increasing the time required to refresh or insert data into the hash table.

[0150] If a certain error rate is allowed, compared to the scheme of querying a massive number of logical addresses on a hash table, the scheme of querying a massive number of logical addresses on a mapping table obtained by a Bloom filter has comprehensive advantages in terms of space efficiency and speed efficiency.

[0151] For example, when implementing a Bloom filter with a write granularity of 4KB, memory efficiency is improved by 20 times; the overhead of storing a 1-second write address can be reduced from 1.84MB (hash table) to 92KB (Bloom filter); and the time to look up a key on a Bloom filter is approximately ~40ns.

[0152] By employing a scheme that queries a massive number of logical addresses on a mapping table obtained through a Bloom filter, it is possible to store a massive number of logical addresses, actively compress the storage size of on-chip memory, and avoid consuming on-chip memory resources. At the same time, it can realize fast and efficient insertion and lookup operations, and can also cover logical addresses of any length.

[0153] Figure 3A and Figure 3B A flowchart and a data heatmap of an operation method for a memory system provided in this disclosure are shown as embodiments. Figure 3A and Figure 3B As shown, in some embodiments, the data heat level includes: hot data, warm data, and cold data; the average time difference for writing and reading corresponding to hot data, warm data, and cold data increases sequentially; the memory controller 120 is specifically configured to perform the following steps:

[0154] Step S3002: When the data mapped by the logical address is in the first type table, determine whether the data corresponding to the logical address is hot data or warm data;

[0155] Step S3003: When the data mapped by the logical address is not in the first type table but in the second type table, determine whether the data corresponding to the logical address is warm data or cold data;

[0156] Step S3004: When the data mapped by the logical address is not in the first type table and not in the second type table, the data corresponding to the logical address is determined to be cold data.

[0157] refer to Figure 3A and Figure 3BFor example, data for the logical address mapping of the write completion queue is obtained by using multiple second-class tables and one first-class table.

[0158] The first type of table can store data mapped to hot logical addresses or data mapped to warm logical addresses; the second type of table can store data mapped to hot logical addresses, data mapped to warm logical addresses, or data mapped to cold logical addresses; logical addresses not stored in the first or second type of table are cold logical addresses.

[0159] If the data mapping the logical address can be found in the first type of table, then the logical address is a hot logical address or a warm logical address; otherwise, the query comes from multiple second type of tables. If the data mapping the logical address cannot be found in multiple second type of tables, then the logical address is a cold logical address. If the data mapping the logical address can be found in two second type of tables, then the logical address is a cold logical address or a warm logical address.

[0160] Figure 4A and Figure 4B A flowchart and a data heatmap illustrating another method for operating a memory system provided in this disclosure. Figure 4A and Figure 4B As shown, in some embodiments, the number of first-type tables includes two, and the number of second-type tables includes two;

[0161] The memory controller 120 is specifically configured to perform the following steps:

[0162] Step S4002: When the data mapped by the logical address is in the first type table of the previous first time interval, determine that the data corresponding to the logical address is hot data;

[0163] Step S4003: When the data mapped by the logical address is not in the first type table of the previous first time interval, but is in the first type table of the current first time interval, determine whether the data corresponding to the logical address is hot data or warm data.

[0164] Step S4004: When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, but is in the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data.

[0165] Step S4005: When the data mapped by the logical address is not in the first type table of the current first time interval, the first type table of the previous first time interval, or the second type table of the previous second time interval, but is in the second type table of the current second time interval, determine whether the data corresponding to the logical address is warm data or cold data.

[0166] Step S4006: When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

[0167] refer to Figure 4A and Figure 4B For example, two second-class tables and two first-class tables are used to alternately write data to the logical address mapping of the completion queue.

[0168] The previous first-class table can store data mapped to hot logical addresses, and the current first-class table can store data mapped to hot logical addresses or data mapped to warm logical addresses; the previous second-class table can store data mapped to hot logical addresses or data mapped to warm logical addresses, and the current second-class table can store data mapped to warm logical addresses or data mapped to cold logical addresses; logical addresses not stored in the first-class table or the second-class table are cold logical addresses.

[0169] For example, each second type table is used to store logical address mapping data with a 1-second granularity and a bit width of 31 bits, hereinafter referred to as the 1-second granularity second type table; each first type table is used to store logical address mapping data with a 1-ms granularity and a bit width of 31 bits, hereinafter referred to as the 1-ms granularity first type table.

[0170] If the data mapping the logical address can be retrieved from the first type table at the previous 1ms level, then the logical address is a hot logical address.

[0171] If the data for the logical address mapping cannot be found in the first type table of the previous 1ms level, but the data for the logical address mapping can be found in the first type table of the current 1ms level, then the logical address is a hot logical address or a warm logical address.

[0172] If the data for the logical address mapping cannot be found in the two 1ms-level first-class tables, but the data for the logical address mapping can be found in the previous 1-second-level second-class table, then the logical address is a warm logical address.

[0173] If logical address mapping data cannot be found in the two 1ms-level first-class tables, and cannot be found in the previous 1-second-level second-class table, but can be found in the current 1-second-level second-class table, then the logical address is a warm logical address or a cold data address.

[0174] If the logical address mapping data cannot be found in either of the two 1ms-level first-class tables, and the logical address mapping data cannot be found in either of the two 1-second-level second-class tables, then the logical address is a cold data address.

[0175] In some specific embodiments, the time interval corresponding to hot data and the time interval corresponding to warm data are set to overlap, and the time interval corresponding to warm data and the time interval corresponding to cold data are set to overlap; this increases the margin for the memory controller to determine the heat of the data corresponding to the logical address of the received read command.

[0176] For example, refer to Figure 4B The time interval for hot data is 1μs to 2ms, the time interval for warm data is 1ms to 2Ses, and the time interval for cold data is greater than 2Ses. Among these, the time intervals for hot data and warm data overlap by 1ms to 2ms, and the time intervals for warm data and cold data overlap by 1Ses to 2Ses.

[0177] Figure 5A and Figure 5B A flowchart and a data heatmap illustrating another method of operating a memory system provided in this disclosure. Figure 5A and Figure 5B As shown, in some embodiments, the number of first-type tables includes two, and the number of second-type tables includes two;

[0178] The memory controller 120 is specifically configured as follows:

[0179] S5002 and S5003: When the data mapped by the logical address is in the first type table of the current first time interval or the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data.

[0180] S5004 and S5005: When the data mapped by the logical address is not in the first type table of the current first time interval or the first type table of the previous first time interval, but is in the second type table of the current second time interval or the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data.

[0181] S5006. When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

[0182] refer to Figure 5A and Figure 5B For example, two second-class tables and two first-class tables are used to alternately write data to the logical address mapping of the completion queue.

[0183] Both the previous first-class table and the current first-class table are used to store data mapped to hot logical addresses; the previous second-class table can store data mapped to hot logical addresses or data mapped to warm logical addresses, and the current second-class table can store data mapped to warm logical addresses; no data mapped to cold logical addresses in the first-class table or the second-class table is stored.

[0184] For example, each second type table is used to store logical address mapping data with a 1-second granularity and a bit width of 31 bits, hereinafter referred to as the 1-second granularity second type table; each first type table is used to store logical address mapping data with a 1-ms granularity and a bit width of 31 bits, hereinafter referred to as the 1-ms granularity first type table.

[0185] If the data mapping the logical address can be found in the first type table at the previous 1ms level or the first type table at the current 1ms level, then the logical address is a hot logical address.

[0186] If the logical address mapping data cannot be found in the two 1ms-level first-class tables, but the read logical address mapping data can be found in the current 1-second-level second-class table or the previous 1-second-level second-class table, then the logical address is a warm logical address.

[0187] If the logical address mapping data cannot be found in either of the two 1ms-level first-class tables, and the read logical address mapping data cannot be found in either of the two 1sec-level second-class tables, then the logical address is a cold data address.

[0188] In some specific embodiments, the time intervals corresponding to hot data, warm data, and cold data together constitute a continuous time interval; this increases the certainty of the memory controller in determining the heat of the data corresponding to the logical address of the received read command.

[0189] For example, refer to Figure 5B The time intervals for hot data are 1 μs to 2 ms, for warm data are 2 ms to 2 ses, and for cold data are greater than 2 ses. There is no overlap between the time intervals for hot data and warm data, or between the time intervals for warm data and cold data.

[0190] In some embodiments, the memory controller 120 is further configured to:

[0191] When the data corresponding to the logical address is hot data, the drift amount corresponding to the logical address is determined as the first-level drift amount;

[0192] When the data corresponding to the logical address is warm data, the drift amount corresponding to the logical address is determined to be the second-level drift amount;

[0193] When the data corresponding to the logical address is cold data, the drift amount corresponding to the logical address is determined to be the third-level drift amount;

[0194] The first-level drift is less than the second-level drift, and the second-level drift is less than the third-level drift.

[0195] In practical applications, the reading voltage with the first-level drift corresponds to reading thermal data (1μs~2ms); the reading voltage with the first-level drift corresponds to reading temperature data (1ms~2s); and the reading voltage with the first-level drift corresponds to reading cold data (1s~several hours).

[0196] In this embodiment, the "hotness" of hot data, warm data, and cold data decreases from high to low, meaning the average time difference between writing and reading increases from low to high, specifically 1μs to 2ms, 1ms to 2s, and 1s to several hours, respectively. Higher data "hotness" indicates that the memory cell corresponding to that logical address is read or written more frequently, resulting in a smaller threshold voltage offset for that memory cell, requiring a smaller drift amount. For example, based on the decreasing "hotness" of hot data, warm data, and cold data, the corresponding first-level drift amount, second-level drift amount, and third-level drift amount increase from low to high, respectively.

[0197] In some embodiments, the memory controller 120 is specifically configured to:

[0198] When the data corresponding to the logical address is determined to be warm data using the first and second type tables, and a read failure occurs when reading the data of the memory cell corresponding to the logical address using the read voltage corresponding to the warm data, the data of the memory cell corresponding to the logical address is reread using the read voltage corresponding to the cold data.

[0199] As mentioned above Figure 3A , Figure 4A and Figure 5A In steps S3005, S4007, and S5007 shown respectively, when the logical address mapping data cannot be found in the two first-class tables, but the read logical address mapping data can be found in the current second-class table or the previous second-class table, it is necessary to determine whether the logical address mapping data is a false positive: if it is a false positive, the logical address mapping data is cold data; if it is not a false positive, the logical address mapping data is warm data.

[0200] The accuracy of querying the second type of table is not 100% and there may be a false positive rate. For example, some Bloom filters have a false positive rate of about 0.1%.

[0201] For example, such as Figure 4A and Figure 5A As shown, when the data mapped to the logical address cannot be found in either of the two first-class tables, but the data mapped to the logical address can be found in the current second-class table or the previous second-class table, the data of the memory cell corresponding to the logical address is first read using the read voltage corresponding to the warm data. If the read fails, it indicates that the data mapped to the logical address may be a false positive, and the data mapped to the logical address may actually be cold data. In this case, the read voltage corresponding to the cold data can be changed to reread the data of the memory cell corresponding to the logical address, or an error correction code (ECC) can be used to correct it. If the read is successful and the data mapped to the logical address does not have a false positive, then the data mapped to the logical address is warm data, and the read voltage corresponding to the warm data is still used to reread the data of the memory cell corresponding to the logical address.

[0202] The above details how to determine the level of drift corresponding to a logical address. The following section will introduce some specific application scenarios for determining the level of drift corresponding to a logical address.

[0203] Figure 6 This is a block diagram of a memory system provided in an embodiment of the present disclosure. Figure 7 This is a flowchart illustrating the operation method of a memory system provided in an embodiment of this disclosure. Figure 6 and Figure 7 As shown, this disclosure provides an operation method for a memory system 100, which includes: at least one non-volatile memory device 110 and a memory controller 120 coupled to the non-volatile memory device 110; the memory controller is further configured to:

[0204] Step S201: Check whether the logical address corresponding to the received host read command is stored in the write buffer;

[0205] Step S202: When the logical address is not stored in the write buffer, determine the level of the drift amount corresponding to the logical address that is not stored in the write buffer;

[0206] Step S203: Send a read command to the non-volatile memory device according to the level of the drift amount corresponding to the logical address; wherein, at least two processes are executed in parallel during the process of checking whether the logical address is saved, determining the level of the drift amount and sending the read command.

[0207] In this embodiment of the present disclosure, in step S201, the host sends a read command to the memory controller 120. After receiving the read command sent by the host, the memory controller 120 checks whether the logical address corresponding to the received read command is stored in the write buffer, that is, checks whether the logical address corresponding to the read command is available in the write buffer.

[0208] In some embodiments, if the logical address corresponding to the read command is stored in a write buffer, the data corresponding to that logical address can be retrieved from the write buffer. Here, the write buffer can be located within the host. When the logical address corresponding to the read command is stored in the write buffer, the data corresponding to that logical address can be retrieved from the write buffer, and the access distance to retrieve the data corresponding to that logical address is relatively short.

[0209] In some embodiments, if the logical address corresponding to the read command is not stored in the write buffer, the data corresponding to the logical address can be obtained from the non-volatile memory device 110. Here, when the logical address corresponding to the read command is not stored in the write buffer, the data corresponding to the logical address can be obtained from the non-volatile memory device 110 through the memory controller 120, but the access distance to obtain the data corresponding to the logical address is relatively long.

[0210] It should be noted that the above Figure 3A , Figure 4A , Figure 5A The data mapped by the logical address in steps S3001, S4001, and S5001 can be understood as the data mapped by logical operations on the logical address that is not stored in the write buffer after step S201.

[0211] In this embodiment of the disclosure, in step S202, when the logical address is not stored in the write buffer, for the logical address not stored in the write buffer, considering the different drift amounts of the threshold voltages of different memory cells, the level of the drift amount corresponding to the logical address not stored in the write buffer is determined. Different levels of drift amount correspond to different read voltages, and in subsequent steps, the read voltage for performing read command operations on the non-volatile memory device 110 can be determined based on the level of drift amount.

[0212] In this embodiment of the present disclosure, in step S203, a read command is sent to the non-volatile memory device 110 according to the level of drift corresponding to the logical address. Thus, the read voltage for performing the read command operation on the non-volatile memory device 110 can be determined based on the level of drift corresponding to the logical address, thereby ensuring the correctness of the read command operation and improving the reliability of the memory device 110.

[0213] In this embodiment, steps S201, S202, and S203 can be executed in a pipeline manner. Specifically, in step S201, it is checked whether the logical address corresponding to the host read command is stored in the write buffer. Depending on whether the logical address is stored in the write buffer, different steps are executed subsequently. For logical addresses not stored in the write buffer, step S202 continues. In other words, for a fixed logical address, if step S201 is executed and the logical address is not stored in the write buffer, step S202 can be executed for that logical address. In step S202, the drift level corresponding to the logical address not stored in the write buffer is determined, and step S203 continues. That is, for a fixed logical address, if step S202 is executed and the drift level corresponding to the logical address is determined, step S203 can be executed for that logical address. In step S203, a read command is sent to the non-volatile memory device 110 according to the drift level corresponding to the logical address. In other words, for a fixed logical address, step S203 is executed, and a read command is sent to the non-volatile memory device 110 according to the level of drift corresponding to the logical address.

[0214] It should be noted that for a fixed logical address, steps S201, S202, and S203 are executed in a pipelined manner, that is, sequentially. However, for multiple logical addresses, steps S201, S202, and S203 can be executed in parallel. This is because the time spent executing steps S201, S202, and S203 is different. For example, for two logical addresses, namely a first logical address and a second logical address, steps S201, S202, and S203 can be executed sequentially for the first logical address, while step S201 can be executed for the second logical address simultaneously with step S202. In other words, there is no need to wait for the first logical address to complete steps S201, S202 and S203 before executing step S201 on the second logical address; at the same time, the logical addresses corresponding to the execution of steps S201, S202 and S203 are different.

[0215] In this embodiment of the disclosure, at least two processes are executed in parallel: checking whether the logical address is stored in the write buffer, determining the level of the drift amount corresponding to the logical address not stored in the write buffer, and sending the read command. This can optimize the read latency and improve the read efficiency.

[0216] It should be noted that the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command involve at least two steps with three possible scenarios. In the first scenario, steps S201 and S202 are combined; that is, one processor executes steps S201 and S202 sequentially in a serial manner, while another processor executes step S203. In this case, the processing of steps S201 and S202 is executed in parallel with the processing of step S203. This can save read time to some extent, optimize read latency, and improve read efficiency.

[0217] In the second case, step S201 is executed using one processor; steps S202 and S203 are combined, that is, steps S202 and S203 are executed sequentially using another processor. In this case, the processing of step S201 is executed in parallel with the processing of steps S202 and S203. This can save reading time to some extent, optimize reading latency, and improve reading efficiency.

[0218] In the third case, steps S201, S202, and S203 are executed using three processors respectively. In this case, the processing of steps S201, S202, and S203 is performed in parallel. This further saves reading time, optimizes reading latency, and improves reading efficiency.

[0219] The following is for reference. Figure 8 , Figure 8 A flowchart illustrating an operation method of a memory system provided in an embodiment of this disclosure. (In conjunction with...) Figure 6 and Figure 8 As shown, this paper explains in detail how the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command are all executed in parallel.

[0220] like Figure 6 and Figure 8 As shown, in some embodiments, the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command are all executed in parallel; the memory controller 120 includes: a first processor 121, a second processor 122, a third processor 123, a first on-chip memory 124, and a second on-chip memory 125; wherein,

[0221] The first processor 121 is configured to: check whether the logical address corresponding to the host read command is stored in the write buffer, and submit the logical address that is not stored in the write buffer to the first submission queue;

[0222] The first on-chip memory 124 is configured to store the first submission queue;

[0223] The second processor 122 is configured to: determine the level of the drift amount corresponding to each logical address in the first submission queue, and submit the level of the drift amount corresponding to each logical address to the second submission queue;

[0224] The second on-chip memory 125 is configured to store the second submission queue;

[0225] The third processor 123 is configured to send a read command to the non-volatile memory device 110 according to the level of drift corresponding to each logical address in the second submission queue;

[0226] At the same time, the logical addresses corresponding to the first submission queue, the second submission queue, and the read command are different.

[0227] like Figure 8 As shown, in step S301, the host dispatch task is performed, that is, the host sends a read command. The execution entity of step S301 is the host.

[0228] In step S302, it is checked whether the logical address corresponding to the host read command is stored in the write buffer. If the result of step S302 is "no", that is, the logical address corresponding to the host read command is not stored in the write buffer, then step S303 is executed; if the result of step S302 is "yes", that is, the logical address corresponding to the host read command is stored in the write buffer, then step S304 is executed.

[0229] In other words, in step S302, it is checked whether the logical address corresponding to the host read command and the logical address in the write buffer overlap (Read LBA overlap check). If the logical address corresponding to the host read command and the logical address in the write buffer do not overlap (Writer Buffer Miss), that is, the logical address corresponding to the host read command is not stored in the write buffer, then step S303 is executed; if the logical address corresponding to the host read command and the logical address in the write buffer overlap (Writer Buffer Hit), that is, the logical address corresponding to the host read command is stored in the write buffer, then step S304 is executed.

[0230] In this embodiment of the disclosure, the main body executing step S302 is the first processor 121 (i.e., Core 1), which is located within the memory controller 120.

[0231] In step S303, logical addresses not stored in the write buffer are submitted to the first submission queue. The first submission queue is stored in the first on-chip memory (OCM) 124, which is located within the memory controller 120. In other words, the first submission queue can also be called a filtered submission queue, that is, logical addresses not stored in the write buffer are filtered out to form a filtered submission queue.

[0232] In this embodiment of the present disclosure, the first processor 121 returns the data corresponding to the logical address when the logical address corresponding to the read command is stored in the write buffer; the first on-chip memory 124 stores the returned data.

[0233] In step S304, for a logical address stored in the write buffer, the data corresponding to the logical address can be returned, completing the data reading process for the logical address. The data corresponding to the logical address stored in the write buffer is stored in the first on-chip memory 124.

[0234] In step S305, the drift level corresponding to each logical address in the first commit queue is determined, that is, the drift level corresponding to each logical address in the first commit queue is predicted, and the drift level corresponding to each logical address is submitted to the second commit queue.

[0235] In this embodiment of the disclosure, the main body executing step S305 is the second processor 122 (i.e., Core 2), which is located within the memory controller 120.

[0236] Please refer to the above for further information. Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B The following section will explain in detail how to determine the drift level corresponding to each logical address in the first commit queue.

[0237] In some embodiments, before the second processor 122 determines the level of the drift amount corresponding to each logical address in the first submission queue and submits the level of the drift amount corresponding to each logical address to the second submission queue, the above operation method further includes:

[0238] The second processor 122 determines the level of drift corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue; the heat of the data represents the length of the average time difference between data writing and reading.

[0239] Here, the drift level for each logical address is determined based on the "heat" of the data corresponding to each logical address in the first commit queue, specifically the length of the time difference between writing and reading the data at each logical address. A shorter time difference between writing and reading the data at a logical address indicates higher "heat" of the data; correspondingly, the threshold voltage drift of the storage unit used to store this high-heat data is smaller. Conversely, a longer time difference between writing and reading the data at a logical address indicates lower "heat" of the data; correspondingly, the threshold voltage drift of the storage unit used to store this low-heat data is larger.

[0240] In this embodiment of the disclosure, based on the heat of the data corresponding to each logical address in the first submission queue, and considering the different drift amounts of the threshold voltage of the storage cell used to store this data, different read voltages are applied when performing read command operations on the non-volatile storage device, thereby ensuring the correctness of the read command operations and improving the reliability of the memory system.

[0241] In some embodiments, the second processor 122 determines the level of drift corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue, including:

[0242] When the data corresponding to the logical address is hot data, the second processor 122 determines the drift amount corresponding to the logical address as the first-level drift amount; when the data corresponding to the logical address is warm data, the second processor 122 determines the drift amount corresponding to the logical address as the second-level drift amount; when the data corresponding to the logical address is cold data, the second processor 122 determines the drift amount corresponding to the logical address as the third-level drift amount; wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

[0243] As mentioned above, the threshold voltage drift of storage cells storing hot data is the smallest, followed by those storing warm data, and the threshold voltage drift of storage cells storing cold data is the largest. Therefore, based on the different temperatures of the data stored in the storage cells, the threshold voltage drift of each storage cell can be determined to be different. Subsequently, based on these different threshold voltage drifts, different read voltages can be applied when performing read command operations on these storage cells.

[0244] In some embodiments, the above-described operation method further includes:

[0245] The second processor 122 determines the order of logical addresses in the second submission queue based on the popularity of the data corresponding to each logical address in the first submission queue; wherein, the higher the popularity of the data corresponding to the logical address, the higher the priority of the logical address order in the second submission queue.

[0246] Here, the logical addresses in the first commit queue are in an unordered state; that is, the order of hot, warm, and cold data corresponding to logical addresses in the first commit queue is random. In other words, a logical address can be committed to the first commit queue as long as it is determined that it is not stored in the write buffer. Therefore, the order of the logical addresses in the first commit queue corresponds to the moment when it is determined that a logical address is not stored in the write buffer. The "hotness" of the data corresponding to the logical addresses not stored in the write buffer is randomly distributed. Without considering the order of hot, warm, and cold data corresponding to logical addresses in the first commit queue, the drift level corresponding to each logical address in the first commit queue is determined sequentially to obtain the second commit queue; read command operations are then performed on each logical address in the second commit queue sequentially.

[0247] It's important to note that the write and read time difference for hot data is extremely short (i.e., 1 microsecond to 2 milliseconds). If the hot data corresponding to a logical address in the first commit queue is ranked low (i.e., operations on the hot data corresponding to that logical address have a lower priority), then the process waits until the drift level of the hot data corresponding to that logical address in the first commit queue is determined, and further waits before a read command operation can be performed on that hot data. In other words, the time to operate on the hot data corresponding to that logical address may exceed the timeliness requirement of the hot data. Therefore, the ranking of logical addresses in the second commit queue can be determined based on the popularity of the data corresponding to each logical address in the first commit queue; the higher the popularity of the data corresponding to a logical address in the first commit queue, the higher the ranking of the logical address in the second commit queue, and the higher the priority of read command operations on that logical address. In this way, the process of performing read command operations on hot data can be accelerated, meeting the timeliness requirements of hot data.

[0248] In step S306, the level of drift corresponding to each logical address is submitted to the second submission queue. The second submission queue is stored in the second on-chip memory 125, which is located within the memory controller 120. In other words, the second submission queue can also be called the Preficted Submission Queue, which predicts the level of drift corresponding to each logical address to form the predictive submission queue.

[0249] In step S307, a read command is sent to the non-volatile memory device 110 according to the drift level corresponding to each logical address in the second submission queue. If the read is successful, step S308 is executed; if the read fails, step S309 is executed.

[0250] Specifically, the third processor 123 sends a read command to the non-volatile memory device 110 according to the drift level corresponding to each logical address in the second submission queue. The third processor 123 is specifically configured as follows:

[0251] Based on the level of drift corresponding to each logical address in the second submission queue, determine the read voltage for performing a read command operation on the non-volatile memory device 110;

[0252] A read command is sent to the non-volatile memory device 110 based on the read voltage used to perform the read command operation on the non-volatile memory device 110.

[0253] In this embodiment of the disclosure, the main body executing step S307 is the third processor 123, which is located within the memory controller 120. In other words, the third processor 123 can also be called a storage media controller (Media Controller). The storage media controller is located within the memory controller 120, coupled to the non-volatile storage device 110, and is used to control the non-volatile storage device 110.

[0254] In some embodiments, after the third processor 123 sends a read command to the non-volatile memory device 110 according to the drift level corresponding to each logical address in the second submission queue, the third processor is specifically configured as follows:

[0255] The third processor 123 is specifically configured to: when a read operation on the non-volatile memory device 110 is successful, submit the logical address of the read command to the read completion queue; and when a read operation on the non-volatile memory device 110 fails, submit the logical address of the read command to the write completion queue.

[0256] The second on-chip memory 125 is configured to store a complete read queue and a complete write queue;

[0257] The second processor 122 is configured to: redetermine the level of drift corresponding to each logical address in the write completion queue.

[0258] In step S308, when the non-volatile memory device 110 is successfully read, the logical address corresponding to the read command is submitted to the read completion queue. The read completion queue is stored in the second on-chip memory 125, which is located within the memory controller 120.

[0259] In step S309, when a read operation on the non-volatile memory device 110 fails, the logical address corresponding to the read command is submitted to the write completion queue. For each logical address in the write completion queue, step S305 is executed again to redetermine the drift level corresponding to each logical address in the write completion queue. The write completion queue is stored in the second on-chip memory 125, which is located within the memory controller 120.

[0260] For example, the second processor 122 can determine whether the data corresponding to each logical address in the first submission queue is warm or cold data by querying a Bloom filter. However, the accuracy of querying the Bloom filter is not 100%, meaning there may be a false positive rate. In other words, the second processor 122 determines that the data corresponding to a logical address in the first submission queue is warm (or cold) data by querying the Bloom filter, but in reality, the data corresponding to that logical address is cold (or warm). Further, based on the "warmth" of the data corresponding to the logical address, the level of the drift amount corresponding to the logical address is determined, and subsequently, the read voltage is determined based on the level of the drift amount corresponding to the logical address. Since the result of determining the "warmth" of the data corresponding to the logical address in the first submission queue is incorrect, the result of determining the level of the drift amount corresponding to the logical address based on the "warmth" of the data corresponding to the logical address is also incorrect, and the result of determining the read voltage based on the level of the drift amount corresponding to the logical address is also incorrect. Using an incorrect read voltage to perform read command operations may lead to read failure. Therefore, it is necessary to re-determine the level of the drift amount corresponding to the logical address of these read command operations that failed.

[0261] In this embodiment, the algorithm design of the memory controller 120 can be optimized without increasing costs, i.e., without adding hardware. The read voltage for performing read command operations on the non-volatile memory device 110 can be determined based on the drift amount corresponding to the logical address, thereby ensuring the correctness of the read command operation and improving the reliability of the memory system. Furthermore, by executing the processes of checking whether the logical address is stored in the write buffer, determining the level of the drift amount corresponding to the logical address not stored in the write buffer, and sending the read command in parallel, the read latency can be optimized and the read efficiency can be improved.

[0262] refer to Figure 9 , Figure 9 This is a schematic diagram showing the logical addresses of the first processor, the second processor, and the third processor during the nth time interval of the operation method of the memory system provided in the embodiments of this disclosure.

[0263] Figure 9 Steps S201, S202, and S203 are illustrated, separated by dashed lines. The first processor executes step S201, the second processor executes step S202, and the third processor executes step S203.

[0264] Specifically, the first processor executes step S201, checking whether the logical address corresponding to the host read command is stored in the write buffer, and submitting the logical addresses not stored in the write buffer to the first commit queue. That is, if each logical address in the first commit queue is not stored in the write buffer, the first processor filters out the logical addresses corresponding to the host read command that are not stored in the write buffer. For example, the first processor can check a total of 20 logical addresses in each time interval and submit the logical addresses not stored in the write buffer to the first commit queue.

[0265] It should be noted that multiple logical addresses in the first submission queue are in an unordered state; that is, the order of hot data, warm data, and cold data corresponding to logical addresses in the first submission queue is irregular.

[0266] Specifically, the second processor executes step S202, determining the level of the drift amount corresponding to each logical address in the first submission queue, and submitting the level of the drift amount corresponding to each logical address to the second submission queue. For example, the second processor can determine (or calculate) the drift amount levels corresponding to a total of 5 logical addresses within each time interval. That is, the number of logical addresses processed by the first processor and the second processor can be different within the same time interval.

[0267] Specifically, the third processor is used to execute step S203, which sends a read command to the non-volatile memory device 110 according to the level of drift corresponding to each logical address in the second submission queue.

[0268] In this embodiment of the disclosure, for a fixed logical address, steps S201, S202, and S203 are executed sequentially in a pipelined manner. However, for multiple logical addresses, within the nth time interval, the first processor performs the (n+1)th round to check whether the logical address is stored in the write buffer; the second processor performs the nth round to determine the drift level corresponding to the logical address in the first commit queue; and the third processor performs the (n-1)th round to send the read command corresponding to the drift level of the logical address in the second commit queue; where n is a positive integer. That is, steps S201, S202, and S203 are executed in parallel, and at the same time, the logical addresses processed by steps S201, S202, and S203 are different.

[0269] It should be noted that each step in steps S201, S202, and S203 has consecutive time intervals, such as the (n-1)th round, the nth round, and the (n+1)th round, with each round's processing time corresponding to a time interval. The specific duration of this time interval can be selected based on actual conditions, taking into account factors such as the time period corresponding to the heat level and the parameters of each processor in the memory controller. For example, the duration of the time interval can be K*160ns, where K can be obtained empirically.

[0270] It should be noted that the number of rounds processed by two adjacent steps in the same time interval must differ by at least one round; the difference in the number of rounds processed by two adjacent steps in the same time interval can be adjusted according to actual needs.

[0271] In some instances, the number of rounds processed by two adjacent steps in the same time interval differs by 1 round, such as Figure 9 As shown, in the nth time interval, step S201 processes the (n+1)th round, step S202 processes the nth round, and step S203 processes the (n-1)th round. The logical address corresponding to the received read command is processed by consecutive time intervals of the (n-1)th, nth, (n+1)th, (n+2)th, ... time intervals. For example, the logical address corresponding to the read command triggered in the (n-1)th time interval is checked by the first processor in the nth round of the (n-1)th time interval. Figure 9 The check (n) shown is processed by the first processor in the nth round of checks, and then by the second processor in the nth time interval in the nth round of calculations. Figure 9 The calculation (n) shown is processed by the second processor, and after the second processor completes the nth round of calculation, the third processor will complete the nth round of reading at the (n+1)th time interval. Figure 9 The reading n) process is shown.

[0272] In other words, the logical address corresponding to the read command triggered in the (n-1)th time interval will sequentially complete the checking, calculation, and reading processes in the three immediately following triggering time intervals (the (n-1)th time interval, the nth time interval, and the (n+1)th time interval). No redundant time is allocated between adjacent processing steps. For example, data checked by the first processor will immediately be processed by the second processor; there is no redundant time between checking and calculation, which improves data processing efficiency.

[0273] In other examples, the number of rounds processed by two adjacent steps in the same time interval differs by 2 rounds. Figure 9 (Not shown), in the (n-1)th time interval, step S201 processes the nth round, and step S202 processes the (n-2)th round (…). Figure 9 (Not shown), step S203 is in the process of the (n-4th) round ( Figure 9 (Not shown).

[0274] The logical address corresponding to the read command triggered in the (n-1)th time interval will be determined in three separate triggering time intervals (the (n-1)th time interval, the (n+1)th time interval, the (n+3)th time interval). Figure 9 (Not shown) The processing steps of checking, calculating, and reading are performed sequentially. A redundant time interval is set between two adjacent processing steps. For example, data checked by the first processor in the (n-1)th time interval will not be immediately processed by the second processor. After waiting for one time interval (the nth time interval), the calculation is performed in the (n+1)th time interval. A redundant time interval is set between checking and calculation. The memory controller can use one time interval (the nth time interval) for other processing (such as ECC verification), which can improve the reliability of data processing.

[0275] It is understandable that for a fixed logical address, the execution steps S201, S202 and S203 are executed serially, but for multiple logical addresses, the execution steps S201, S202 and S203 are executed in parallel.

[0276] In this embodiment of the disclosure, the memory system may include storage class memory (SCM); the non-volatile memory device may include phase change memory.

[0277] In the existing storage hierarchy, there is a gap in storage speed and capacity between Dynamic Random Access Memory (DRAM) and non-volatile storage devices (such as NAND flash memory), limiting further improvements in computing power. To address this, a storage-level memory (PMM) is proposed that falls between DRAM and non-volatile storage devices in terms of storage speed and capacity. Various attributes of DRAM, Phase-Change Memory (PCM), and NAND flash memory are considered, including whether they are non-volatile, storage density, erase requirements, software support, erase / write cycles, read latency, and write latency. Among these, PCM's storage speed (read and write latency) and storage capacity (storage density) allow it to effectively occupy a position between DRAM and non-volatile storage devices, serving as an intermediate memory.

[0278] Currently, there are many types of storage media for storage-class memory, with the most mainstream including phase-change memory, resistive random access memory, magnetic random access memory, and carbon nanotube random access memory.

[0279] The basic principle of phase-change memory (PCM) is as follows: A short-duration electrical pulse with a large signal value is applied to the PCM cell. Under Joule heating, a portion of the initially crystalline PCM layer melts because its temperature exceeds the melting point. After the pulse is interrupted, the molten portion cools rapidly and remains in an amorphous state with low atomic order, thus completing the transition from low resistance to high resistance—this is the reset process. The molten portion in this process is called the programming volume. If a short-duration electrical pulse with a small signal value is applied, causing the temperature within the programming volume to reach above the crystallization temperature but below the melting point, and this is sustained for a sufficient time for the amorphous structure within the programming volume to crystallize, a low-resistance state is obtained—this is the set process. The read process of PCM involves applying a short-duration electrical pulse to the PCM cell, keeping the PCM layer below the crystallization temperature, and measuring the resistance of the PCM cell.

[0280] As the storage medium of phase change memory (PDM), the performance of phase change memory materials directly affects the characteristics of the device. Typically, the characteristics of PDM are mainly measured by indicators such as write operation speed, data retention capability, and on / off ratio. Therefore, research on the performance of PDM materials includes studies on parameters such as crystallization rate, crystallization temperature, amorphous structure stability, thermal stability, and resistivity window (i.e., the ratio of resistivity of the amorphous state to that of the crystalline state).

[0281] For phase-change memory (PCM), the write operation generally takes the longest time among the write, erase, and read operations, becoming a key factor limiting the high-speed operation of PCM. The write operation time is related to the crystallization rate of the PCM material. The faster the crystallization rate, the shorter the write operation time, and the faster the PCM operation speed.

[0282] The data retention capability of phase change memory (PCM) depends on the amorphous structure stability and thermal stability of the PCM material. Better amorphous structure stability and thermal stability result in longer data retention. To achieve better amorphous structure stability and thermal stability, the PCM material needs to have a higher crystallization temperature.

[0283] The on / off ratio of a phase-change memory (PCM) is determined by the resistance window of the PCM material. The resistance window refers to the resistivity difference between the amorphous and crystalline states. A larger resistivity difference between the amorphous and crystalline states results in a larger resistance window, ensuring a higher on / off ratio and enabling accurate and rapid data reading during operations.

[0284] In this embodiment of the disclosure, both the first on-chip memory 124 and the second on-chip memory 125 include dynamic random access memory or static random access memory.

[0285] In this embodiment, the first on-chip memory 124 is used to store the intermediate results of step S201, including a first submission queue and data corresponding to logical addresses stored in a write buffer; the second on-chip memory 125 is used to store the intermediate results of step S202, including a second submission queue, a write completion queue, and a read completion queue. By executing steps S201, S202, and S203 in parallel, the efficiency of reading from the non-volatile storage device 110 can be accelerated, thereby minimizing the storage capacity of the first on-chip memory 124 and the second on-chip memory 125 used to store these intermediate results.

[0286] refer to Figure 10 , Figure 10 A block diagram of a memory provided for an embodiment of this disclosure. (As shown) Figure 10 As shown, according to a second aspect of the present disclosure, a memory controller 120 is provided, the memory controller 120 being coupled to at least one non-volatile memory device ( Figure 10 (Not shown in the diagram) Coupling; the memory controller 120 is configured to:

[0287] Using a first type of table and a second type of table, the "heat" of the data corresponding to the logical address of the received read command is determined; the "heat" of the data characterizes the length of the average time difference between data writing and reading; the first type of table includes at least one, and at least one first type of table is used to store the data of logical address mapping for each first time interval within a first preset time period after writing; the second type of table includes multiple, and multiple second type of tables are used to alternately store the data of logical address mapping for each second time interval within a second preset time period after writing; the first preset time period is less than the second preset time period, and the first time interval is less than the second time interval;

[0288] Based on the popularity of the data corresponding to the logical address, the level of drift corresponding to the logical address is determined; different levels of drift correspond to different read voltages sent to the non-volatile memory device.

[0289] Figure 10 The memory controller 120 is illustrated to include a first processor 121, a second processor 122, a third processor 123, a first on-chip memory 124, and a second on-chip memory 125. Specifically, the first processor 121 checks whether the logical address corresponding to the host read command is stored in the write buffer, and submits logical addresses not stored in the write buffer to a first commit queue; the first on-chip memory 124 stores the first commit queue; the second processor 122 determines the drift level corresponding to each logical address in the first commit queue and submits the drift level corresponding to each logical address to a second commit queue; the second on-chip memory 125 stores the second commit queue; the third processor 123 sends a read command to the non-volatile memory device 110 according to the drift level corresponding to each logical address in the second commit queue; at any given time, the logical addresses corresponding to the first commit queue, the second commit queue, and the read command are different.

[0290] Refer to the above Figure 1 According to a third aspect of the present disclosure, a method of operating a memory system is provided. The memory system 100 includes: at least one non-volatile memory device 110 and a memory controller 120 coupled to the non-volatile memory device 110; the method of operating includes:

[0291] Using a first type of table and a second type of table, the heat of the data corresponding to the logical address of the received read command is determined; the heat of the data characterizes the length of the average time difference between data writing and reading; the first type of table includes at least one, and at least one first type of table is used to store the data of logical address mapping for each first time interval within a first preset time period after writing; the second type of table includes multiple, and multiple second type of tables are used to alternately store the data of logical address mapping for each second time interval within a second preset time period after writing; the first preset time period is shorter than the second preset time period, and the first time interval is shorter than the second time interval;

[0292] Based on the popularity of the data corresponding to the logical address, the level of drift corresponding to the logical address is determined; different levels of drift correspond to different read voltages sent to the non-volatile memory device 110.

[0293] Refer to the above Figure 2A and Figure 2B In some embodiments, the method further includes: forming a first type of table and a second type of table;

[0294] Forming the first type of table and the second type of table, including:

[0295] The logical address of each first time interval within the first preset time period after writing is stored in the first type table, which is mapped by the hash table mapping function.

[0296] The logical addresses of each second time interval within the second preset time period after writing are mapped by mapping functions in Bloom filter, Cuckoo filter, XOR filter or vacuum filter and stored in the second type table.

[0297] Refer to the above Figure 3A and Figure 3B In some embodiments, the data heat includes: hot data, warm data, and cold data; the average time difference for writing and reading corresponding to hot data, warm data, and cold data increases sequentially.

[0298] Using the first and second type tables, the heat of the data corresponding to the logical address of the received read command is determined, including:

[0299] When the data group mapped by the logical address is in the first type of table, it is determined whether the data corresponding to the logical address is hot data or warm data.

[0300] When the data group mapped by the logical address is not in the first type table but in the second type table, the data corresponding to the logical address is determined to be warm data or cold data.

[0301] When the data group mapped by the logical address is not in the first type table and not in the second type table, the data corresponding to the logical address is determined to be cold data.

[0302] Refer to the above Figure 4A and Figure 4B In some embodiments, the number of first-type tables includes two, and the number of second-type tables includes two;

[0303] Using the first and second type tables, the heat of the data corresponding to the logical address of the received read command is determined, including:

[0304] When the data mapped by the logical address is in the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data;

[0305] When the data mapped by the logical address is not in the first type table of the previous first time interval, but is in the first type table of the current first time interval, the data corresponding to the logical address is determined to be hot data or warm data.

[0306] When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, but is in the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data.

[0307] When the data mapped by the logical address is not in the first type table of the current first time interval, the first type table of the previous first time interval, or the second type table of the previous second time interval, but is in the second type table of the current second time interval, the data corresponding to the logical address is determined to be warm data or cold data.

[0308] When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

[0309] Refer to the above Figure 5A and Figure 5B In some embodiments, the number of first-type tables includes two, and the number of second-type tables includes two;

[0310] Using the first and second type tables, the heat of the data corresponding to the logical address of the received read command is determined, including:

[0311] When the array data mapped by the logical address is in the first type table of the current first time interval or the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data.

[0312] When the array data mapped by the logical address is not in the first type table of the current first time interval or the first type table of the previous first time interval, but is in the second type table of the current second time interval or the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data.

[0313] When the array data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

[0314] In some embodiments, determining the level of drift corresponding to a logical address based on the popularity of the data corresponding to that logical address includes:

[0315] When the data corresponding to the logical address is hot data, the drift amount corresponding to the logical address is determined as the first-level drift amount;

[0316] When the data corresponding to the logical address is warm data, the drift amount corresponding to the logical address is determined to be the second-level drift amount;

[0317] When the data corresponding to the logical address is cold data, the drift amount corresponding to the logical address is determined to be the third-level drift amount;

[0318] The first-level drift is less than the second-level drift, and the second-level drift is less than the third-level drift.

[0319] In some embodiments, the method further includes:

[0320] When the data corresponding to the logical address is determined to be warm data using the first and second type tables, and a read failure occurs when reading the data of the memory cell corresponding to the logical address using the read voltage corresponding to the warm data, the data of the memory cell corresponding to the logical address is reread using the read voltage corresponding to the cold data.

[0321] Refer to the above Figure 7 In some embodiments, the method further includes:

[0322] Check whether the logical address corresponding to the received read command is stored in the write buffer;

[0323] When the logical address is not stored in the write buffer, determine the level of the drift amount corresponding to the logical address;

[0324] Based on the level of drift corresponding to the logical address, a read command is sent to the non-volatile storage device 110; wherein, the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command are executed in parallel.

[0325] refer to Figure 11 , Figure 11 A block diagram of a readable storage medium provided in embodiments of this disclosure. (See diagram below.) Figure 11As shown, this disclosure provides a readable storage medium 200 storing a computer program 210. When executed, the computer program 210 can implement the operation method of the memory system as described in the above technical solution. The operation method includes: checking whether the logical address corresponding to a host read command is stored in a write buffer; determining the level of the drift amount corresponding to the logical address not stored in the write buffer; different levels of drift amount correspond to different read voltages; and sending a read command to the non-volatile memory device 110 according to the level of the drift amount corresponding to the logical address. At least two of the processes—checking whether the logical address is stored, determining the level of the drift amount, and sending the read command—are executed in parallel.

[0326] refer to Figure 12 , Figure 12 A block diagram of a system provided in an embodiment of this disclosure. (See diagram below.) Figure 12 As shown, system 300 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, or any other suitable electronic device having a non-volatile storage device 310 therein.

[0327] like Figure 12 As shown, system 300 may include a host 330 and a memory system, the memory system including a memory controller 320 and at least one non-volatile storage device 310. The host 330 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 330 may be configured to send data to or receive data from the non-volatile storage device 310. Figure 12 The illustration shows the memory controller 320 connected to four non-volatile memory devices 310. In fact, this embodiment of the present disclosure does not impose a special limitation on the number of non-volatile memory devices 310 connected to the memory controller 320. The number of non-volatile memory devices 310 connected to the memory controller 320 may be less than four (e.g., one); or the number of non-volatile memory devices 310 connected to the memory controller 320 may be greater than four (e.g., five).

[0328] In some embodiments, the memory controller 320 may be coupled to the host 330 and the non-volatile storage device 310, respectively, and is configured to control the non-volatile storage device 310. The memory controller 320 may manage the data stored in the non-volatile storage device 310 and communicate with the host 330.

[0329] In one specific example, the memory system may include at least one non-volatile memory device 310 and a memory controller 320 coupled to the non-volatile memory device 310; wherein, the memory system may include storage-class memory; and the non-volatile memory device 310 may include phase-change memory.

[0330] Still referencing Figure 12 As shown, the memory controller 320 includes a first communication interface 321, a second communication interface 322, a processing unit 323, a read-only memory (ROM) 324, a static random access memory (SRAM) 325, and a storage medium controller 326. The processing unit 323 and the host 330 communicate via the first communication interface 321 and the second communication interface 322. The processing unit 323 can also be connected to the storage medium controller 326 to control the storage medium controller 326. The storage medium controller 326 is connected to the non-volatile storage device 310 to control the non-volatile storage device 310. The processing unit 323 can also be connected to the ROM 324 and the SRAM 325. The processing unit 323 can obtain data from the ROM 324 and can store some temporary data in the SRAM 325.

[0331] In some embodiments, the first communication interface 321 can be a Peripheral Component Interconnect Express (PCIE), that is, the first communication interface can be an interface set according to the high-speed serial computer expansion bus standard; the second communication interface 322 can be a Compute Express Link (CXL).

[0332] In a specific example, a non-volatile memory device may include phase-change memory (PCM). System-level read latency affects the actual throughput of the memory-class system. The threshold voltage of the phase-change material in the PCM within the memory-class system varies over time. Only by predicting the drift corresponding to the logical address of the data based on its frequency of occurrence, and adjusting the read voltage accordingly, can the initial raw bit error rate (RBER) be guaranteed.

[0333] When the read latency of the storage medium is very small (~160 nanoseconds), the drift amount corresponding to each logical address read is predicted, and the read voltage is adjusted according to the drift amount corresponding to the logical address. On the one hand, the drift time range of the threshold voltage is large, making it difficult to track all written logical addresses. Different drift rates can lead to read margin loss and Uncorrectable Error Correction Code (UECC). On the other hand, the time difference between writing and reading hot data is short. By prioritizing the reading of logical addresses corresponding to hot data, the timeliness of hot data can be avoided. Therefore, predicting the drift amount of the storage medium (i.e., phase change material) in the storage-class memory and ensuring the reliability and correctness of the data stored in the storage medium are very important.

[0334] In a specific example, a pipelined approach is used to execute querying the Bloom filter and reading data from the storage medium in parallel, thereby avoiding read latency. This scheme focuses on the read flow efficiency between the core processors (i.e., the first and second processors), the storage medium controller (i.e., the third processor), and the storage medium (i.e., the non-volatile storage device). In this way, the promised initial bit error rate can be guaranteed without affecting the overall read latency.

[0335] In a specific example, the read operation includes the following three steps:

[0336] Step 1: Use the core processor (i.e., Core1) to check whether the logical address to be read overlaps with the logical address in the write buffer; pack the logical addresses not stored in the write buffer to obtain the first submission queue; the core processor here can correspond to the first processor as described above.

[0337] Step 2: Use the core processor (i.e., Core2) to predict the drift amount of logical addresses that are not stored in the write buffer; the drift amount corresponding to the logical address can be predicted based on the popularity of the data corresponding to the logical address; the core processor here can correspond to the second processor as described above.

[0338] Step 3: Use the storage medium controller to send a read command to the non-volatile storage device. The logical address corresponding to the read command has already had its drift amount predicted in step 2. The storage medium controller here can correspond to the third processor as described above.

[0339] The above three steps can be executed in a pipelined manner to improve read efficiency. The three steps run in parallel, and the intermediate results obtained from each step can be stored in the on-chip memory.

[0340] This disclosure provides a memory system and its operating method, a memory controller, and a readable storage medium. The memory system includes at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device. The memory controller is configured to: determine whether the data mapped to the logical address of a received read command belongs to a first type table or a second type table, and determine the "hotness" of the data corresponding to the logical address of the received read command based on the determination result; determine the level of drift corresponding to the logical address based on the "hotness" of the data corresponding to the logical address; and apply different read voltages to the non-volatile memory device depending on the level of drift corresponding to the logical address of the received read command. In other words, this disclosure allows for the determination of the level of logical address drift, enabling targeted delivery of read voltages to the non-volatile memory device, thereby ensuring the correctness of the read command operation and improving the reliability of the memory system. Furthermore, the alternating use of multiple second type tables is more flexible and saves more space compared to using a single table.

[0341] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0342] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory system, characterized in that, The memory system includes: at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller is configured to: Using a first type of table and a second type of table, the "heat" of the data corresponding to the logical address of the received read command is determined; the "heat" of the data characterizes the length of the average time difference between data writing and reading; the first type of table includes at least one, and at least one first type of table is used to store the data of logical address mapping for each first time interval within a first preset time period after writing; the second type of table includes multiple, and multiple second type of tables are used to alternately store the data of logical address mapping for each second time interval within a second preset time period after writing; the first preset time period is less than the second preset time period, and the first time interval is less than the second time interval; Based on the popularity of the data corresponding to the logical address, the level of drift corresponding to the logical address is determined; different levels of drift correspond to different read voltages sent to the non-volatile memory device.

2. The memory system according to claim 1, characterized in that, The first type of table is obtained through a hash table; the second type of table is obtained through a Bloom filter, a Cuckoo filter, an XOR filter, or a vacuum filter.

3. The memory system according to claim 1, characterized in that, The data's popularity includes: hot data, warm data, and cold data; the average time difference for writing and reading corresponding to the hot data, warm data, and cold data increases sequentially; the memory controller is specifically configured as follows: When the data mapped by the logical address is in the first type of table, it is determined that the data corresponding to the logical address is hot data or warm data; When the data mapped by the logical address is not in the first type of table but is in the second type of table, the data corresponding to the logical address is determined to be warm data or cold data. When the data mapped by the logical address is not in the first type of table and not in the second type of table, the data corresponding to the logical address is determined to be cold data.

4. The memory system according to claim 3, characterized in that, The first type of table includes two tables, and the second type of table also includes two tables. The memory controller is specifically configured as follows: When the data mapped by the logical address is in the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data. When the data mapped by the logical address is not in the first type table of the previous first time interval, but is in the first type table of the current first time interval, the data corresponding to the logical address is determined to be hot data or warm data. When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, but is in the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data. When the data mapped by the logical address is not in the first type table of the current first time interval, the first type table of the previous first time interval, or the second type table of the previous second time interval, but is in the second type table of the current second time interval, the data corresponding to the logical address is determined to be warm data or cold data. When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

5. The memory system according to claim 3, characterized in that, The first type of table includes two tables, and the second type of table also includes two tables. The memory controller is specifically configured as follows: When the data mapped by the logical address is in the first type table of the current first time interval or the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data. When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, but is in the second type table of the current second time interval or the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data. When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

6. The memory system according to claim 3, characterized in that, The memory controller is also configured to: When the data corresponding to the logical address is the hot data, the drift amount corresponding to the logical address is determined to be the first-level drift amount; When the data corresponding to the logical address is the temperature data, the drift amount corresponding to the logical address is determined to be the second-level drift amount; When the data corresponding to the logical address is the cold data, the drift amount corresponding to the logical address is determined to be the third-level drift amount; Wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

7. The memory system according to claim 3, characterized in that, The memory controller is specifically configured as follows: When the data corresponding to the logical address is determined to be warm data using the first type of table and the second type of table, and a read failure occurs when reading the data of the storage unit corresponding to the logical address using the read voltage corresponding to the warm data, the data of the storage unit corresponding to the logical address is reread using the read voltage corresponding to the cold data.

8. The memory system according to claim 1, characterized in that, The memory controller is also configured to: Check whether the logical address corresponding to the received read command is stored in the write buffer; When the logical address is not stored in the write buffer, determine the level of the drift amount corresponding to the logical address; A read command is sent to the non-volatile memory device according to the level of drift corresponding to the logical address; wherein at least two processes are executed in parallel during the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command.

9. The memory system according to claim 8, characterized in that, The processes of checking whether the logical address is saved, determining the level of drift, and sending the read command are all executed in parallel; the memory controller includes: a first processor, a second processor, a third processor, a first on-chip memory, and a second on-chip memory; wherein, The first processor is configured to: check whether the logical address corresponding to the received read command is stored in the write buffer, and submit the logical address not stored in the write buffer to the first submission queue; The first on-chip memory is configured to store the first submission queue; The second processor is configured to: determine the level of drift corresponding to each logical address in the first submission queue, and submit the level of drift corresponding to each logical address to the second submission queue; The second on-chip memory is configured to store the second submission queue; The third processor is configured to send a read command to the non-volatile memory device according to the level of drift corresponding to each logical address in the second submission queue; At any given time, the logical addresses corresponding to the first submission queue, the second submission queue, and the read command are different.

10. The memory system according to claim 9, characterized in that, The third processor is specifically configured as follows: Based on the level of drift corresponding to each logical address in the second submission queue, determine the read voltage for performing a read command operation on the non-volatile memory device; A read command is sent to the non-volatile memory device based on the read voltage used to perform the read command operation.

11. The memory system according to claim 10, characterized in that, Both the first on-chip memory and the second on-chip memory include dynamic random access memory or static random access memory.

12. The memory system according to claim 1, characterized in that, The memory system includes storage-level memory; the non-volatile memory device includes phase-change memory.

13. A memory controller, characterized in that, At least one non-volatile memory device is coupled to the memory controller, which is configured to: Using a first type of table and a second type of table, the "heat" of the data corresponding to the logical address of the received read command is determined; the "heat" of the data characterizes the length of the average time difference between data writing and reading; the first type of table includes at least one, and at least one first type of table is used to store the data of logical address mapping for each first time interval within a first preset time period after writing; the second type of table includes multiple, and multiple second type of tables are used to alternately store the data of logical address mapping for each second time interval within a second preset time period after writing; the first preset time period is less than the second preset time period, and the first time interval is less than the second time interval; Based on the popularity of the data corresponding to the logical address, the level of drift corresponding to the logical address is determined; different levels of drift correspond to different read voltages sent to the non-volatile memory device.

14. A method for operating a memory system, characterized in that, The memory system includes: at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device; the operation method includes: Using a first type of table and a second type of table, the "heat" of the data corresponding to the logical address of the received read command is determined; the "heat" of the data characterizes the length of the average time difference between data writing and reading; the first type of table includes at least one, and at least one first type of table is used to store the data of logical address mapping for each first time interval within a first preset time period after writing; the second type of table includes multiple, and multiple second type of tables are used to alternately store the data of logical address mapping for each second time interval within a second preset time period after writing; the first preset time period is less than the second preset time period, and the first time interval is less than the second time interval; Based on the popularity of the data corresponding to the logical address, the level of drift corresponding to the logical address is determined; different levels of drift correspond to different read voltages sent to the non-volatile memory device.

15. The method of operating the memory system according to claim 14, characterized in that, The method further includes: forming the first type of table and the second type of table; The formation of the first type of table and the second type of table includes: The data mapped by the hash table mapping function for each first time interval within the first preset time period after writing is stored in the first type of table; The logical addresses of each second time interval within the second preset time period after writing are mapped by mapping functions in Bloom filter, Cuckoo filter, XOR filter or vacuum filter and stored in the second type table.

16. The method of operating the memory system according to claim 14, characterized in that, The data popularity includes: hot data, warm data, and cold data; the average time difference for writing and reading the hot data, warm data, and cold data increases sequentially. The step of using the first type of table and the second type of table to determine the popularity of the data corresponding to the logical address of the received read command includes: When the data group mapped by the logical address is in the first type of table, it is determined that the data corresponding to the logical address is hot data or warm data. When the data group mapped by the logical address is not in the first type of table but is in the second type of table, the data corresponding to the logical address is determined to be warm data or cold data. When the data group mapped by the logical address is not in the first type of table and not in the second type of table, the data corresponding to the logical address is determined to be cold data.

17. The method of operating a memory system according to claim 16, characterized in that, The first type of table includes two tables, and the second type of table also includes two tables. The step of using the first type of table and the second type of table to determine the popularity of the data corresponding to the logical address of the received read command includes: When the data mapped by the logical address is in the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data. When the data mapped by the logical address is not in the first type table of the previous first time interval, but is in the first type table of the current first time interval, the data corresponding to the logical address is determined to be hot data or warm data. When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, but is in the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data. When the data mapped by the logical address is not in the first type table of the current first time interval, the first type table of the previous first time interval, or the second type table of the previous second time interval, but is in the second type table of the current second time interval, the data corresponding to the logical address is determined to be warm data or cold data. When the data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

18. The method of operating the memory system according to claim 16, characterized in that, The first type of table includes two tables, and the second type of table also includes two tables. The step of using the first type of table and the second type of table to determine the popularity of the data corresponding to the logical address of the received read command includes: When the array data mapped by the logical address is in the first type table of the current first time interval or the first type table of the previous first time interval, the data corresponding to the logical address is determined to be hot data. When the array data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, but is in the second type table of the current second time interval or the second type table of the previous second time interval, the data corresponding to the logical address is determined to be warm data. When the array data mapped by the logical address is not in the first type table of the current first time interval and the first type table of the previous first time interval, and is not in the second type table of the current second time interval and the second type table of the previous second time interval, the data corresponding to the logical address is determined to be cold data.

19. The method of operating the memory system according to claim 16, characterized in that, The step of determining the level of drift corresponding to the logical address based on the heat of the data corresponding to the logical address includes: When the data corresponding to the logical address is the hot data, the drift amount corresponding to the logical address is determined to be the first-level drift amount; When the data corresponding to the logical address is the temperature data, the drift amount corresponding to the logical address is determined to be the second-level drift amount; When the data corresponding to the logical address is the cold data, the drift amount corresponding to the logical address is determined to be the third-level drift amount; Wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

20. The method of operating a memory system according to claim 16, characterized in that, The method further includes: When the data corresponding to the logical address is determined to be warm data using the first type of table and the second type of table, and a read failure occurs when reading the data of the storage unit corresponding to the logical address using the read voltage corresponding to the warm data, the data of the storage unit corresponding to the logical address is reread using the read voltage corresponding to the cold data.

21. The method of operating the memory system according to claim 14, characterized in that, The method further includes: Check whether the logical address corresponding to the received read command is stored in the write buffer; When the logical address is not stored in the write buffer, determine the level of the drift amount corresponding to the logical address; A read command is sent to the non-volatile memory device according to the level of drift corresponding to the logical address; wherein the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command are executed in parallel.

22. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed, can implement the method of operating the memory system as described in any one of claims 14-21.

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