Flow entry storage systems, devices, and clusters

Abstract

The present application provides a flow table storage system, device and cluster. The system includes a first random access memory for storing flow table items; a second random access memory for storing flow table items; a processor for copying the first flow table item in the first random access memory to obtain a copied first flow table item, and storing the copied first flow table item in the second random access memory; the processor is also used to distribute the traffic of the first service accessing the first flow table item to the first random access memory and the second random access memory according to the diversion strategy. The above scheme can effectively improve the reading efficiency of the table items.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a flow entry storage system, device, and cluster. Background Art

[0002] Flow table entries are usually stored in random access memory. When a large number of data packets need to be processed quickly in the network, being able to quickly and accurately read flow table entries to determine how the data packets are processed is the key to reducing network pressure. If the reading efficiency of flow table entries is low, it will cause delays and packet loss during the processing of data packets, affecting the real-time performance, throughput and overall performance of the network, and may even cause network congestion and performance bottlenecks. Summary of the invention

[0003] The present application provides a flow table entry storage system, device and cluster, which can effectively improve the reading efficiency of table entries.

[0004] In a first aspect, a flow entry storage system is provided, including:

[0005] A first random access memory, used to store flow table entries;

[0006] A second random access memory, used to store flow table entries;

[0007] a processor, configured to copy the first flow table entry in the first random access memory to obtain a copied first flow table entry, and store the copied first flow table entry in the second random access memory;

[0008] The processor is further configured to distribute the traffic of the first service accessing the first flow table entry to the first random access memory and the second random access memory according to the diversion strategy.

[0009] In some possible designs, the traffic diversion strategy includes one or more of a bit width of a random access memory and a number of flow table entries in the random access memory.

[0010] In some possible designs, the processor is further configured to use the ratio of the bit width of the second random access memory to the bit width of the first random access memory as the ratio of the traffic allocated to the first random access memory and the traffic allocated to the second random access memory.

[0011] In some possible designs, the processor is also used to use the ratio of the number of flow table entries in the second random access memory to the number of flow table entries in the first random access memory as the ratio of the traffic allocated to the first random access memory and the traffic of the second random access memory.

[0012] In some possible designs, the processor is also used to dynamically adjust the ratio of the flow of the first service accessing the first flow table item allocated to the first random access memory and the second random access memory according to the back pressure time of the second random access memory and the back pressure time of the first random access memory.

[0013] In some possible designs, the processor is further configured to reduce the flow allocated to the second random access memory when the back pressure time of the second random access memory is much greater than the back pressure time of the first random access memory.

[0014] In some possible designs, the processor is further used to, when the back pressure time of the second random access memory is much greater than the back pressure time of the first random access memory, reduce the traffic allocated to the second random access memory from the first traffic value by a specified amount in a first unit time to obtain a second traffic value, and reduce the traffic allocated to the second random access memory from the second traffic value by the specified amount in a second unit time to obtain a third traffic value, and so on, until the difference between the back pressure time of the second random access memory and the back pressure time of the first random access memory is less than a specified threshold.

[0015] In some possible designs, the processor is further used to access the first random access memory and the second random access memory in the following order: a first access request of the first service is allocated to the first random access memory, a second access request of the first service is allocated to the second random access memory, a third access request of the first service is allocated to the first random access memory, a fourth access request of the first service is allocated to the second random access memory, a fifth access request of the first service is allocated to the first random access memory, a sixth access request of the first service is allocated to the second random access memory, and a seventh access request of the first service is allocated to the first random access memory, when the ratio of the traffic allocated to the first random access memory to the traffic allocated to the second random access memory is 4:3.

[0016] In a second aspect, a computing device is provided, comprising a flow table entry storage system and a memory, wherein the memory is used to store instructions, the flow table entry storage system and the memory can communicate with each other, and the flow table entry storage system is a system as described in any one of the first aspects.

[0017] In a third aspect, a computing device cluster is provided, comprising a plurality of computing devices, wherein at least one computing device comprises a flow table entry storage system and a memory, wherein the memory is used to store instructions, the flow table entry storage system and the memory can communicate with each other, and the flow table entry storage system is a system as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0019] Figure 1 It is a schematic diagram of the structure of a memory provided by this application;

[0020] Figure 2 It is a schematic diagram of the structure of a random access memory provided by the present application;

[0021] Figure 3 It is a structural diagram of a flow table entry storage system provided by the present application;

[0022] Figure 4 It is a schematic diagram of a flow table entry storage method provided by this application;

[0023] Figure 5 It is a structural schematic diagram of a computing device provided by this application. DETAILED DESCRIPTION

[0024] The embodiments of the present invention are described below in conjunction with the accompanying drawings in the embodiments of the present invention. The terms used in the implementation mode of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0025] Memory is a key component in a computer system for storing and quickly accessing data. It helps improve the overall performance of a computer because it can be accessed much faster than a hard drive or other storage device. Memory transfers data via double data rate (DDR). DDR is a synchronous dynamic random access memory (SDRAM) technology, and there are mainly DDR1, DDR2, DDR3, DDR4 and DDR5 versions. The main feature of DDR is its high data transfer rate, which is achieved by transferring data on both the rising and falling edges of each clock cycle, thus achieving a double data transfer rate.

[0026] Memory is usually used to store various running software in the operating system, input and output data, and information exchanged with external memory. In order to improve the access speed of the processor, the memory needs to have the advantage of fast access speed. In the traditional computer system architecture, dynamic random access memory (DRAM) is usually used as memory. The processor can access the memory at high speed through the memory controller and perform read and write operations on any storage unit in the memory.

[0027] like Figure 1 As shown, the memory may include one or more Dual-Inline-Memory-Modules (DIMMs) 110 . Figure 1 In the figure, a memory including two DIMMs 110 is used as an example. Usually, a DIMM can be regarded as a memory bar entity. A memory bar has two sides. A high-end memory bar has memory chips on both sides. We call each side a Rank, which means that a memory bar has Rank 0 and Rank 1. Figure 1 As shown, a DIMM 110 may include one or more Ranks 111. Each Rank 111 may include a plurality of Random Access Memories (RAMs) 112.

[0028] Data is stored in the memory, and data is stored in the storage unit in the random access memory 112. A storage unit refers to the smallest storage unit (cell) for storing data. Usually, a storage unit can store 1 bit of data. Of course, some storage units can also implement multi-value storage. When the random access memory is DRAM, the storage units in the DRAM (also referred to as DRAM cells) are arranged and distributed into a matrix, which we call a memory bank or a DRAM memory bank. In this way, the storage units in a memory chip can be logically divided into multiple banks, and each bank can be regarded as a storage array composed of multiple storage units. Each memory cell (memory cell) in the memory bank is identified by its row address and column address, and the memory controller can locate any storage unit in the memory bank through the corresponding row and column decoders. The memory bank can also be referred to as a bank.

[0029] like Figure 2As shown, a random access memory including 8 memory banks is used as an example for illustration. The random access memory may include a control and refresh circuit, a plurality of memory banks (memory banks) 1121, a row address buffer, a column address buffer, a row decoder, and a column decoder. Among them, the control and refresh circuit is used to control the refresh operation of the memory cell. Random access memory (for example, DRAM) uses the amount of electricity stored in a capacitor to represent data 0 and 1, and is a volatile memory. Due to the leakage of the capacitor, the charge can only be maintained for a very short time. The leakage of the capacitor causes charge drift, which will cause errors in the stored data. Therefore, in order to store data, the control and refresh circuit needs to automatically perform a refresh operation to refresh and charge the memory cell storing the data to prevent the memory from losing data.

[0030] During the memory access process, after receiving a memory access request, the memory controller generates an address signal and a control signal according to the received memory access request, and sends the generated address signal and control signal to the DIMM to perform memory access. Among them, the address signal may include a row address signal and a column address signal, and the control signal may include a chip select signal (CS), a write enable signal (WE), a column access select signal (CAS), and a row access select signal (RAS). These signals can be received by the control and refresh circuit, the row address signal is cached in the row address buffer, the column address signal is cached in the column address buffer, and the control signal is passed to the storage bank corresponding to the row address specified by the address signal.

[0031] The row address buffer is used to cache the row address signal sent by the memory controller. The column address buffer is used to cache the column address signal sent by the memory controller. The row decoder is connected to the row address buffer and the plurality of memory banks 1121, respectively, and the column decoder is connected to the column address buffer and the plurality of memory banks, respectively. The row decoder is used to decode the row address signal, and the column decoder is used to decode the column address signal, so that the corresponding storage unit in the memory bank 1121 can be located according to the decoded row address signal and column address signal.

[0032] When the memory controller accesses DRAM, the memory controller needs to first identify the storage row corresponding to the data to be accessed and determine the memory bank to which the storage row to be accessed belongs. Then the memory controller will "open" the corresponding memory bank and storage row. In some implementations, the storage row may also be referred to as a "page". A "page" is a logical concept. In this case, a page includes the memory cells of a storage row in DRAM. Typically, the size of a memory page can include 512, 1024 (1K), 2048 (2K), 4098 (4K), 8196 (8K), 16392 (16K), or 32,768 (32K) bits of data.

[0033] Generally, when performing memory access, the storage row to be accessed may be in one of the following three states: row hit, row idle, or row conflict. Row hit means that the storage row to be accessed has been opened, that is, the data of the storage row to be accessed has been loaded into the row buffer corresponding to the storage bank storing the data of the row, and data can be read from the storage unit of the row or written to the storage unit of the row by directly sending a column access command. Among them, the column access command may include a read command or a write command. Row idle is used to indicate that the storage bank corresponding to the storage row to be accessed is in an idle state, no storage row is opened, and the storage row to be accessed needs to be opened by an "activate" command before access. That is, the data of the storage row to be accessed needs to be loaded into the row buffer corresponding to the storage bank by an "activate" command before a column access command can be sent for access. Row conflict is used to indicate that the currently opened storage row is different from the storage row to be accessed. In the case of rowconflict, the currently opened storage row needs to be "closed" first, specifically including using the "precharge" command to write the data of the opened storage row back to the memory array, and then using the activate command to load the data of the row to be accessed into the corresponding row cache, and then send the column access command to access it. In an embodiment of the present invention, the above three states of the storage row to be accessed can be referred to as the row hit state of the storage row. The "storage row" can also be referred to as a "row", and the storage row to be accessed can also be referred to as a target row.

[0034] From the above description, it can be seen that in the process of memory access, different states of the row to be accessed will cause different delays in access. In the state of row hit, since the row to be accessed is already in the open state, the memory controller can directly send a column access command. After sending the column access command, data can be read from the memory or written to the memory. In the case where the column access command is a read command, the read data can be obtained after a delay. In the case of row idle, since no row is opened in the memory bank, the row to be accessed needs to be opened by the "activate" command before access. Therefore, the memory controller needs to send a row activation command first, wait for the delay, and then send a column access command to access the open row. In the case where the column access command is a read command, it is necessary to wait for a delay before obtaining the read data. In the case of row conflict, since the currently open row is not the row to be accessed, you need to first send a pre-charge command to close the currently open row, wait for a delay, then send a row activation command to open the row to be accessed, and then wait for a delay before sending a column access command to access the row to be accessed. If the column access command is a read command, after sending the column access command, you need to wait for a delay to obtain the read data.

[0035] Therefore, the memory may include multiple storage banks, each storage bank includes one or more storage rows, and each storage row may be used to store one or more flow table entries.

[0036] like Figure 3 As shown, for the convenience of description, the flow table entry storage system including the processor 210, the first random access memory 220 and the second random access memory 230 will be taken as an example for description below.

[0037] The first random access memory is used to store flow table entries. The bit width of the first random access memory refers to the number of data bits that can be processed in one data transmission. For example, common DRAM bit widths include 32 bits, 64 bits, 128 bits, 256 bits, etc. The number of flow table entries in the first random access memory can be determined according to the capacity of the first random access memory. The number of flow table entries in the first random access memory can be single digits, tens digits, hundreds digits, thousands digits, tens of thousands digits, etc.

[0038] The second random access memory is used to store flow table entries. The bit width of the second random access memory refers to the number of data bits that can be processed in one data transmission. For example, common DRAM bit widths are 32 bits, 64 bits, 128 bits, 256 bits, etc. The number of flow table entries in the second random access memory can be determined according to the capacity of the second random access memory. The number of flow table entries in the second random access memory can be single digits, tens digits, hundreds digits, thousands digits, tens of thousands digits, etc.

[0039] Here, the bit width of the first random access memory and the bit width of the second random access memory may be the same or different, for example, the bit width of the first random access memory is 64 bits, and the bit width of the second random access memory is 64 bits; or, the bit width of the first random access memory is 64 bits, and the bit width of the second random access memory is 32 bits, etc. The number of flow table entries of the first random access memory and the number of flow table entries of the second random access memory may be the same or different.

[0040] like Figure 4 As shown, if the first random access memory stores the first flow table item and the second flow table item; the second random access memory stores the third flow table item. Assuming that the read performance of the flow table items of the first random access memory and the flow table items of the second random access memory are both 100 megabytes, when the access frequency of each flow table item is the same, the access frequency of the first random access memory is higher, and the relationship with the second random access memory is 2:1. Therefore, when reading the first flow table item and the second flow table item in the first random access memory, the average performance can only reach 50 megabytes, and the first random access memory will become the performance bottleneck of the system.

[0041] Therefore, the processor 210 may copy the first flow table entry in the first random access memory to obtain a copied first flow table entry, and store the copied first flow table entry in the second random access memory. The first flow table entry may be a frequently accessed flow table entry. The number of first flow table entries may be one or more. The second random access memory may be a random access memory with a relatively large capacity, a random access memory with a relatively small number of stored flow table entries, a random access memory with relatively good reading performance, and the like.

[0042] Then, the processor 210 distributes the traffic of the first service accessing the first flow table entry to the first random access memory and the second random access memory according to the diversion strategy, wherein the diversion strategy includes one or more of the bit width of the random access memory and the number of flow table entries in the random access memory.

[0043] When the number of flow table entries in the first random access memory and the number of flow table entries in the second random access memory are the same, the larger the ratio of the bit width of the second random access memory to the bit width of the first random access memory, the larger the ratio of the traffic of the first service allocated to the first random access memory for accessing the first flow table entry to the traffic of the first service allocated to the second random access memory for accessing the first flow table entry. On the contrary, the smaller the ratio of the bit width of the second random access memory to the bit width of the first random access memory, the smaller the ratio of the traffic of the first service allocated to the first random access memory for accessing the first flow table entry to the traffic of the first service allocated to the first random access memory for accessing the first flow table entry to the traffic of the first service allocated to the second random access memory for accessing the first flow table entry. In a specific embodiment, the ratio of the bit width of the second random access memory to the bit width of the first random access memory is used as the ratio of the traffic of the first service allocated to the first random access memory for accessing the first flow table entry to the traffic of the first service allocated to the second random access memory for accessing the first flow table entry. For example, the bit width of the first random access memory is 64 bits and the bit width of the second random access memory is 32 bits, then the ratio of the traffic of the first service accessing the first flow table entry allocated to the first random access memory and the traffic of the first service accessing the first flow table entry allocated to the second random access memory will be 2:1.

[0044] In the case where the bit width of the first random access memory and the bit width of the second random access memory are the same, the larger the ratio of the number of flow table entries in the second random access memory to the number of flow table entries in the first random access memory, the smaller the ratio of the traffic of the first service accessing the first flow table entry allocated to the first random access memory to the traffic of the first service accessing the first flow table entry of the second random access memory, and conversely, the smaller the ratio of the number of flow table entries in the second random access memory to the number of flow table entries in the first random access memory, the larger the ratio of the traffic of the first service accessing the first flow table entry allocated to the first random access memory to the traffic of the first service accessing the first flow table entry of the second random access memory. In a specific embodiment, the ratio of the number of flow table entries in the second random access memory to the number of flow table entries in the first random access memory is used as the ratio of the traffic of the first service accessing the first flow table entry allocated to the first random access memory to the traffic of the first service accessing the first flow table entry of the second random access memory. For example, the number of flow table entries in the first random access memory is 64, and the number of flow table entries in the second random access memory is 32. Then, the ratio of the traffic of the first service accessing the first flow table entry allocated to the first random access memory and the traffic of the first service accessing the first flow table entry allocated to the second random access memory will be 1:2.

[0045] Of course, the diversion strategy may also include the bit width of the random access memory and the number of flow table entries in the random access memory. For example, the bit width of the first random access memory is 64 bits, the bit width of the second random access memory is 32 bits, the number of flow table entries in the first random access memory is 64, and the number of flow table entries in the second random access memory is 32. Then, the ratio of the traffic of the first business accessing the first flow table entry allocated to the first random access memory to the traffic of the first business accessing the first flow table entry of the second random access memory will be 1:4.

[0046] It can be understood that the above-mentioned diversion strategies are all examples. In actual applications, the diversion strategy may also be other, which is not specifically limited here.

[0047] As the network environment changes, the previous diversion strategy may not be suitable for the actual situation of the first random access memory and the second random access memory. Therefore, it is necessary to adjust the ratio of the traffic of the first business accessing the first flow table item of the first random access memory and the traffic of the first business accessing the first flow table item of the second random access memory. In a specific embodiment, the processor can dynamically adjust the ratio of the traffic of the first business accessing the first flow table item allocated to the first random access memory and the second random access memory according to the back pressure time of the second random access memory and the back pressure time of the first random access memory. Among them, the back pressure time is when the memory (such as DRAM) is under high pressure and not working smoothly due to some reason (such as a large amount of data reading and writing causing the memory to be busy, delays in reading data, etc.), the period of time from the beginning of the memory showing this high pressure to the pressure gradually easing and returning to normal.

[0048] Specifically, when the back pressure time of the second random access memory is much greater than the back pressure time of the first random access memory, the processor reduces the flow allocated to the second random access memory. The back pressure time of the second random access memory being much greater than the back pressure time of the first random access memory can be set by the user as needed. For example, when the back pressure time of the second random access memory and the back pressure time of the first random access memory are not of the same order of magnitude, it is considered that the back pressure time of the second random access memory is much greater than the back pressure time of the first random access memory. For another example, when the back pressure time of the second random access memory minus the back pressure time of the first random access memory is greater than the back pressure threshold, it is considered that the back pressure time of the second random access memory is much greater than the back pressure time of the first random access memory. The back pressure threshold can be set according to the user's experience.

[0049] The method of reducing the flow allocated to the second random access memory may include: reducing the flow allocated to the second random access memory from the first flow value by a specified amount in the first unit time to obtain a second flow value, reducing the flow allocated to the second random access memory from the second flow value by a specified amount in the second unit time to obtain a third flow value, and so on, until the difference between the back pressure time of the second random access memory and the back pressure time of the first random access memory is less than the specified threshold. The first unit time may be a time period set by the user, for example, it may be several milliseconds, tens of milliseconds, hundreds of milliseconds, several seconds, tens of seconds, etc. The length of the second unit time may be the same as the length of the first unit time, or it may be different, which is not specifically limited here. The specified amount may be set by the user. When the user needs to reduce the back pressure time of the second random access memory, the specified amount may be set to be relatively large. When the user needs to ensure a more stable network and avoid large fluctuations in the network, the specified amount may be set to be relatively small. The specified threshold may be set by the user based on experience, for example, it may be several milliseconds, tens of milliseconds, hundreds of milliseconds, several seconds, tens of seconds, etc. Of course, the above-mentioned method of reducing the flow allocated to the second random access memory is only a specific example. In practical applications, in addition to reducing the flow allocated to the second random access memory multiple times, the flow of the second random access memory can also be directly reduced once, etc. For example, the ratio of the flow of the first service allocated to the first random access memory to access the first flow table item and the flow of the first service allocated to the second random access memory to access the first flow table item is 3:1, which is 75 / 25 in percentage. When the back pressure time of the second random access memory is significantly longer than the back pressure time of the first random access memory, the diversion ratio of the second random access memory is reduced by 5 percentages. If the back pressure time of the second random access memory is longer, the back pressure ratio is adjusted to 70:25; if the back pressure time of the first random access memory is longer, the back pressure ratio is adjusted to 70:20. This adjustment is performed in each unit time until the back pressure time of each random access memory is at the same order of magnitude. Since the processing performance fluctuation range of random access memory is limited, this adjustment method is safe as long as the configuration base is accurate and large enough.

[0050] In order to make the random access memory more stable, the ratio of the traffic of the first business of the first random access memory accessing the first flow table item to the traffic of the first business of the second random access memory accessing the first flow table item can be set as the weight of the first random access memory and the second random access memory. During scheduling, the first random access memory and the second random access memory are scheduled in turn until the weight of one of the random access memories is zero, and then the other random access memory is scheduled intensively until the weight of the last random access memory is zero, and then the ratio of the traffic of the first business of the first random access memory accessing the first flow table item to the traffic of the first business of the second random access memory accessing the first flow table item is re-read for scheduling. For example, when the ratio of the traffic allocated to the first random access memory and the traffic allocated to the second random access memory is 4:3, the first random access memory and the second random access memory are accessed in the order of a first access request of the first service being allocated to the first random access memory, a second access request of the first service being allocated to the second random access memory, a third access request of the first service being allocated to the first random access memory, a fourth access request of the first service being allocated to the second random access memory, a fifth access request of the first service being allocated to the first random access memory, a sixth access request of the first service being allocated to the second random access memory, and a seventh access request of the first service being allocated to the first random access memory. For another example, when the ratio of the traffic allocated to the first random access memory, the traffic of the second random access memory, and the traffic of the third random access memory is 4:3:2, the first access request of the first service is allocated to the first random access memory, the second access request of the first service is allocated to the second random access memory, the third access request of the first service is allocated to the third random access memory, the fourth access request of the first service is allocated to the first random access memory, the fifth access request of the first service is allocated to the second random access memory, the sixth access request of the first service is allocated to the third random access memory, the seventh access request of the first service is allocated to the first random access memory, the eighth access request of the first service is allocated to the second random access memory, and the ninth access request of the first service is allocated to the first random access memory.

[0051] It can be understood that the above cases are only specific examples. In actual applications, there may be other implementation methods, which are not specifically limited here.

[0052] See also Figure 5 , Figure 5 4 is a schematic diagram of a computing device provided by the present application. The computing device 400 includes: one or more processing units 410 , a communication interface 420 and a memory 430 .

[0053] The processing unit 410, the communication interface 420 and the memory 430 are interconnected via a bus 440. Optionally, the computing device 400 may also include an input / output interface 450, which is connected to an input / output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement part or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processing unit 410 can also be used to implement part or all of the operation steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 400 can refer to the specific details in the above-mentioned embodiment, such as the processing unit 410 is used to perform part or all of the steps in the above-mentioned method embodiment or part or all of the operations in the above-mentioned method embodiment. For another example, in the embodiment of the present application, the computing device 400 can be used to implement part or all of the functions of one or more components in the above-mentioned device embodiment, and the communication interface 420 can be specifically used for the communication functions necessary to implement the functions of these devices and components, and the processing unit 410 can be specifically used for the processing functions necessary to implement the functions of these devices and components, etc.

[0054] Figure 5 The computing device 400 may include one or more processing units 410, and the multiple processing units 410 may provide processing capabilities in a coordinated manner in a parallel connection manner, a serial connection manner, a serial-parallel connection manner, or any connection manner, or the multiple processing units 410 may constitute a processor sequence or a processor array, or the multiple processing units 410 may be divided into a main processor and an auxiliary processor, or the multiple processing units 410 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 5 The computing device 400 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include Figure 5 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0055] The processing unit 410 may have a variety of specific implementation forms. For example, the processing unit 410 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processing unit 410 may also be a single-core processor or a multi-core processor. The processing unit 410 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processing unit 410 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 420 may be a wired interface or a wireless interface for communicating with other modules or devices, the wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., the wireless interface may be a cellular network interface or a wireless local area network interface, etc. The processing unit 410 may also be equipped with one or more random access memories, and the one or more random access memories are used to store flow table entries.

[0056] The memory 430 may be a non-volatile memory, such as a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 430 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). The memory 430 may also be used to store program codes and data, so that the processing unit 410 calls the program codes stored in the memory 430 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 5 Show more or fewer components, or have different component configurations.

[0057] The bus 440 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 440 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 440 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0058] The present application also provides a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0059] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one network site, computer, server or data center to another network site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or it can be a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape, etc.), an optical medium (e.g., a DVD, etc.), or a semiconductor medium (e.g., a solid-state hard disk), etc. In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Claims

1. A flow entry storage system, characterized in that: include: A first random access memory, used to store flow table entries; A second random access memory, used to store flow table entries; a processor, configured to copy the first flow table entry in the first random access memory to obtain a copied first flow table entry, and store the copied first flow table entry in the second random access memory; The processor is further configured to distribute traffic of the first service accessing the first flow table entry to the first random access memory and the second random access memory according to a diversion strategy, wherein the diversion strategy includes one or more of a bit width of the random access memory and a number of flow table entries in the random access memory; When the number of flow table entries in the first random access memory and the number of flow table entries in the second random access memory are the same, the larger the ratio of the bit width of the second random access memory to the bit width of the first random access memory, the larger the ratio of the traffic of the first service for accessing the first flow table entry allocated to the first random access memory to the traffic of the first service for accessing the first flow table entry of the second random access memory; when the bit width of the first random access memory and the bit width of the second random access memory are the same, the larger the ratio of the number of flow table entries in the second random access memory to the number of flow table entries in the first random access memory, the smaller the ratio of the traffic of the first service for accessing the first flow table entry allocated to the first random access memory to the traffic of the first service for accessing the first flow table entry of the second random access memory.

2. The system according to claim 1, characterized in that The processor is further configured to use the ratio of the bit width of the second random access memory to the bit width of the first random access memory as the ratio of the flow allocated to the first random access memory and the flow of the second random access memory.

3. The system according to claim 1, characterized in that The processor is further configured to use the ratio of the number of flow table entries in the second random access memory to the number of flow table entries in the first random access memory as the ratio of the flow allocated to the first random access memory and the flow allocated to the second random access memory.

4. The system according to any one of claims 1 to 3, characterized in that: The processor is also used to dynamically adjust the ratio of the flow of the first service accessing the first flow table item allocated to the first random access memory and the second random access memory according to the back pressure time of the second random access memory and the back pressure time of the first random access memory.

5. The system according to claim 4, characterized in that The processor is further configured to reduce the flow allocated to the second random access memory when the back pressure time of the second random access memory is much greater than the back pressure time of the first random access memory.

6. The system according to claim 5, characterized in that The processor is further configured to, when the back pressure time of the second random access memory is much greater than the back pressure time of the first random access memory, reduce the flow allocated to the second random access memory from the first flow value by a specified amount in a first unit time to obtain a second flow value, and reduce the flow allocated to the second random access memory from the second flow value by the specified amount in a second unit time to obtain a third flow value, and so on, until the difference between the back pressure time of the second random access memory and the back pressure time of the first random access memory is less than a specified threshold.

7. The system according to any one of claims 1 to 3, characterized in that: The processor is further configured to access the first random access memory and the second random access memory in the following order: a first access request of the first service is allocated to the first random access memory, a second access request of the first service is allocated to the second random access memory, a third access request of the first service is allocated to the first random access memory, a fourth access request of the first service is allocated to the second random access memory, a fifth access request of the first service is allocated to the first random access memory, a sixth access request of the first service is allocated to the second random access memory, and a seventh access request of the first service is allocated to the first random access memory, when the ratio of the traffic allocated to the first random access memory to the traffic allocated to the second random access memory is 4:

3.

8. A computing device, characterized in that It comprises a flow entry storage system and a memory, wherein the memory is used to store instructions, the flow entry storage system and the memory can communicate with each other, and the flow entry storage system is a system as described in any one of claims 1-7.

9. A computing device cluster, characterized in that: It includes multiple computing devices, at least one computing device includes a flow table entry storage system and a memory, the memory is used to store instructions, the flow table entry storage system and the memory can communicate with each other, and the flow table entry storage system is a system as described in any one of claims 1-7.

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