A communication management method for multi-acceleration card computing power test

Abstract

The present invention provides a multi-accelerator card computing power test communication management method, comprising the following steps: building a multi-accelerator card computing power test system architecture; the CPU creates and stores a first DMA transfer flag bit array; the PCI-E controller creates and stores a second DMA transfer flag bit array; the CPU and the PCI-E controller use a preemption mechanism to communicate with the idle upstream PCI-E link in the PCI-E bus. Aiming at the communication efficiency problem caused by the simultaneous operation of multiple accelerator cards, the present invention proposes a multi-accelerator card computing power test communication management method, which effectively improves the DMA communication efficiency between the CPU and the PCI-E accelerator card device, thereby improving the computing power test efficiency, and further ensuring the computing power test accuracy.

Description

Technical Field

[0001] The present invention belongs to the technical field of computing power testing, and in particular relates to a communication management method for computing power testing of multiple accelerator cards. Background Art

[0002] With the rapid development of science and technology, deep learning has become a popular technology in the field of artificial intelligence. Deep learning is a branch of machine learning. Its basic principle is to simulate the learning method of the human brain by establishing a multi-layer neural network. Deep learning can automatically extract useful features from a large amount of data to solve complex classification and recognition problems.

[0003] In deep learning, PCIx1, as an important hardware device, provides powerful computing power for deep learning. PCIx1 is an accelerator card based on the PCIe (Peripheral Component Interconnect Express) bus, which provides powerful computing power for deep learning and can greatly improve the training speed of deep learning.

[0004] Testing the computing power of PCIe accelerator cards is the basis for using PCIe accelerator cards for deep learning. In the prior art, when testing the computing power of multiple PCIe accelerator cards, PCI bus congestion often occurs, thereby reducing the computing power test efficiency. Summary of the invention

[0005] In view of the defects of the prior art, the present invention provides a multi-acceleration card computing power test communication management method, which can effectively solve the above problems.

[0006] The technical solution adopted by the present invention is as follows:

[0007] The present invention provides a multi-acceleration card computing power test communication management method, comprising the following steps:

[0008] Step S1, building a multi-accelerator card computing power test system architecture; the multi-accelerator card computing power test system architecture includes a CPU, an upstream PCI-E link, a PCI-E controller, a downstream PCI-E link and a PCI-E accelerator card device; wherein, the number of the upstream PCI-E links is N, the number of the downstream PCI-E links is M, and the N upstream PCI-E links form a PCI-E bus; the CPU is connected to the upstream side of the PCI-E controller through the PCI-E bus; the downstream side of the PCI-E controller is connected to the M downstream PCI-E links, and the M downstream PCI-E links are divided into multiple groups, each group is connected to one PCI-E accelerator card device, and therefore, there are a total of Q PCI-E accelerator card devices; the number of cores of each PCI-E accelerator card device is R; wherein, M>N;

[0009] Step S2, initializing Q PCI-E accelerator card devices, and the CPU loading the accelerator card operator library; the accelerator card operator library obtains the number of PCI-E accelerator card devices and the device ID of each PCI-E accelerator card device, and sends them to the CPU;

[0010] Step S3, the CPU creates and stores a first DMA transfer flag array, which is used to store the transfer flag of each PCI-E accelerator card device. The transfer flag of each PCI-E accelerator card device has two states, 0 and 1, where 0 represents an idle state and 1 represents an occupied state.

[0011] The PCI-E controller creates and stores a second DMA transfer flag array for storing the transfer flag of each PCI-E accelerator card device. The transfer flag of each PCI-E accelerator card device has two states, 0 and 1, where 0 represents an idle state and 1 represents an occupied state.

[0012] The first DMA transfer flag bit array and the second DMA transfer flag bit array adopt a mutual exclusion lock synchronization mechanism;

[0013] Step S4, the CPU calculates the maximum number card_num of PCI-E acceleration card devices allowed by the full bandwidth of the PCI-E bus according to the number N of upstream PCI-E links and the number M of downstream PCI-E links;

[0014] Step S5, the CPU determines whether there is an idle upstream PCI-E link in the PCI-E bus by analyzing the first DMA transfer flag bit array, and if so, calls the daemon process to obtain the identifier of the idle upstream PCI-E link; if not, continues to monitor and analyze the first DMA transfer flag bit array; the PCI-E controller determines whether there is an idle upstream PCI-E link in the PCI-E bus by analyzing the second DMA transfer flag bit array, and if so, calls the daemon process to obtain the identifier of the idle upstream PCI-E link; if not, continues to monitor and analyze the second DMA transfer flag bit array;

[0015] The CPU and the PCI-E controller adopt a preemption mechanism for the idle upstream PCI-E link in the PCI-E bus. When the idle upstream PCI-E link is preempted by the CPU, step S5.1 is executed; when the idle upstream PCI-E link is preempted by the PCI-E controller, step S5.2 is executed;

[0016] Step S5.1, when the idle upstream PCI-E link is preempted by the CPU, the CPU updates the first DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device to be tested to 1, and synchronizes the updated first DMA transfer flag array to the second DMA transfer flag array;

[0017] Then, the CPU reads the test data in the test set, and sends the test data to the PCI-E controller through the seized upstream PCI-E link, the process bound to the PCI-E accelerator card device to be tested, and multiple threads under the process;

[0018] When the PCI-E controller receives test data from a process and an upstream PCI-E link, on the one hand, the PCI-E controller updates the second DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device bound to the process received this time to 0, and synchronizes the updated second DMA transfer flag array to the first DMA transfer flag array; on the other hand, the PCI-E controller sends the received test data to the corresponding PCI-E accelerator card device, so that the PCI-E accelerator card device performs computing power calculations on the test data to obtain computing power result data, and then the PCI-E accelerator card device immediately sends the computing power result data to the PCI-E controller through the corresponding downstream PCI-E link;

[0019] Step S5.2, when the idle upstream PCI-E link is preempted by the PCI-E controller, the PCI-E controller updates the second DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device corresponding to the computing result data to be transferred this time to 1, and synchronizes the updated second DMA transfer flag array to the first DMA transfer flag array;

[0020] Then, the PCI-E controller sends the computing power result data to the CPU through the seized upstream PCI-E link and the process bound to the PCI-E accelerator card device;

[0021] When the CPU receives computing power result data from a PCI-E accelerator card device, on the one hand, the CPU updates the first DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device bound to the process received this time to 0, and synchronizes the updated first DMA transfer flag array to the second DMA transfer flag array; on the other hand, the CPU records the time when the computing power result data is received;

[0022] Step S6, when the test is finished, the CPU obtains the computing power of each PCI-E accelerator card device and the combined computing power of all PCI-E accelerator card devices through statistics.

[0023] Preferably, in step S5, the CPU determines whether there is an idle upstream PCI-E link in the PCI-E bus by analyzing the first DMA transfer flag bit array, specifically:

[0024] The CPU reads the number N1 of transmission flag bits in the occupied state in the first DMA transmission flag bit array, and determines whether the number N1 reaches the maximum number card_num. If reached, it indicates that there is no idle upstream PCI-E link in the PCI-E bus, and the PCI-E bus is fully loaded; if not reached, it indicates that there is an idle upstream PCI-E link in the PCI-E bus.

[0025] Preferably, the CPU calls the detection function GetSet() to obtain the number N1 of transmission flag bits in the first DMA transmission flag bit array that are in an occupied state.

[0026] Preferably, step S5, calling the daemon process to obtain the identifier of the upstream PCI-E link in the idle state, is specifically:

[0027] Start a daemon process, monitor the status of each upstream PCI-E link of the PCI-E bus, and obtain the identifier of the upstream PCI-E link in the idle state.

[0028] Preferably, the PCI-E accelerator card device performs computing power calculation on the test data to obtain computing power result data, specifically:

[0029] The test data is a feature map, and its spatial size is H*W, where H and W are the length and width of the feature map respectively; the calculation speed FLOPS of the accelerator card is calculated using the following formula:

[0030]

[0031] Where: the accelerator card uses convolution operation to perform computing power test, K is the size of the convolution unit used by the accelerator card; C in and C out are the number of input channels and output channels of the convolution unit respectively; T s and T d They are the start processing time and processing completion time of the accelerator card.

[0032] The multi-acceleration card computing power test communication management method provided by the present invention has the following advantages:

[0033] In view of the communication efficiency problem caused by the simultaneous operation of multiple accelerator cards, the present invention proposes a multi-accelerator card computing power test communication management method, which effectively improves the DMA communication efficiency between the CPU and the PCI-E accelerator card device, thereby improving the computing power test efficiency and further ensuring the computing power test accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 An architectural diagram of a multi-acceleration card computing power test communication management method provided by the present invention. DETAILED DESCRIPTION

[0035] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0036] In view of the communication efficiency problem caused by the simultaneous operation of multiple accelerator cards, the present invention proposes a multi-accelerator card computing power test communication management method, which effectively improves the DMA communication efficiency between the CPU and the PCI-E accelerator card device, thereby improving the computing power test efficiency and further ensuring the computing power test accuracy.

[0037] See also Figure 1 The present invention provides a multi-acceleration card computing power test communication management method, comprising the following steps:

[0038] Step S1, building a multi-accelerator card computing power test system architecture; the multi-accelerator card computing power test system architecture includes a CPU, an upstream PCI-E link, a PCI-E controller, a downstream PCI-E link and a PCI-E accelerator card device; wherein, the number of the upstream PCI-E links is N, the number of the downstream PCI-E links is M, and the N upstream PCI-E links form a PCI-E bus; the CPU is connected to the upstream side of the PCI-E controller through the PCI-E bus; the downstream side of the PCI-E controller is connected to the M downstream PCI-E links, and the M downstream PCI-E links are divided into multiple groups, each group is connected to one PCI-E accelerator card device, and therefore, there are a total of Q PCI-E accelerator card devices; the number of cores of each PCI-E accelerator card device is R; wherein, M>N;

[0039] For example, assuming that the upstream PCI-E links are 2 16×PCIe 3.0, there are 32 upstream PCI-E links; assuming that the downstream PCI-E links are 10 8×PCIe 3.0, there are 80 downstream PCI-E links, and each 8 downstream PCI-E links form a group, corresponding to one PCIE slot, connected to one PCI-E acceleration card device, so a total of 10 PCI-E acceleration card devices are connected.

[0040] In this example, the upstream and downstream bandwidth ratio is 32:80. When the number of PCI-E accelerator card devices that need to be tested simultaneously is greater than 4, the upstream PCI-E link cannot transmit the test data of 4 PCI-E accelerator card devices at the same time. Therefore, communication congestion will occur in the upstream PCI-E link, which will affect the actual performance evaluation effect of the multi-accelerator card computing power test and reduce the computing power test efficiency.

[0041] In view of this situation, in order to solve the problem of communication efficiency between the CPU and multiple PCI-E acceleration card devices, the present invention proposes a DMA communication management method, which can effectively solve the problem of decreased communication efficiency caused by the lack of communication scheduling and coordination between the CPU and multiple PCI-E acceleration card devices in a multi-PCI-E acceleration card device environment.

[0042] Specifically, the Direct Message Access (DMA) communication method is adopted between the CPU and the PCI-E accelerator card device. The inventors have studied and tested the DMA communication mechanism between the CPU and the PCI-E accelerator card device, proposed a multi-accelerator card computing power test communication management method, and carried out performance verification. The verification results show that this method can effectively improve the DMA communication efficiency, thereby improving the computing power test efficiency, and then ensuring the accuracy of the computing power test.

[0043] Step S2, initializing Q PCI-E accelerator card devices, and the CPU loading the accelerator card operator library; the accelerator card operator library obtains the number of PCI-E accelerator card devices and the device ID of each PCI-E accelerator card device, and sends them to the CPU;

[0044] Step S3, the CPU creates and stores a first DMA transfer flag array, which is used to store the transfer flag of each PCI-E accelerator card device. The transfer flag of each PCI-E accelerator card device has two states, 0 and 1, where 0 represents an idle state and 1 represents an occupied state.

[0045] The PCI-E controller creates and stores a second DMA transfer flag array for storing the transfer flag of each PCI-E accelerator card device. The transfer flag of each PCI-E accelerator card device has two states, 0 and 1, where 0 represents an idle state and 1 represents an occupied state.

[0046] The first DMA transfer flag bit array and the second DMA transfer flag bit array adopt a mutual exclusion lock synchronization mechanism;

[0047] For example, when there are 10 PCI-E accelerator card devices connected in total, the first DMA transfer flag array is used to store the transfer flag of each PCI-E accelerator card device. Assuming that the CPU needs to transmit the test data of a PCI-E accelerator card device to the PCI-E controller through the upstream PCI-E link, the transfer flag of the PCI-E accelerator card device is first set to 1, indicating that 4 upstream PCI-E links are required to transmit the test data; when the test data is transmitted to the PCI-E controller, the transfer flag of the PCI-E accelerator card device is set to 0, indicating that the occupation of the 4 upstream PCI-E links is released.

[0048] Similarly, when the PCI-E controller needs to transmit the computing power result data of a PCI-E acceleration card device to the CPU, the transmission flag bit of the PCI-E acceleration card device is first set to 1, indicating that 4 upstream PCI-E links need to be occupied to transmit the computing power result data; when the computing power result data is transmitted to the CPU, the transmission flag bit of the PCI-E acceleration card device is set to 0, indicating that the occupation of these 4 upstream PCI-E links is released.

[0049] Therefore, by counting the number of transfer flag bits with a value of 1 in the DMA transfer flag bit array, the load condition of the upstream PCI-E link can be obtained.

[0050] In the present invention, since each PCI-E acceleration card device needs to occupy 4 upstream PCI-E links during data transmission, by recording the transmission flag data of the PCI-E acceleration card device, it is possible to determine whether the upstream PCI-E link is fully loaded, without the need to record and store in real time whether each upstream PCI-E link is idle, thereby reducing the occupancy of storage space and reducing communication overhead.

[0051] In the present invention, the CPU and the PCI-E controller each maintain a DMA transfer flag bit array, and the two DMA transfer flag bit arrays adopt a mutual exclusion lock synchronization mechanism to ensure the complete synchronization of the two DMA transfer flag bit arrays, so that the CPU and the PCI-E controller can simply and accurately obtain the number of occupied transfer flag bits in the DMA transfer flag bit array, thereby counting whether the upstream PCI-E link is fully loaded, which has the advantage of a simple implementation method.

[0052] Step S4, the CPU calculates the maximum number card_num of PCI-E acceleration card devices allowed by the full bandwidth of the PCI-E bus according to the number N of upstream PCI-E links and the number M of downstream PCI-E links;

[0053] In this example, the maximum number of card_num is 4.

[0054] Step S5, the CPU analyzes the first DMA transfer flag array to determine whether there is an idle upstream PCI-E link in the PCI-E bus. The specific method is: the CPU reads the number N1 of the transfer flags in the first DMA transfer flag array that are in the occupied state, and determines whether the number N1 reaches the maximum number card_num. If it reaches, it indicates that there is no idle upstream PCI-E link in the PCI-E bus, and the PCI-E bus is fully loaded; if it does not reach, it indicates that there is an idle upstream PCI-E link in the PCI-E bus. In this step, when it is specifically implemented, the CPU calls the detection function GetSet() to obtain the number N1 of the transfer flags in the first DMA transfer flag array that are in the occupied state.

[0055] If it exists, the daemon process is called to obtain the identifier of the upstream PCI-E link in the idle state; specifically, the daemon process is started to monitor the state of each upstream PCI-E link of the PCI-E bus to obtain the identifier of the upstream PCI-E link in the idle state.

[0056] If not, continue to monitor and analyze the first DMA transfer flag array; the PCI-E controller determines whether there is an idle upstream PCI-E link in the PCI-E bus by analyzing the second DMA transfer flag array, and if so, start the daemon process to monitor the status of each upstream PCI-E link of the PCI-E bus to obtain the identifier of the idle upstream PCI-E link; if not, continue to monitor and analyze the second DMA transfer flag array;

[0057] The CPU and the PCI-E controller adopt a preemption mechanism for the idle upstream PCI-E link in the PCI-E bus. When the idle upstream PCI-E link is preempted by the CPU, step S5.1 is executed; when the idle upstream PCI-E link is preempted by the PCI-E controller, step S5.2 is executed;

[0058] Therefore, in the present invention, it is not necessary to set up a monitoring process to monitor in real time whether each upstream PCI-E link is occupied. Instead, it is first determined whether there is an upstream PCI-E link in an idle state through the DMA transmission flag array. Only when it is found that there is an upstream PCI-E link in an idle state, a daemon process is started to obtain the identifier of the upstream PCI-E link in an idle state, and the upstream PCI-E link in the idle state is used to transmit data. Once the daemon process is finished with this detection, the daemon process enters a dormant state.

[0059] Therefore, the method of the present invention can significantly reduce the complexity of the system and reduce communication overhead.

[0060] Step S5.1, when the idle upstream PCI-E link is preempted by the CPU, the CPU updates the first DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device to be tested to 1, and synchronizes the updated first DMA transfer flag array to the second DMA transfer flag array;

[0061] Then, the CPU reads the test data in the test set, and sends the test data to the PCI-E controller through the seized upstream PCI-E link, the process bound to the PCI-E accelerator card device to be tested, and multiple threads under the process;

[0062] When the PCI-E controller receives test data from a process and an upstream PCI-E link, on the one hand, the PCI-E controller updates the second DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device bound to the process received this time to 0, and synchronizes the updated second DMA transfer flag array to the first DMA transfer flag array; on the other hand, the PCI-E controller sends the received test data to the corresponding PCI-E accelerator card device, so that the PCI-E accelerator card device performs computing power calculations on the test data to obtain computing power result data, and then the PCI-E accelerator card device immediately sends the computing power result data to the PCI-E controller through the corresponding downstream PCI-E link;

[0063] In this step, the PCI-E accelerator card device performs computing power calculations on the test data to obtain computing power result data, specifically:

[0064] The test data is a feature map, and its spatial size is H*W, where H and W are the length and width of the feature map respectively; the calculation speed FLOPS of the accelerator card is calculated using the following formula:

[0065]

[0066] Where: the accelerator card uses convolution operation to perform computing power test, K is the size of the convolution unit used by the accelerator card; C in and C out are the number of input channels and output channels of the convolution unit respectively; T s and T d They are the start processing time and processing completion time of the accelerator card.

[0067] Step S5.2, when the idle upstream PCI-E link is preempted by the PCI-E controller, the PCI-E controller updates the second DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device corresponding to the computing result data to be transferred this time to 1, and synchronizes the updated second DMA transfer flag array to the first DMA transfer flag array;

[0068] Then, the PCI-E controller sends the computing power result data to the CPU through the upstream PCI-E link that it has seized and the process bound to the PCI-E accelerator card device;

[0069] When the CPU receives computing power result data from a PCI-E accelerator card device, on the one hand, the CPU updates the first DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device bound to the process received this time to 0, and synchronizes the updated first DMA transfer flag array to the second DMA transfer flag array; on the other hand, the CPU records the time when the computing power result data is received;

[0070] Step S6, when the test is finished, the CPU obtains the computing power of each PCI-E accelerator card device and the combined computing power of all PCI-E accelerator card devices through statistics.

[0071] The present invention provides a multi-acceleration card computing power test communication management method, which has the following characteristics:

[0072] (1) In the present invention, for a multi-accelerator card computing power test scenario, the PCI-E accelerator card device has two states: computing mode and communication mode. The computing mode and communication mode are intermittent, that is, when the test data or computing power result data of a certain PCI-E accelerator card device is transmitted through the upstream PCI-E link, the PCI-E accelerator card device is in communication mode, and occupies the upstream PCI-E link at this time; and as soon as the upstream PCI-E link data transmission is completed, the occupancy of the upstream PCI-E link is immediately released, so that the upstream PCI-E link can transmit the test data or computing power result data of other PCI-E accelerator card devices, thereby improving communication efficiency.

[0073] For example, when the CPU transmits the test data of a PCI-E accelerator card device through the upstream PCI-E link, the PCI-E accelerator card device is in communication mode; and when the test data transmission reaches the PCI-E accelerator card device, the PCI-E accelerator card device enters the calculation mode, but at this time, the PCI-E accelerator card device has released the state of the upstream PCI-E link. In other words, the PCI-E accelerator card device is intermittently in the calculation mode and the communication mode. When it is in the calculation mode, it releases the occupation of the upstream PCI-E link; only when it is in the communication mode will it occupy the upstream PCI-E link, thereby maximizing the utilization rate of the upstream PCI-E link and improving communication efficiency.

[0074] (2) In the present invention, a DMA transfer flag array is used to indicate whether each PCI-E accelerator card device occupies the upstream PCI-E link, and the CPU and the PCI-E controller each create a DMA transfer flag array. The two DMA transfer flag arrays use a mutex lock synchronization mechanism, so that the CPU and the PCI-E controller can simply and efficiently determine whether the upstream PCI-E link is in a fully loaded state without the need to monitor each upstream PCI-E link in real time, thereby simplifying the complexity of system configuration and improving communication efficiency.

[0075] Therefore, the present invention provides a multi-acceleration card computing power test communication management method for managing computing power test communication between multiple acceleration cards and a CPU on a PCIe bus, including an optimization method for data transmission and a sequence or rule for command interaction. This algorithm is used for resource scheduling and allocation of resources of multiple acceleration cards on a PCIe bus, which can maximize overall performance testing and efficiency.

[0076] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be considered as the scope of protection of the present invention.

Claims

1. A multi-accelerator card computing power test communication management method, characterized in that: The following steps are involved: Step S1, building a multi-accelerator card computing power test system architecture; the multi-accelerator card computing power test system architecture includes a CPU, an upstream PCI-E link, a PCI-E controller, a downstream PCI-E link and a PCI-E accelerator card device; wherein, the number of the upstream PCI-E links is N, the number of the downstream PCI-E links is M, and the N upstream PCI-E links form a PCI-E bus; the CPU is connected to the upstream side of the PCI-E controller through the PCI-E bus; the downstream side of the PCI-E controller is connected to the M downstream PCI-E links, and the M downstream PCI-E links are divided into multiple groups, each group is connected to one PCI-E accelerator card device, and therefore, there are a total of Q PCI-E accelerator card devices; the number of cores of each PCI-E accelerator card device is R; wherein, M>N; Step S2, initializing Q PCI-E accelerator card devices, and the CPU loading the accelerator card operator library; the accelerator card operator library obtains the number of PCI-E accelerator card devices and the device ID of each PCI-E accelerator card device, and sends them to the CPU; Step S3, the CPU creates and stores a first DMA transfer flag array, which is used to store the transfer flag of each PCI-E accelerator card device. The transfer flag of each PCI-E accelerator card device has two states, 0 and 1, where 0 represents an idle state and 1 represents an occupied state. The PCI-E controller creates and stores a second DMA transfer flag array for storing the transfer flag of each PCI-E accelerator card device. The transfer flag of each PCI-E accelerator card device has two states, 0 and 1, where 0 represents an idle state and 1 represents an occupied state. The first DMA transfer flag bit array and the second DMA transfer flag bit array adopt a mutual exclusion lock synchronization mechanism; Step S4, the CPU calculates the maximum number card_num of PCI-E acceleration card devices allowed by the full bandwidth of the PCI-E bus according to the number N of upstream PCI-E links and the number M of downstream PCI-E links; Step S5, the CPU determines whether there is an idle upstream PCI-E link in the PCI-E bus by analyzing the first DMA transfer flag bit array, and if so, calls the daemon process to obtain the identifier of the idle upstream PCI-E link; if not, continues to monitor and analyze the first DMA transfer flag bit array; the PCI-E controller determines whether there is an idle upstream PCI-E link in the PCI-E bus by analyzing the second DMA transfer flag bit array, and if so, calls the daemon process to obtain the identifier of the idle upstream PCI-E link; if not, continues to monitor and analyze the second DMA transfer flag bit array; The CPU and the PCI-E controller adopt a preemption mechanism for the idle upstream PCI-E link in the PCI-E bus. When the idle upstream PCI-E link is preempted by the CPU, step S5.1 is executed; when the idle upstream PCI-E link is preempted by the PCI-E controller, step S5.2 is executed; Step S5.1, when the idle upstream PCI-E link is preempted by the CPU, the CPU updates the first DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device to be tested to 1, and synchronizes the updated first DMA transfer flag array to the second DMA transfer flag array; Then, the CPU reads the test data in the test set, and sends the test data to the PCI-E controller through the seized upstream PCI-E link, the process bound to the PCI-E accelerator card device to be tested, and multiple threads under the process; When the PCI-E controller receives test data from a process and an upstream PCI-E link, on the one hand, the PCI-E controller updates the second DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device bound to the process received this time to 0, and synchronizes the updated second DMA transfer flag array to the first DMA transfer flag array; on the other hand, the PCI-E controller sends the received test data to the corresponding PCI-E accelerator card device, so that the PCI-E accelerator card device performs computing power calculations on the test data to obtain computing power result data, and then the PCI-E accelerator card device immediately sends the computing power result data to the PCI-E controller through the corresponding downstream PCI-E link; Step S5.2, when the idle upstream PCI-E link is preempted by the PCI-E controller, the PCI-E controller updates the second DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device corresponding to the computing result data to be transferred this time to 1, and synchronizes the updated second DMA transfer flag array to the first DMA transfer flag array; Then, the PCI-E controller sends the computing power result data to the CPU through the upstream PCI-E link that it has seized and the process bound to the PCI-E accelerator card device; When the CPU receives computing power result data from a PCI-E accelerator card device, on the one hand, the CPU updates the first DMA transfer flag array, sets the transfer flag position of the PCI-E accelerator card device bound to the process received this time to 0, and synchronizes the updated first DMA transfer flag array to the second DMA transfer flag array; on the other hand, the CPU records the time when the computing power result data is received; Step S6, when the test is finished, the CPU obtains the computing power of each PCI-E accelerator card device and the combined computing power of all PCI-E accelerator card devices through statistics.

2. A method for managing communication of multi-acceleration card computing power test according to claim 1, characterized in that: Step S5, the CPU determines whether there is an idle upstream PCI-E link in the PCI-E bus by analyzing the first DMA transfer flag bit array, specifically: The CPU reads the number N1 of transmission flag bits in the occupied state in the first DMA transmission flag bit array, and determines whether the number N1 reaches the maximum number card_num. If reached, it indicates that there is no idle upstream PCI-E link in the PCI-E bus, and the PCI-E bus is fully loaded; if not reached, it indicates that there is an idle upstream PCI-E link in the PCI-E bus.

3. A method for managing communication of multi-acceleration card computing power test according to claim 2, characterized in that: The CPU calls the detection function GetSet() to obtain the number N1 of transmission flag bits in the first DMA transmission flag bit array that are in the occupied state.

4. The method for managing communication of multi-acceleration card computing power test according to claim 1, characterized in that: Step S5, calling the daemon process to obtain the identifier of the upstream PCI-E link in the idle state, specifically: Start a daemon process, monitor the status of each upstream PCI-E link of the PCI-E bus, and obtain the identifier of the upstream PCI-E link in the idle state.

5. The method for managing communication of multi-acceleration card computing power test according to claim 1, characterized in that: The PCI-E accelerator card device performs computing power calculations on the test data to obtain computing power result data, specifically: The test data is a feature map, and its spatial size is H*W, where H and W are the length and width of the feature map respectively; the calculation speed FLOPS of the accelerator card is calculated using the following formula: Where: the accelerator card uses convolution operation to perform computing power test, K is the size of the convolution unit used by the accelerator card; C in and C out are the number of input channels and output channels of the convolution unit respectively; T s and T d They are the start processing time and processing completion time of the accelerator card.

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