A command generating circuit and memory

Abstract

The present disclosure relates to the field of integrated circuits and discloses a command generation circuit and memory. The command generation circuit includes a command receiving module and a command decoding module. The command receiving module is configured to receive a first command address signal, a first chip select signal, and a clock signal, and sample and register the first command address signal and the first chip select signal based on the clock signal to obtain a second command address signal and a second chip select signal. The command decoding module is connected to the command receiving module and configured to receive and decode an on-chip termination command based on the second command address signal and the second chip select signal. The on-chip termination command is used to control on-chip termination in a non-target chip when the target chip is performing any one of at least two operations. The present disclosure can simplify circuits, reduce circuit power consumption and occupied area, and thus improve memory performance.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a command generating circuit and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speeds when manufacturing and using computers and other devices. To achieve faster data transmission speeds, a series of devices such as memories that can transmit data at double the data rate (DDR) have emerged.

[0003] In dynamic random access memory (DRAM) chips, the command / address (CMD / ADD, or CA) signal can be sampled and decoded as both an address and an instruction. For example, the CA signal can generate an on-die termination (ODT) command. For ODT commands in non-target chips, the circuitry involved can be further optimized. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a command generation circuit and a memory, which can simplify the circuit, reduce circuit power consumption and occupied area, and thus improve the performance of the memory.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] An embodiment of the present disclosure provides a command generation circuit, which includes: a command receiving module, configured to receive a first command address signal, a first chip select signal and a clock signal, and sample and register the first command address signal and the first chip select signal according to the clock signal to obtain a second command address signal and a second chip select signal; a command decoding module, connected to the command receiving module, configured to receive and decode an on-chip termination command according to the second command address signal and the second chip select signal; the on-chip termination command is used to control the on-chip termination in a non-target chip when the target chip is performing any one of at least two operations.

[0007] In the above solution, the on-chip termination command is used to control the on-chip termination in the non-target chip when the target chip is performing a mode register read operation or a read operation.

[0008] In the above scheme, the second command address signal includes multiple command address sub-signals; wherein, when the second chip select signal is at a low level and the target chip performs the mode register read operation or the read operation, the first command address sub-signal is valid at a high level, the second command address sub-signal is valid at a low level, the third command address sub-signal is valid at a high level, and the fifth command address sub-signal is valid at a high level.

[0009] In the above scheme, the command decoding module includes: a first inverter, a second inverter, a first NAND gate, a second NAND gate and a first NOR gate; the input end of the first inverter receives the second chip select signal, and the output end of the first inverter is connected to the first input end of the first NAND gate; the second input end of the first NAND gate receives the first command address sub-signal; the input end of the second inverter receives the second command address sub-signal, and the output end of the second inverter is connected to the third input end of the first NAND gate; the first input end of the second NAND gate receives the third command address sub-signal; the second input end of the second NAND gate is connected to the power supply end; the third input end of the second NAND gate receives the fifth command address sub-signal; the output end of the first NAND gate is connected to the first input end of the first NOR gate; the output end of the second NAND gate is connected to the second input end of the first NOR gate; and the output end of the first NOR gate outputs the on-chip termination command.

[0010] In the above scheme, the command decoding module also includes: a first delay, a second delay and a third delay; the input end of the first delay receives the first command address sub-signal, and the output end of the first delay is connected to the second input end of the first NAND gate; the input end of the second delay receives the third command address sub-signal, and the output end of the second delay is connected to the first input end of the second NAND gate; the input end of the third delay receives the fifth command address sub-signal, and the output end of the third delay is connected to the third input end of the second NAND gate.

[0011] In the above solution, the first inverter, the second inverter, the first delay device, the second delay device and the third delay device have consistent device delays.

[0012] In the above scheme, the command decoding module includes: a third inverter, a fourth inverter, a fifth inverter, a second NOR gate, a third NOR gate and a first AND gate; the first input end of the second NOR gate receives the second chip select signal; the input end of the third inverter receives the first command address sub-signal, and the output end of the third inverter is connected to the second input end of the second NOR gate; the third input end of the second NOR gate receives the second command address sub-signal; the input end of the fourth inverter receives the third command address sub-signal, and the output end of the fourth inverter is connected to the first input end of the third NOR gate; the second input end of the third NOR gate is grounded; the input end of the fifth inverter receives the fifth command address sub-signal, and the output end of the fifth inverter is connected to the third input end of the third NOR gate; the output end of the second NOR gate is connected to the first input end of the first AND gate; the output end of the third NOR gate is connected to the second input end of the first AND gate; and the output end of the first AND gate outputs the on-chip termination command.

[0013] In the above scheme, the command decoding module also includes: a fourth delay and a fifth delay; the input end of the fourth delay receives the second chip select signal, and the output end of the fourth delay is connected to the first input end of the second NOR gate; the input end of the fifth delay receives the second command address sub-signal, and the output end of the fifth delay is connected to the third input end of the second NOR gate.

[0014] In the above solution, the third inverter, the fourth inverter, the fifth inverter, the fourth delay device and the fifth delay device have consistent device delays.

[0015] In the above scheme, the command receiving module includes: a command address signal receiving module, configured to receive the first command address signal and the clock signal, and sample and register the first command address signal according to the clock signal to obtain the second command address signal; a chip select signal receiving module, configured to receive the first chip select signal and the clock signal, and sample and register the first chip select signal according to the clock signal to obtain the second chip select signal.

[0016] In the above scheme, the command address signal receiving module includes: a multi-stage first D flip-flop group; the in-phase output terminal of the first D flip-flop group of each stage is connected to the data input terminal of the first D flip-flop group of the next stage; the data input terminal of the first D flip-flop group of the first stage is connected to receive the first command address signal; the in-phase output terminal of the first D flip-flop group of the last stage is connected to output the second command address signal; and the clock input terminal of the first D flip-flop group of each stage is connected to receive the clock signal.

[0017] In the above solution, the first D flip-flop group in each stage includes: multiple first D flip-flops; each of the first D flip-flops is used to process one of the first, second, third and fifth command address sub-signals.

[0018] In the above scheme, the chip select signal receiving module includes: multiple stages of second D flip-flops; the non-inverting output end of the second D flip-flop of each stage is connected to the data input end of the second D flip-flop of the next stage; the data input end of the second D flip-flop of the first stage receives the first chip select signal; the non-inverting output end of the second D flip-flop of the last stage outputs the second chip select signal; and the clock input end of the second D flip-flop of each stage receives the clock signal.

[0019] An embodiment of the present disclosure further provides a memory, characterized in that the memory includes the command generating circuit described in the above solution.

[0020] In the above solution, the memory is DRAM and complies with DDR5 memory specifications.

[0021] Thus, the disclosed embodiments provide a command generation circuit and memory. The command generation circuit includes: a command receiving module and a command decoding module. The command receiving module is configured to receive a first command address signal, a first chip select signal, and a clock signal, and sample and register the first command address signal and the first chip select signal according to the clock signal to obtain a second command address signal and a second chip select signal. The command decoding module is connected to the command receiving module and configured to receive and decode an on-chip termination command according to the second command address signal and the second chip select signal. The on-chip termination command is used to control the on-chip termination in a non-target chip when the target chip is performing any one of at least two operations. In this way, only one set of command generation circuits is required to generate on-chip termination commands for multiple operations; there is no need to set up a command generation circuit for each operation to generate an on-chip termination command. This simplifies the circuit, reduces circuit power consumption and occupied area, and improves the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the structure of an ODT functional circuit;

[0023] Figure 2 It is a schematic diagram of the structure of the double-row chip in the memory;

[0024] Figure 3 A schematic diagram of the structure of the command generation circuit provided in the embodiment of the present disclosure Figure 1 ;

[0025] Figure 4 A schematic diagram of the structure of the command decoding module provided in the embodiment of the present disclosure Figure 1 ;

[0026] Figure 5 A schematic diagram of the structure of the command decoding module provided in the embodiment of the present disclosure Figure 2 ;

[0027] Figure 6 A schematic diagram of the structure of the command decoding module provided in the embodiment of the present disclosure Figure 3 ;

[0028] Figure 7 A schematic diagram of the structure of the command decoding module provided in the embodiment of the present disclosure Figure 4 ;

[0029] Figure 8 A schematic diagram of the structure of the command receiving module provided in the embodiment of the present disclosure Figure 1 ;

[0030] Figure 9 A schematic diagram of the structure of the command receiving module provided in the embodiment of the present disclosure Figure 2 ;

[0031] Figure 10 A schematic diagram of the structure of a command address signal receiving module provided in an embodiment of the present disclosure;

[0032] Figure 11 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0034] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0035] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0037] With the rapid development of semiconductor technology, signal transmission rates are increasing, leading to increasingly prominent signal integrity issues. To improve data signal integrity during high-speed signal transmission, DDR3, DDR4, and DDR5 designs incorporate dedicated ODT resistors. These resistors are used to impedance-match transmission lines, minimizing reflections and energy loss during transmission, thereby ensuring signal integrity at the receiving end.

[0038] Taking DDR5 DRAM as an example, DDR5 DRAM supports ODT function, which can adjust the terminal resistance (also called "termination resistance") of each device's DQ, DQS_t / c, DM_n and TDQS_t / c ports through ODT pin control, write commands or mode register setting default resistance values. In addition, the purpose of the ODT function is to reduce reflections and effectively improve the signal integrity on the memory interface by independently controlling the terminal resistance of all or any DRAM by the controller. Figure 1 As shown, it shows a structural diagram of an ODT functional circuit provided by the related art. Figure 1 In the example, the ODT functional circuit may include at least a switch S1, a terminal resistor RTT, and a power supply VDDQ. One end of the switch S1 is connected to one end of the terminal resistor RTT, the other end of the terminal resistor RTT is connected to the power supply VDDQ, and the other end of the switch S1 is connected to other circuits, as well as the DQ, DQS, DM, and TDQS ports. It should be noted that DQS can be a pair of differential data strobe signals DQS_t and DQS_c, and TDQS can be a pair of differential data strobe signals TDQS_t and TDQS_c.

[0039] in addition, Figure 1 Switch S1 in the circuit is controlled by the ODT control logic. The ODT control logic includes the external ODT pin input, mode register configuration, and other control information. The RTT value is controlled by the configuration information in the mode register.

[0040] It should be noted that DDR DRAM uses a two-rank chip structure. Accordingly, when performing an operation on the target chip in one rank, it is necessary to perform ODT on the non-target chip in the other rank to ensure that the two-rank chips can match each other. Figure 2 The structure of the double-row chip is shown. Figure 2 As shown, when Rank1 receives the command signal CMD and performs an operation, that is, the chip in Rank1 serves as the target chip; the non-target chip in Rank2 performs NT_ODT, that is, the ODT circuit of the non-target chip in Rank2 is in the on state.

[0041] However, in related art, for each operation executed by the target chip, a corresponding circuit must be set up to generate ODT commands for the non-target chip. This makes the circuit more complex, consumes more power and occupies more area, thus hindering the improvement of memory performance.

[0042] like Figure 3 As shown, an embodiment of the present disclosure provides a command generation circuit 80, which includes a command receiving module 10 and a command decoding module 20. The command receiving module 10 is configured to receive a first command address signal CA, a first chip select signal CS_n, and a clock signal CLK. Based on the clock signal CLK, the command receiving module 10 samples and registers the first command address signal CA and the first chip select signal CS_n to obtain a second command address signal CA_2T and a second chip select signal CS_2T. The command decoding module 20 is connected to the command receiving module 10 and is configured to receive and decode an on-chip termination command NT_ODT_CMD based on the second command address signal CA_2T and the second chip select signal CS_2T. The on-chip termination command NT_ODT_CMD is used to control on-chip termination in a non-target chip when the target chip is performing any of at least two operations.

[0043] In the disclosed embodiment, when the target chip performs any of at least two operations, the command generation circuit 80 can decode the on-chip termination command NT_ODT_CMD using the same first command address signal CA and first chip select signal CS_n. In other words, the command generation circuit 80 can decode the same on-chip termination command NT_ODT_CMD for different operations performed by the target chip to control on-chip termination in non-target chips.

[0044] It is understood that the disclosed embodiments only require one set of command generation circuits to generate on-chip termination commands for multiple operations, eliminating the need for separate command generation circuits for each operation. This simplifies the circuitry, reduces power consumption and footprint, and improves memory performance.

[0045] In some embodiments of the present disclosure, reference Figure 3The on-chip termination command NT_ODT_CMD is used to control the on-chip termination in the non-target chip when the target chip is performing a mode register read (Mode Register Read) operation or a read (Read) operation.

[0046] In some embodiments of the present disclosure, the second command address signal CA_2T includes multiple command address sub-signals. When the second chip select signal CS_2T is low and the target chip is performing a mode register read operation or a read operation, the first command address sub-signal CA0 is active high, the second command address sub-signal CA1 is active low, the third command address sub-signal CA2 is active high, and the fifth command address sub-signal CA4 is active high.

[0047] Table 1 below shows the truth table for some commands specified in the DDR DRAM SPEC (Design Specification). Referring to Table 1, according to the SPEC definition, during the target chip's mode register read and read operations, the command address sub-signals (CA0-CA4) used to generate the ODT command for the non-target chip are similar. The first command address sub-signal CA0 is always valid at a high level (H), the second command address sub-signal CA1 is always valid at a low level (L), the third command address sub-signal CA2 is always valid at a high level (H), and the fifth command address sub-signal CA4 is always valid at a high level (H). Only the fourth command address sub-signal CA3 has a different valid level.

[0048] Function abbreviation CS_n CA0 CA1 CA2 CA3 CA4 Mode register read MRR L H L H L H Read RD L H L H H H

[0049] Table 1

[0050] Therefore, combined Figure 3 As shown in Table 1, when executing both a mode register read and a read operation on a target chip, the command decoding module 20 provided in the disclosed embodiment can generate ODT commands for non-target chips based on the same set of command address sub-signals (including CA0-CA4). In other words, a single command generation circuit 80 is required to generate on-chip termination commands for both mode register read and read operations. This simplifies the circuit, reduces power consumption and area occupied, and improves memory performance.

[0051] In some embodiments of the present disclosure, Figure 4 As shown, the command decoding module 20 includes: a first inverter Inv1, a second inverter Inv2, a first NAND gate Nand1, a second NAND gate Nand2 and a first NOR gate Nor1.

[0052] The input of the first inverter Inv1 receives the second chip select signal CS_2T, and the output of the first inverter Inv1 is connected to the first input of the first NAND gate Nand1. The second input of the first NAND gate Nand1 receives the first command address sub-signal CA0_2T. The input of the second inverter Inv2 receives the second command address sub-signal CA1_2T, and the output of the second inverter Inv2 is connected to the third input of the first NAND gate Nand1. The first input of the second NAND gate Nand2 receives the third command address sub-signal CA2_2T; the second input of the second NAND gate Nand2 is connected to the power supply VDD; and the third input of the second NAND gate Nand2 receives the fifth command address sub-signal CA4_2T. The output of the first NAND gate Nand1 is connected to the first input of the first NOR gate Nor1; the output of the second NAND gate Nand2 is connected to the second input of the first NOR gate Nor1. The output of the first NOR gate Nor1 outputs the on-chip termination command NT_ODT_CMD.

[0053] Combine Figure 4 As shown in Table 1, when the second chip select signal CS_2T is low, the first command address sub-signal CA0_2T is high, the second command address sub-signal CA1_2T is low, the third command address sub-signal CA2_2T is high, and the fifth command address sub-signal CA4_2T is high, the first NAND gate Nand1 and the second NAND gate Nand2 both output low levels, and then the first NOR gate Nor1 outputs a high-level on-chip termination command NT_ODT_CMD, that is, the on-chip termination command NT_ODT_CMD is a valid level.

[0054] That is, when the second chip select signal CS_2T, the first command address sub-signal CA0_2T, the second command address sub-signal CA1_2T, the third command address sub-signal CA2_2T, and the fifth command address sub-signal CA4_2T satisfy the truth table shown in Table 1 (i.e., the truth table corresponding to the mode register read operation and the read operation), the on-chip termination command NT_ODT_CMD is at a valid level (i.e., the on-chip termination command NT_ODT_CMD is at a high level). Correspondingly, if any of the second chip select signal CS_2T, the first command address sub-signal CA0_2T, the second command address sub-signal CA1_2T, the third command address sub-signal CA2_2T, and the fifth command address sub-signal CA4_2T does not satisfy the truth table shown in Table 1, the on-chip termination command NT_ODT_CMD is not at a valid level (i.e., the on-chip termination command NT_ODT_CMD is at a low level).

[0055] It should be noted that, in the truth table shown in Table 1, the valid level of the fourth command address sub-signal CA3 corresponding to the mode register read operation is inconsistent with the valid level of the fourth command address sub-signal CA3 corresponding to the read operation. Figure 4 In the illustrated circuit, the fourth command address sub-signal CA3_2T is not introduced, and the second input of the second NAND gate Nand2 is connected to the power supply terminal VDD. Therefore, the fourth command address sub-signal CA3_2T, which differs between the two operations, does not affect the output on-chip termination command NT_ODT_CMD.

[0056] It is understandable that Figure 4 The command decoding module 20 shown can generate corresponding on-chip termination commands for both mode register read and read operations. In other words, a single set of command decoding module 20 circuitry can generate on-chip termination commands for multiple operations, eliminating the need for separate command generation circuitry for each operation. This simplifies the circuitry, reduces power consumption and footprint, and improves memory performance.

[0057] In some embodiments of the present disclosure, Figure 5 As shown, the command decoding module 20 further includes: a first delay DL1 , a second delay DL2 and a third delay DL3 .

[0058] The input of the first delay unit DL1 receives the first command address sub-signal CA0_2T, and the output of the first delay unit DL1 is connected to the second input of the first NAND gate Nand1. The input of the second delay unit DL2 receives the third command address sub-signal CA2_2T, and the output of the second delay unit DL2 is connected to the first input of the second NAND gate Nand2. The input of the third delay unit DL3 receives the fifth command address sub-signal CA4_2T, and the output of the third delay unit DL3 is connected to the third input of the second NAND gate Nand2.

[0059] In the embodiments of the present disclosure, reference Figure 5The first inverter Inv1 and the second inverter Inv2 have device delays. That is, the second chip select signal CS_2T is delayed after passing through the first inverter Inv1, and the second command address sub-signal CA1_2T is delayed after passing through the second inverter Inv2. The first delay device DL1, the second delay device DL2, and the third delay device DL3 also have device delays. That is, the first command address sub-signal CA0_2T is delayed after passing through the first delay device DL1, the third command address sub-signal CA2_2T is delayed after passing through the second delay device DL2, and the fifth command address sub-signal CA4_2T is delayed after passing through the third delay device DL3. This balances the delays of the various signals, avoiding large timing differences between the signals and ensuring the accuracy and stability of the output on-chip termination commands.

[0060] In some embodiments of the present disclosure, reference Figure 5 The first inverter Inv1, the second inverter Inv2, the first delay DL1, the second delay DL2, and the third delay DL3 all have consistent device delays. This ensures consistent delays for each signal during transmission, aligning the timing of each signal and ensuring the accuracy and stability of the output on-chip termination command.

[0061] In some embodiments of the present disclosure, Figure 4 and Figure 5 The second NAND gate Nand2 shown can be a two-input NAND gate, and the two input terminals of the second NAND gate Nand2 receive the third command address sub-signal CA2_2T and the fifth command address sub-signal CA4_2T respectively; that is, the Figure 4 and Figure 5 In this way, the fourth command address sub-signal CA3_2T, which is different between the two operations, will not affect the output on-chip termination command NT_ODT_CMD.

[0062] In some embodiments of the present disclosure, Figure 6 As shown, the command decoding module 20 includes: a third inverter Inv3, a fourth inverter Inv4, a fifth inverter Inv5, a second NOR gate Nor2, a third NOR gate Nor3 and a first AND gate And1.

[0063] The first input of the second NOR gate Nor2 receives the second chip select signal CS_2T. The input of the third inverter Inv3 receives the first command address sub-signal CA0_2T, and the output of the third inverter Inv3 is connected to the second input of the second NOR gate Nor2. The third input of the second NOR gate Nor2 receives the second command address sub-signal CA1_2T. The input of the fourth inverter Inv4 receives the third command address sub-signal CA2_2T, and the output of the fourth inverter Inv4 is connected to the first input of the third NOR gate Nor3. The second input of the third NOR gate Nor3 is grounded (i.e., connected to the ground terminal VSS). The input of the fifth inverter Inv5 receives the fifth command address sub-signal CA4_2T, and the output of the fifth inverter Inv5 is connected to the third input of the third NOR gate Nor3. The output of the second NOR gate Nor2 is connected to the first input of the first AND gate And1; the output of the third NOR gate Nor3 is connected to the second input of the first AND gate And1. The output end of the first AND gate And1 outputs the on-chip termination command NT_ODT_CMD.

[0064] Combine Figure 6 As shown in Table 1, when the second chip select signal CS_2T is low, the first command address sub-signal CA0_2T is high, the second command address sub-signal CA1_2T is low, the third command address sub-signal CA2_2T is high, and the fifth command address sub-signal CA4_2T is high, the second NOR gate Nor2 and the third NOR gate Nor3 both output high levels, and then, the first AND gate And1 outputs a high-level on-chip termination command NT_ODT_CMD, that is, the on-chip termination command NT_ODT_CMD is at a valid level.

[0065] That is, when the second chip select signal CS_2T, the first command address sub-signal CA0_2T, the second command address sub-signal CA1_2T, the third command address sub-signal CA2_2T, and the fifth command address sub-signal CA4_2T satisfy the truth table shown in Table 1 (i.e., the truth table corresponding to the mode register read operation and the read operation), the on-chip termination command NT_ODT_CMD is at a valid level (i.e., the on-chip termination command NT_ODT_CMD is at a high level). Correspondingly, if any of the second chip select signal CS_2T, the first command address sub-signal CA0_2T, the second command address sub-signal CA1_2T, the third command address sub-signal CA2_2T, and the fifth command address sub-signal CA4_2T does not satisfy the truth table shown in Table 1, the on-chip termination command NT_ODT_CMD is not at a valid level (i.e., the on-chip termination command NT_ODT_CMD is at a low level).

[0066] It should be noted that, in the truth table shown in Table 1, the valid level of the fourth command address sub-signal CA3 corresponding to the mode register read operation is inconsistent with the valid level of the fourth command address sub-signal CA3 corresponding to the read operation. Figure 6 In the illustrated circuit, the fourth command address sub-signal CA3_2T is not introduced, and the second input of the third NOR gate Nor3 is connected to the ground terminal VSS. Therefore, the fourth command address sub-signal CA3_2T, which differs between the two operations, does not affect the output on-chip termination command NT_ODT_CMD.

[0067] It is understandable that Figure 6 The command decoding module 20 shown can generate corresponding on-chip termination commands for both mode register read and read operations. In other words, a single set of command decoding module 20 circuitry can generate on-chip termination commands for multiple operations, eliminating the need for separate command generation circuitry for each operation. This simplifies the circuitry, reduces power consumption and footprint, and improves memory performance.

[0068] In some embodiments of the present disclosure, Figure 7 As shown, the command decoding module 20 further includes a fourth delay unit DL4 and a fifth delay unit DL5.

[0069] The input of the fourth delay circuit DL4 receives the second chip select signal CS_2T, and the output of the fourth delay circuit DL4 is connected to the first input of the second NOR gate Nor2. The input of the fifth delay circuit DL5 receives the second command address sub-signal CA1_2T, and the output of the fifth delay circuit DL5 is connected to the third input of the second NOR gate Nor2.

[0070] In the embodiments of the present disclosure, reference Figure 7 The third inverter Inv3, the fourth inverter Inv4, and the fifth inverter Inv5 have device delays. That is, the first command address sub-signal CA0_2T is delayed after passing through the third inverter Inv3, the third command address sub-signal CA2_2T is delayed after passing through the fourth inverter Inv4, and the fifth command address sub-signal CA4_2T is delayed after passing through the fifth inverter Inv5. The fourth delay device DL4 and the fifth delay device DL5 also have device delays. That is, the second chip select signal CS_2T is delayed after passing through the fourth delay device DL4, and the second command address sub-signal CA1_2T is delayed after passing through the fifth delay device DL5. This balances the delays of the various signals, avoiding large timing discrepancies between the signals and ensuring the accuracy and stability of the output on-chip termination commands.

[0071] In some embodiments of the present disclosure, reference Figure 7 The third inverter Inv3, the fourth inverter Inv4, the fifth inverter Inv5, the fourth delay DL4, and the fifth delay DL5 all have consistent device delays. This ensures consistent delays for all signals during transmission, aligning the timing of each signal and ensuring the accuracy and stability of the output on-chip termination command.

[0072] In some embodiments of the present disclosure, Figure 6 and Figure 7 The third NOR gate Nor3 shown can be a two-input NOR gate, and the two input terminals of the third NOR gate Nor3 receive the third command address sub-signal CA2_2T and the fifth command address sub-signal CA4_2T respectively; that is, the Figure 6 and Figure 7 In this way, the fourth command address sub-signal CA3_2T, which is different between the two operations, will not affect the output on-chip termination command NT_ODT_CMD.

[0073] In some embodiments of the present disclosure, Figure 8 As shown, the command receiving module 10 includes a command address signal receiving module 30 and a chip select signal receiving module 40. The command address signal receiving module 30 is configured to receive a first command address signal CA and a clock signal CLK, and to sample and register the first command address signal CA according to the clock signal CLK to obtain a second command address signal CA_2T. The chip select signal receiving module 40 is configured to receive a first chip select signal CS_n and a clock signal CLK, and to sample and register the first chip select signal CS_n according to the clock signal CLK to obtain a second chip select signal CS_2T.

[0074] In some embodiments of the present disclosure, Figure 9 As shown, the command address signal receiving module 30 includes multiple stages of first D flip-flop groups 301. The non-inverting output terminal Q of each stage of the first D flip-flop group 301 is connected to the data input terminal D of the next stage of the first D flip-flop group 301. The data input terminal D of the first stage of the first D flip-flop group 301 receives the first command address signal CA. The non-inverting output terminal Q of the last stage of the first D flip-flop group 301 outputs the second command address signal CA_2T. The clock input terminal of each stage of the first D flip-flop group 301 receives the clock signal CLK.

[0075] In the embodiments of the present disclosure, reference Figure 9The multi-stage first D flip-flop group 301 samples and registers the first command address signal CA under the triggering of the clock signal CLK, and outputs the second command address signal CA_2T.

[0076] It should be noted that Figure 8 and Figure 9 The first command address signal CA shown in FIG includes multiple command address sub-signals. Correspondingly, the second command address signal CA_2T also includes multiple command address sub-signals. Each flip-flop in the first D flip-flop group 301 processes one command address sub-signal.

[0077] In some embodiments of the present disclosure, Figure 9 and Figure 10 Each stage of the first D flip-flop group 301 includes a plurality of first D flip-flops (including 3011, 3012, 3013, and 3014). Each first D flip-flop is configured to process one of the first, second, third, and fifth command address sub-signals (i.e., CA0, CA1, CA2, and CA4).

[0078] In the embodiments of the present disclosure, reference Figure 10 The non-inverting output terminal Q of the first D flip-flop 3011 in each stage is connected to the data input terminal D of the first D flip-flop 3011 in the next stage. The data input terminal D of the first D flip-flop 3011 in the first stage receives the first command address sub-signal CA0. The non-inverting output terminal Q of the first D flip-flop 3011 in the last stage outputs the registered first command address sub-signal CA0_2T. The clock input terminal of the first D flip-flop 3011 in each stage receives the clock signal CLK. The other first D flip-flops 3012, 3013, and 3014 have similar connection structures to the first D flip-flop 3011 and are not further described here.

[0079] In the embodiment of the present disclosure, referring to Table 1, there is a difference in the effective level of the fourth command address sub-signal CA3 for the truth table of the mode register read operation and the read operation. Figure 9 In each stage of the first D flip-flop group 301, no first D flip-flop is configured to process the fourth command address sub-signal CA3. This means that the different fourth command address sub-signal CA3 is not introduced, ensuring that the generated on-chip termination command can address both mode register read operations and read operations. This eliminates the need for a corresponding first D flip-flop for the fourth command address sub-signal CA3, thereby simplifying the circuit, reducing circuit power consumption and footprint, and improving memory performance.

[0080] In some embodiments of the present disclosure, reference Figure 9The chip select signal receiving module 40 includes multiple stages of second D flip-flops 401. The non-inverting output terminal Q of each stage of the second D flip-flop 401 is connected to the data input terminal D of the next stage of the second D flip-flop 401. The data input terminal D of the first stage of the second D flip-flop 401 receives the first chip select signal CS_n. The non-inverting output terminal Q of the last stage of the second D flip-flop 401 outputs the second chip select signal CS_2T. The clock input terminal of each stage of the second D flip-flop 401 receives the clock signal CLK.

[0081] In the embodiments of the present disclosure, reference Figure 9 The multi-stage second D flip-flop 401 samples and registers the first chip select signal CS_n under the triggering of the clock signal CLK, and outputs the second chip select signal CS_2T.

[0082] An embodiment of the present disclosure further provides a memory, such as Figure 11 As shown, the memory 90 may include the command generating circuit 80 described in any one of the aforementioned embodiments.

[0083] In some embodiments of the present disclosure, reference Figure 11 , the memory 90 may be a DRAM chip. Further, in some embodiments, the memory 90 complies with the DDR5 memory specification.

[0084] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0085] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0086] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A command generating circuit, characterized in that: The command generating circuit comprises: a command receiving module configured to receive a first command address signal, a first chip select signal, and a clock signal, and sample and register the first command address signal and the first chip select signal according to the clock signal to obtain a second command address signal and a second chip select signal; a command decoding module connected to the command receiving module, configured to receive and decode an on-chip termination command according to the second command address signal and the second chip select signal; the on-chip termination command is used to control on-chip termination in a non-target chip when the target chip is performing any one of at least two operations; The on-chip termination command is used to control the on-chip termination in the non-target chip when the target chip performs a mode register read operation or a read operation; The second command address signal includes a plurality of command address sub-signals; wherein, When the second chip select signal is at a low level and the target chip performs the mode register read operation or the read operation, the first command address sub-signal is valid at a high level, the second command address sub-signal is valid at a low level, the third command address sub-signal is valid at a high level, and the fifth command address sub-signal is valid at a high level.

2. The command generating circuit according to claim 1, wherein: The command decoding module includes: a first inverter, a second inverter, a first NAND gate, a second NAND gate and a first NOR gate; An input end of the first inverter receives the second chip selection signal, and an output end of the first inverter is connected to a first input end of the first NAND gate; The second input terminal of the first NAND gate receives the first command address sub-signal; An input terminal of the second inverter receives the second command address sub-signal, and an output terminal of the second inverter is connected to the third input terminal of the first NAND gate; The first input terminal of the second NAND gate receives the third command address sub-signal; the second input terminal of the second NAND gate is connected to the power supply terminal; the third input terminal of the second NAND gate receives the fifth command address sub-signal; The output end of the first NAND gate is connected to the first input end of the first NOR gate; the output end of the second NAND gate is connected to the second input end of the first NOR gate; The output end of the first NOR gate outputs the on-chip termination command.

3. The command generating circuit according to claim 2, wherein: The command decoding module further includes: a first delay device, a second delay device and a third delay device; The input end of the first delay device receives the first command address sub-signal, and the output end of the first delay device is connected to the second input end of the first NAND gate; The input end of the second delay device receives the third command address sub-signal, and the output end of the second delay device is connected to the first input end of the second NAND gate; An input end of the third delay device receives the fifth command address sub-signal, and an output end of the third delay device is connected to a third input end of the second NAND gate.

4. The command generating circuit according to claim 3, wherein: The first inverter, the second inverter, the first delay device, the second delay device and the third delay device have consistent device delays.

5. The command generating circuit according to claim 1, wherein: The command decoding module includes: a third inverter, a fourth inverter, a fifth inverter, a second NOR gate, a third NOR gate and a first AND gate; The first input terminal of the second NOR gate receives the second chip select signal; The input end of the third inverter receives the first command address sub-signal, and the output end of the third inverter is connected to the second input end of the second NOR gate; The third input terminal of the second NOR gate receives the second command address sub-signal; The input end of the fourth inverter receives the third command address sub-signal, and the output end of the fourth inverter is connected to the first input end of the third NOR gate; The second input terminal of the third NOR gate is grounded; The input end of the fifth inverter receives the fifth command address sub-signal, and the output end of the fifth inverter is connected to the third input end of the third NOR gate; The output end of the second NOR gate is connected to the first input end of the first AND gate; the output end of the third NOR gate is connected to the second input end of the first AND gate; The output end of the first AND gate outputs the on-chip termination command.

6. The command generating circuit according to claim 5, characterized in that: The command decoding module further includes: a fourth delay device and a fifth delay device; An input end of the fourth delay device receives the second chip selection signal, and an output end of the fourth delay device is connected to a first input end of the second NOR gate; An input end of the fifth delay device receives the second command address sub-signal, and an output end of the fifth delay device is connected to the third input end of the second NOR gate.

7. The command generating circuit according to claim 6, wherein: The third inverter, the fourth inverter, the fifth inverter, the fourth delay device and the fifth delay device have consistent device delays.

8. The command generating circuit according to claim 1, wherein: The command receiving module includes: a command address signal receiving module, configured to receive the first command address signal and the clock signal, and sample and register the first command address signal according to the clock signal to obtain the second command address signal; The chip select signal receiving module is configured to receive the first chip select signal and the clock signal, and sample and register the first chip select signal according to the clock signal to obtain the second chip select signal.

9. The command generating circuit according to claim 8, characterized in that: The command address signal receiving module includes: a multi-stage first D flip-flop group; The non-inverting output terminal of the first D flip-flop group of each stage is connected to the data input terminal of the first D flip-flop group of the next stage; the data input terminal of the first D flip-flop group of the first stage receives the first command address signal; the non-inverting output terminal of the first D flip-flop group of the last stage outputs the second command address signal; The clock input terminal of the first D flip-flop group in each stage receives the clock signal.

10. The command generating circuit according to claim 9, characterized in that: The first D flip-flop group of each stage includes: a plurality of first D flip-flops; Each of the first D flip-flops is used to correspondingly process one of the first, second, third and fifth command address sub-signals.

11. The command generating circuit according to claim 8, wherein: The chip select signal receiving module includes: a multi-stage second D flip-flop; The non-inverting output terminal of the second D flip-flop of each stage is connected to the data input terminal of the second D flip-flop of the next stage; the data input terminal of the second D flip-flop of the first stage receives the first chip select signal; the non-inverting output terminal of the second D flip-flop of the last stage outputs the second chip select signal; The clock input terminal of the second D flip-flop in each stage receives the clock signal.

12. A memory, characterized in that: The memory includes the command generation circuit according to any one of claims 1 to 11.

13. The memory according to claim 12, wherein: The memory is DRAM and complies with DDR5 memory specifications.

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