Data writing circuit, memory and data writing method

Abstract

The present invention relates to a data writing circuit, a memory, and a data writing method. The data writing circuit includes: a multi-level driving module, wherein each level of the driving module is used to connect multiple storage arrays of a corresponding level and the driving module of the next level, and is used to drive the data to be written to the data path corresponding to the multiple storage arrays of the corresponding level and / or the driving module of the next level; a control module, connected to each level of the driving module, and used to send a driving control signal to the driving module of the corresponding level of the target storage array to be written and / or the driving module of the next level according to the write control signal of each storage array, wherein the driving control signal is used to adjust the driving capability of the driving module; wherein the data paths corresponding to different storage arrays are used to receive different write control signals, and the write control signal is used to connect the data path and the corresponding storage array. The present invention can reduce the difficulty of time matching.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a data writing circuit, a memory, and a data writing method. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] DRAM is typically arranged in a two-dimensional matrix, with a capacitor and a transistor as a unit. Its basic operation mechanism is divided into read and write. Traditionally, multiple memory arrays are arranged in multiple levels, with each level equipped with a driver module. When writing data, the driver module drives the data according to the write control signals of the different memory arrays to ensure accurate data writing.

[0004] However, as the capacity of DRAM increases and the number of memory arrays continues to grow, timing matching of write control signals becomes increasingly difficult. Summary of the Invention

[0005] Based on this, it is necessary to provide a data writing circuit, a memory and a data writing method that can reduce the difficulty of time matching.

[0006] In a first aspect, a data writing circuit is provided, comprising:

[0007] Multi-level driver modules, each level of the driver modules is used to connect the multiple storage arrays of the corresponding level and the driver modules of the next level, and is used to drive the transmission of data to be written to the data paths corresponding to the multiple storage arrays of the corresponding level and / or to the driver modules of the next level;

[0008] a control module connected to the driver modules at each level, and configured to send a drive control signal to the driver module at the corresponding level of the target storage array to which data is to be written and / or the driver module at the next level according to the write control signal of each storage array, wherein the drive control signal is used to adjust the drive capability of the driver module;

[0009] The data paths corresponding to different storage arrays are used to receive different write control signals, and the write control signals are used to connect the data paths and the corresponding storage arrays.

[0010] The data writing circuit includes a multi-stage driver module and a control module. Each stage of the driver module is connected to multiple storage arrays at the corresponding level and the driver module at the next level, driving the data to be written to be transferred to the data paths corresponding to the multiple storage arrays at the corresponding level and / or to the driver module at the next level. Through the cooperation of the multi-stage driver modules, the data to be written can be transferred to the data path corresponding to any storage array. The control module is connected to each stage of the driver module and, based on the write control signal of each storage array, sends a drive control signal to the driver module at the corresponding level of the target storage array and / or the driver module at the next level. The drive control signal is used to adjust the driving capability of the driver module, and can control the multi-stage driver module to transfer the data to be written to the data path corresponding to the target storage array without affecting time matching. In addition, the data paths corresponding to different storage arrays receive different write control signals, and the write control signal is used to connect the data path and the storage array. In this way, the write control signal can be further used to control the data to be written to the target storage array, achieving correct data writing. Moreover, the write control signal only needs to be time-matched with the data signal transmitted to the corresponding storage array, significantly reducing the difficulty of time matching.

[0011] In one embodiment, the control module is configured to send the drive control signal to the drive module at the corresponding level and / or the drive module at the next level if the write control signals of the plurality of storage arrays at the same level are at different levels.

[0012] In one embodiment, the driving module is configured to adjust its own driving capability upon receiving the driving control signal, wherein the adjusted driving capability is smaller than the driving capability required to transmit the data to be written to the next-level driving module.

[0013] In one embodiment, the control module is further configured to send the driving control signal to each driving module of a level subsequent to the corresponding level of the target storage array.

[0014] In one embodiment, the driving module includes:

[0015] a first driving unit, configured to, when not receiving the driving control signal, drive the data to be written to be transmitted to the data paths corresponding to the plurality of storage arrays at the corresponding level and to the driving module at the next level; and, when receiving the driving control signal, adjust its own driving capability, wherein the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driving module at the next level;

[0016] When the control module sends a driving control signal to the driving module at the next level of the target storage array to which the data is to be written, the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays at the corresponding level; when the control module sends a driving control signal to the driving module at the corresponding level of the target storage array to which the data is to be written, the adjusted driving capability is greater than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays at the corresponding level.

[0017] In one embodiment, the driving module includes:

[0018] A second driving unit, configured to drive the data to be written to be transmitted to data paths corresponding to the plurality of storage arrays at a corresponding level;

[0019] The third driving unit is used to drive the data to be written to be transmitted to the driving module of the next level when the driving control signal is not received; and when the driving control signal is received, adjust its own driving capability, and the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the driving module of the next level.

[0020] In one embodiment, the second driving unit is configured to adjust its own driving capability upon receiving the driving control signal, wherein the adjusted driving capability is greater than the driving capability required for transmitting the data to be written to the data paths corresponding to the plurality of storage arrays at the corresponding level.

[0021] In one embodiment, the driving control signal includes a first sub-control signal and a second sub-control signal, and the driving module includes:

[0022] a fourth driving unit, configured to adjust its own driving capability upon receiving the first sub-control signal, wherein the adjusted driving capability is greater than a driving capability required by data paths corresponding to the plurality of storage arrays at a corresponding level for transmitting the to-be-written data;

[0023] a fifth driving unit, configured to drive the data to be written to be transmitted to the driving module of the next level when the second sub-control signal is not received; and to adjust its own driving capability when the second sub-control signal is received, wherein the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driving module of the next level.

[0024] In a second aspect, a memory is provided, comprising a plurality of memory arrays and the data writing circuit provided in the first aspect.

[0025] The above-mentioned memory includes multiple storage arrays and the data writing circuit as described above, which can also effectively reduce the difficulty of time matching while correctly writing the data to be written into the target storage array.

[0026] In a third aspect, a data writing method is provided, comprising:

[0027] Generate a drive control signal based on the write control signal of each storage array, wherein the drive control signal is used to adjust the driving capability of the drive module. The drive module at each level is used to connect the multiple storage arrays at the corresponding level and the drive module at the next level, and to drive the data to be written to the data path corresponding to the multiple storage arrays at the corresponding level and / or the drive module at the next level;

[0028] sending the driving control signal to the driving module at a corresponding level of the target storage array to which the data is to be written and / or the driving module at a next level, so that the driving module receiving the driving control signal adjusts its own driving capability, wherein the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driving module at the next level;

[0029] The data paths corresponding to different storage arrays are used to receive different write control signals, and the write control signals are used to connect the data paths and the corresponding storage arrays.

[0030] The above-mentioned data writing method first generates a drive control signal based on the write control signal of each storage array. The drive control signal is used to adjust the driving capability of the driver module. Each level of the driver module is connected to multiple storage arrays of the corresponding layer and the driver module of the next layer, and can drive the data to be written to be transmitted to the data path corresponding to the multiple storage arrays of the corresponding layer and / or the driver module of the next layer. The drive control signal is then sent to the driver module of the corresponding layer of the target storage array to which the data is to be written and / or the driver module of the next layer, so that the driver module receiving the drive control signal adjusts its own driving capability. The adjusted driving capability is less than the driving capability required to transmit the data to be written to the driver module of the next layer. In this way, the multi-level driver module transmits the data to be written to the driver module of the corresponding layer of the target storage array step by step, i.e., stops transmitting the data to be written to the driver module of the next layer, and transmits the data to be written to the data path corresponding to the target storage array. Then, the data paths corresponding to different storage arrays receive different write control signals. The write control signals are used to connect the data paths and the corresponding storage arrays, and can further transmit the data to be written to the target storage array to achieve correct data writing. In addition, the write control signals only need to be time-matched with the data signals transmitted to the corresponding storage array, which greatly reduces the difficulty of time matching. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A schematic diagram of a data writing circuit in related technology;

[0033] Figure 2 is a structural schematic diagram of a data writing circuit according to an embodiment;

[0034] Figure 3 is a schematic structural diagram of a memory according to an embodiment;

[0035] Figure 4 FIG. 1 is a flow chart of a data writing method according to an embodiment of the present invention.

[0036] Description of reference numerals:

[0037] 110, data module, 120, controller, 130, storage array, 140, driver module;

[0038] 200, data writing circuit, 210, driving module, 220, control module, 230, storage array, 290, data module. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0041] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0042] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0043] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0044] DRAM is typically arranged in a two-dimensional matrix, with one capacitor and one transistor as a unit. The transistor's gate is electrically connected to the wordline (WL), the transistor's source is electrically connected to the bitline (BL), and the transistor's drain is electrically connected to the capacitor. The voltage on the wordline controls the transistor's on and off, allowing the bitline to read or write data stored in the capacitor.

[0045] The data writing process is implemented by the data writing circuit. Figure 1 It is a structural diagram of a data writing circuit in related technology, such as Figure 1 As shown, the data module 110 and the controller 120 are disposed on the same side of a plurality of memory arrays (banks) 130. The plurality of memory arrays 130 are arranged in a plurality of levels in a direction away from the data module 110 and the controller 120. Each level is provided with a driver module 140.

[0046] When writing data, the data module 110 sends a data signal to the first-level driver module 140. Each driver module 140 drives the data signal to the data paths of each storage array 130 at the same level, as well as the driver modules 140 at the next level. Each storage array 130 receives the data signal from the corresponding data path, thereby enabling the transmission of the data signal to any storage array 130.

[0047] The control process of transmitting the data signal to the storage array 130 to be written with data is as follows:

[0048] The controller 120 sends the write control signal of each storage array 130 to the first-level driver module 140. The driver module 140 of each level transmits the write control signal to the driver module 140 of the next level to determine whether to continue driving the data signal to the driver module 140 of the next level based on the write control signal.

[0049] Each driver module 140 performs a logical OR operation on the write control signals of the memory arrays 130 in the corresponding level and, based on the result of the logical OR operation, drives data signals to the data paths of the memory arrays 130 in the same level or to the driver module 140 in the next level. If the result of the logical OR operation is valid, the memory array 130 to be written is located in the memory array 130 in the level below the corresponding driver module 140. This driver module 140 drives the data signals to the driver module 140 in the next level based on the result of the logical OR operation. Conversely, if the result of the logical OR operation is invalid, the memory array 130 to be written is located in the memory array 130 in the level above the corresponding driver module 140. This driver module 140 drives the data signals to the data paths corresponding to the multiple memory arrays 130 in the corresponding level based on the result of the logical OR operation. It will be understood that in this case, the driver module 140 in the last level does not need to receive the write control signal and directly transmits the data signals to the data paths corresponding to the multiple memory arrays 130 in the corresponding level.

[0050] The controller 120 also sends a write control signal of each memory array 130 to the corresponding memory array 130. Each memory array 130 determines whether to receive a data signal from a corresponding data path according to the corresponding write control signal.

[0051] by Figure 1 For example, 16 storage arrays 130 are arranged in four levels ( Figure 1Only the first and second levels are shown. The first-level memory arrays 130 are BANK0, BANK1, BANK2, and BANK3, respectively, and their respective write control signals are WrtBnk0, WrtBnk1, WrtBnk2, and WrtBnk3, respectively. The second-level memory arrays 130 are BANK4, BANK5, BANK6, and BANK7, respectively, and their respective write control signals are WrtBnk4, WrtBnk5, WrtBnk6, and WrtBnk7, respectively. The third-level memory arrays 130 are BANK8, BANK9, BANK10, and BANK11, respectively, and their respective write control signals are WrtBnk8, WrtBnk9, WrtBnk10, and WrtBnk11, respectively. The fourth-level memory arrays 130 are BANK12, BANK13, BANK14, and BANK15, respectively, and their respective write control signals are WrtBnk12, WrtBnk13, WrtBnk14, and WrtBnk15, respectively.

[0052] The controller 120 sends the write control signals WrtBnk<15:0> of the 16 memory arrays 130 to the first-stage driver module 140. Each driver module 140 in each stage transmits the write control signals WrtBnk<15:0> to the next-stage driver module 140. The first-stage driver module 140 performs a logical OR operation on the write control signals WrtBnk<15:4> of the second through fourth-stage memory arrays 130 and, based on the result of the logical OR operation, drives data signals to the data paths of the four memory arrays 130 in the first stage or the second-stage driver module 140. The second-stage driver module 140 performs a logical OR operation on the write control signals WrtBnk<15:8> of the third through fourth-stage memory arrays 130 and, based on the result of the logical OR operation, drives data signals to the data paths of the four memory arrays 130 in the second stage or the third-stage driver module 140. That is, each driver module 140 receives write control signals from all memory arrays 130, but only drives the data signal to be transmitted to the corresponding data path or the next driver module 140 based on part of the write control signals, or does not drive the data signal to be transmitted to the corresponding data path based on the write control signals.

[0053] The controller 120 also sends the write control signals WrtBnk0, WrtBnk1, WrtBnk2, WrtBnk3, WrtBnk4, WrtBnk5, WrtBnk6, WrtBnk7, WrtBnk8, WrtBnk9, WrtBnk10, WrtBnk11, WrtBnk12, WrtBnk13, WrtBnk14, and WrtBnk15 of each storage array 130 to BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7, BANK8, BANK9, BANK10, BANK11, BANK12, BANK13, BANK14, and BANK15 respectively. For example, if BANK0 is the memory array 130 to which data is to be written, BANK0 receives a data signal from a corresponding data path according to a corresponding write control signal WrtBnk0, while other memory arrays 130 do not receive data signals from corresponding data paths according to their respective corresponding write control signals.

[0054] Therefore, in the related art, the data signal and the write control signal of each memory array 130 need to be time-matched to ensure that the data can be written correctly. As the capacity of DRAM increases, the number of memory arrays continues to increase, and the number of write control signals also increases, time matching becomes increasingly difficult.

[0055] Based on the above situation, the present application provides a data writing circuit. Figure 2 FIG. 1 is a structural diagram of a data writing circuit according to an embodiment of the present application. Figure 2 As shown, the data writing circuit 200 includes a multi-stage driving module 210 and a control module 220 .

[0056] Each level of driver module 210 is used to connect the multiple storage arrays 230 of the corresponding level and the driver module 210 of the next level, and to drive the transmission of the data to be written to the corresponding data path of the multiple storage arrays 230 of the corresponding level and / or the driver module 210 of the next level.

[0057] The control module 220 is connected to each level of the driver module 210 and is used to send a drive control signal WrtEn to the driver module 210 of the corresponding layer of the target storage array to which data is to be written and / or the driver module 210 of the next layer based on the write control signal WrtBnk of each storage array 230. The drive control signal WrtEn is used to adjust the driving capability of the driver module 210.

[0058] The data paths corresponding to different storage arrays 230 are used to receive different write control signals WrtBnk, and the write control signal WrtBnk is used to connect the data paths and the corresponding storage arrays 230 .

[0059] In one embodiment, the control module 220 sends a drive control signal WrtEn to the driver module 210 at the corresponding level of the target storage array where the data is to be written, based on the write control signal WrtBnk from each storage array 230. The driver module 210 at the corresponding level of the target storage array adjusts its drive capability to only drive the data to be written to the data path corresponding to the target storage array, and cannot drive the data to be written to the driver module 210 at the next level. Accordingly, the driver modules 210 at the previous level of the target storage array maintain their default drive capability and can drive the data to be written to the driver module 210 at the next level. In this way, the multiple levels of driver modules 210 cooperate with each other to transmit the data to be written from the first level of driver module 210 to the corresponding data path of the target storage array step by step. The target storage array then receives the data to be written from the corresponding data path based on the corresponding write control signal WrtBnk, thereby further transmitting the data to be written to the target storage array.

[0060] In another embodiment, the control module 220 sends a drive control signal WrtEn to the driver module 210 at the next level of the target storage array to which the data is to be written, based on the write control signal WrtBnk of each storage array 230. The driver module 210 at the next level of the target storage array adjusts its drive capability and is unable to drive the data to be written to the data paths corresponding to the multiple storage arrays 230 at the corresponding level, nor to the driver module 210 at the next level. Accordingly, the driver modules 210 at the previous level of the target storage array maintain their default drive capability and can drive the data to be written to the driver module 210 at the next level. In this way, the multiple levels of driver modules 210 cooperate with each other to transmit the data to be written from the first level of driver module 210 to the data path corresponding to the target storage array step by step.

[0061] That is to say, the present invention has two ideas for realizing that the data to be written is only written to the data path corresponding to the target storage array, and not written to the data path corresponding to the storage array 230 of the next level of the target storage array. The first is to change the driving capability of the driver module 210 of the corresponding level of the target storage array, so that the driver module 210 can only transmit the data to be written (data signal) to the data path of the corresponding level, but cannot transmit it to the driver module 210 of the next level; the second is to change the driving capability of the driver module 210 of the next level of the target storage array, so that the driver module 210 of the next level cannot transmit the data to the data path of the corresponding level after receiving the data, nor can it transmit it to the driver module 210 of the next level. It should be noted that the adjusted driving capability in this article that is less than the driving capability required for a certain action includes two types: "weakened and unable" and "lost and unable".

[0062] In the related art, each driver module 140 performs a logical judgment based on the write control signals WrtBnk of multiple storage arrays 130. When the logical judgment result is valid, the driver module 140 at the next level transmits the data signal to the driver module 140 at the corresponding level of the target storage array where the data is to be written. Therefore, the write control signals WrtBnk of each storage array 130 must be time-matched with the timing of the data signal being written to the corresponding data path to ensure accurate data writing. This can seriously affect the timing matching of the data signals when there are a large number of storage arrays 130. This is because as the target storage array reaches higher levels, the path time becomes longer and the interference it is subject to becomes greater, making timing matching very difficult. In the present application, the control module 220 generates a drive control signal WrtEn based on the write control signals WrtBnk of the plurality of storage arrays 230, and sends the drive control signal WrtEn to the drive module 210 of the corresponding layer of the target storage array to be written and / or the next-layer drive module 210, so as to prevent the data signal from being further transmitted. Before the data signal is blocked from transmission, there is no judgment step that may cause the data signal to wait or be delayed. Therefore, it is only necessary to ensure that the data signal and the write control signal WrtBnk of the target storage array maintain timing matching, without considering the impact of the judgment step on the timing, which is conducive to ensuring normal data writing.

[0063] For example, Figure 2 As shown, the control module 220 and the data module 290 are arranged on the same side of the multiple storage arrays 230, and the multiple storage arrays 230 are arranged in multiple levels in a direction away from the data module 290 and the control module 220, and each level is provided with multiple storage arrays 230 and a drive module 210.

[0064] The control module 220 includes a logic control device, such as a multiplexer, which sends a drive control signal WrtEn to the driver module 210 at the corresponding level of the target storage array to which data is to be written and / or to the driver module 210 at the next level, based on the write control signal WrtBnk of each storage array 230. The driver module 210 may include multiple cascaded inverters to drive the transmission of the data to be written to the corresponding data paths of the multiple storage arrays 230 at the corresponding level and / or to the driver module 210 at the next level. The driver module 210 may also include a switch to adjust its own driving capability based on the drive control signal WrtEn.

[0065] In one embodiment, the control module 220 is configured to send a driving control signal WrtEn to a corresponding level of driving module 210 and / or a next level of driving module 210 if the write control signals WrtBnk of multiple storage arrays 230 at the same level are at different levels.

[0066] In the above embodiment, the write control signals WrtBnk of the multiple storage arrays 230 of the same level are at different levels, indicating that one of the multiple storage arrays 230 of this level is a target storage array. In this case, sending the drive control signal WrtEn to the driver module 210 of the corresponding level and / or the driver module 210 of the next level can enable the driver module 210 of the corresponding level of the target storage array and / or the driver module 210 of the next level to adjust its own driving capability.

[0067] Accordingly, the control module 220 is configured to not send the drive control signal WrtEn to the corresponding driver module 210 and / or the next driver module 210 if the write control signals WrtBnk of multiple storage arrays 230 at the same level are at the same level, thereby avoiding unnecessary adjustment.

[0068] In one embodiment, the driving module 210 is configured to adjust its own driving capability upon receiving the driving control signal WrtBnk, wherein the adjusted driving capability is smaller than the driving capability required to transmit the to-be-written data to the next-level driving module 210 .

[0069] In the above embodiment, when the driving module 210 receives the driving control signal WrtBnk, it adjusts its own driving capability to be less than the driving capability required to transmit the data to be written to the driving module 210 of the next level, so that the driving module 210 that receives the driving control signal WrtBnk cannot transmit the data to be written to the driving module 210 of the next level, and the step-by-step transmission of the data to be written is stopped.

[0070] In one implementation, if the driver module 210 of the corresponding level of the target storage array receives the driving control signal WrtBnk, the adjusted driving capability is greater than or equal to the driving capability required by the data paths corresponding to the multiple storage arrays 230 of the corresponding level to transmit the data to be written.

[0071] In another implementation, if the driver module 210 at the next level of the target storage array receives the drive control signal WrtBnk, the adjusted drive capability may be greater than or equal to the drive capability required for transmitting the to-be-written data to the data paths corresponding to the multiple storage arrays 230 at the corresponding level, or may be less than the drive capability required for transmitting the to-be-written data to the data paths corresponding to the multiple storage arrays 230 at the corresponding level.

[0072] Exemplarily, the control module 220 is further configured to send a driving control signal WrtEn to each driving module 210 subsequent to the corresponding level of the target storage array.

[0073] In the above embodiment, the control module 220 sends the drive control signal WrtEn to each driver module 210 subsequent to the corresponding layer of the target storage array, so that each driver module 210 subsequent to the corresponding layer of the target storage array adjusts its own drive capability. In this way, all driver modules 210 that do not need to transmit data can be turned off. This avoids data transmission errors and additional power consumption caused by the normal data transmission of subsequent driver modules 210 when the driver modules 210 of the corresponding layer of the target storage array fail to operate normally.

[0074] In one embodiment, the control module 220 is further configured to send a write enable signal to the driver module 210 of each stage.

[0075] Correspondingly, the driving module 210 is further configured to drive the to-be-written data to be transmitted to the next-stage driving module 210 if the write enable signal is received but the drive control signal WrtEn is not received.

[0076] In the above embodiment, the control module 220 first sends a write enable signal to the driver modules 210 at each level, so that the driver modules 210 at each level have the ability to drive the data to be written to be transmitted to the driver modules 210 at the next level. Through the cooperation of the multiple levels of driver modules 210, the data to be written can be transmitted step by step to the driver modules 210 at the corresponding level of the target storage array.

[0077] Exemplarily, the data writing circuit 200 further includes an enable signal line connected to the control module 220 or the driving module 210 , and configured to transmit a write enable signal to the driving module 210 of each stage via the control module 220 or directly.

[0078] In the above embodiment, if the enable signal line is connected to the control module 220, the control module 220 transmits the write enable signal to the driver module 210 of each stage via the enable signal line. If the enable signal line is connected to the driver module 210, the write enable signal is directly transmitted to the driver module 210 of each stage via the enable signal line. Therefore, by providing the enable signal line, the write enable signal can be transmitted to the driver module 210 of each stage.

[0079] In one embodiment, the driver module 210 includes a first driver unit. The first driver unit is configured to, when not receiving the drive control signal WrtEn, drive the data to be written to be transmitted to the data paths corresponding to the plurality of storage arrays 230 at the corresponding level and to the driver module 210 at the next level; and, when receiving the drive control signal WrtEn, adjust its own driving capability, where the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driver module 210 at the next level.

[0080] Among them, when the control module 220 sends the driving control signal WrtEn to the driving module 210 of the next level of the target storage array to which data is to be written, the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays 230 of the corresponding level; when the control module 220 sends the driving control signal WrtEn to the driving module 210 of the corresponding level of the target storage array to which data is to be written, the adjusted driving capability is greater than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays 230 of the corresponding level.

[0081] In the above embodiment, if the driver modules 210 at the previous level corresponding to the target storage array do not receive the drive control signal WrtEn, the first driver unit can drive the data to be written to be transmitted to the data paths corresponding to the multiple storage arrays 230 at the corresponding level, as well as to the driver modules 210 at the next level. In this way, the data to be written can be transmitted step by step to the driver modules 210 at the corresponding level of the target storage array.

[0082] If the driver module 210 at the corresponding level of the target storage array receives the drive control signal WrtEn, the first driver unit adjusts its own drive capability. The adjusted drive capability is less than the drive capability required to transmit the data to be written to the driver module 210 at the next level, but greater than the drive capability required to transmit the data to be written to the data paths corresponding to the multiple storage arrays 230 at the corresponding level. The data to be written can then be driven to be transmitted to the data paths corresponding to the multiple storage arrays 230 at the corresponding level. In this way, the data to be written can be further transmitted to the data paths corresponding to the target storage array.

[0083] If the driver module 210 at the next level of the target storage array receives the drive control signal WrtEn, but the driver module 210 at the corresponding level of the target storage array does not receive the drive control signal WrtEn, the first driver unit at the corresponding level of the target storage array may drive the data to be written to be transmitted to the data paths corresponding to the multiple storage arrays 230 at the corresponding level and to the driver module 210 at the next level, thereby further transmitting the data to be written to the data paths corresponding to the target storage array. If the driver module 210 at the next level of the target storage array receives the drive control signal WrtEn, the first driver unit adjusts its own drive capability. If the adjusted drive capability is less than the drive capability required to transmit the data to be written to the driver module 210 at the next level and less than the drive capability required to transmit the data to be written to the data paths corresponding to the multiple storage arrays 230 at the corresponding level, the transmission of the data to be written is stopped.

[0084] In one embodiment, the driver module 210 includes a second driver unit and a third driver unit. The second driver unit is configured to drive the transmission of the data to be written to the corresponding data paths of the plurality of storage arrays 230 at the corresponding level. The third driver unit is configured to, when not receiving the drive control signal WrtEn, drive the transmission of the data to be written to the next-level driver module 210; and, when receiving the drive control signal WrtEn, adjust its own drive capability, where the adjusted drive capability is less than the drive capability required to transmit the data to be written to the next-level driver module 210.

[0085] If the driver module 210 at the corresponding level of the target storage array receives the drive control signal WrtEn, the third driver unit adjusts its own drive capability. The adjusted drive capability is less than the drive capability required to transmit the data to be written to the driver module 210 at the next level. In this case, the second driver unit can still drive the data to be written to the data paths corresponding to the multiple storage arrays at the corresponding level. In this way, the data to be written can be further transmitted to the data path corresponding to the target storage array.

[0086] If the driver module 210 at the next level of the target storage array receives the drive control signal WrtEn, and the driver module 210 at the corresponding level of the target storage array does not receive the drive control signal WrtEn, the third driver unit at the corresponding level of the target storage array can drive the data to be written to be transmitted to the driver module 210 at the next level. At this time, the second driver unit can still drive the data to be written to be transmitted to the data paths corresponding to the multiple storage arrays at the corresponding level, thereby further transmitting the data to be written to the data paths corresponding to the target storage array. When the driver module 210 at the next level of the target storage array receives the drive control signal WrtEn, the third driver unit adjusts its own driving capability. If the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driver module 210 at the next level, the transmission of the data to be written is stopped.

[0087] Exemplarily, the second driving unit is configured to adjust its own driving capability upon receiving the driving control signal WrtEn, wherein the adjusted driving capability is greater than the driving capability required for transmitting the to-be-written data to the data paths corresponding to the plurality of storage arrays 230 at the corresponding level.

[0088] In the above embodiment, when the driver module 210 at the corresponding level of the target storage array receives the drive control signal WrtEn, the second driver unit adjusts its drive capability. The adjusted drive capability is greater than the drive capability required to transmit the data to be written to the data paths corresponding to the multiple storage arrays 230 at the corresponding level, thereby further transmitting the data to be written to the data paths corresponding to the target storage array. When the driver module 210 at the corresponding level of the non-target storage array does not receive the drive control signal WrtEn, the drive capability of the second driver unit is less than the drive capability required to transmit the data to be written to the data paths corresponding to the multiple storage arrays 230 at the corresponding level, thereby reducing unnecessary transmission.

[0089] In one embodiment, the drive control signal includes a first sub-control signal and a second sub-control signal, and the drive module includes a fourth drive unit and a fifth drive unit. The fourth drive unit is used to adjust its own drive capability when receiving the first sub-control signal, and the adjusted drive capability is greater than the drive capability required to transmit the data to be written to the data path corresponding to the multiple storage arrays 230 of the corresponding level. The fifth drive unit is used to drive the data to be written to be transmitted to the next-level drive module 210 when the second sub-control signal is not received; and to adjust its own drive capability when receiving the second sub-control signal, and the adjusted drive capability is less than the drive capability required to transmit the data to be written to the next-level drive module 210. In other words, the first sub-control signal and the second sub-control signal can be two independent signals.

[0090] In the above embodiment, if the driver modules 210 at the previous level corresponding to the target storage array do not receive the first sub-control signal and the second sub-control signal, and the driving capability of the fourth driver unit is less than the driving capability required to transmit the data to be written to the data paths corresponding to the multiple storage arrays 230 at the corresponding level, the fifth driver unit can drive the data to be written to be transmitted to the driver module 210 at the next level. In this way, the data to be written can be transmitted step by step from the first-level driver module 210 to the driver modules 210 at the corresponding level of the target storage array.

[0091] When the driver module 210 at the corresponding level of the target storage array receives the first sub-control signal, the fourth driver unit adjusts its own driving capability. The adjusted driving capability is greater than the driving capability required to transmit the data to be written to the data paths corresponding to the multiple storage arrays 230 at the corresponding level. The fourth driver unit can then drive the data to be written to the data paths corresponding to the multiple storage arrays at the corresponding level. This allows the data to be written to be further transmitted to the data paths corresponding to the target storage array.

[0092] The driver module 210 of the corresponding level or the next level of the target storage array receives the second sub-control signal, and the fifth driver unit adjusts its own driving capability. The adjusted driving capability is less than the driving capability required to transmit the data to be written to the driver module 210 of the next level, and the transmission of the data to be written is stopped.

[0093] Based on the same inventive concept, the present application also provides a memory. Figure 3 This is a schematic diagram of the structure of a memory according to an embodiment of the present application. Figure 3 As shown, the memory includes multiple memory arrays 230 and a data writing circuit 200. The memory includes multiple memory arrays 230 and the aforementioned data writing circuit 200, which can effectively reduce the difficulty of time matching while correctly writing the data to be written into the target memory array.

[0094] Based on the same inventive concept, the present application also provides a data writing method. Figure 4 This is a flow chart of a data writing method according to an embodiment of the present application. Figure 4 As shown, the data writing method includes the following steps:

[0095] S401: Generate a drive control signal based on the write control signal of each storage array. The drive control signal is used to adjust the drive capability of the drive module. Each level of the drive module is used to connect multiple storage arrays at a corresponding level and the drive module at the next level, and to drive the data to be written to the data path corresponding to the multiple storage arrays at the corresponding level and / or to the drive module at the next level.

[0096] S402, sending a driving control signal to a driving module at a corresponding level of a target storage array to which data is to be written and / or a driving module at a next level, so that the driving module receiving the driving control signal adjusts its own driving capability, wherein the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driving module at the next level.

[0097] The data paths corresponding to different storage arrays are used to receive different write control signals, and the write control signals are used to connect the data paths and the corresponding storage arrays.

[0098] The above-mentioned data writing method first generates a drive control signal based on the write control signal of each storage array. The drive control signal is used to adjust the driving capability of the driver module. Each level of the driver module is connected to multiple storage arrays of the corresponding layer and the driver module of the next layer, and can drive the data to be written to be transmitted to the data path corresponding to the multiple storage arrays of the corresponding layer and / or the driver module of the next layer. The drive control signal is then sent to the driver module of the corresponding layer of the target storage array to which the data is to be written and / or the driver module of the next layer, so that the driver module receiving the drive control signal adjusts its own driving capability. The adjusted driving capability is less than the driving capability required to transmit the data to be written to the driver module of the next layer. In this way, the multi-level driver module transmits the data to be written to the driver module of the corresponding layer of the target storage array step by step, i.e., stops transmitting the data to be written to the driver module of the next layer, and transmits the data to be written to the data path corresponding to the target storage array. Then, the data paths corresponding to different storage arrays receive different write control signals. The write control signals are used to connect the data paths and the corresponding storage arrays, and can further transmit the data to be written to the target storage array to achieve correct data writing. In addition, the write control signals only need to be time-matched with the data signals transmitted to the corresponding storage array, which greatly reduces the difficulty of time matching.

[0099] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0100] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A data writing circuit, characterized in that: include: Multi-level driver modules, each level of the driver modules is used to connect the multiple storage arrays of the corresponding level and the driver modules of the next level, and is used to drive the transmission of data to be written to the data paths corresponding to the multiple storage arrays of the corresponding level and / or to the driver modules of the next level; a control module connected to each level of the driver modules and configured to send a drive control signal to the driver module at the corresponding level of the target storage array to which the data is to be written and / or the driver module at the next level according to the write control signal of each storage array, wherein the drive control signal is used to adjust the drive capability of the driver module; wherein the timing of the write control signal corresponding to the target storage array matches the timing of the data signal containing the data to be written; The data paths corresponding to different storage arrays are used to receive different write control signals, and the write control signals are used to connect the data paths and the corresponding storage arrays.

2. The circuit according to claim 1, wherein: The control module is configured to send the driving control signal to the driving module at the corresponding level and / or the driving module at the next level if the write control signals of the plurality of storage arrays at the same level are at different levels.

3. The circuit according to claim 2, characterized in that The driving module is configured to adjust its own driving capability upon receiving the driving control signal, wherein the adjusted driving capability is smaller than the driving capability required for transmitting the to-be-written data to the next-level driving module.

4. The circuit according to claim 3, characterized in that The control module is further configured to send the driving control signal to the driving modules at each level subsequent to the corresponding level of the target storage array.

5. The circuit according to any one of claims 1 to 4, characterized in that: The driving module includes: a first driving unit, configured to, when not receiving the driving control signal, drive the data to be written to be transmitted to the data paths corresponding to the plurality of storage arrays at the corresponding level and to the driving module at the next level; and, when receiving the driving control signal, adjust its own driving capability, wherein the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driving module at the next level; When the control module sends a driving control signal to the driving module at the next level of the target storage array to which the data is to be written, the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays at the corresponding level; when the control module sends a driving control signal to the driving module at the corresponding level of the target storage array to which the data is to be written, the adjusted driving capability is greater than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays at the corresponding level.

6. The circuit according to any one of claims 1 to 4, characterized in that: The driving module includes: A second driving unit, configured to drive the data to be written to be transmitted to data paths corresponding to the plurality of storage arrays at a corresponding level; The third driving unit is used to drive the data to be written to be transmitted to the driving module of the next level when the driving control signal is not received; and when the driving control signal is received, adjust its own driving capability, and the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the driving module of the next level.

7. The circuit according to claim 6, characterized in that The second driving unit is configured to adjust its own driving capability upon receiving the driving control signal, wherein the adjusted driving capability is greater than the driving capability required for transmitting the to-be-written data to the data paths corresponding to the plurality of storage arrays at the corresponding level.

8. The circuit according to any one of claims 1 to 4, characterized in that: The driving control signal includes a first sub-control signal and a second sub-control signal, and the driving module includes: a fourth driving unit, configured to adjust its own driving capability upon receiving the first sub-control signal, wherein the adjusted driving capability is greater than a driving capability required by data paths corresponding to the plurality of storage arrays at a corresponding level for transmitting the to-be-written data; a fifth driving unit, configured to drive the data to be written to be transmitted to the driving module of the next level when the second sub-control signal is not received; and to adjust its own driving capability when the second sub-control signal is received, wherein the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driving module of the next level.

9. A memory, characterized in that: The device comprises a plurality of storage arrays and a data writing circuit as claimed in any one of claims 1 to 8.

10. A data writing method, characterized in that: include: Generate a drive control signal based on the write control signal of each storage array, wherein the drive control signal is used to adjust the driving capability of the drive module. The drive module at each level is used to connect the multiple storage arrays at the corresponding level and the drive module at the next level, and to drive the data to be written to the data path corresponding to the multiple storage arrays at the corresponding level and / or the drive module at the next level; sending the driving control signal to the driving module at a corresponding level of the target storage array to which the data is to be written and / or the driving module at a next level, so that the driving module receiving the driving control signal adjusts its own driving capability, wherein the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driving module at the next level; The data paths corresponding to different storage arrays are used to receive different write control signals, and the write control signals are used to connect the data paths and the corresponding storage arrays.

Images