Memory and electronic device

Abstract

The present disclosure provides a memory and an electronic device, wherein an external clock signal and N internal clock signals are present in the memory, the external clock signal is used to sample a data signal received from the outside, and the N internal clock signals are used to sample and generate a data signal sent to the outside; based on a test selection signal, a selection circuit outputs one of the N internal clock signals and the external clock signal as a detection clock signal.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory and an electronic device. Background Art

[0002] To achieve higher data processing speeds, memories use delay-locked loops (PLLs) to generate multiple internal clock signals with sequentially offset phases. These signals are used to sample and generate the data signals sent externally. However, because these multiple internal clock signals are packaged as a data strobe clock signal and then transmitted externally, it's difficult for testers to obtain information about the internal clock signals, making it difficult to debug the memory. Summary of the Invention

[0003] The present disclosure provides a memory and an electronic device.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, the memory comprising:

[0006] A clock receiving circuit is configured to generate an external clock signal based on a data selection clock signal received from the outside; wherein the data selection clock signal is used to sample a data signal received synchronously from the outside; a clock generating circuit includes a delay phase-locked loop, configured to generate N internal clock signals through the delay phase-locked loop; wherein the N internal clock signals are used to perform data sampling processing to generate a data signal sent to the outside; a selection circuit is connected to both the clock receiving circuit and the clock generating circuit, and is configured to output one of the N internal clock signals and the external clock signal as a detection clock signal based on a test selection signal; N is a positive integer.

[0007] In some embodiments, the clock generation circuit further includes N clock tree units, the output end of each clock tree unit includes a first type of signal end and a second type of signal end, and the first type of signal end and the second type of signal end are symmetrically distributed; the first type of signal end includes multiple low-order data ends, low-order clock ends and redundant ports, and the second type of signal end includes multiple high-order data ends, high-order clock ends and local clock ports; the i-th clock tree unit is connected to the delay phase-locked loop and is configured to transmit the i-th internal clock signal to the first type of signal end based on the enable signal group; or, based on the enable signal group, transmit the i-th internal clock signal to the second type of signal end; or, based on the enable signal group, transmit the i-th internal clock signal to the first type of signal end and the second type of signal end; i is a positive integer, i≤N; the selection circuit is connected to the N local clock ports and is configured to receive the N internal clock signals from the local clock port.

[0008] In some embodiments, the clock generation circuit further includes N clock tree units, the output end of each clock tree unit includes a first type of signal end and a second type of signal end, and the first type of signal end and the second type of signal end are symmetrically distributed; the first type of signal end includes multiple low-order data ends, low-order clock ends and local clock ports, and the second type of signal end includes multiple high-order data ends, high-order clock ends and redundant ports; the i-th clock tree unit is connected to the delay locked loop and is configured to transmit the i-th internal clock signal to the first type of signal end based on the enable signal group; or, based on the enable signal group, transmit the i-th internal clock signal to the second type of signal end; or, based on the enable signal group, transmit the i-th internal clock signal to the first type of signal end and the second type of signal end; the selection circuit is connected to the N local clock ports and is configured to receive the N internal clock signals from the local clock port.

[0009] In some embodiments, the enable signal group includes a first enable signal, a second enable signal, a third enable signal and a test enable signal, and each of the clock tree units includes a first transmission unit, a second transmission unit and a third transmission unit; the i-th first transmission unit is configured to delay the transmission of the i-th internal clock signal when the first enable signal or the test enable signal is in a valid state, thereby generating the i-th first transmission signal and the i-th second transmission signal; wherein the level state of the i-th first transmission signal is the same as the level state of the i-th second transmission signal; the i-th second transmission unit is connected to the i-th first transmission unit, and is configured to transmit the i-th first transmission signal to each of the first-type signal terminals when the second enable signal is in a valid state, so as to realize the transmission of the i-th internal clock signal to each first-type signal terminal; the i-th third transmission unit is connected to the i-th first transmission unit and is configured to transmit the i-th second transmission signal to each second-type signal terminal when the third enable signal or the test enable signal is in a valid state, so as to realize the transmission of the i-th internal clock signal to each second-type signal terminal; wherein, the test enable signal in a valid state indicates that the memory is in a test mode; when the memory is in a first output mode, the first enable signal and the second enable signal are both in a valid state and the third enable signal is in an invalid state; when the memory is in a second output mode, the first enable signal, the second enable signal and the third enable signal are all in a valid state, and the number of data signal bits of the second output mode is twice that of the data signal bit of the first output mode.

[0010] In some embodiments, each of the first transmission units includes a first transmission path and a first gating unit; each of the second transmission units includes a second gating unit and a second transmission path group; each of the third transmission units includes a third gating unit and a third transmission path group; the input end of the i-th first transmission path receives the i-th internal clock signal, the first input end of the i-th first gating unit is connected to the output end of the i-th first transmission path, the second input end of the i-th first gating unit receives the first enable signal, the third input end of the i-th first gating unit receives the test enable signal, the first output end of the i-th first gating unit outputs the i-th first transmission signal, and the second output end of the i-th first gating unit outputs the i-th second transmission signal; the first The input end receives the i-th first transmission signal, the second input end of the i-th second gating unit receives the second enable signal, the input end of each transmission path in the i-th second transmission path group is connected to the output end of the second gating unit, and the output end of a transmission path in the i-th second transmission path group forms a first-type signal end; the first input end of the i-th third gating unit receives the i-th second transmission signal, the second input end of the i-th third gating unit receives the third enable signal, the third input end of the i-th third gating unit receives the test enable signal, the input end of each transmission path in the i-th third transmission path group is connected to the output end of the third gating unit, and the output end of a transmission path in the i-th third transmission path group forms a second-type signal end.

[0011] In some embodiments, when the valid states of the first enable signal, the second enable signal, the third enable signal and the test enable signal are all high, the first gating unit includes a first AND gate, a second AND gate, and a first OR gate; the first input end of the first AND gate and the first input end of the second AND gate are both connected to the output end of the first transmission path, the second input end of the first AND gate and the first input end of the first OR gate both receive the first enable signal, the second input end of the first OR gate receives the test enable signal, the output end of the first OR gate is connected to the second input end of the second AND gate, the output end of the first AND gate outputs the first transmission signal, and the output end of the second AND gate outputs the second transmission signal; the second gating unit includes a third AND gate and a fourth AND gate; the first input end of the third AND gate and the first input end of the fourth AND gate both receive the first transmission signal, the third The second input end of the AND gate and the second input end of the fourth AND gate both receive the second enable signal, the output end of the third AND gate is connected to a part of the transmission paths in the second transmission path group, and the output end of the fourth AND gate is connected to another part of the transmission paths in the second transmission path group; the third gating unit includes a fifth AND gate, a sixth AND gate, and a second OR gate; the first input end of the fifth AND gate and the first input end of the sixth AND gate both receive the second transmission signal, the second input end of the fifth AND gate and the first input end of the second OR gate both receive the third enable signal, the second input end of the second OR gate receives the test enable signal, the output end of the second OR gate is connected to the second input end of the sixth AND gate, the output end of the fifth AND gate is connected to a part of the transmission paths in the third transmission path group, and the output end of the sixth AND gate is connected to another part of the transmission paths in the third transmission path group.

[0012] In some embodiments, the test selection signal includes A first selection signals and a second selection signal; the selection circuit is specifically configured to receive A first selection signals and a second selection signal, and when the second selection signal is in an invalid state, based on the A first selection signals, output one of the multiple internal clock signals as a detection clock signal; when the second selection signal is in a valid state, output the external clock signal as a detection clock signal; wherein, 2A≥N.

[0013] In some embodiments, the selection circuit includes: a preprocessing unit, configured to perform logical processing on A first selection signals and a second selection signal to generate N fourth enable signals; wherein, when the second selection signal is in an invalid state, based on the A first selection signals, the N fourth enable signals are controlled to have and only have one fourth enable signal in a valid state; when the second selection signal is in a valid state, the N fourth enable signals are controlled to be in an invalid state; a first selection unit, configured to output the i-th internal clock signal as an intermediate clock signal when the i-th fourth enable signal is in a valid state; and to keep the level state of the intermediate clock signal unchanged when the N fourth enable signals are in an invalid state; a second selection unit, configured to output the intermediate clock signal as the detection clock signal when the second selection signal is in an invalid state; and to output the external clock signal as the detection clock signal when the second selection signal is in a valid state.

[0014] In some embodiments, when N=4 and A=2, the pre-processing unit includes a first logic unit and a second logic unit; the first logic unit is configured to perform a negation operation on the first first selection signal to generate a first inverted signal, and perform a negation operation on the first inverted signal to generate a first positive signal; perform a negation operation on the second first selection signal to generate a second inverted signal, and perform a negation operation on the second inverted signal to generate a second positive signal; perform a negation operation on the second selection signal to generate a third inverted signal, and perform a negation operation on the third inverted signal to generate a third positive signal; and perform a negation operation on the third positive signal. The signal is NOT operated to generate a fourth inverted signal; the second logic unit is configured to perform logic processing on the first inverted signal, the second inverted signal and the fourth inverted signal to generate the first fourth enable signal; perform logic processing on the second inverted signal, the first positive phase signal and the fourth inverted signal to generate the second fourth enable signal; perform logic processing on the second positive phase signal, the first inverted signal and the fourth inverted signal to generate the third fourth enable signal; perform logic processing on the second positive phase signal, the first positive phase signal and the fourth inverted signal to generate the fourth fourth enable signal.

[0015] In some embodiments, when the valid state of the fourth enable signal is a high level and the valid state of the second selection signal is a low level, the second logic unit includes a first NAND gate, a first NOR gate, a second NAND gate, a second NOR gate, a third NAND gate, a third NOR gate, a fourth NAND gate, and a fourth NOR gate; the first input end of the first NAND gate receives a first inverted signal, the second input end of the first NAND gate receives a second inverted signal, the first input end of the first NOR gate is connected to the output end of the first NAND gate, the second input end of the first NOR gate receives the fourth inverted signal, and the output end of the first NOR gate outputs the first fourth enable signal; the first input end of the second NAND gate receives a first positive phase signal, the second input end of the second NAND gate receives a second inverted signal, and the first input end of the second NOR gate is connected to the output end of the second NAND gate. The first input terminal of the third NAND gate receives the first inverted signal, the second input terminal of the third NAND gate receives the second positive signal, the first input terminal of the third NOR gate is connected to the output terminal of the third NAND gate, the second input terminal of the third NOR gate receives the fourth inverted signal, and the output terminal of the third NOR gate outputs the third fourth enable signal; the first input terminal of the fourth NAND gate receives the first positive signal, the second input terminal of the fourth NAND gate receives the second positive signal, the first input terminal of the fourth NOR gate is connected to the output terminal of the fourth NAND gate, the second input terminal of the fourth NOR gate receives the fourth inverted signal, and the output terminal of the fourth NOR gate outputs the fourth fourth enable signal.

[0016] In some embodiments, the first selection unit includes a first selector, a second selector, and a third selector; the first selector is configured to output the first internal clock signal as a first preselected signal when the first fourth enable signal is in a valid state; output the second internal clock signal as the first preselected signal when the second fourth enable signal is in a valid state; the second selector is configured to output the third internal clock signal as a second preselected signal when the third fourth enable signal is in a valid state; and output the fourth internal clock signal as a second preselected signal when the fourth fourth enable signal is in a valid state. The four internal clock signals are output as the second pre-selected signal; the third selector is configured to output the first pre-selected signal as the intermediate clock signal when the second inverted signal is in a valid state; and output the second pre-selected signal as the intermediate clock signal when the second positive signal is in a valid state; the second selection unit includes a fourth selector; the fourth selector is configured to output the intermediate clock signal as the detection clock signal when the third positive signal is in a valid state; and output the external clock signal as the detection clock signal when the third inverted signal is in a valid state.

[0017] In some embodiments, any one of the first selector, the second selector, the third selector and the fourth selector includes a fifth NAND gate, a sixth NAND gate, a seventh NAND gate and an eighth NAND gate; the first input end of the fifth NAND gate forms the first control end of the corresponding selector, the second input end of the fifth NAND gate forms the first input end of the corresponding selector, the first input end of the sixth NAND gate forms the second control end of the corresponding selector, the second input end of the sixth NAND gate forms the second input end of the corresponding selector, the first input end of the seventh NAND gate and the first input end of the eighth NAND gate are connected to the output end of the fifth NAND gate, the second input end of the seventh NAND gate and the second input end of the eighth NAND gate are connected to the output end of the sixth NAND gate; the output end of the seventh NAND gate and the output end of the eighth NAND gate are connected to form the output end of the corresponding selector; for the first selector, its first control end receives the first fourth enable signal, and its first input end receives the first internal clock signal signal, its second control end receives the second fourth enable signal, its second input end receives the second internal clock signal, and its output end outputs the first pre-selected signal; for the second selector, its first control end receives the third fourth enable signal, its first input end receives the third internal clock signal, its second control end receives the fourth fourth enable signal, its second input end receives the fourth internal clock signal, and its output end outputs the second pre-selected signal; for the third selector, its first control end receives the second inverted signal, its first input end receives the first pre-selected signal, its second control end receives the second positive phase signal, its second input end receives the second pre-selected signal, and its output end outputs the intermediate clock signal; for the fourth selector, its first control end receives the third positive phase signal, its first input end receives the intermediate clock signal, its second control end receives the third inverted signal, its second input end receives the external clock signal, and its output end outputs the detection clock signal.

[0018] In some embodiments, the memory further includes N transmission driving units, the input ends of the N transmission driving units are connected one-to-one with the N local clock ends, and the output ends of the N transmission driving units are connected one-to-one with the N input ends of the selection circuit.

[0019] In some embodiments, the memory further includes a data driving circuit; the data driving circuit includes a pull-up driving unit and a pull-down driving unit, configured to receive the detection clock signal, use the pull-up driving unit to pull-up the detection clock signal, and use the pull-down driving unit to pull-down the detection clock signal.

[0020] In a second aspect, an embodiment of the present disclosure provides an electronic device, which includes the memory as described in the first aspect.

[0021] Embodiments of the present disclosure provide a memory and an electronic device, which can output one of N internal clock signals and an external clock signal as a detection clock signal, thereby conveniently debugging the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of the structure of another memory provided in an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of the structure of a clock tree unit provided in an embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of the specific structure of a clock tree unit provided in an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of the specific structure of another clock tree unit provided in an embodiment of the present disclosure;

[0027] Figure 6 A schematic diagram of the structure of another memory provided in an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of the structure of a selection circuit provided in an embodiment of the present disclosure;

[0029] Figure 8 A schematic diagram of a partial structure of a selection circuit provided in an embodiment of the present disclosure Figure 1 ;

[0030] Figure 9 A schematic diagram of a partial structure of a selection circuit provided in an embodiment of the present disclosure Figure 2 ;

[0031] Figure 10 A schematic structural diagram of another selection circuit provided in an embodiment of the present disclosure;

[0032] Figure 11 A schematic structural diagram of another selection circuit provided in an embodiment of the present disclosure;

[0033] Figure 12 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The following, in conjunction with the accompanying drawings, provides a clear and complete description of the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are intended solely to illustrate the related applications and are not intended to limit those applications. It should also be noted that, for ease of description, only portions of the drawings related to the related applications are shown. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure relates. The terms used herein are for the purpose of describing the embodiments of the present disclosure only and are not intended to limit the present disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it should be understood that "some embodiments" may refer to the same or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first," "second," and "third" in the embodiments of the present disclosure are used solely to distinguish similar objects and do not represent a specific ordering of the objects. It should be understood that "first," "second," and "third" may be interchanged in a specific order or sequential order, where permitted, to enable the embodiments of the present disclosure described herein to be implemented in an order other than that illustrated or described.

[0035] The following are explanations of professional terms involved in the embodiments of this disclosure and the corresponding relationships between some terms:

[0036] Dynamic Random Access Memory (DRAM);

[0037] Synchronous Dynamic Random Access Memory (SDRAM);

[0038] Double Data Rate SDRAM (DDR);

[0039] Fourth generation DDR (DDR4);

[0040] Fifth generation DDR (5th DDR, DDR5);

[0041] Delay Locked Loop (DLL).

[0042] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0043] For DDR4, only one internal clock signal is needed on the read path to achieve data sampling and output. This internal clock signal subsequently generates a data strobe clock signal DQS_out, which is sent out through the memory's data strobe clock port (DQS port). Therefore, the internal clock information can be displayed through the DQS port, making it easier for testers to debug. However, due to the significant increase in the data processing speed of DDR5, it needs to use four internal clock signals with the same clock period but 90 degrees different phases on the read path to achieve data sampling and output. These four internal clock signals are synthesized and packaged to form the data strobe clock signal DQS_out and sent to the outside through the DQS port. Therefore, the internal clock information cannot be checked through the DQS port.

[0044] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic structural diagram of a memory 10 provided by an embodiment of the present disclosure. Figure 1 As shown, the memory 10 includes:

[0045] The clock receiving circuit 11 is configured to generate an external clock signal based on a data strobe clock signal received from the outside; wherein the data strobe clock signal is used to sample a data signal synchronously received from the outside;

[0046] The clock generating circuit 12 includes a delay phase locked loop 121, which is configured to generate N internal clock signals (i.e. Figure 1 CLKI, CLKQ, CLKIB, CLKQB); wherein the N internal clock signals are used for data sampling processing to generate data signals sent to the outside;

[0047] The selection circuit 13 is connected to both the clock receiving circuit 11 and the clock generating circuit 12 , and is configured to output one of the N internal clock signals and the external clock signal as a detection clock signal based on a test selection signal.

[0048] It should be noted that the memory 10 may be a high-speed memory, such as DRAM, SDRAM, SRAM, etc. In other words, any memory that performs internal processing through multiple internal clock signals can be applied to this embodiment.

[0049] It should be understood that during a write operation, an external device (e.g., a memory controller) synchronously sends a data signal Data_in and a data strobe clock signal DQS_in to the memory 10. The data strobe clock signal DQS_in is used to sample the data signal Data_in. In some embodiments, the data strobe clock signal DQS_in includes two clock signals with opposite phases, namely a first data strobe clock signal DQS_T and a second data strobe clock signal DQS_B. The clock receiving circuit 11 receives the first data strobe clock signal DQS_T and the second data strobe clock signal DQS_B from the outside and generates an external clock signal based on the first data strobe clock signal DQS_T and the second data strobe clock signal DQS_B. The external clock signal will then sample the received data signal Data_in for writing into the internal storage unit.

[0050] Similarly, during a read operation, the memory 10 reads the internal storage cells to generate the data signal Data_0. The delay-locked loop 121 generates N internal clock signals, which are used to sample the data signal Data_0 to form the data signal Data_out. The data signal Data_out is then transmitted to an external device (e.g., a memory controller). The N internal clock signals are then packaged into a data strobe clock signal DQS_out and transmitted to the external device, so that the external device can sample and process the received data signal Data_out using the received data strobe clock signal DQS_out. Here, the data strobe clock signal DQS_out also includes at least two clock signals with opposite phases.

[0051] On this basis, the memory 10 is also provided with a selection circuit 13, which can output an external clock signal during a write operation or any internal clock signal during a read operation, so that the tester can obtain any internal clock signal or external clock signal without executing the "read operation instruction READ" or the "write operation instruction Write". It can not only detect the quality of the clock signal, but also adjust the memory 10 to obtain the best storage performance, for example, by adjusting the internal clock signal to obtain an excellent valid data window time (DVW).

[0052] Here, the specific parameter value of the test selection signal can be adjusted by the tester to select which specific clock signal to obtain. In addition, "connection" means that different modules are directly connected through their respective ports, or that the respective ports of different modules are indirectly connected through other components, modules, etc.

[0053] It should be noted that Figure 1Only N=4 is used as an example for illustration, but the value of N can be any positive integer, such as 2, 3, 6, etc. In some embodiments, the clock periods of the N internal clock signals are the same and the phase difference (within the allowable error range) of each internal clock signal relative to the previous internal clock signal is a preset value. At this time, the phase difference (within the allowable error range) between the two adjacent internal clock signals is 90 degrees. The embodiments of this disclosure are subsequently described using N=4 as an example. Please refer to this for understanding other situations.

[0054] See Figure 2 The clock generation circuit 12 further includes N clock tree units 122 , the input ends of the N clock tree units 122 are linked to the output ends of the delay phase-locked loop 121 in a one-to-one correspondence, and each clock tree unit 122 is used to transmit an internal clock signal.

[0055] Specifically, the output signals of the delay-locked loop 121 are denoted as CLKI_0, CLKQ_0, CLKIB_0, and CLKQB_0, respectively. The first clock tree unit 122 is configured to transmit CLKI_0 to generate CLKI, the second clock tree unit 122 is configured to transmit CLKQ_0 to generate CLKQ, the third clock tree unit 122 is configured to transmit CLKIB_0 to generate CLKIB, and the fourth clock tree unit 122 is configured to transmit CLKQB_0 to generate CLKQB. It should be understood that since the clock tree units 122 merely transmit signals without changing their waveforms, the signals CLKI_0, CLKBQ_0, CLKIB_0, and CLKQB_0 received by the clock tree units 122 can be considered "N internal clock signals." Simultaneously, the signals CLKI, CLKBQ, CLKIB, and CLKQB output by the clock tree circuit 122 can also be considered "N internal clock signals."

[0056] In some embodiments, the N clock tree units 122 have the same structure. Figure 3 As shown, the output terminals of each clock tree unit 122 include first-type signal terminals (i.e., LDQ0-LDQ7, LDQS, and redundant ports) and second-type signal terminals (i.e., HDQ0-HDQ7, HDQS, and LBDQS), with the first-type signal terminals and the second-type signal terminals being symmetrically distributed. The first-type signal terminals include multiple low-order data terminals (i.e., LDQ0-LDQ7), a low-order clock terminal (i.e., LDQS), and redundant ports, while the second-type signal terminals include multiple high-order data terminals (i.e., HDQ0-HDQ7), a high-order clock terminal (i.e., HDQS), and a local clock port (i.e., LBDQS).

[0057] The i-th clock tree unit 122 is connected to the delay locked loop 121 and is configured to transmit the i-th internal clock signal to the first type signal terminal based on the enable signal group; or, based on the enable signal group, transmit the i-th internal clock signal to the second type signal terminal; or, based on the enable signal group, transmit the i-th internal clock signal to the first type signal terminal and the second type signal terminal; i is a positive integer, i≤N;

[0058] The selection circuit 13 is connected to the N local clock ports and is configured to receive the N internal clock signals from the local clock ports when the N internal clock signals are transmitted to each second-type signal port.

[0059] It should be noted that if Figure 3 As shown, each clock tree unit 122 has an input terminal, a first-type signal terminal, and a second-type signal terminal. For any clock tree unit 122, the delay between its input terminal and any of its first-type signal terminals (within an allowable error range) is a preset delay value, and the delay between its input terminal and any of its second-type signal terminals (within an allowable error range) is also a preset delay value. This ensures that the transmission delays of different internal clock signals along different paths within the clock tree unit 122 are consistent.

[0060] In a specific embodiment, the data signal Data_out sent by the memory 10 to the outside actually includes Data <0> 、Data <1> ...Data <15> A set of signals. Data<7:0> is called the low-order data signal, and Data<15:8> is called the high-order data signal. If the memory 10 is in the first output mode (x8), only Data<7:0> is enabled. If the memory 10 is in the second output mode (x16), both Data<15:0> are enabled.

[0061] Based on this, the functions of the internal clock signals at different ports in the clock tree unit 122 are as follows:

[0062] (1) For the internal clock signal transmitted to the low-order data terminal (LDQ0 to LDQ7), it is used to sample the data signal to form the low-order data signal Data<7:0> sent to the outside; for example, for the internal clock signal transmitted to the low-order data terminal LDQ0, it is used to sample the data signal to form the low-order data signal Data<7:0> sent to the outside. <0> .

[0063] (2) The internal clock signal transmitted to the low-order clock terminal LDQS is subsequently packaged to form a data selection clock signal.

[0064] (3) Redundant ports are only for structural symmetry and have no practical significance.

[0065] (4) For the internal clock signal transmitted to the high-order data terminal (HDQ0~HDQ7), it is used to sample the data signal to form the high-order data signal Data<15:8> sent to the outside; for example, for the internal clock signal transmitted to the low-order data terminal LDQ0, it is used to sample the data signal to form Data<15:8>. <8> .

[0066] (5) The internal clock signal transmitted to the high-bit clock terminal HDQS is subsequently encapsulated to form a data selection clock signal.

[0067] (6) The internal clock signal transmitted to the local clock terminal LBDQS is subsequently transmitted to the selection circuit 13 for testing.

[0068] So, for Figure 3 For example, the local clock end LBDQS is implemented by using the transmission path related to high-order data sampling (or called x16 path), that is, the local clock end LBDQS is set on the side of the high-order data end (HDQ0~HDQ7), which can ensure that the delay of the internal clock signal transmitted to the local clock end LBDQS is consistent with the delay of its transmission to other ports, and better reflect the quality of the internal clock signal.

[0069] It should be noted that in the disclosed embodiment, there are 8 low-order data terminals and 8 high-order data terminals, that is, the data output by the memory 10 is 16 bits, but this does not constitute a specific limitation. The number of low-order data terminals can be 4, 16, etc.; the number of high-order data terminals can also be 4, 16, etc., and the corresponding implementation methods can be understood by reference.

[0070] In a specific embodiment, please refer to Figure 3 , the enable signal group includes a first enable signal x8_EN, a second enable signal x4_EN, a third enable signal x16_EN and a test enable signal TM_EN, and each clock tree unit 122 includes a first transmission unit 21, a second transmission unit 22 and a third transmission unit 23;

[0071] The i-th first transmission unit 21 is configured to delay the transmission of the i-th internal clock signal when the first enable signal x8_EN or the test enable signal TM_EN is in a valid state, thereby generating an i-th first transmission signal and an i-th second transmission signal; wherein the level state of the i-th first transmission signal is the same as the level state of the i-th second transmission signal;

[0072] The i-th second transmission unit 22 is connected to the i-th first transmission unit 21 and is configured to transmit the i-th first transmission signal to each first-category signal terminal when the second enable signal x4_EN is in a valid state, so as to transmit the i-th internal clock signal to each first-category signal terminal;

[0073] The i-th third transmission unit 23 is connected to the i-th first transmission unit 21, and is configured to transmit the i-th second transmission signal to each second-type signal terminal when the third enable signal x16_EN or the test enable signal TM_EN is in a valid state, so as to realize the transmission of the i-th internal clock signal to each second-type signal terminal.

[0074] Here, the active test enable signal TM_EN indicates that the memory 10 is in test mode. When the memory 10 is in the first output mode, the first enable signal x8_EN and the second enable signal x4_EN are both active and the third enable signal x16_EN is inactive. When the memory is in the second output mode, the first enable signal x8_EN, the second enable signal x4_EN, and the third enable signal are all active, and the number of data signal bits in the second output mode is twice that of the first output mode. For example, the first output mode can be an x8 mode, in which the output data has 8-bit sub-signals, i.e., 8-bit data is output synchronously. The second output mode can be an x16 mode, in which the output data has 16-bit sub-signals, i.e., 16-bit data is output synchronously. This example will be used for the following explanation.

[0075] It should be noted that the enable signal groups received by different clock tree units 122 are the same. The memory 10 has at least a test mode, a first output mode (x8), and a second output mode (x16), as described below:

[0076] (1) In the test mode, the test enable signal TM_EN is in the valid state. At this time, all the first transmission units 21 and the third transmission units 23 are in operation, and the internal clock signals CLKI_0, CLKQ_0, CLKIB_0, and CLKQB_0 are transmitted to at least all the second-type signal terminals, so that any internal clock signal or external clock signal can be derived through the selection circuit 13. In particular, in the test mode, the states of the first enable signal x8_EN to the third enable signal x16_EN may depend on the actual application scenario and are not limited here.

[0077] (2) In the first output mode (x8), the first enable signal x8_EN and the second enable signal x4_EN are both in the valid state, and the third enable signal x16_EN and the test enable signal TM_EN are both in the invalid state. At this time, all the first transmission units 21 and the second transmission units 22 are working, and the third transmission unit 23 is not working. The internal clock signals CLKI_0, CLKQ_0, CLKIB_0, and CLKQB_0 are only transmitted to the first type signal terminal, thereby realizing the sampling output of Data<7:0> and the output of the related data selection clock signal;

[0078] (3) In the second output mode (x16), the first enable signal x8_EN, the second enable signal x4_EN, and the third enable signal x16_EN are all in the valid state, and the test enable signal TM_EN is in the invalid state. At this time, all the first transmission units 21, the second transmission units 22, and the third transmission units 23 are working, and the internal clock signals CLKI_0, CLKQ_0, CLKIB_0, and CLKQB_0 are transmitted to the first type signal terminal and the second type signal terminal, thereby realizing the sampling output of Data<15:0> and the output of the related data selection clock signal.

[0079] It should be understood that in the embodiments of the present disclosure, the valid state may refer to a high level or a low level, and the valid states of different signals may refer to different level states.

[0080] For example, Figure 3 As shown, each first transmission unit 21 includes a first transmission path 211 and a first gating unit 212 ; each second transmission unit 22 includes a second gating unit 221 and a second transmission path group 222 ; each third transmission unit 23 includes a third gating unit 231 and a third transmission path group 232 .

[0081] like Figure 3 As shown, the input end of the i-th first transmission path 211 receives the i-th internal clock signal, the first input end of the i-th first gating unit 212 is connected to the output end of the i-th first transmission path 211, the second input end of the i-th first gating unit 212 receives the first enable signal x8_EN, the third input end of the i-th first gating unit 212 receives the test enable signal TM_EN, the first output end of the i-th first gating unit 212 outputs the i-th first transmission signal, and the second output end of the i-th first gating unit 212 outputs the i-th second transmission signal;

[0082] The first input terminal of the i-th second gating unit 221 receives the i-th first transmission signal, the second input terminal of the i-th second gating unit 221 receives the second enable signal x4_EN, and each transmission path (i.e. Figure 3 The input end of the second transmission path in the i-th second transmission path group 222 is connected to the output end of the second gating unit 221, and the output end of a transmission path in the i-th second transmission path group 222 forms a first type signal end;

[0083] The first input terminal of the i-th third gating unit 231 receives the i-th second transmission signal, the second input terminal of the i-th third gating unit 231 receives the third enable signal x16_EN, the third input terminal of the i-th third gating unit 231 receives the test enable signal TM_EN, and each transmission path (i.e. Figure 3 The input end of each of the third transmission paths in the i-th third transmission path group 232 is connected to the output end of the third gating unit 231, and the output end of a transmission path in the i-th third transmission path group 232 forms a second type signal end.

[0084] It should be noted that the second transmission path group 222 includes multiple second transmission paths, and the third transmission path group 232 includes multiple third transmission paths. In the same clock tree unit 122, the multiple second transmission paths and the multiple third transmission paths are symmetrically distributed, and the delays of all second transmission paths and all third transmission paths (within the allowable error range) are the same. The transmission paths involved above can all be constructed by metal wires and an even number of NOT gates.

[0085] Thus, (1) in the test mode, the first gating unit 212 and the third gating unit 231 can be considered to be connected, that is, the internal clock signals CLKI_0, CLKQ_0, CLKIB_0, and CLKQB_0 are transmitted to the second type of signal terminal; (2) in the first output mode (x8), the first gating unit 212 and the second gating unit 221 can be considered to be connected, and the third gating unit 231 can be considered to be turned off, that is, the internal clock signals CLKI_0, CLKQ_0, CLKIB_0, and CLKQB_0 are transmitted to the first type of signal terminal; (3) in the second output mode (x16), the first gating unit 212, the second gating unit 221, and the third gating unit 231 can be considered to be connected, that is, the internal clock signals CLKI_0, CLKQ_0, CLKIB_0, and CLKQB_0 are transmitted to the first type of signal terminal and the second type of signal terminal.

[0086] From the above, it can be seen that when the tester tests the memory 10, it is only necessary to adjust the test enable signal TM_EN to a valid state to lead the N internal clock signals to the selection circuit 13. The subsequent selection circuit 13 outputs one of the N internal clock signals and the external clock signal as a detection clock signal according to the received test selection signal, so that the tester can understand the clock information of the memory 10.

[0087] The valid states of the first enable signal x8_EN, the second enable signal x4_EN, the third enable signal x16_EN and the test enable signal TM_EN are all set to high levels. A specific structure of a clock tree unit 122 is provided below for this setting scenario.

[0088] See Figure 4 The first gating unit 212 includes a first AND gate 2121 (composed of a NAND gate + a NOT gate), a second AND gate 2122 (composed of a NAND gate + a NOT gate), and a first OR gate 2123 (composed of a NOR gate + a NOT gate); a first input end of the first AND gate 2121 and a first input end of the second AND gate 2122 are both connected to the output end of the first transmission path 211, a second input end of the first AND gate 2121 and a first input end of the first OR gate 2123 both receive a first enable signal x8_EN, a second input end of the first OR gate 2123 receives a test enable signal TM_EN, an output end of the first OR gate 2123 is connected to a second input end of the second AND gate 2122, an output end of the first AND gate 2121 outputs a first transmission signal, and an output end of the second AND gate 2122 outputs a second transmission signal.

[0089] The second gating unit 221 includes a third AND gate 2211 and a fourth AND gate 2212; the first input end of the third AND gate 2211 and the first input end of the fourth AND gate 2212 both receive the first transmission signal, the second input end of the third AND gate 2211 and the second input end of the fourth AND gate 2212 both receive the second enable signal x4_EN, the output end of the third AND gate 2211 is connected to a part of the transmission path in the second transmission path group 222, and the output end of the fourth AND gate 2212 is connected to another part of the transmission path in the second transmission path group 222.

[0090] The third gating unit 231 includes a fifth AND gate 2311, a sixth AND gate 2312, and a second OR gate 2313; the first input end of the fifth AND gate 2311 and the first input end of the sixth AND gate 2312 both receive the second transmission signal, the second input end of the fifth AND gate 2311 and the first input end of the second OR gate 2313 both receive the third enable signal x16_EN, the second input end of the second OR gate 2313 receives the test enable signal TM_EN, the output end of the second OR gate 2313 is connected to the second input end of the sixth AND gate 2312, the output end of the fifth AND gate 2311 is connected to a part of the transmission paths in the third transmission path group 232, and the output end of the sixth AND gate 2312 is connected to another part of the transmission paths in the third transmission path group 232.

[0091] It should be noted that, since the structures of different clock tree units 122 are the same, Figure 4 Only the specific structure of the first clock tree unit 122 is shown, and the rest can be understood by reference.

[0092] In another embodiment, the active states of the first enable signal x8_EN, the second enable signal x4_EN, the third enable signal x16_EN, and the test enable signal TM_EN are all low. In this case, the first OR gate 2123 and the second OR gate 2313 are each adjusted to a corresponding AND gate, and the first through sixth AND gates 2121 through 2312 are each adjusted to a corresponding OR gate. Of course, the definitions of the active states of the first enable signal x8_EN, the second enable signal x4_EN, the third enable signal x16_EN, and the test enable signal TM_EN can differ from one another. In this case, the specific configurations of the first gating unit 212, the second gating unit 221, and the third gating unit 231 may need to be adaptively adjusted. In other words, due to the diversity of logic devices, the configurations of the first through third gating units 212 through 231 are diverse and can be composed of one or more combinations of the following devices: NAND gates, NOR gates, NOT gates, XNOR gates, and XOR gates. In addition, the composition of the first to third gating units 212 to 231 needs to be adapted to the definitions of the valid states of the first enable signal x8_EN, the second enable signal x4_EN, the third enable signal x16_EN, and the test enable signal TM_EN.

[0093] It should also be noted that in an actual circuit, since there is a certain distance between the local clock terminal LBDQS and the input terminal of the selection circuit 13, a transmission driving unit can be set between the local clock terminal LBDQS and the selection circuit 13 to increase the signal strength of the internal clock signal and reduce the loss during the transmission process. That is to say, in some embodiments, such as Figure 4 As shown, the memory 10 further includes N transmission driving units 15 ( Figure 4 Only one is shown), the input terminals of the N transmission driving units 15 are connected to the N local clock terminals in a one-to-one correspondence, and the output terminals of the N transmission driving units 15 are connected to the N input terminals of the selection circuit 13 in a one-to-one correspondence. Here, the transmission driving unit 15 may include an even number of NOT gates.

[0094] for Figure 3 For example, the internal clock signal is transmitted to the selection circuit 13 via a transmission path (or x16 path) related to high-order data sampling. In other embodiments, such as Figure 5As shown, the internal clock signal can also be transmitted to the selection circuit 13 via the transmission path associated with low-order data sampling (also known as the x8 path). Specifically, the local clock terminal LBDQS can be located on one side of the low-order data terminals (LDQ0-LDQ7). Each clock tree unit 122 includes a first type of signal terminals (i.e., LDQ0-LDQ7, LDQS, and LBDQS) and a second type of signal terminals (i.e., HDQ0-HDQ7, HDQS, and redundant ports). The first type of signal terminals includes multiple low-order data terminals (i.e., LDQ0-LDQ7), a low-order clock terminal (i.e., LDQS), and a local clock port (i.e., LBDQS). The second type of signal terminals includes multiple high-order data terminals (i.e., HDQ0-HDQ7, HDQS), a high-order clock terminal (i.e., HDQS), and redundant ports.

[0095] Accordingly, the i-th clock tree unit 122 is connected to the delay locked loop 121 and is configured to transmit the i-th internal clock signal to each first-category signal terminal based on the enable signal group; or, based on the enable signal group, transmit the i-th internal clock signal to each second-category signal terminal; or, based on the enable signal group, transmit the i-th internal clock signal to each first-category signal terminal and each second-category signal terminal;

[0096] The selection circuit 13 is connected to the N local clock ports and is configured to receive the N internal clock signals from the local clock ports when the N internal clock signals are transmitted to each first-type signal port.

[0097] Thus, according to the actual circuit layout of the memory 10, if the final output port of the detection clock signal is closer to the output port of the high-order data, the Figure 3 If the final output port of the detection clock signal is closer to the output port of the low-order data, it can be used Figure 5 The embodiment shown reduces the path for the internal clock signal to be transmitted from the local clock terminal LBDQS to the selection circuit 13 , while reducing the number of buffers (every two NOT gates can be regarded as a buffer) in the transmission driving unit 15 .

[0098] It should also be noted that the aforementioned delay phase-locked loop 121 can adopt a conventional structure. It should be understood that the memory 10 also receives the command address signal CA and the initial clock signal CK (specifically including two sub-signals CK_B and CK_T with opposite phases) from an external device. The initial clock signal CK is used to sample the command address signal CA. Figure 6The memory 10 further includes a signal receiver for receiving the initial clock signal CK. The input end of the delay phase-locked loop 121 is connected to the output end of the signal receiver. That is, the delay phase-locked loop 121 actually generates N internal clock signals based on the initial clock signal CK. The subsequent N internal clock signals are transmitted to the selection circuit 13 via the clock tree unit 122.

[0099] In this way, clock generation circuit 12 generates N internal clock signals and transmits them to selection circuit 13. Selection circuit 13 outputs one of the N internal clock signals and the external clock signal as the detection clock signal based on the test selection signal. The operating principle and specific structure of selection circuit 13 are described below.

[0100] In the first embodiment, please refer to Figure 7 , the test selection signal includes A first selection signals TM_S<1:0> and a second selection signal TM_S_ENT; the selection circuit 13 is specifically configured to receive A first selection signals TM_S<1:0> and a second selection signal TM_S_ENT, and when the second selection signal TM_S_ENT is in an invalid state, based on the A first selection signals TM_S<1:0>, multiple internal clock signals (i.e. Figure 7 One of CLK_I, CLK_Q, CLK_IB, CLK_QB) is output as a detection clock signal; when the second selection signal TM_S_ENT is in a valid state, the external clock signal LBCLK is output as a detection clock signal; wherein, 2 A ≥N. Here, Figure 7 N=4 and A=2 are used as an example for illustration, but this does not constitute a specific limitation.

[0101] It should be noted that, for the same signal, the valid state and the invalid state are two different level states. For example, the specific levels of the valid state of different signals may be different, and the specific levels of the invalid state of different signals may be different.

[0102] For details, see Figure 7 , the selection circuit 13 includes:

[0103] The pre-processing unit 1310 is configured to perform logic processing on the A first selection signals TM_S<1:0> and the second selection signal TM_S_ENT to generate N fourth enable signals (ie Figure 7 wherein, when the second selection signal TM_S_ENT is in an invalid state, based on the A first selection signals, one and only one of the N fourth enable signals is controlled to be in a valid state; when the second selection signal TM_S_ENT is in a valid state, all of the N fourth enable signals are controlled to be in an invalid state;

[0104] The first selection unit 1320 is configured to output the i-th internal clock signal as the intermediate clock signal when the i-th fourth enable signal is in a valid state; and to keep the level of the intermediate clock signal unchanged when all N fourth enable signals are in an invalid state;

[0105] The second selection unit 1330 is configured to output the intermediate clock signal as the detection clock signal when the second selection signal TM_S_ENT is in an invalid state; and to output the external clock signal LBCLK as the detection clock signal when the second selection signal TM_S_ENT is in a valid state.

[0106] In particular, in the aforementioned Figure 6 Only the first selection unit 1320 and the second selection unit 1330 are shown, and the pre-processing unit 1310 is omitted.

[0107] In this way, the first selection unit 1320 can at least realize the function of selecting one from N, and the second selection unit 1330 can realize the function of selecting one from two.

[0108] Furthermore, for the circuit scenario where N=4 and A=2, a specific structure of the pre-processing unit 1310 is provided. Figure 8 , the pre-processing unit 1310 includes a first logic unit 31 and a second logic unit 32;

[0109] The first logic unit 31 is configured to respond to the first selection signal TM_S <0> Perform a NOT operation to generate a first inverted signal TM_S_B <0> , for the first inverted signal TM_S_B <0> Perform a NOT operation to generate a first positive phase signal TM_S_T <0> ; For the second first selection signal TM_S <1> Perform a NOT operation to generate a second inverted signal TM_S_B <1> , for the second inverted signal TM_S_B <1> Perform a NOT operation to generate a second positive phase signal TM_S_T <1> ; performing a NOT operation on the second selection signal TM_S_ENT to generate a third inverted signal TM_S_ENTBD, performing a NOT operation on the third inverted signal TM_S_ENTBD to generate a third positive phase signal TM_S_ENTD; performing a NOT operation on the third positive phase signal TM_S_ENTD to generate a fourth inverted signal TM_S_ENBDD;

[0110] The second logic unit 32 is configured to process the first inverted signal TM_S_B <0> , the second inverted signal TM_S_B <1> and the fourth inverted signal TM_S_ENBDD to generate the first fourth enable signal ICLK_ENT; the second inverted signal TM_S_B <1> , first positive phase signal TM_S_T <0> and the fourth inverting signal TM_S_ENBDD to generate a second fourth enable signal QCLK_ENT; the second positive phase signal TM_S_T <1> , first inverted signal TM_S_B <0> and the fourth inverting signal TM_S_ENBDD to generate a third fourth enabling signal IBCLK_ENT; the second positive phase signal TM_S_T <1> , first positive phase signal TM_S_T <0> The fourth enable signal QBCLK_ENT is logically processed with the fourth inverted signal TM_S_ENBDD to generate a fourth fourth enable signal QBCLK_ENT.

[0111] It should be noted that if Figure 8 As shown, first logic unit 31 includes at least seven NOT gates, namely NOT gates 311 through 317, which are respectively used to implement the aforementioned NOT operation. Second logic unit 32 can be composed of one or more combinations of the following devices: NAND gate, NOR gate, NOT gate, XNOR gate, XOR gate, flip-flop, and latch, depending on the specific definition of the valid state of each signal.

[0112] It should be noted that a circuit scenario is provided: (1) If TM_S_T<0:1>=00, TM_S_ENT=1, the first internal clock signal ICLK is output as the detection clock signal; (2) If TM_S_T<0:1>=10, TM_S_ENT=1, the second internal clock signal QCLK is output as the detection clock signal; (3) If TM_S_T<0:1>=01, TM_S_ENT=1, the third internal clock signal IBCLK is output as Detection clock signal; (4) If TM_S_T<0:1>=11, TM_S_ENT=1, the fourth internal clock signal QBCLK is output as the detection clock signal; (5) If TM_S_ENT=0, the external clock signal LBCLK is output as the detection clock signal, that is, the effective state of TM_S_ENT is low level; in addition, the effective state of the enable signals ICLK_ENT, QCLK_ENT, IBCLK_ENT, and QBCLK_ENT is set to high level.

[0113] To implement the above scenario, see Figure 8The second logic unit 32 includes a first NAND gate 321, a first NOR gate 322, a second NAND gate 323, a second NOR gate 324, a third NAND gate 325, a third NOR gate 326, a fourth NAND gate 327, and a fourth NOR gate 328. Specifically, the first input terminal of the first NAND gate 321 receives the first inverted signal TM_S_B. <0> The second input terminal of the first NAND gate 321 receives the second inverted signal TM_S_B <1> The first input terminal of the first NOR gate 322 is connected to the output terminal of the first NAND gate 321, the second input terminal of the first NOR gate 322 receives the fourth inverted signal TM_S_ENBDD, and the output terminal of the first NOR gate 322 outputs the first fourth enable signal ICLK_ENT; the first input terminal of the second NAND gate 323 receives the first positive phase signal TM_S_T <0> The second input terminal of the second NAND gate 323 receives the second inverted signal TM_S_B <1> The first input terminal of the second NOR gate 324 is connected to the output terminal of the second NAND gate 323, the second input terminal of the second NOR gate 324 receives the fourth inverted signal TM_S_ENBDD, and the output terminal of the second NOR gate 324 outputs the second fourth enable signal QCLK_ENT; the first input terminal of the third NAND gate 325 receives the first inverted signal TM_S_B <0> The second input terminal of the third NAND gate 325 receives the second positive phase signal TM_S_T <1> The first input terminal of the third NOR gate 326 is connected to the output terminal of the third NAND gate 325, the second input terminal of the third NOR gate 326 receives the fourth inverted signal TM_S_ENBDD, and the output terminal of the third NOR gate 326 outputs the third fourth enable signal IBCLK_ENT; the first input terminal of the fourth NAND gate 327 receives the first positive phase signal TM_S_T <0> The second input terminal of the fourth NAND gate 327 receives the second positive phase signal TM_S_T <1> A first input terminal of the fourth NOR gate 328 is connected to the output terminal of the fourth NAND gate 327, a second input terminal of the fourth NOR gate 328 receives the fourth inverted signal TM_S_ENBDD, and an output terminal of the fourth NOR gate 328 outputs the fourth enable signal QBCLK_ENT.

[0114] Thus, when TM_S_ENT=0, since TM_S_ENBDD=1, ICLK_ENT=QCLK_ENT=ICLK_ENT=QCLK_ENT=0, that is, the N fourth enable signals are all in an invalid state. When TM_S_ENT=1, TM_S_T<0:1>=00, since TM_S_ENBDD=0, and TM_S_B <0> =TM_S_B <1> =1, so ICLK_ENT=1, but QCLK_ENT=ICLK_ENT=QCLK_ENT=0, that is, the first fourth enable signal is in a valid state, and the other enable signals are in an invalid state. Other situations can be understood by yourself.

[0115] In a specific embodiment, see Figure 9 The first selection unit 1320 includes a first selector 41, a second selector 42, and a third selector 43; the first selector 41 is configured to output the first internal clock signal ICLK as the first pre-selected signal when the first fourth enable signal ICLK_ENT is in a valid state; and output the second internal clock signal QCLK as the first pre-selected signal when the second fourth enable signal QCLK_ENT is in a valid state; the second selector 42 is configured to output the third internal clock signal IBCLK as the second pre-selected signal when the third fourth enable signal IBCLK_ENT is in a valid state; and output the fourth internal clock signal QBCLK as the second pre-selected signal when the fourth fourth enable signal QBCLK_ENT is in a valid state;

[0116] The third selector 43 is configured to receive the inverted signal TM_S_B at the second <1> When in the valid state, the first preselected signal is output as the intermediate clock signal; <1> When in the active state, the second preselected signal is output as the intermediate clock signal.

[0117] The second selection unit 1330 includes a fourth selector 44; the fourth selector 44 is configured to output the intermediate clock signal as the detection clock signal when the third positive phase signal TM_S_ENTD is in a valid state; and to output the external clock signal LBCLK as the detection clock signal when the third negative phase signal TM_S_ENTBD is in a valid state.

[0118] It should be noted that the first selector 41, the second selector 42, and the third selector 43 are responsible for selecting one of the four internal clock signals and outputting it as the intermediate clock signal (the level state of the intermediate clock signal may also be kept unchanged), and the fourth selector 44 is responsible for outputting the intermediate clock signal or the external clock signal LBCLK as the detection clock signal.

[0119] It should be noted that the first selector 41, the second selector 42, the third selector 43 and the fourth selector 44 have the same structure. Figure 9 As shown, any selector includes a fifth NAND gate (eg Figure 9 501, 505, 509, 513), the sixth NAND gate (e.g. Figure 9 502, 506, 510 or 514), the seventh NAND gate (e.g. Figure 9 503, 507, 511 or 515), the eighth NAND gate (e.g. Figure 9 504, 508, 512, or 516);

[0120] The first input end of the fifth NAND gate forms the first control end of the corresponding selector, the second input end of the fifth NAND gate forms the first input end of the corresponding selector, the first input end of the sixth NAND gate forms the second control end of the corresponding selector, the second input end of the sixth NAND gate forms the second input end of the corresponding selector, the first input end of the seventh NAND gate and the first input end of the eighth NAND gate are connected to the output end of the fifth NAND gate, the second input end of the seventh NAND gate and the second input end of the eighth NAND gate are connected to the output end of the sixth NAND gate; the output end of the seventh NAND gate and the output end of the eighth NAND gate are connected to form the output end of the corresponding selector.

[0121] For the first selector 41, its first control terminal receives the first fourth enable signal ICLK_ENT, its first input terminal receives the first internal clock signal ICLK, its second control terminal receives the second fourth enable signal QCLK_ENT, its second input terminal receives the second internal clock signal QCLK, and its output terminal outputs the first pre-selected signal;

[0122] For the second selector 42, its first control terminal receives the third fourth enable signal IBCLK_ENT, its first input terminal receives the third internal clock signal IBCLK, its second control terminal receives the fourth fourth enable signal QBCLK_ENT, its second input terminal receives the fourth internal clock signal QBCLK, and its output terminal outputs the second pre-selected signal;

[0123] Regarding the third selector 43, its first control terminal receives the second inverted signal TM_S_B <1> , whose first input terminal receives the first preselected signal, and whose second control terminal receives the second positive phase signal TM_S_T <1> , a second input terminal of which receives a second preselected signal, and an output terminal of which outputs an intermediate clock signal;

[0124] For the fourth selector 44, its first control terminal receives the third positive phase signal TM_S_ENTD, its first input terminal receives the intermediate clock signal, its second control terminal receives the third negative phase signal TM_S_ENTBD, its second input terminal receives the external clock signal LBCLK, and its output terminal outputs the detection clock signal.

[0125] It should be noted that, since the working principles of the first selector 41 to the fourth selector 44 are the same, the following description will only take the first selector 41 as an example. As mentioned above, assuming that ICLK_ENT = 1 (valid state), QCLK_ENT = 0 (invalid state), at this time, the output signal of the fifth NAND gate 501 is opposite in phase to the first internal clock signal ICLK, but the output signal of the sixth NAND gate 502 remains at a high level; furthermore, the output signal of the seventh NAND gate 503 is opposite in phase to the output signal of the fifth NAND gate 501 (that is, the output signal of the seventh NAND gate 503 has the same waveform as the first internal clock signal ICLK), and the output signal of the eighth NAND gate 504 is also opposite to the output signal of the fifth NAND gate 501. The waveforms of the signals are inverted (i.e., the output signal of the eighth AND gate 504 is also the same as the waveform of the first internal clock signal ICLK). Therefore, the first preselected signal generated by superimposing the output signals of the seventh NAND gate 503 and the eighth NAND gate 504 is the same as the waveform of the first internal clock signal ICLK. Assuming ICLK_ENT = QCLK_ENT = 0 (inactive state), the output signals of the fifth NAND gate 501 and the sixth NAND gate 502 both remain at a high level. Based on this, the output signals of the seventh NAND gate 503 and the eighth NAND gate 504 both remain at a low level. Please understand the remaining situations accordingly.

[0126] In this way, pre-processing unit 1310 jointly decodes the first selection signal (i.e., TM_S<1:0>) and the second selection signal TM_S_ENT. If the internal clock signal needs to be tested, the selected internal clock signal is output as an intermediate clock signal, which is then output as a detection clock signal. If the external clock signal needs to be tested, the level of the intermediate clock signal is controlled to remain unchanged, and only the external clock signal is output as the detection clock signal. This prevents the level of the intermediate clock signal from being flipped in some scenarios, saving power.

[0127] In the second embodiment, see Figure 10 , the test selection signal includes A first selection signal TM_S<1:0> and a second selection signal TM_S_ENT; the selection circuit 13 includes:

[0128] The pre-processing unit 1311 is configured to perform logic processing on the A first selection signals TM_S<1:0> to generate N fourth enable signals, wherein only one of the N fourth enable signals is in a valid state;

[0129] The first selection unit 1321 is configured to output the i-th internal clock signal as the intermediate clock signal when the i-th fourth enable signal is in a valid state;

[0130] The second selection unit 1331 is configured to output the intermediate clock signal as the detection clock signal when the second selection signal TM_S_ENT is in an invalid state; and to output the external clock signal as the detection clock signal when the second selection signal TM_S_ENT is in a valid state.

[0131] In particular, the preprocessing unit 1311 can be modified and implemented with reference to the structure of the aforementioned preprocessing unit 1310, the first selection unit 1321 can be modified and implemented with reference to the structure of the aforementioned first selection unit 1320, and the second selection unit 1331 can be modified and implemented with reference to the structure of the aforementioned second selection unit 1330, which will not be repeated in the embodiments of the present disclosure.

[0132] In this way, the pre-processing unit 1311 only decodes the first selection signal TM_S<1:0>, so that only one of the N fourth enable signals is in a valid state. At this time, the first selection unit 1321 must output one of the N intermediate clock signals as the intermediate clock signal. In this way, the number of components and the area of ​​the pre-processing unit 1311 are both small.

[0133] In the third embodiment, Figure 11 As shown, the test selection signal includes B selection sub-signals TM_S<2:0>; the selection circuit 13 is specifically configured to uniformly decode the B selection sub-signals TM_S<2:0> and output one of the multiple internal clock signals and the external clock signal as a detection clock signal based on the decoding result; wherein, 2 B ≥N+1. Figure 11 The following is illustrated by taking N=4 and B=2 as an example.

[0134] Accordingly, the selection circuit 13 includes a decoding unit 1313 and N+1 enable output units 1323; the decoding unit 1313 is configured to decode B selection sub-signals TM_S<2:0> and output N+1 decoding signals Decode<4:0>, and one of the N+1 decoding signals Decode<4:0> is in a valid state. <0> When the 1st enable output unit 1323 is enabled, the 1st internal clock signal is output as the detection clock signal. <4> When in the active state, the fifth enable output unit 1323 is enabled to output the external clock signal LBCLK as the detection clock signal. Here, the decoding unit and the enable output unit can be formed by a combination of the following logic devices: NAND gate, NOR gate, XNOR gate, XOR gate, and NOT gate.

[0135] In some embodiments, see Figure 4 , the memory 10 further includes a data driving circuit 14;

[0136] The data driving circuit 14 includes a pull-up driving unit 141 and a pull-down driving unit 142 , and is configured to receive a detection clock signal, pull-up the detection clock signal using the pull-up driving unit 141 , and pull-down the detection clock signal using the pull-down driving unit 142 .

[0137] It should be noted that pull-up driving refers to increasing the voltage value of a high-level signal, and pull-down driving refers to decreasing the voltage value of a low-level signal. Both the pull-up driving unit and the pull-down driving unit can be formed by N-type field effect transistors (NMOS) and / or P-type field effect transistors (PMOS).

[0138] In summary, the embodiments of the present disclosure provide a memory that can selectively output any internal clock signal or external clock signal, so that the tester can obtain the internal clock signal or external clock signal without executing the "read operation instruction READ" or the "write operation instruction Write". Not only can the quality of the clock signal be detected, but the memory 10 can also be adjusted accordingly to obtain the best storage performance, for example, by adjusting the internal clock signal to obtain an excellent valid data window time (DVW).

[0139] In another embodiment of the present disclosure, see Figure 12 , which shows a schematic diagram of the structure of an electronic device 60 provided by an embodiment of the present disclosure. Figure 12 As shown, the electronic device 60 at least includes the aforementioned memory 10 .

[0140] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. The above serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that: The memory includes: A clock receiving circuit configured to generate an external clock signal based on a data strobe clock signal received from the outside; wherein the data strobe clock signal is used to sample a data signal synchronously received from the outside; A clock generation circuit, comprising a delay phase-locked loop, configured to generate N internal clock signals through the delay phase-locked loop; wherein the N internal clock signals are used for data sampling processing to generate data signals sent to the outside; a selection circuit connected to both the clock receiving circuit and the clock generating circuit, and configured to output one of the N internal clock signals and the external clock signal as a detection clock signal based on a test selection signal; N is a positive integer; The clock generation circuit further includes N clock tree units, wherein the output end of each clock tree unit includes a first-type signal end and a second-type signal end, and the first-type signal end and the second-type signal end are symmetrically distributed; the first-type signal end includes a plurality of low-bit data ends, a low-bit clock end, and a redundant port, and the second-type signal end includes a plurality of high-bit data ends, a high-bit clock end, and a local clock port; The i-th clock tree unit is connected to the delay phase-locked loop and is configured to transmit the i-th internal clock signal to the first type signal terminal based on the enable signal group; or, based on the enable signal group, transmit the i-th internal clock signal to the second type signal terminal; or, based on the enable signal group, transmit the i-th internal clock signal to the first type signal terminal and the second type signal terminal; i is a positive integer, i≤N; The selection circuit is connected to the N local clock ports and is configured to receive the N internal clock signals from the local clock ports.

2. The memory according to claim 1, wherein The enable signal group includes a first enable signal, a second enable signal, a third enable signal and a test enable signal, and each of the clock tree units includes a first transmission unit, a second transmission unit and a third transmission unit; The i-th first transmission unit is configured to, when the first enable signal or the test enable signal is in a valid state, delay the transmission of the i-th internal clock signal to generate an i-th first transmission signal and an i-th second transmission signal; wherein the level state of the i-th first transmission signal is the same as the level state of the i-th second transmission signal; an i-th second transmission unit connected to the i-th first transmission unit, and configured to transmit the i-th first transmission signal to each of the first-category signal terminals when the second enable signal is in a valid state, so as to transmit the i-th internal clock signal to each of the first-category signal terminals; the i-th third transmission unit being connected to the i-th first transmission unit and being configured to, when the third enable signal or the test enable signal is in a valid state, transmit the i-th second transmission signal to each of the second-type signal terminals, so as to transmit the i-th internal clock signal to each of the second-type signal terminals; Among them, the test enable signal in the valid state indicates that the memory is in the test mode; when the memory is in the first output mode, the first enable signal and the second enable signal are both in the valid state and the third enable signal is in the invalid state; when the memory is in the second output mode, the first enable signal, the second enable signal and the third enable signal are all in the valid state, and the number of data signal bits of the second output mode is twice that of the data signal bit of the first output mode.

3. The memory according to claim 2, wherein: Each of the first transmission units includes a first transmission path and a first gating unit; each of the second transmission units includes a second gating unit and a second transmission path group; each of the third transmission units includes a third gating unit and a third transmission path group; an input end of the i-th first transmission path receiving the i-th internal clock signal, a first input end of the i-th first gating unit being connected to an output end of the i-th first transmission path, a second input end of the i-th first gating unit receiving the first enable signal, a third input end of the i-th first gating unit receiving the test enable signal, a first output end of the i-th first gating unit outputting the i-th first transmission signal, and a second output end of the i-th first gating unit outputting the i-th second transmission signal; The first input end of the i-th second gating unit receives the i-th first transmission signal, the second input end of the i-th second gating unit receives the second enable signal, the input end of each transmission path in the i-th second transmission path group is connected to the output end of the second gating unit, and the output end of a transmission path in the i-th second transmission path group forms a first-type signal end; The first input end of the i-th third gating unit receives the i-th second transmission signal, the second input end of the i-th third gating unit receives the third enable signal, the third input end of the i-th third gating unit receives the test enable signal, the input end of each transmission path in the i-th third transmission path group is connected to the output end of the third gating unit, and the output end of a transmission path in the i-th third transmission path group forms a second-type signal end.

4. The memory according to claim 3, wherein: When the first enable signal, the second enable signal, the third enable signal and the test enable signal are all in the high level state, The first gating unit includes a first AND gate, a second AND gate, and a first OR gate; the first input end of the first AND gate and the first input end of the second AND gate are both connected to the output end of the first transmission path, the second input end of the first AND gate and the first input end of the first OR gate both receive the first enable signal, the second input end of the first OR gate receives the test enable signal, the output end of the first OR gate is connected to the second input end of the second AND gate, the output end of the first AND gate outputs the first transmission signal, and the output end of the second AND gate outputs the second transmission signal; The second gating unit includes a third AND gate and a fourth AND gate; a first input end of the third AND gate and a first input end of the fourth AND gate both receive the first transmission signal, a second input end of the third AND gate and a second input end of the fourth AND gate both receive the second enable signal, an output end of the third AND gate is connected to a portion of the transmission paths in the second transmission path group, and an output end of the fourth AND gate is connected to another portion of the transmission paths in the second transmission path group; The third gating unit includes a fifth AND gate, a sixth AND gate, and a second OR gate; the first input end of the fifth AND gate and the first input end of the sixth AND gate both receive the second transmission signal, the second input end of the fifth AND gate and the first input end of the second OR gate both receive the third enable signal, the second input end of the second OR gate receives the test enable signal, the output end of the second OR gate is connected to the second input end of the sixth AND gate, the output end of the fifth AND gate is connected to a part of the transmission paths in the third transmission path group, and the output end of the sixth AND gate is connected to another part of the transmission paths in the third transmission path group.

5. The memory according to any one of claims 1 to 4, characterized in that: The test selection signal includes A first selection signal and a second selection signal; The selection circuit is specifically configured to receive A first selection signals and a second selection signal, and when the second selection signal is in an invalid state, output one of the multiple internal clock signals as a detection clock signal based on the A first selection signals; when the second selection signal is in a valid state, output the external clock signal as a detection clock signal; wherein 2A≥N.

6. The memory according to claim 5, wherein: The selection circuit includes: a preprocessing unit configured to perform logic processing on the A first selection signals and the second selection signal to generate N fourth enable signals; wherein, when the second selection signal is in an invalid state, based on the A first selection signals, control one and only one of the N fourth enable signals to be in a valid state; and when the second selection signal is in a valid state, control all of the N fourth enable signals to be in an invalid state; a first selection unit configured to output the i-th internal clock signal as an intermediate clock signal when the i-th fourth enable signal is in a valid state; and to keep the level state of the intermediate clock signal unchanged when all N fourth enable signals are in an invalid state; The second selection unit is configured to output the intermediate clock signal as the detection clock signal when the second selection signal is in an invalid state; and to output the external clock signal as the detection clock signal when the second selection signal is in a valid state.

7. The memory according to claim 6, wherein: In the case of N=4 and A=2, the pre-processing unit includes a first logic unit and a second logic unit; The first logic unit is configured to perform a negation operation on the first first selection signal to generate a first inverted signal, and perform a negation operation on the first inverted signal to generate a first positive signal; perform a negation operation on the second first selection signal to generate a second inverted signal, and perform a negation operation on the second inverted signal to generate a second positive signal; perform a negation operation on the second selection signal to generate a third inverted signal, and perform a negation operation on the third inverted signal to generate a third positive signal; and perform a negation operation on the third positive signal to generate a fourth inverted signal; The second logic unit is configured to perform logic processing on the first inverted signal, the second inverted signal and the fourth inverted signal to generate the first fourth enable signal; perform logic processing on the second inverted signal, the first positive phase signal and the fourth inverted signal to generate the second fourth enable signal; perform logic processing on the second positive phase signal, the first inverted signal and the fourth inverted signal to generate the third fourth enable signal; and perform logic processing on the second positive phase signal, the first positive phase signal and the fourth inverted signal to generate the fourth fourth enable signal.

8. The memory according to claim 7, wherein: When the valid state of the fourth enable signal is a high level and the valid state of the second selection signal is a low level, the second logic unit includes a first NAND gate, a first NOR gate, a second NAND gate, a second NOR gate, a third NAND gate, a third NOR gate, a fourth NAND gate, and a fourth NOR gate; The first input terminal of the first NAND gate receives the first inverted signal, the second input terminal of the first NAND gate receives the second inverted signal, the first input terminal of the first NOR gate is connected to the output terminal of the first NAND gate, the second input terminal of the first NOR gate receives the fourth inverted signal, and the output terminal of the first NOR gate outputs the first fourth enable signal; The first input terminal of the second NAND gate receives the first positive phase signal, the second input terminal of the second NAND gate receives the second negative phase signal, the first input terminal of the second NOR gate is connected to the output terminal of the second NAND gate, the second input terminal of the second NOR gate receives the fourth negative phase signal, and the output terminal of the second NOR gate outputs the second fourth enable signal; The first input terminal of the third NAND gate receives the first inverted signal, the second input terminal of the third NAND gate receives the second positive signal, the first input terminal of the third NOR gate is connected to the output terminal of the third NAND gate, the second input terminal of the third NOR gate receives the fourth inverted signal, and the output terminal of the third NOR gate outputs the third fourth enable signal; The first input end of the fourth NAND gate receives the first positive phase signal, the second input end of the fourth NAND gate receives the second positive phase signal, the first input end of the fourth NOR gate is connected to the output end of the fourth NAND gate, the second input end of the fourth NOR gate receives the fourth negative phase signal, and the output end of the fourth NOR gate outputs the fourth fourth enable signal.

9. The memory according to claim 8, wherein: The first selection unit includes a first selector, a second selector and a third selector; The first selector is configured to output the first internal clock signal as the first preselected signal when the first fourth enable signal is in an active state; and to output the second internal clock signal as the first preselected signal when the second fourth enable signal is in an active state; the second selector being configured to output the third internal clock signal as the second preselected signal when the third fourth enable signal is in an active state; and to output the fourth internal clock signal as the second preselected signal when the fourth fourth enable signal is in an active state; the third selector is configured to output the first preselected signal as the intermediate clock signal when the second inverted signal is in an active state; and to output the second preselected signal as the intermediate clock signal when the second positive signal is in an active state; The second selection unit includes a fourth selector; the fourth selector is configured to output the intermediate clock signal as the detection clock signal when the third positive phase signal is in a valid state; and to output the external clock signal as the detection clock signal when the third negative phase signal is in a valid state.

10. The memory according to claim 9, wherein: Any one of the first selector, the second selector, the third selector and the fourth selector includes a fifth NAND gate, a sixth NAND gate, a seventh NAND gate and an eighth NAND gate; The first input end of the fifth NAND gate forms the first control end of the corresponding selector, the second input end of the fifth NAND gate forms the first input end of the corresponding selector, the first input end of the sixth NAND gate forms the second control end of the corresponding selector, the second input end of the sixth NAND gate forms the second input end of the corresponding selector, the first input end of the seventh NAND gate and the first input end of the eighth NAND gate are connected to the output end of the fifth NAND gate, the second input end of the seventh NAND gate and the second input end of the eighth NAND gate are connected to the output end of the sixth NAND gate; the output end of the seventh NAND gate and the output end of the eighth NAND gate are connected to form the output end of the corresponding selector; For the first selector, its first control terminal receives the first fourth enable signal, its first input terminal receives the first internal clock signal, its second control terminal receives the second fourth enable signal, its second input terminal receives the second internal clock signal, and its output terminal outputs the first pre-selected signal; For the second selector, its first control terminal receives the third fourth enable signal, its first input terminal receives the third internal clock signal, its second control terminal receives the fourth fourth enable signal, its second input terminal receives the fourth internal clock signal, and its output terminal outputs the second pre-selected signal; For the third selector, its first control terminal receives the second inverted signal, its first input terminal receives the first preselected signal, its second control terminal receives the second positive signal, its second input terminal receives the second preselected signal, and its output terminal outputs the intermediate clock signal; For the fourth selector, its first control end receives the third positive phase signal, its first input end receives the intermediate clock signal, its second control end receives the third negative phase signal, its second input end receives the external clock signal, and its output end outputs the detection clock signal.

11. The memory according to claim 1, wherein: The memory further includes N transmission driving units, the input ends of the N transmission driving units are connected to the N local clock ends in a one-to-one correspondence, and the output ends of the N transmission driving units are connected to the N input ends of the selection circuit in a one-to-one correspondence.

12. The memory according to any one of claims 1 to 11, characterized in that: The memory further includes a data driving circuit; The data driving circuit includes a pull-up driving unit and a pull-down driving unit, and is configured to receive the detection clock signal, pull-up drive the detection clock signal using the pull-up driving unit, and pull-down drive the detection clock signal using the pull-down driving unit.

13. An electronic device, characterized in that: The electronic device comprises the memory according to any one of claims 1 to 12.

14. A memory, characterized in that: The memory includes: A clock receiving circuit configured to generate an external clock signal based on a data strobe clock signal received from the outside; wherein the data strobe clock signal is used to sample a data signal synchronously received from the outside; A clock generation circuit, comprising a delay phase-locked loop, configured to generate N internal clock signals through the delay phase-locked loop; wherein the N internal clock signals are used for data sampling processing to generate data signals sent to the outside; a selection circuit connected to both the clock receiving circuit and the clock generating circuit, and configured to output one of the N internal clock signals and the external clock signal as a detection clock signal based on a test selection signal; N is a positive integer; The clock generation circuit further includes N clock tree units, wherein the output end of each clock tree unit includes a first-type signal end and a second-type signal end, and the first-type signal end and the second-type signal end are symmetrically distributed; the first-type signal end includes a plurality of low-bit data ends, a low-bit clock end, and a local clock port, and the second-type signal end includes a plurality of high-bit data ends, a high-bit clock end, and a redundant port; The i-th clock tree unit is connected to the delay locked loop and is configured to transmit the i-th internal clock signal to the first type signal terminal based on the enable signal group; or, based on the enable signal group, transmit the i-th internal clock signal to the second type signal terminal; or, based on the enable signal group, transmit the i-th internal clock signal to the first type signal terminal and the second type signal terminal; The selection circuit is connected to the N local clock ports and is configured to receive the N internal clock signals from the local clock ports.

15. The memory according to claim 14, wherein: The test selection signal includes A first selection signal and a second selection signal; The selection circuit is specifically configured to receive A first selection signals and a second selection signal, and when the second selection signal is in an invalid state, output one of the multiple internal clock signals as a detection clock signal based on the A first selection signals; when the second selection signal is in a valid state, output the external clock signal as a detection clock signal; wherein 2A≥N.

16. The memory according to claim 14, wherein: The memory further includes N transmission driving units, the input ends of the N transmission driving units are connected to the N local clock ends in a one-to-one correspondence, and the output ends of the N transmission driving units are connected to the N input ends of the selection circuit in a one-to-one correspondence.

17. The memory according to claim 14, wherein: The memory further includes a data driving circuit; The data driving circuit includes a pull-up driving unit and a pull-down driving unit, and is configured to receive the detection clock signal, pull-up drive the detection clock signal using the pull-up driving unit, and pull-down drive the detection clock signal using the pull-down driving unit.

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