A method for optimizing the sidewall of Bosch etching process

Abstract

The present invention discloses a method for optimizing the sidewalls of a Bosch etching process, comprising the following steps: S1, pretreatment: providing a wafer subjected to a Bosch etching process; pre-treating the wafer subjected to the Bosch etching process using a first cleaning solution; S2, etching: placing the wafer subjected to the pre-treatment in step S1 in a silicon etching solution for room-temperature etching; S3, mask removal: cleaning the wafer subjected to the etching in step S2 using a second cleaning solution at room temperature to remove the SiO2 mask on the wafer surface. The optimization method of the present invention smoothes the sidewall ripples produced by the Bosch etching process, thereby improving device performance and lifespan.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor element preparation, and in particular to a method for optimizing a side wall of a Bosch etching process. Background Art

[0002] The Bosch etching process is a method for etching deep silicon wafers (SIs) to create high-aspect-ratio, steep features. This process utilizes inductively coupled plasma (ICP) etching technology. The Bosch etching process involves injecting specific gases (such as SF6, C4F8, Ar), applying radio frequency (RF) power, and generating a plasma through glow discharge. Deflection electrodes then accelerate the active ions and radicals in the plasma into the silicon wafer surface under the action of an electric field, where they react chemically with the surface material to produce volatile byproducts. The physical impact of the ions also strips away the reacted material, resulting in an etching effect. This dual mechanism of chemical reaction and physical impact enables the Bosch etching process to achieve high selectivity while maintaining a good vertical etch profile. However, in the Bosch etch process, because each etching step is isotropic, it can cause a ripple effect on the etched sidewall surface. The height of the sidewall ripples can reach hundreds of nanometers. This rough surface can cause discontinuous barbed structures in the coating during the subsequent magnetron sputtering process and easily lead to voids in the metal interconnect layer during subsequent processing, thus affecting device performance and lifespan. Therefore, it is necessary to provide a method to optimize the sidewall of the Bosch etch process. Summary of the Invention

[0003] The object of the present invention is to solve the above problems and provide a method for optimizing the sidewall of the Bosch etching process. The optimization method processes the sidewall corrugations of the Bosch etching process to form a smooth morphology, thereby improving the performance and life of the device.

[0004] In order to solve the above technical problems, the technical solutions adopted by the present invention are as follows:

[0005] The present invention provides a method for optimizing the sidewall of a Bosch etching process, comprising the steps of:

[0006] S1, pretreatment: providing a wafer processed by a Bosch etching process; using a first cleaning solution to pretreat the wafer processed by the Bosch etching process;

[0007] S2, etching: placing the wafer pre-treated in step S1 in a silicon etching solution for room temperature etching;

[0008] S3, removing the mask: using a second cleaning solution to clean the wafer after etching in step S2 at room temperature to remove the SiO2 mask on the surface of the wafer.

[0009] Optionally, the first cleaning solution is an alkaline cleaning solution.

[0010] Optionally, the first cleaning solution includes SYS9070 solution.

[0011] Optionally, the pretreatment in step S1 specifically includes the steps of: soaking the wafer after the Bosch etching process in the first cleaning solution at 75-80° C. for 30-35 minutes.

[0012] Optionally, in step S3, the second cleaning solution includes hydrofluoric acid.

[0013] Optionally, the second cleaning solution includes a BOE solution; in parts by weight, the ratio of the BOE solution is HF:H2O=1:5.

[0014] Optionally, providing a wafer processed by the Bosch etching process as described in step S1 includes the steps of: using fluorine-based gas as passivation and etching gas, Ar as bombardment gas, and performing passivation, silicon etching and ion bombardment in sequence as a cycle, and performing the cycle several times to etch the wafer along the depth direction.

[0015] Optionally, step S2 includes cleaning and drying the wafer pretreated in step S1 before etching the wafer pretreated in step S1.

[0016] Optionally, before removing the mask on the wafer after the etching process in step S2, step S3 includes: cleaning and drying the wafer after the etching process in step S2.

[0017] The beneficial effects produced by the present invention include at least:

[0018] The method for optimizing the sidewalls of the Bosch etching process disclosed herein optimizes the sidewall morphology of the wafer after the Bosch etching process through pretreatment, etching, and mask removal. Etching the sidewall corrugations reduces the roughness of the sidewalls, resulting in a smoother sidewall morphology. This effectively eliminates the sharp corners of the sidewall corrugations, allowing the coating to completely adhere to the sidewalls and remain continuous and void-free. This avoids the formation of discontinuous barbed structures in the coating formed during subsequent coating processes, as well as voids in the metal interconnect layer during subsequent processing, thereby improving the performance and service life of the resulting semiconductor device. Furthermore, the present invention has a simple production process, is easy to operate, and is easily implemented. It can process multiple wafers simultaneously, resulting in high production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a scanning electron microscope test image of the wafer sidewall after Bosch etching process.

[0020] Figure 2 This is a scanning electron microscope test image of the wafer sidewall after being processed by the method for optimizing the Bosch etching process sidewall of the present invention.

[0021] Figure 3 This is a scanning electron microscope test image of the side wall after magnetron sputtering coating is performed on the wafer processed by the method for optimizing the side wall of the Bosch etching process of the present invention. DETAILED DESCRIPTION

[0022] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present invention.

[0023] Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0024] In the present invention, descriptions such as “first”, “second”, etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features.

[0025] The raw materials used in the present invention can be obtained from suppliers known in the art, or prepared by known methods.

[0026] The present invention provides a method for optimizing the sidewall of a Bosch etching process, comprising the steps of:

[0027] S1, Pretreatment: Providing a wafer processed by a Bosch etching process; Pretreatment of the wafer using a first cleaning solution: Immersing the wafer in the first cleaning solution at 75-80°C for 30-35 minutes. This pretreatment step not only removes solid products formed on the wafer surface and sidewalls after etching, but also prevents the reaction between the silicon etching solution and the silicon on the wafer in the subsequent step S2.

[0028] S2, etching: placing the wafer pretreated in step S1 in a silicon etching solution for room temperature etching; in some embodiments, in step S2, the wafer pretreated in step S1 is placed in the silicon etching solution for room temperature etching for 3-5 minutes; in step S2, the silicon etching solution has a ratio of HNO3:H2O:HAC:HF=45-50:20-25:2-3:1-1.5 in parts by weight, and the silicon etching rate is 3000-3500 A / min.

[0029] The principle of etching the wafer pretreated in step S1 using the silicon etching solution of the present invention includes the following: during immersion in the silicon etching solution, the protruding portions of the sidewall corrugations are preferentially oxidized by the nitric acid component in the silicon etching solution into silicon dioxide, forming a dense silicon dioxide film, according to the reaction formula: 3Si + 4HNO3 = 3SiO2↓ + 2H2O + 4NO↑. The resulting silicon dioxide film is insoluble in water and nitric acid, but soluble in hydrofluoric acid. The hydrofluoric acid in the silicon etching solution removes the formed silicon dioxide film by etching, according to the reaction formula: SiO2 + 6HF = H2[SiF6] + 2H2O. During the immersion process, the silicon etching solution repeatedly etches the sidewall corrugations, reducing the sidewall height difference. The wafer is then placed in the silicon etching solution for etching at room temperature for 3-5 minutes.

[0030] S3, removing the mask: at room temperature, using a second cleaning solution to clean the wafer after etching in step S2 to remove the SiO2 mask on the surface of the wafer.

[0031] Optionally, the first cleaning solution is an alkaline cleaning solution. In some embodiments, the first cleaning solution includes SYS9070 solution.

[0032] Optionally, in step S3, the second cleaning solution includes hydrofluoric acid. Using the second cleaning solution of the present invention to clean the wafer after etching in step S2 can remove the SiO2 mask on the wafer surface at room temperature without causing secondary corrosion of the wafer surface. The second cleaning solution includes a BOE solution; the BOE solution has a weight ratio of HF:H2O = 1:5.

[0033] Optionally, in step S1, providing a wafer after Bosch etching process includes the steps of: using a fluorine-based gas as a passivation and etching gas, Ar as a bombardment gas, and performing passivation, silicon etching, and ion bombardment in sequence as a cycle, and repeating the cycle several times to etch the wafer along the depth direction. The passivation is used to passivate the etched surface, the silicon etching is used to etch the passivated surface, and the ion bombardment is used to etch along the depth direction to remove the passivation layer at the bottom.

[0034] Furthermore, in some embodiments, the passivation process uses C4F8 as a passivation gas and Ar as a bombardment gas to passivate the surface to be etched at a pressure of 25 mt, a time of 2.5 s, and a power of 5+2000, wherein the C4F8 gas flow rate is 150 sccm and the Ar gas flow rate is 30 sccm. The silicon etching process uses SF6 as an etching gas and Ar as a bombardment gas to etch the wafer surface at a pressure of 40 mt, a time of 3 s, and a power of 50+2000, wherein the SF6 gas flow rate is 150 sccm and the Ar gas flow rate is 30 sccm. The ion bombardment process uses SF6 as an etching gas and Ar as a bombardment gas to perform ion bombardment in the depth direction at a pressure of 40 mt, a time of 3 s, and a power of 5+2800 to remove the bottom passivation layer, wherein the SF6 gas flow rate is 150 sccm and the Ar gas flow rate is 30 sccm. The three steps of passivation, silicon etching, and ion bombardment are performed sequentially to form a cycle. After the ion bombardment is completed, the process returns to the passivation step. After 111 cycles, the etching depth can reach 100 μm. It is understood that the parameter settings described in the embodiments of the present invention are not to be understood as specific limitations on the Bosch etching process. The process parameters of the Bosch etching process can be specifically set according to the parameters of the desired product.

[0035] Optionally, step S2 includes cleaning and drying the wafer pretreated in step S1 before etching. Step S3 includes cleaning and drying the wafer after etching in step S2 before removing the mask.

[0036] Embodiment: A method for optimizing the sidewall of a Bosch etching process, comprising the steps of:

[0037] S1, pretreatment: providing a wafer processed by a Bosch etching process; and using a first cleaning solution to pretreat the wafer processed by the Bosch etching process.

[0038] Specifically, a wafer treated by a Bosch etching process is provided, which includes the following steps: using a fluorine-based gas as a passivation and etching gas, Ar as a bombardment gas, and performing passivation, silicon etching, and ion bombardment in sequence as a cycle, which is repeated several times to etch the wafer along the depth direction.

[0039] The passivation is used to passivate the etched surface, the silicon etching is used to etch the passivated surface, and the ion bombardment is used to etch in the depth direction to remove the passivation layer at the bottom. Specifically, the passivation uses C4F8 as the passivation gas and Ar as the bombardment gas, and passivates the surface to be etched under the conditions of a pressure of 25mt, a time of 2.5s, and a power of 5+2000; wherein the gas flow rate of C4F8 is 150sccm, and the gas flow rate of Ar is 30sccm. The silicon etching uses SF6 as the etching gas and Ar as the bombardment gas, and etches the wafer surface under the conditions of a pressure of 40mt, a time of 3s, and a power of 50+2000; wherein the gas flow rate of SF6 is 150sccm, and the gas flow rate of Ar is 30sccm. The ion bombardment is performed in the depth direction with SF6 as the etching gas and Ar as the bombardment gas at a pressure of 40mt, a time of 3s, and a power of 5+2800 to remove the bottom passivation layer. The SF6 gas flow rate is 150sccm and the Ar gas flow rate is 30sccm. The three steps of passivation, silicon etching, and ion bombardment are performed sequentially to form a cycle. After the ion bombardment is completed, the process jumps back to the passivation step. After 111 cycles, the etching depth can reach 100um. Figure 1 As shown in FIG. 1 , after the Bosch etching process, the sidewalls are corrugated and relatively rough.

[0040] Wafers processed by the Bosch etching process are pretreated with a first cleaning solution to remove difficult-to-clean solid products formed on the wafer surface and sidewalls after etching. This process specifically involves immersing the wafers in the first cleaning solution at 75°C for 30 minutes. SYS9070 solution is used as the first cleaning solution, which has excellent cleaning performance and can be reused multiple times.

[0041] S2, etching: The wafer pretreated in step S1 is cleaned and dried; then the wafer pretreated in step S1 is placed in a silicon etching solution for room temperature etching: The wafer pretreated in step S1 is placed in the silicon etching solution for room temperature etching for 3 minutes; the ratio of the silicon etching solution is HNO3:H2O:HAC:HF=50:20:2:1 by weight, and the silicon etching rate is 3000A / min. Figure 2 As shown in FIG, after the corrosion treatment, the sharp corners of the side wall corrugations are eliminated, the surface roughness of the side wall is reduced, and a relatively smooth morphology is formed.

[0042] S3, Mask Removal: The wafer etched in step S2 is cleaned and dried; then, at room temperature, the wafer etched in step S2 is cleaned with a second cleaning solution to remove the SiO2 mask from the wafer surface. The second cleaning solution comprises a BOE solution; the BOE solution has a weight ratio of HF to H2O of 1:5.

[0043] The wafer processed by the above-mentioned method of optimizing the sidewall of the Bosch etching process is subjected to magnetron sputtering coating to form a sputtered metal film layer. Figure 3 As shown, after being processed by the optimization method of the present invention, the sharp corners of the corrugations on the sidewalls are eliminated, and the subsequent sputtered metal layer is completely adhered to the sidewalls and is continuous without voids.

[0044] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0045] The above embodiments merely represent preferred embodiments of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for optimizing the sidewall of a Bosch etching process, characterized in that: Including steps: S1, pre-treatment: providing wafers processed by Bosch etching process: using fluorine-based gas as passivation and etching gas, Ar as bombardment gas, with passivation, silicon etching and ion bombardment performed in sequence as one cycle, and repeating the cycle several times to etch the wafer in the depth direction; The passivation process uses C4F8 as the passivation gas and Ar as the bombardment gas, and passivates the surface to be etched under the conditions of a pressure of 25mt, a time of 2.5s, and a power of 5+2000; wherein the gas flow rate of C4F8 is 150sccm and the gas flow rate of Ar is 30sccm; The silicon etching uses SF6 as etching gas and Ar as bombardment gas, and etches the wafer surface under the conditions of pressure of 40mt, time of 3s, and power of 50+2000; wherein the SF6 gas flow rate is 150sccm and the Ar gas flow rate is 30sccm; The ion bombardment is performed in the depth direction with SF6 as etching gas and Ar as bombardment gas under the conditions of pressure of 40mt, time of 3s and power of 5+2800 to remove the bottom passivation layer; wherein the SF6 gas flow rate is 150sccm and the Ar gas flow rate is 30sccm; Pre-treating the wafer after the Bosch etching process using a first cleaning solution; the first cleaning solution includes a SYS9070 solution; S2, etching: placing the wafer pretreated in step S1 in a silicon etching solution for room temperature etching for 3-5 minutes; in step S2, the silicon etching solution has a ratio of HNO3:H2O:HAC:HF=45-50:20-25:2-3:1-1.5 by weight, and the silicon etching rate is 3000-3500 A / min; S3, mask removal: At room temperature, the wafer after etching in step S2 is cleaned with a second cleaning solution to remove the SiO2 mask on the wafer surface; the second cleaning solution includes a BOE solution; in parts by weight, the ratio of the BOE solution is HF:H2O=1:

5.

2. The method according to claim 1, characterized in that The pretreatment in step S1 specifically includes the following steps: immersing the wafer after the Bosch etching process in the first cleaning solution at 75-80° C. for 30-35 minutes.

3. The method according to claim 1, characterized in that Step S2 includes cleaning and drying the wafer pretreated in step S1 before etching the wafer pretreated in step S1.

4. The method according to claim 1, wherein Before removing the mask from the wafer after the etching process in step S2, step S3 includes: cleaning and drying the wafer after the etching process in step S2.

Images