Semiconductor structure and its formation method

Abstract

This application relates to a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate with multiple memory regions on it; a peripheral region between adjacent memory regions, and a circuit region within the peripheral region; an insulating layer covering the substrate; and a first vertical interconnect structure located above the circuit region, penetrating the insulating layer. The bottom of the first vertical interconnect structure is connected to the circuit region, and its top is connected to a first circuit interconnect layer. The top of the first vertical interconnect structure is at least partially embedded in the bottom surface of the first circuit interconnect layer. The upper surface of the insulating layer, partially located in the peripheral region, is concave downwards. This disclosed semiconductor structure helps reduce structural defects, avoid delamination of different material layers, reduce vertical transmission impedance, and improve product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the back-end of line (BEOL) process of semiconductor manufacturing, dissimilar materials located in different layers are prone to delamination at the interface. This is especially true when the step difference at the interface cannot meet the standard, which seriously affects the reliability of semiconductor products and reduces product yield.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can reduce step differences and improve the bonding strength of dissimilar materials.

[0005] This disclosure provides a semiconductor structure, including:

[0006] The substrate has multiple storage areas on it;

[0007] There are peripheral areas between adjacent memory areas, and circuit areas are located within the peripheral areas.

[0008] Insulating layer, covering the substrate;

[0009] A first vertical interconnect structure is located above the circuit region and penetrates the insulating layer. The bottom of the first vertical interconnect structure is connected to the circuit region, and the top is connected to the first circuit interconnect layer. The top of the first vertical interconnect structure is at least partially embedded in the bottom surface of the first circuit interconnect layer. The upper surface of the insulating layer in the peripheral region is concave downward.

[0010] The semiconductor structure disclosed herein helps to reduce structural defects, avoid delamination of different material layers, reduce vertical transmission impedance, and improve product yield.

[0011] In one embodiment, a second vertical interconnect structure is also included, located above the storage area and penetrating the insulating layer. The bottom of the second vertical interconnect structure is connected to the storage area, and the top is connected to the second circuit interconnect layer. The top of the second vertical interconnect structure is at least partially embedded in the bottom surface of the second circuit interconnect layer.

[0012] In one embodiment, a dicing region is also included, located at the edge of the substrate, and the upper surface of the insulating layer located in the dicing region is concave downwards.

[0013] In one embodiment, the bottom surface of the first circuit interconnect layer and the bottom surface of the second circuit interconnect layer are flush.

[0014] In one embodiment, the insulating layer located on the bottom surface of the second circuit interconnect layer has a greater density than the insulating layer located on the bottom surface of the first circuit interconnect layer.

[0015] The technical solution disclosed herein ensures the consistency of surface flatness across multiple memory areas, prevents signal discontinuity in the horizontal direction of the interconnect layer, and avoids delamination between the insulating layer and the upper material, thus minimizing the warpage and structural stress of the entire chip.

[0016] This disclosure also provides a method for forming a semiconductor structure, including:

[0017] A storage region is formed on the substrate;

[0018] There are peripheral areas between adjacent memory areas, and circuit areas are located within the peripheral areas.

[0019] An insulating layer is formed, which covers the substrate;

[0020] A through-hole is formed in the insulating layer, and the through-hole penetrates the insulating layer;

[0021] Filling the vias forms the first vertical interconnect structure;

[0022] A first circuit interconnect layer is formed, the bottom of the first vertical interconnect structure is connected to the circuit area, the top is connected to the first circuit interconnect layer, and the top of the first vertical interconnect structure is at least partially embedded in the bottom surface of the first circuit interconnect layer; the upper surface of the insulating layer located in the peripheral area is concave downward.

[0023] In one embodiment, after the insulating layer is formed and before the via is formed, a suppression film is deposited on the insulating layer. The suppression film has a substantially uniform thickness at various locations above the insulating layer. The suppression film and the insulating layer include a first region and a second region located between adjacent storage regions, and a third region located above the storage regions. The first region has a first width, and the second region has a second width, wherein the second width is greater than the first width.

[0024] In one embodiment, the suppression film can be one or more of polysilicon, silicon nitride, silicon carbonitride, silicon carbide, etc., and the larger the selective etching ratio between the insulating layer and the suppression film, the smaller the thickness of the suppression film.

[0025] In one embodiment, a portion of the inhibition film and a portion of the insulating layer are removed sequentially from top to bottom until the insulating layer in the third region is exposed, while a portion of the inhibition film in the first and second regions remains; wherein the remaining portion of the inhibition film has a first thickness in the first region and a second thickness in the second region, the second thickness being greater than the first thickness.

[0026] In one embodiment, the average of the first thickness and the second thickness is the third thickness, and the larger the selective etching ratio of the insulating layer and the suppressing film layer, the smaller the third thickness.

[0027] In one embodiment, the larger the first width, the larger the first thickness; the larger the second width, the larger the second thickness.

[0028] In one embodiment, the remaining portion of the inhibition film layer in the first region is removed sequentially from top to bottom, as well as a portion of the insulating layer in the third region and a portion of the inhibition film layer in the second region, until the inhibition film layer in the first region is completely removed. The removed insulating layer in the third region has a fourth thickness, and the ratio of the fourth thickness to the first thickness is close to the selective etching ratio of the insulating layer to the inhibition film layer.

[0029] In one embodiment, the inhibition film layer in the second region has a sixth thickness. The inhibition film layer in the second region is removed sequentially from top to bottom, and a portion of the insulating layer in the first region and the third region is removed, until the inhibition film layer in the second region is completely removed. The removed insulating layer has a fifth thickness, and the ratio of the fifth thickness to the sixth thickness is close to the selective etching ratio of the insulating layer to the inhibition film layer.

[0030] In one embodiment, after the insulating layer is formed and before the via is formed, a suppression film is deposited on the insulating layer, the thickness of the suppression film being not uniform at different locations above the insulating layer; the suppression film and the insulating layer include a first region and a second region located between adjacent storage regions, and a third region located above the storage regions, the thickness of the suppression film in the second region, the first region, and the third region decreasing sequentially.

[0031] In one embodiment, the third region location has no inhibition film layer.

[0032] In one embodiment, filling a via to form a first vertical interconnect structure includes depositing a first metal within the via and on the surface of an insulating layer, and removing the first metal located on the surface of the insulating layer to form a first vertical interconnect structure whose top end is above the surface of the insulating layer.

[0033] In one embodiment, forming a first circuit interconnect layer includes depositing a second insulating layer, forming a window in the second insulating layer, and depositing the first circuit interconnect layer in the window, wherein the top end of the first vertical interconnect structure is entirely embedded in the bottom surface of the first circuit interconnect layer.

[0034] In one embodiment, before forming the first circuit interconnect layer, the process includes depositing a second insulating layer, forming a window penetrating the insulating layer and the second insulating layer, depositing a first metal in the window, removing the first metal from the surface of the second insulating layer and the inner surface of the window to form a first vertical interconnect structure; forming the first circuit interconnect layer in the window; wherein the top end of the first vertical interconnect structure is embedded in the first circuit interconnect layer, and a portion of the lower surface of the second insulating layer protrudes downward.

[0035] The technical solution disclosed herein forms an insulating layer with a completely flat upper surface and high uniformity of flatness. There are virtually no step differences in the insulating layer above multiple memory areas, and the upper surfaces of the insulating layers above the memory areas and the peripheral areas are also flat. This provides a good foundation for the fabrication of subsequent circuits, ensures the signal continuity and integrity of the same layer of circuits or interconnection structures, and avoids chip warping. Attached Figure Description

[0036] Figure 1 , Figure 2A-2C , Figures 3A-3B This is a schematic diagram of an embodiment of the semiconductor structure disclosed herein;

[0037] Figures 4-9 This is a schematic diagram of the corresponding structure of the semiconductor structure formation method disclosed herein;

[0038] Figures 10A-10D This is a schematic diagram of the corresponding structure of the semiconductor structure formation method disclosed herein;

[0039] Figures 11A-11C , Figures 12A-12E This is a schematic diagram of the corresponding structure of the semiconductor structure formation method disclosed herein;

[0040] Figures 13-16 This is a flowchart of a method for forming a semiconductor structure according to the present disclosure.

[0041] Explanation of reference numerals in the attached figures:

[0042] 1-Substrate; 20-Storage region; 21-Peripheral region; 22-Cut-out region; 3-Circuit region; 4-Insulating layer; 5-First vertical interconnect structure; 50-Second vertical interconnect structure; 6-First circuit interconnect layer; 60-Second circuit interconnect layer; 8-Suppression film layer; 9-First metal; 10-Second insulating layer. Detailed Implementation

[0043] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0045] In the description of this invention, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0046] In the back-end of line (BEOL) process of semiconductor manufacturing, dissimilar materials located in different layers are prone to delamination at the interface. Especially when the surface flatness of the interface cannot meet the standard and the step difference is too large, structural defects are easily generated in the semiconductor product, which in turn affects the performance and reliability of the semiconductor product and reduces the product yield.

[0047] Based on this, the present disclosure provides a semiconductor structure, such as Figure 1 Shown, including:

[0048] Substrate 1, on which storage regions 20 are located; a peripheral region 21 is located between adjacent storage regions 20, and a circuit region 3 is located in the peripheral region 21; an insulating layer 4 covers the substrate 1; a first vertical interconnect structure 5 is located above the circuit region 3 and penetrates the insulating layer 4, the bottom of the first vertical interconnect structure 5 is connected to the circuit region 3 and the top is connected to the first circuit interconnect layer 6; the top of the first vertical interconnect structure 5 is at least partially embedded in the bottom surface of the first circuit interconnect layer 6; the upper surface of the insulating layer 4 located in the peripheral region 21 is concave downwards.

[0049] The semiconductor structure disclosed herein helps to reduce structural defects, avoid delamination of different material layers, reduce vertical transmission impedance, and improve product yield.

[0050] The semiconductor structure of this disclosure will be specifically described below with reference to embodiments.

[0051] Substrate 1 may include, but is not limited to, a single-crystal silicon substrate 1, a polycrystalline silicon substrate 1, a gallium nitride substrate 1, or a sapphire substrate 1. When substrate 1 is a single-crystal substrate 1 or a polycrystalline substrate 1, it may also be an intrinsic silicon substrate 1 or a doped silicon substrate 1. Furthermore, it may be an N-type polycrystalline silicon substrate 1 or a P-type polycrystalline silicon substrate 1. Substrate 1 may include, but is not limited to, one or more of organic substrates, glass substrates, ceramic substrates, and metal substrates.

[0052] Substrate 1 can be any semiconductor structure, such as a chip, in a wafer or semiconductor manufacturing process. It can be a memory chip, such as volatile memory or non-volatile memory, and can be DRAM or NAND. Figure 1 As shown, each chip includes at least one memory region 20. Between adjacent memory regions 20 are peripheral regions 21. Memory regions 20 may include arrays of transistors, capacitors, etc. Transistors may include gates, word lines, bit lines, etc. Peripheral regions 21 may include devices such as inverters, amplifiers, and decoders. Peripheral regions 21 also include circuit regions 3, which may be NMOS, PMOS, or other structural units. The chip edges may include a seal ring, a scribe line, a test group, etc.

[0053] like Figure 2A As shown, a first vertical interconnect structure 5 is connected above the circuit region 3, and the top of the first vertical interconnect structure 5 is connected to the first circuit interconnect layer 6. The circuit region 3, the first vertical interconnect structure 5, and the first circuit interconnect layer 6 together constitute the devices in the peripheral region 21. The top of the first vertical interconnect structure 5 is at least partially embedded in the bottom surface of the first circuit interconnect layer 6. This structural design can prevent the first vertical interconnect structure 5 from being delaminated from the first circuit interconnect layer 6 and reduce the transmission impedance in the vertical direction.

[0054] like Figure 2A In the T region shown, the top of the first vertical interconnect structure 5 is embedded in the bottom surface of the first circuit interconnect layer 6, wherein the horizontal dimension of the top of the first vertical interconnect structure 5 is smaller than the horizontal dimension of the bottom surface of the first circuit interconnect layer 6, and the top of the first vertical interconnect structure 5 is completely embedded in the bottom surface of the first circuit interconnect layer 6, as shown. Figure 3A As shown. In this embodiment, a rectangle is used to illustrate the bottom surface of the first circuit interconnect layer 6, and a circle is used to illustrate the top surface of the first vertical interconnect structure 5. This is merely an example and does not constitute a specific limitation of the technical solution. Or as... Figure 3B As shown, the diameter of the top of the first vertical interconnect structure 5 is smaller than the width of the bottom surface of the first circuit interconnect layer 6, so the top of the first vertical interconnect structure 5 is only partially embedded in the bottom surface of the first circuit interconnect layer 6.

[0055] This structural design can increase the contact area between the first vertical interconnect structure 5 and the first circuit interconnect layer 6, and also prevent the first vertical interconnect structure 5 and the first circuit interconnect layer 6 from delamination. When there are multiple first vertical interconnect structures 5, it can prevent short circuits between the first vertical interconnect structures 5 and reduce the transmission impedance of the first vertical interconnect structure 5 and the first circuit interconnect layer 6 in the vertical direction.

[0056] The technical solution disclosed herein, as an example, only shows a schematic diagram of the one-to-one correspondence between the first vertical interconnect structure 5 and the first circuit interconnect layer 6. Alternatively, more than one first vertical interconnect structure 5 may be connected to one first circuit interconnect layer 6.

[0057] like Figure 1 , Figure 2B , Figure 2C As shown, the insulating layer 4 covers the entire substrate 1, including the storage region 20, the peripheral region 21, and the circuit region 3. The first vertical interconnect structure 5 penetrates the insulating layer 4, and the first circuit interconnect layer 6 is above the insulating layer 4. The upper surface of the insulating layer 4 located in the peripheral region 21 is concave downwards. As an example, the upper surface of the insulating layer 4 in a portion of the peripheral region 21 may be concave downwards; in some peripheral regions, the upper surface of the insulating layer 4 may not be concave downwards. As an example, only the top of the first vertical interconnect structure 5 is partially embedded in the bottom surface of the first circuit interconnect layer 6, and the upper surface of the insulating layer 4 penetrated by the first vertical interconnect structure 5 is concave downwards.

[0058] In one embodiment, such as Figure 2B As shown, there is a second vertical interconnect structure 50 above the storage area 20, and a second circuit interconnect layer 60 connected to the second vertical interconnect structure 50. The top of the second vertical interconnect structure 50 may be partially embedded in the bottom surface of the second circuit interconnect layer 60. The upper surface of the insulating layer 4 located below the second circuit interconnect layer 60 is concave downward (not shown in the figure).

[0059] The second circuit interconnect layer 60 and the first circuit interconnect layer 6 can be disposed on the same layer, such as... Figure 2B As shown, the bottom surface of the first circuit interconnect layer 6 is substantially flush with the bottom surface of the second circuit interconnect layer 60. The second circuit interconnect layer 60 and the first circuit interconnect layer 6 may also not be set on the same layer. For example, the first circuit interconnect layer 6 may be set first and the second circuit interconnect layer 60 may be set later, or the bottom surface of the first circuit interconnect layer 6 may be lower than the bottom surface of the second circuit interconnect layer 60.

[0060] like Figure 2BAs shown, the first circuit interconnect layer 6 and the second circuit interconnect layer 60 are both above the insulating layer 4. The bottom surfaces of the multiple first circuit interconnect layers 6 located on the multiple memory areas 20 can be substantially flush, meaning that the surface flatness of the insulating layer 4 on the multiple memory areas 20 is required to be highly consistent. As an example, the bottom surfaces of the multiple first circuit interconnect layers 6 and the multiple second circuit interconnect layers 60 are also substantially flush. The upper surface of the insulating layer 4 located below the second circuit interconnect layer 60 can be concave downwards.

[0061] As an example, such as Figure 2C As shown, a dicing region 22 is located at the edge of the substrate 1, and the upper surface of the insulating layer therein may also be concave downwards. The dicing region 22 is the part of the chip that remains after dicing or dicing. Above the insulating layer of the dicing region 22, there may be test pads or interconnection structures (not shown in the figure) connecting test pads and connecting test pads to internal devices. The bottom surface of these interconnection structures may be flush with the bottom surface of the first circuit interconnection layer 6 and the bottom surface of the second circuit interconnection layer 60.

[0062] The concave design of the upper surface of the first circuit interconnect layer 6, the second circuit interconnect layer 60, and the insulating layer 4 in the above technical solution ensures the consistency of surface flatness of multiple storage areas 20, prevents signal discontinuity in the horizontal direction of the interconnect layer, and avoids delamination between the insulating layer 4 and the upper material, so as to minimize the warpage and structural stress of the entire chip.

[0063] like Figure 2A-2C As shown, a second insulating layer 10 is located above the insulating layer 4, and the two are tightly bonded together. The first circuit interconnect layer 6 and the second circuit interconnect layer 60 are embedded within the second insulating layer 10. Figure 2B , Figure 2C As shown, there is a second insulating layer 10 between the first circuit interconnect layer 6 and the insulating layer 4 below it. The lower surface of the second insulating layer 10 protrudes downward because the upper surface of the insulating layer 4 is concave downward. The second insulating layer 10 and the insulating layer 4 can fit tightly together to avoid delamination.

[0064] In one embodiment, such as Figure 2B The insulating layer 4 located on the bottom surface of the second interconnect layer 60 has a higher density than the insulating layer 4 located on the bottom surface of the first interconnect layer 6. This allows the materials of the second insulating layer 10 and the insulating layer 4 to bond tightly at the interface, and also provides a stress-relieving area for the entire chip or memory region 20 structure. Here, density can refer to the density of the material on the surface of the insulating layer 4, such as whether it is porous or dense. For example, the insulating layer 4 on the bottom surface of the second interconnect layer 60 can be a porous structure.

[0065] This disclosure also provides a method for forming a semiconductor structure, including:

[0066] A storage region 20 is formed on a substrate 1; a peripheral region 21 is formed between adjacent storage regions 20, and a circuit region 3 is contained in the peripheral region 21; an insulating layer 4 is formed, which covers the substrate 1; a via is formed in the insulating layer 4, and the via penetrates the insulating layer 4; the via is filled to form a first vertical interconnect structure 5; a first circuit interconnect layer 6 is formed, the bottom of the first vertical interconnect structure 5 is connected to the circuit region 3, and the top is connected to the first circuit interconnect layer 6, wherein the top of the first vertical interconnect structure 5 is at least partially embedded in the bottom surface of the first circuit interconnect layer 6; the upper surface of the insulating layer 4 located in the peripheral region 21 is concave downward.

[0067] The method for forming the semiconductor structure disclosed herein is as follows: Figures 13-16 The flowcharts and structural diagrams corresponding to the methods for forming semiconductor structures are all included. Figure 1 The two cross-sectional views, E-E' and F-F', are explained in detail below.

[0068] Steps S1-S5 are steps taken before forming the through hole.

[0069] Step S1, as follows Figure 4 As shown, a plurality of storage regions 20 are formed on the substrate 1; wherein, there is a peripheral region 21 between adjacent storage regions 20, and there is a circuit region 3 in the peripheral region 21; an insulating layer 4 is formed, and the insulating layer 4 covers the substrate 1.

[0070] The upper surface of the storage region 20 is higher than the upper surface of the circuit region 3, and the area between adjacent storage regions 20 may not have a circuit region 3. The insulating layer 4 completely covers the substrate 1, including the area above the storage region 20, the area between storage regions 20, and other areas above the substrate 1.

[0071] As an example, the upper surface of the formed insulating layer 4 can be an uneven surface. For instance, the upper surface of the insulating layer 4 above the storage area 20 may be higher than the upper surface of the insulating layer 4 in other areas, while the upper surface of the insulating layer 4 in the area between adjacent storage areas 20 may be lower or concave. In one embodiment, the highest points of the upper surfaces of the insulating layers 4 above multiple storage areas 20 are substantially the same; the surfaces of the insulating layers 4 in the area between multiple adjacent storage areas 20 are concave, with a lowest point that is substantially the same.

[0072] In this embodiment, the insulating layer 4 can be one or more of silicon oxide, silicon nitride, etc.

[0073] Step S2, as follows Figure 5 , Figure 9As shown, an inhibition film layer 8 is deposited above the insulating layer 4, dividing the inhibition film layer 8 and the insulating layer 4 into a first region I and a second region II located between adjacent storage regions, and a third region III located above the storage regions. The first region has a first width W1, and the second region has a second width W2, wherein the second width W2 is greater than the first width W1. The surfaces of the insulating layer 4 in the first and second regions between the multiple adjacent storage regions 20 are concave, with a lowest point; the lowest point of the second region is lower than the lowest point of the first region.

[0074] like Figure 5 As shown, an inhibition film is deposited on top of the insulating layer. The thickness of the inhibition film is basically the same at all points above the insulating layer, which is H0. This thickness is the initial thickness of the inhibition film 8, that is, the thickness after deposition without thinning treatment.

[0075] like Figure 5 As shown, the upper surface of the formed inhibition film layer 8 can be an uneven surface. For example, the upper surface of the inhibition film layer 8 located above the storage area 20 is higher than the upper surface of the inhibition film layer 8 in other areas, while the upper surface of the inhibition film layer 8 in the area between adjacent storage areas 20 has the lowest height, or it may be concave. Because the thickness of the inhibition film layer 8 is basically the same everywhere above the insulating layer 4, the shape of the upper surface of the insulating layer 4 is completely extended to the upper surface of the inhibition film layer 8.

[0076] In one embodiment, such as Figure 9 As shown, the thickness of the inhibition film 8 is not exactly the same at different locations above the insulating layer 4. The thickness of the inhibition film 8 located in the second region II is greater than that located in the first region I, and the thickness of the inhibition film 8 located in the first region I is greater than that located in the third region III, with the thickness decreasing sequentially.

[0077] In one embodiment, such as Figure 9 As shown, the third region III may not have the inhibition film 8, while the thickness of the inhibition film 8 in the second region II is greater than the thickness of the inhibition film 8 in the first region I.

[0078] In this embodiment, the suppression film 8 can be one or more of polycrystalline silicon, silicon nitride, silicon carbonitride, silicon carbon oxide, etc.

[0079] Step S3, as follows Figure 6As shown, taking the example that the thickness of the inhibition film layer 8 is basically the same at all places above the insulating layer 4, part of the inhibition film layer 8 and part of the insulating layer 4 are removed from top to bottom until the insulating layer 4 located in the third region III is exposed or completely exposed; wherein the inhibition film layer 8 located in the first region I and the second region II is also partially removed along the thickness direction, and there is still a part remaining along the thickness direction; wherein the remaining part of the inhibition film layer 8 has a first thickness H1 in the first region I and a second thickness H2 in the second region II, and the second thickness H2 is greater than the first thickness H1.

[0080] The upper surface of the formed insulating layer 4 or suppression film layer 8 includes a flush or uneven surface. For example, the upper surface of the insulating layer 4 located above the storage area 20 is flush and higher than the upper surface of the insulating layer 4 or suppression film layer 8 in other areas, while the suppression film layer 8 above the area between adjacent storage areas 20 is concave.

[0081] In a certain first region I, the first thickness H1 is basically the same throughout the region; in a certain second region II, the second thickness is basically the same throughout the region.

[0082] The thinning treatment, removal process or method, and removal steps in the technical solution of this disclosure can be chemical mechanical polishing, wet etching, dry etching, etc. In the removal process, to form a surface that meets certain flatness requirements, when chemical mechanical polishing or etching is used, the polishing slurry, polishing medium, or etching medium has different removal rates for different materials. This removal rate constitutes the selective etching ratio as referred to in this disclosure. For example, when the insulating layer 4 is silicon oxide and the inhibition film layer 8 is one or more of polycrystalline silicon, silicon nitride, silicon carbonitride, or silicon carbide, the same polishing slurry has different removal rates for different materials, and the ratio between these removal rates is the selective etching ratio. The polishing slurry selected in this disclosure can be different, and when a different polishing slurry is used, the removal rate for the same material may change. At this time, the ratio of the removal rates of different materials may also change, i.e., the selective etching ratio also changes. Alternatively, dry etching can be used to remove materials. In this case, different types and energies of plasma can have different removal rates for different materials, and the ratio of the removal rates of different materials also constitutes the selective etching ratio.

[0083] Taking chemical mechanical polishing or etching as an example, when partially removing the inhibition film layer 8 and partially removing the insulating layer 4 from top to bottom, the inhibition film layer 8 located in the third region III is first removed at a first removal rate, while the inhibition film layer 8 located in the first region I is removed at a second removal rate, and the inhibition film layer 8 located in the second region II is removed at a third removal rate, with the first, second, and third removal rates decreasing sequentially. This continues until the insulating layer 4 located in the third region III is exposed or completely exposed. The inhibition film layers 8 located in the first region I and the second region II are partially removed along the thickness direction, with some remaining along the thickness direction. The remaining portion of the inhibition film layer 8 has a first thickness H1 in the first region I and a second thickness H2 in the second region II, with the second thickness H2 being greater than the first thickness H1.

[0084] As an example, when removing the inhibition film layer 8 located in the third region III at the first removal rate, the removal rate is the fastest when mechanical and chemical removal processes are combined; when removing the inhibition film layer 8 located in the first region I at the second removal rate, the chemical removal process is dominant, with some mechanical removal process, and the removal rate is in the middle; when removing the inhibition film layer 8 located in the second region II at the third removal rate, the chemical removal process is dominant, with no mechanical removal process, and the rate is the lowest among the three.

[0085] Here we continue with Figure 5 As shown in the example, the thickness of the inhibition film 8 is basically the same at various locations above the insulating layer 4. The larger the selective etching ratio between the insulating layer 4 and the inhibition film 8, the smaller the thickness H0 of the inhibition film 8 can be. That is, the larger the ratio of the removal rate of the insulating layer 4 to the removal rate of the inhibition film 8, the smaller the thickness H0 of the initially deposited inhibition film 8.

[0086] At this point, to achieve a higher selective etching ratio between the insulating layer 4 and the suppressor film 8, or to control the selective etching ratio between the insulating layer 4 and the suppressor film 8, at least two methods are available. The first method is to change the type of the insulating layer 4 or the suppressor film 8. For example, if the insulating layer 4 is determined to be silicon oxide, the suppressor film 8 can be one or more of polysilicon, silicon nitride, silicon carbonitride, or silicon carbide. Selecting the same polishing slurry will result in different removal rates for different materials in the suppressor film 8, thus affecting the selective etching ratio between the insulating layer 4 and the suppressor film 8. To control the thickness of the suppressor film 8, different materials for the suppressor film 8 can be controlled or selected. Alternatively, the type of the suppressor film 8 can be determined, and the selective etching ratio can be controlled by changing the material type of the insulating layer 4, thereby controlling the initial thickness H0 of the suppressor film 8. The second method, when the type or material of the insulating layer 4 and the suppressor film 8 is determined, can be achieved by designing different polishing slurries or etching media. For example, different oxide particles can be added to the polishing slurry, different chemical additives can be used in the polishing slurry, and different types or energies of plasma can be used as the etching media. Ultimately, the higher the ratio of the removal rate of the insulating layer 4 to the removal rate of the inhibition film 8 (i.e., the higher the selective etching ratio of the insulating layer 4 to the inhibition film 8), the smaller the initial thickness H0 of the deposited inhibition film 8. With controllable initial thickness H0 of the inhibition film 8, costs can be reduced, and unnecessary defects can be avoided.

[0087] like Figure 6 As shown, the average of the first thickness H1 of the remaining inhibition film layer 8 in the first region I and the second thickness H2 of the remaining inhibition film layer 8 in the second region II is the third thickness. Therefore, the larger the selective etching ratio of the insulating layer 4 to the inhibition film layer 8, the smaller the third thickness. Specifically, the average value is calculated by averaging the first thickness H1 and the second thickness H2, and this average value is used as the third thickness. A larger selective etching ratio of the insulating layer 4 to the inhibition film layer 8 results in a smaller third thickness.

[0088] In this embodiment, as Figure 5 The first region I has a first width W1 in the horizontal direction. The larger the first width W1, the better. Figure 6 In the middle, the first thickness H1 of the remaining inhibition film layer 8 is also larger; the second region II has a second width W2 in the horizontal direction, and the larger the second width W2 is, the larger the second thickness H2 is.

[0089] Step S4, as follows Figure 7 As shown, the inhibition film layer 8 and the insulating layer 4 are removed sequentially from top to bottom until the inhibition film layer 8 in the first region I and the third region III is completely removed. The removed materials include, as shown in the figure, Figure 6The remaining portion of the inhibition film layer 8 located in the first region I, as shown, includes a portion of the insulating layer 4 located in the third region III and a portion of the inhibition film layer 8 located in the second region II. During this process, the insulating layer 4 removed in the third region III has a fourth thickness H4, as... Figure 6 As shown, the remaining thickness of the removed inhibition film layer 8 in the first region I is the aforementioned first thickness H1, and the ratio of the fourth thickness H4 to the first thickness H1 is close to the selective etching ratio of the insulating layer 4 and the inhibition film layer 8.

[0090] The upper surface of the formed insulating layer 4 or the inhibition film layer 8 includes a flush or uneven surface. For example, the upper surface of the inhibition film layer 8 or the insulating layer 4 in some areas between adjacent storage areas 20 (second area II) is concave, while the upper surface of the insulating layer 4 in other areas is flush and higher than the upper surface of the insulating layer 4 in the second area II.

[0091] Step S5, as follows Figure 7 , Figure 8 As shown, the remaining inhibition film layer 8 in the second region II has a sixth thickness H6. The entire inhibition film layer 8 located in the second region II is removed sequentially from top to bottom, as well as the insulating layer 4 in other regions, until the upper surface of the formed insulating layer 4 is a completely flush surface. The material removed in this step includes a portion of the insulating layer 4 located in the first region I and the third region III, and the inhibition film layer 8 in the second region II is completely removed. During this process, the removed insulating layer 4 has a fifth thickness H5, and the ratio of the fifth thickness H5 to the sixth thickness H6 is close to the selective etching ratio of the insulating layer 4 and the inhibition film layer 8.

[0092] It is worth noting that in steps S4 and S5, before the removal operation or removal process is executed, after the thickness of the inhibition film layer 8 or the remaining inhibition film layer 8 is determined, the selective etching ratio of the insulating layer 4 and the inhibition film layer 8 can be adjusted by adjusting different polishing slurries or etching media. That is, the selective etching ratio of the insulating layer 4 and the inhibition film layer 8 can be varied. In order to form a completely flush surface on the upper surface of the insulating layer 4, the selective etching ratio can be adjusted.

[0093] Thus, the upper surface of the insulating layer 4 is completely flat, with high uniformity of flatness. There is basically no step difference between the insulating layers 4 above the multiple storage areas 20, and the upper surfaces of the insulating layers 4 above the storage areas 20 and the peripheral areas 21 are also flat. This provides a good foundation for the fabrication of subsequent circuits, ensures the signal continuity and integrity of the same layer of circuits or interconnection structures, and avoids chip warping.

[0094] Steps S61-S64 provide steps for forming vias and the first vertical interconnect structure 5 and the second vertical interconnect structure 50, such as... Figures 10A-10D As shown.

[0095] Step S61, as follows Figure 10A As shown, through holes are formed in the insulating layer 4, penetrating the insulating layer 4 and exposing the circuit structures that need to be connected below, such as the circuit area 3 and the storage area 20.

[0096] Step S62, as follows Figure 10B As shown, filling the vias to form a first vertical interconnect structure 5 includes depositing a first metal 9 inside the vias and on the surface of the insulating layer 4, with the bottom surface of the first metal 9 in contact with the circuit structure to be connected below.

[0097] Step S63, as follows Figure 10C As shown, the first metal 9 located on the surface of the insulating layer 4 is removed to form the first vertical interconnect structure 5 and the second vertical interconnect structure 50. At this time, the exposed surfaces of the first vertical interconnect structure 5 and the second vertical interconnect structure 50 are flush with the upper surface of the insulating layer 4.

[0098] Step S64, as follows Figure 10D As shown, the top of the first vertical interconnect structure 5 is higher than the surface of the insulating layer 4.

[0099] An embodiment of step S64 may be in Figure 10C Based on this, a certain thickness of insulating layer 4 is removed, while the material including the first metal 9 of the first vertical interconnect structure 5 is not removed or is essentially not removed. The upper surface of the insulating layer 4 formed at this time, including the upper surface of the insulating layer 4 located above the plurality of storage areas 20, remains substantially flush; while the upper surface of the insulating layer 4 located between adjacent storage areas 20 may have a concave shape (not shown in the figure). The sidewalls at the top of the first vertical interconnect structure 5 and the second vertical interconnect structure 50 may have insulating layer 4, such as... Figure 10D As shown, the upper surface of the insulating layer 4 at this location is connected to the top of the first vertical interconnect structure 5 and the second vertical interconnect structure 50 to form a continuous structure, that is, the insulating layer 4 at this location is a slope.

[0100] As an example, the insulating layer 4 at this location may not be a slope. For example, the sidewalls at the top of the first vertical interconnect structure 5 and the second vertical interconnect structure 50 may not have an insulating layer 4, and the sidewalls of the first vertical interconnect structure 5 and the second vertical interconnect structure 50 may be substantially perpendicular to the upper surface of the surrounding insulating layer 4 (not shown in the figure).

[0101] In an embodiment of step S64, it can also be in the formation Figure 10C The structure is formed simultaneously. While removing the first metal 9 located on the surface of the insulating layer 4, the top of the first vertical interconnect structure 5 and the second vertical interconnect structure 50 are formed above the upper surface of the insulating layer 4.

[0102] Steps S71-S73 provide an embodiment for forming the first circuit interconnect layer 6 and the second circuit interconnect layer 60, such as... Figures 11A-11C As shown.

[0103] Step S71, in Figure 10D On the basis of, such as Figure 11A As shown, a second insulating layer 10 is deposited, which completely covers the top of the insulating layer 4 and the first vertical interconnect structure 5 and the second vertical interconnect structure 50. The upper surface of the insulating layer 4 located between adjacent storage areas 20 may be concave, and the lower surface of the second insulating layer 10 located between adjacent storage areas 20 is convex downward (not shown in the figure).

[0104] Step S72, as follows Figure 11B As shown, an opening is formed in the second insulating layer 10, exposing the top ends of the first vertical interconnect structure 5 and the second vertical interconnect structure 50, and exposing the upper surface of the insulating layer 4 at the opening position.

[0105] Step S73, as follows Figure 11C As shown, a first circuit interconnect layer 6 and a second circuit interconnect layer 60 are deposited in the window, wherein the top portion or all of the first vertical interconnect structure 5 is embedded in the bottom surface of the first circuit interconnect layer 6. At this time, the lower surfaces of the plurality of first circuit interconnect layers 6 and the lower surfaces of the plurality of second circuit interconnect layers 60 are substantially flush.

[0106] Steps S41-S45 provide another embodiment for forming the first vertical interconnect structure 5, the second vertical interconnect structure 50, the first circuit interconnect layer 6, and the second circuit interconnect layer 60, as follows: Figures 12A-12E As shown, the vias in the semiconductor structure have not yet been formed before step S41.

[0107] like Figure 7 As shown, on the upper surface of the formed insulating layer 4, the upper surface of the insulating layer 4 between adjacent storage areas 20 can be concave, while the other surfaces of the insulating layer 4 are basically flat, and the surface flatness consistency has met the requirements.

[0108] In one embodiment, removing such as Figure 7 The remaining suppression film layer 8 is shown in the concave portion of the insulating layer 4.

[0109] Then step S41, as follows Figure 12A As shown, a second insulating layer 10 is deposited, wherein the upper surface of the insulating layer 4 located between adjacent storage areas 20 is concave upwards, and the corresponding lower surface of the second insulating layer 10 located between adjacent storage areas 20 is convex downwards.

[0110] Step S42, as follows Figure 12BAs shown, a window is formed that penetrates the insulating layer 4 and the second insulating layer 10, directly exposing the underlying circuit structures that need to be connected, such as the circuit area 3 and the storage area 20. The portion of the window located in the insulating layer 4 (i.e., the aforementioned through-hole) is used to form the first vertical interconnect structure 5 and the second vertical interconnect structure 50, and the portion of the window located in the second insulating layer 10 is used to form the first circuit interconnect layer 6 and the second circuit interconnect layer 60.

[0111] Step S43, as Figure 12C As shown, a first metal 9 is deposited in the opening. In addition to completely filling the opening (i.e., the via) located in the insulating layer 4, the first metal 9 is also located on the upper surface of the second insulating layer 10 and the inner surface of the opening at the location of the second insulating layer 10.

[0112] Step S44, as follows Figure 12D As shown, the first metal 9 is removed from the upper surface of the second insulating layer 10 and the inner surface of the opening at the location of the second insulating layer 10 to form the first vertical interconnect structure 5 and the second vertical interconnect structure 50. At this time, the top of the first vertical interconnect structure 5 and the second vertical interconnect structure 50 is higher than the upper surface of the insulating layer 4.

[0113] Step S45, as Figure 12E As shown, a first circuit interconnect layer 6 and a second circuit interconnect layer 60 are formed. In this embodiment, the top end of the first vertical interconnect structure 5 is embedded in the first circuit interconnect layer 6, the top end of the second vertical interconnect structure 50 is embedded in the second circuit interconnect layer 60, and the lower surface of the second insulating layer 10 located in the first circuit interconnect layer 6 protrudes downward.

[0114] In another embodiment, before step S41, the following steps are not removed: Figure 6 Instead of the remaining suppression film layer 8 located within the concave area of ​​the insulating layer 4, a second insulating layer 10 is directly deposited, and then an opening is formed penetrating both the insulating layer 4 and the second insulating layer 10. A first metal 9 is deposited in the opening, and the first metal 9 is removed from the surface of the second insulating layer 10 and the inner surface of the opening to form a first vertical interconnect structure 5. A first circuit interconnect layer 6 and a second circuit interconnect layer 60 are formed in the opening. In this embodiment, the top of the first vertical interconnect structure 5 is embedded in the first circuit interconnect layer 6, and the lower surface of the second insulating layer 10 located in the first circuit interconnect layer 6 protrudes downward.

[0115] The material of the second insulating layer 10 can be one or more of silicon oxide, silicon nitride, and silicon carbonitride. The materials of the second insulating layer 10 and the inhibition film layer 8 can be the same or different.

[0116] The embodiments of steps S41-S45 provide a preferred embodiment for forming a first vertical interconnect structure 5, a second vertical interconnect structure 50, a first circuit interconnect layer 6, and a second circuit interconnect layer 7. Compared with steps S61-S64 combined with steps S71-S73, this embodiment is simpler and more efficient.

[0117] The technical solution disclosed herein can form an insulating layer 4, an inhibitory film layer 8, and a second insulating layer 10 through chemical vapor deposition, physical vapor deposition, or atomic layer deposition. A first vertical interconnect structure 5, a second vertical interconnect structure 50, a first circuit interconnect layer 6, and a second circuit interconnect layer 60 can be formed through electroplating, sputtering, or deposition; the specific formation method is not particularly limited. The material of the first metal 9 can be a conductive material, for example, it may include one or more of copper, tungsten, aluminum, and titanium nitride. The materials of the first circuit interconnect layer 6 and the second circuit interconnect layer 60 can be the same as or different from those of the first metal 9. The insulating layer 4 can be removed by dry etching, including plasma etching or wet etching, to form vias.

[0118] In the technical solution disclosed herein, in order to isolate the first vertical interconnect structure 5, the second vertical interconnect structure 50, the first circuit interconnect layer 6, and the second circuit interconnect layer 60 from the surrounding materials and prevent the metal materials of these structures from diffusing to the surroundings and causing failure, a barrier layer can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The material of the barrier layer can be one or more of tantalum, tantalum nitride, titanium, titanium nitride, etc., without any special limitation.

[0119] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A storage region is formed on the substrate; There is a peripheral area between adjacent storage areas, and the peripheral area contains a circuit area; An insulating layer is formed, the insulating layer covering the substrate; A through-hole is formed in the insulating layer, the through-hole penetrating the insulating layer; The vias are filled to form a first vertical interconnect structure; A first circuit interconnect layer is formed, the bottom of the first vertical interconnect structure is connected to the circuit region, the top of the first circuit interconnect layer is connected to the first circuit interconnect layer, and the top of the first vertical interconnect structure is at least partially embedded in the bottom surface of the first circuit interconnect layer; the upper surface of the insulating layer located in the peripheral region is concave downwards. After forming the insulating layer and before forming the via, an inhibition film is deposited on the insulating layer. The inhibition film has a substantially uniform thickness at various locations on the insulating layer. The inhibition film and the insulating layer include a first region and a second region located between adjacent storage regions, and a third region located above the storage regions. The first region has a first width, and the second region has a second width, wherein the second width is greater than the first width. Part of the inhibition film and part of the insulating layer are removed sequentially from top to bottom until the insulating layer located in the third region is exposed, while part of the inhibition film in the first region and the second region remains; in The remaining portion of the inhibition film has a first thickness in the first region and a second thickness in the second region, the second thickness being greater than the first thickness.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The greater the selective etching ratio between the insulating layer and the suppression film layer, the smaller the thickness of the suppression film layer.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The average of the first thickness and the second thickness is the third thickness. The greater the selective etching ratio of the insulating layer and the inhibition film layer, the smaller the third thickness.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The larger the first width, the larger the first thickness; the larger the second width, the larger the second thickness.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, Continue removing the remaining portion of the inhibition film layer located in the first region from top to bottom, as well as removing a portion of the insulating layer located in the third region, and removing a portion of the inhibition film layer located in the second region, until the inhibition film layer in the first region is completely removed, and the removed insulating layer located in the third region has a fourth thickness.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The inhibition film layer in the second region has a sixth thickness. The inhibition film layer in the second region is removed sequentially from top to bottom, and a portion of the insulating layer in the first region and the third region is removed, until the inhibition film layer in the second region is completely removed. The removed insulating layer has a fifth thickness.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, After the insulating layer is formed and before the via is formed, an inhibition film is deposited on the insulating layer. The thickness of the inhibition film is not uniform in different locations on the insulating layer. The inhibition film and the insulating layer include a first region and a second region located between adjacent storage regions, and a third region located above the storage region. The thickness of the inhibition film located in the second region, the first region, and the third region decreases sequentially.

8. The method for forming a semiconductor structure according to claim 7, wherein the third region does not have the suppression film layer.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, Filling the via to form a first vertical interconnect structure includes depositing a first metal in the via and on the surface of the insulating layer, and removing the first metal located on the surface of the insulating layer to form a first vertical interconnect structure whose top end is above the surface of the insulating layer.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, Form the first circuit interconnect layer. The method includes depositing a second insulating layer, forming a window in the second insulating layer, depositing the first circuit interconnect layer in the window, wherein the top end of the first vertical interconnect structure is completely embedded in the bottom surface of the first circuit interconnect layer.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, Before forming the first circuit interconnect layer, the process includes depositing a second insulating layer, forming a window penetrating the insulating layer and the second insulating layer, depositing a first metal in the window, removing the first metal from the surface of the second insulating layer and the inner surface of the window to form a first vertical interconnect structure; forming the first circuit interconnect layer in the window; wherein the top end of the first vertical interconnect structure is embedded in the first circuit interconnect layer, and a portion of the lower surface of the second insulating layer protrudes downward.

12. A semiconductor structure, manufactured using the method for forming a semiconductor structure as described in any one of claims 1-11, characterized in that, include: A substrate having multiple storage areas; There is a peripheral area between adjacent storage areas, and the peripheral area contains a circuit area; An insulating layer covering the substrate; A first vertical interconnect structure is located above the circuit area and penetrates the insulating layer. The bottom of the first vertical interconnect structure is connected to the circuit area, and the top is connected to the first circuit interconnect layer. The top of the first vertical interconnect structure is at least partially embedded in the bottom surface of the first circuit interconnect layer. The upper surface of the insulating layer, which is partially located in the peripheral area, is concave downwards.

13. The semiconductor structure according to claim 12, characterized in that, It also includes a second vertical interconnect structure located above the storage area and penetrating the insulating layer. The bottom of the second vertical interconnect structure is connected to the storage area, and the top is connected to the second circuit interconnect layer. The top of the second vertical interconnect structure is at least partially embedded in the bottom surface of the second circuit interconnect layer.

14. The semiconductor structure according to claim 12, characterized in that, It also includes a dicing zone located at the edge of the substrate, wherein the upper surface of the insulating layer located in the dicing zone is concave downwards.

15. The semiconductor structure according to claim 13, characterized in that, The bottom surface of the first circuit interconnect layer is flush with the bottom surface of the second circuit interconnect layer.

16. The semiconductor structure according to claim 13, characterized in that, The insulating layer located on the bottom surface of the second circuit interconnect layer has a greater density than the insulating layer located on the bottom surface of the first circuit interconnect layer.

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