A novel bipolar linear power supply and its control method

Abstract

The present invention provides a novel bipolar linear power supply and a control method thereof, relating to the field of electrical performance testing of on-board low-voltage electronic equipment. The power supply comprises a reference generation circuit, a PI controller circuit, a drive conversion circuit, a linear power amplifier circuit, a bus voltage generation circuit, and an output voltage and current sampling circuit. The device can provide a low-noise output for power supply variation experiments of on-board electrical equipment, can meet the power supply requirements of all low-voltage electrical equipment in the vehicle at one time, and simplify the testing process. The device has arbitrary waveform output capability and an AC output capability of at least 200kHz, can simulate power supply variation waveforms under various conditions, and ensure accurate and reliable results of power supply variation experiments.

Description

Technical Field

[0001] The present invention relates to the field of electrical performance testing of vehicle-mounted low-voltage electronic equipment, and in particular to a novel bipolar linear power supply and a control method thereof. Background Art

[0002] Low-voltage (12V, 24V) automotive electrical equipment is powered by batteries. Battery voltage fluctuations can occur due to factors such as engine startup, circuit vibration, and temperature fluctuations. To ensure proper operation of automotive electrical equipment, power supply fluctuation tests are essential, and bipolar power supplies are often used to simulate power supply fluctuations. The international standard ISO 16750-2 (Electrical Loads) and the national standard GB / T 28046.2 (Electrical Loads) specify power supply fluctuation tests for automotive electrical equipment, including DC power supply testing, superimposed AC voltage testing, pulse voltage testing, and reverse voltage testing. These tests require bipolar power supplies with low output ripple, arbitrary waveform output capability, and an AC output frequency of at least 200kHz. Bipolar power supplies using switching technology have high output ripple, which can affect test results. Existing linear power supplies, which mostly have unipolar outputs and limited current output capability, cannot meet the power supply fluctuation testing requirements of entire vehicle electrical equipment. Group testing is often required, resulting in a cumbersome testing process. Summary of the Invention

[0003] The purpose of the present invention is to provide a novel bipolar linear power supply and its control method, which can provide low-noise output for power supply variation experiments of vehicle-mounted electrical equipment and can also simulate power supply variation waveforms under various circumstances.

[0004] To achieve the above-mentioned purpose, the present invention is implemented through the following technical solutions:

[0005] A novel bipolar linear power supply includes a given generation circuit, a PI controller circuit, a drive conversion circuit, a linear power amplifier circuit, a bus voltage generation circuit, and an output voltage and current sampling circuit. The given generation circuit is used to generate a given signal. The output end of the given generation circuit is connected to the input end of the PI controller circuit. The PI controller circuit is used to generate a drive signal. The output end of the PI controller circuit is connected to the input end of the drive conversion circuit. The output end of the drive conversion circuit is connected to the input end of the linear power amplifier circuit. The input end of the bus voltage generation circuit is connected to the mains, and the output end is connected to the linear power amplifier circuit. The input end of the output voltage and current sampling circuit is connected to the output end OUT of the linear power amplifier circuit. The output end of the output voltage and current sampling circuit is connected to the PI controller circuit.

[0006] Furthermore, the bus voltage generating circuit includes a power factor correction circuit and two LLC circuits. The AC power enters the power factor correction circuit to obtain a DC level, which is then connected to two LLC circuits with outputs connected in series to output positive and negative bus voltages +Vs and -Vs to power the linear power amplifier circuit.

[0007] Furthermore, the given generation circuit includes a DSP, an FPGA, a RAM, and a plurality of DACs; the DSP is externally connected to the RAM, and the DSP is connected to the dual-port RAM inside the FPGA;

[0008] The DAC includes a fine-tuning given DAC, a DC given DAC, an AC given waveform DAC, and a dual-channel amplitude adjustment DAC. The FPGA is connected to the fine-tuning given DAC, the DC given DAC, and the AC given waveform DAC respectively. The input of the dual-channel amplitude adjustment DAC is connected to the AC given waveform DAC and the external given. The output of the fine-tuning given DAC is connected to resistor R1, the output of the DC given DAC is connected to resistor R2, the output of the dual-channel amplitude adjustment DAC is connected to resistors R3 and R4, and the remote given is connected to resistor R5, and then connected to the inverting input of the summing operational amplifier. A resistor R6 is connected in series between the inverting input and output of the summing operational amplifier, the non-inverting input is grounded, and the output of the operational amplifier outputs a total given signal that is connected to the input of the PI controller.

[0009] Furthermore, the output voltage and current sampling circuit includes a first-stage operational amplifier proportional amplifier circuit, an AC / DC switching circuit, and a second-stage operational amplifier proportional amplifier circuit connected in sequence. The output end of the second-stage operational amplifier proportional amplifier circuit is connected to a dual-channel ADC, and the dual-channel ADC is connected to the FPGA via an SPI interface. The output end of the first-stage operational amplifier proportional amplifier circuit is also connected to a PI controller circuit.

[0010] The first-stage operational amplifier proportional amplifier circuit includes a voltage first-stage operational amplifier proportional amplifier circuit and a current first-stage operational amplifier proportional amplifier circuit, the AC / DC switching circuit includes a voltage AC / DC switching circuit and a current AC / DC switching circuit, the second-stage operational amplifier proportional amplifier circuit includes a voltage second-stage operational amplifier proportional amplifier circuit and a current second-stage operational amplifier proportional amplifier circuit, the voltage first-stage operational amplifier proportional amplifier circuit, the voltage AC / DC switching circuit, and the voltage second-stage operational amplifier proportional amplifier circuit are connected in sequence, the current first-stage operational amplifier proportional amplifier circuit, the current AC / DC switching circuit, and the current second-stage operational amplifier proportional amplifier circuit are connected in sequence, the output ends of the voltage second-stage operational amplifier proportional amplifier circuit and the current second-stage operational amplifier proportional amplifier circuit are both connected to a dual-channel ADC, and the output ends of the voltage first-stage operational amplifier proportional amplifier circuit and the current first-stage operational amplifier proportional amplifier circuit are both connected to a PI controller circuit;

[0011] The output voltage and current sampling circuit also includes a first voltage-dividing resistor, a second voltage-dividing resistor, and a current sampling resistor. The output voltage OUT is connected to the upper end of the first voltage-dividing resistor, the lower end of the first voltage-dividing resistor is respectively connected to the upper end of the second voltage-dividing resistor and the input end of the first-stage voltage operational amplifier proportional amplifier circuit, the lower end of the second voltage-dividing resistor is respectively connected to the output negative terminal COM and the upper end of the current sampling resistor, the lower end of the current sampling resistor is connected to the bus midpoint 0V, and the output negative terminal COM and the bus midpoint are respectively connected to the current first-stage operational amplifier proportional amplifier circuit.

[0012] Furthermore, the PI controller circuit includes a CV outer loop controller and a CC outer loop controller. The CV outer loop controller includes an integrator composed of an operational amplifier U6 and its peripheral circuits. The CC outer loop controller includes an integrator composed of an operational amplifier U7 and its peripheral circuits, and a proportional controller composed of an operational amplifier U8 and its peripheral circuits. The output end of the operational amplifier U7 is connected to the input end of U8.

[0013] Furthermore, the drive conversion circuit includes an amplifier circuit, a push-pull common emitter amplifier circuit, a push-pull emitter follower, and a positive and negative drive conversion circuit connected in sequence. The inverting input terminal of the amplifier circuit is connected to the drive signal. The push-pull common emitter amplifier circuit uses a mirror current source as the collector resistor. A resistor R16 is connected in series between the output terminal of the push-pull emitter follower and the in-phase input terminal of the amplifier circuit. The positive and negative drive conversion circuit divides the drive into two and outputs two drive signals, drive + and drive -, which are used as the drive for the upper tube MOS and the lower tube MOS respectively.

[0014] Furthermore, the linear power amplifier circuit includes a plurality of MOS tube circuits connected in parallel and having the same structure, and each MOS tube circuit includes an upper MOS tube circuit and a lower MOS tube circuit that are symmetrically connected;

[0015] The upper MOSFET circuit includes: an upper current inner loop integration circuit, an upper overcurrent detection circuit, an upper MOSFET, and an upper bus capacitor C3. The output drive + of the drive conversion circuit is connected to the upper current inner loop integration circuit and the left end of R19 after passing through R17. The right end of R19 is connected to the upper MOSFET source. The upper current inner loop integration circuit is also connected to the upper overcurrent detection circuit and the gate of the upper MOSFET respectively. The drain of the upper MOSFET is connected to the upper end of the upper bus capacitor C3, the source is connected to the upper end of the upper sampling resistor R22, and the lower end of R22 is connected to the upper overcurrent detection circuit.

[0016] The lower MOSFET circuit includes: a lower current inner loop integration circuit, a lower overcurrent detection circuit, a lower MOSFET, and a lower bus capacitor C4. The output drive of the drive conversion circuit is connected to the lower current inner loop integration circuit and the left end of R26 after passing through R18. The right end of R26 is connected to the source of the lower MOSFET. The lower current inner loop integration circuit is also connected to the lower overcurrent detection circuit and the gate of the lower MOSFET respectively. The drain of the lower MOSFET is connected to the lower end of the lower bus capacitor C4, the source is connected to the lower end of the lower sampling resistor R24, and the upper end of R24 is connected to the lower overcurrent detection circuit.

[0017] The lower end of the upper bus capacitor C3 and the upper end of the lower bus capacitor C4 are connected to the midpoint of the bus, the lower end of the resistor R22 and the upper end of the resistor R24 ​​are connected to the midpoint of the MOS tube circuit, and the 0V midpoints of each group of busbars are connected together and then pass through the current sampling resistor to serve as the output negative terminal COM. The midpoints of each group of MOS tube circuits are connected together as the output positive terminal OUT.

[0018] A novel bipolar linear power supply circuit control method is based on the above-mentioned novel bipolar linear power supply circuit, characterized in that a given generation circuit generates a total given signal and inputs it into a PI controller circuit. The PI controller circuit generates a drive signal via a CC outer loop controller and a CV outer loop controller based on the voltage sampling signal and current sampling signal output by the output voltage and current sampling circuit and the total given signal output by the given generation circuit. The drive conversion circuit performs voltage amplification, power amplification, and positive and negative drive conversion on the drive signal output by the PI controller, dividing the drive into two, with drive + and drive - serving as the drives of the upper MOSFET and lower MOSFET in the linear power amplifier circuit respectively. The bus voltage generation circuit outputs positive and negative bus voltages +Vs and -Vs to power part of the linear power amplifier circuit.

[0019] Furthermore, the DSP in the given generation circuit calculates the given output according to the user settings, and the external RAM stores the user-defined waveform. The user collects the output voltage variation waveform of the vehicle battery under various environments, and then inputs the measured waveform into the bipolar power supply through the host computer software to reproduce the actual waveform;

[0020] The FPGA drives the fine-tuning given DAC, DC given DAC, and AC given waveform DAC to generate givens, where the DC given and fine-tuning given are directly output by a single DAC. The AC given uses DDS technology to drive the FPGA-driven parallel port AC given waveform DAC to generate an AC waveform with a fixed amplitude, which serves as the reference voltage for the dual-channel amplitude adjustment DAC. The dual-channel amplitude adjustment DAC adjusts the amplitude of the AC waveform to obtain the final AC given. The FPGA drives the fine-tuning given DAC, DC given DAC, and dual-channel amplitude adjustment DAC all using the SPI interface for communication. The AC given waveform DAC is driven by the parallel port. The sum of each given is used to obtain the total given output.

[0021] Furthermore, in the linear power amplifier circuit, the upper sampling resistor R22 samples the upper MOSFET current. The upper MOSFET current sampling and driving + passes through the current inner loop integration circuit to generate the upper MOSFET drive, which controls the conduction degree of the upper MOSFET Q23. At the same time, the voltage across R22 serves as the input of the upper MOSFET overcurrent protection circuit. When the current flowing through the upper MOSFET is too large, the voltage across R22 increases, the overcurrent detection circuit alarms, and the current inner loop integration circuit is turned off, so that the gate drive voltage of the upper MOSFET Q23 disappears, and the impedance of Q23 increases, thereby reducing the upper MOSFET current.

[0022] The lower sampling resistor R24 ​​samples the lower MOSFET current. The lower MOSFET current sampling and drive + passes through the lower current inner loop integration circuit to generate the lower MOSFET drive, which controls the conduction degree of the lower MOSFET Q24. At the same time, the voltage across R24 serves as the input of the lower MOSFET overcurrent protection circuit. When the current flowing through the lower MOSFET is too large, the voltage across R24 increases, the overcurrent detection circuit alarms, and the current inner loop integration circuit is turned off, so that the gate drive voltage of the lower MOSFET Q24 disappears and the impedance of Q24 increases, thereby reducing the current of the lower MOSFET.

[0023] The advantages of the present invention are:

[0024] The present invention is a linear bipolar power supply. Compared with a switching bipolar power supply, the present invention can provide a lower noise analog power output for power supply variation experiments.

[0025] The present invention adopts a given generation structure of RAM+DSP+FPGA+DAC, which can obtain flexible arbitrary waveform output capability;

[0026] The present invention adopts a control method of the upper and lower tube current inner loop plus the CC / CV outer loop, combined with drive power amplification, to achieve good high-frequency output characteristics and a 200kHz AC output capability, fully meeting the test requirements of power supply variation experiments.

[0027] The present invention adopts an output mode of connecting multiple MOS tubes in parallel, and the number of tubes can be changed according to the test requirements to obtain sufficient current output capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a schematic diagram of the overall structure of a bipolar power supply according to Example 1 of the present invention;

[0029] FIG2 is a schematic diagram of a bipolar power bus voltage generating circuit according to Example 1 of the present invention;

[0030] FIG3 is a schematic diagram of a bipolar power supply reference generating circuit according to Example 1 of the present invention;

[0031] FIG4 is a schematic diagram of output voltage and current sampling of a bipolar power supply according to Example 1 of the present invention;

[0032] FIG5 is a schematic diagram of a bipolar power supply PI controller circuit according to Example 1 of the present invention;

[0033] FIG6 is a schematic diagram of a bipolar power drive conversion circuit according to Example 1 of the present invention;

[0034] 7 is a schematic diagram of a bipolar power supply linear power amplifier circuit according to Example 1 of the present invention;

[0035] FIG8 is a block diagram of a bipolar power supply control loop according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0037] Example 1

[0038] A new bipolar linear power supply circuit, please refer to Figure 1 , including a given generating circuit, a PI controller circuit, a driving conversion circuit, a linear power amplifier circuit, a bus voltage generating circuit and an output voltage and current sampling circuit. The given generating circuit is used to generate a given signal. The output end of the given generating circuit is connected to the input end of the PI controller circuit. The PI controller circuit is used to generate a driving signal. The output end of the PI controller circuit is connected to the input end of the driving conversion circuit. The output end of the driving conversion circuit is connected to the input end of the linear power amplifier circuit. The input end of the bus voltage generating circuit is connected to the mains, and the output end is connected to the linear power amplifier circuit. The input end of the output voltage and current sampling circuit is connected to the output end OUT of the linear power amplifier circuit. The output end of the output voltage and current sampling circuit is connected to the PI controller circuit.

[0039] Please refer to Figure 2 The bus voltage generation circuit includes a power factor correction circuit and two LLC circuits. The AC power enters the power factor correction circuit to obtain a DC level, which is then connected to two LLC circuits with series outputs to output positive and negative bus voltages +Vs and -Vs to power the linear power amplifier circuit.

[0040] Please refer to Figure 3 The reference generation circuit utilizes a dual-core DSP+FPGA architecture, encompassing the DSP, FPGA, RAM, and multiple DACs. The DSP is connected to the external RAM U7, and the DSP is also connected to the dual-port RAM within the FPGA. The DACs include the fine-tuning reference DAC U2, the DC reference DAC U3, the AC waveform DAC U4, and the dual-channel amplitude adjustment DAC U5.

[0041] Please refer to Figure 4 The output voltage and current sampling circuit includes a first-stage operational amplifier proportional amplifier circuit, an AC / DC switching circuit, and a second-stage operational amplifier proportional amplifier circuit connected in sequence. The output end of the second-stage operational amplifier proportional amplifier circuit is connected to a dual-channel ADC, and the dual-channel ADC is connected to the FPGA through an SPI interface. The output end of the first-stage operational amplifier proportional amplifier circuit is also connected to a PI controller circuit.

[0042] The first-stage operational amplifier proportional amplifier circuit includes a voltage first-stage operational amplifier proportional amplifier circuit and a current first-stage operational amplifier proportional amplifier circuit, the AC / DC switching circuit includes a voltage AC / DC switching circuit and a current AC / DC switching circuit, and the second-stage operational amplifier proportional amplifier circuit includes a voltage second-stage operational amplifier proportional amplifier circuit and a current second-stage operational amplifier proportional amplifier circuit. The voltage first-stage operational amplifier proportional amplifier circuit, the voltage AC / DC switching circuit, and the voltage second-stage operational amplifier proportional amplifier circuit are connected in sequence, and the current first-stage operational amplifier proportional amplifier circuit, the current AC / DC switching circuit, and the current second-stage operational amplifier proportional amplifier circuit are connected in sequence. The output ends of the voltage second-stage operational amplifier proportional amplifier circuit and the current second-stage operational amplifier proportional amplifier circuit are both connected to a dual-channel ADC, and the output ends of the voltage first-stage operational amplifier proportional amplifier circuit and the current first-stage operational amplifier proportional amplifier circuit are both connected to a PI controller circuit.

[0043] The output voltage and current sampling circuit also includes a first voltage-dividing resistor, a second voltage-dividing resistor, and a current sampling resistor. The output voltage OUT is connected to the upper end of the first voltage-dividing resistor, the lower end of the first voltage-dividing resistor is respectively connected to the upper end of the second voltage-dividing resistor and the input end of the first-stage voltage operational amplifier proportional amplifier circuit, the lower end of the second voltage-dividing resistor is respectively connected to the output negative terminal COM and the upper end of the current sampling resistor, the lower end of the current sampling resistor is connected to the bus midpoint 0V, and the output negative terminal COM and the bus midpoint are respectively connected to the current first-stage operational amplifier proportional amplifier circuit.

[0044] Please refer to Figure 5 The PI controller circuit includes a CV outer loop controller and a CC outer loop controller. The CV outer loop controller includes an integrator composed of an operational amplifier U6 and its peripheral circuits. The CC outer loop controller includes an integrator composed of an operational amplifier U7 and its peripheral circuits, and a proportional controller composed of an operational amplifier U8 and its peripheral circuits. The output end of the operational amplifier U7 is connected to the input end of U8.

[0045] Please refer to Figure 6The drive conversion circuit includes an amplifier circuit, a push-pull common emitter amplifier circuit, a push-pull emitter follower, and a positive-negative drive conversion circuit connected in sequence. The inverting input terminal of the amplifier circuit is connected to the drive signal. The push-pull common emitter amplifier circuit uses a mirror current source as the collector resistor. A resistor R16 is connected in series between the output terminal of the push-pull emitter follower and the non-inverting input terminal of the amplifier circuit. The positive-negative drive conversion circuit divides the drive into two and outputs two drive signals, drive + and drive -, which are used as the drive of the upper tube MOS and the lower tube MOS respectively.

[0046] Please refer to Figure 7 The linear power amplifier circuit includes multiple groups of parallel-connected MOS tube circuits with the same structure. Each MOS tube circuit includes an upper MOS tube circuit and a lower MOS tube circuit that are symmetrically connected. The upper and lower halves of each group of MOS tube circuits are completely symmetrical.

[0047] The upper MOS tube circuit includes: an upper current inner loop integration circuit, an upper overcurrent detection circuit, an upper MOS tube, and an upper bus capacitor C3. The output drive + of the drive conversion circuit is connected to the upper current inner loop integration circuit and the left end of R19 after passing through R17. The right end of R19 is connected to the upper MOS source. The upper current inner loop integration circuit is also connected to the upper overcurrent detection circuit and the left end of R20 respectively. The right end of R20 is connected to the gate of the upper MOS tube. The drain of the upper MOS tube is connected to the upper end of the upper bus capacitor C3, and the source is connected to the upper end of the upper sampling resistor R22. The lower end of R22 is connected to the upper overcurrent detection circuit, and the gate of the upper MOS tube is also connected to the upper end of the resistor R21.

[0048] The lower MOS tube circuit includes: a lower current inner loop integration circuit, a lower overcurrent detection circuit, a lower MOS tube, and a lower bus capacitor C4. The output drive of the drive conversion circuit is connected to the lower current inner loop integration circuit and the left end of R26 after passing through the resistor R18. The right end of R26 is connected to the lower MOS source. The lower current inner loop integration circuit is also connected to the lower overcurrent detection circuit and the left end of R25 respectively. The right end of R25 is connected to the gate of the lower MOS tube. The drain of the lower MOS tube is connected to the lower end of the lower bus capacitor C4, and the source is connected to the lower end of the lower sampling resistor R24. The upper end of R24 is connected to the lower overcurrent detection circuit, and the gate of the lower MOS tube is also connected to the lower end of the resistor R23.

[0049] The lower end of the upper bus capacitor C3 and the upper end of the lower bus capacitor C4 are connected to the midpoint of the bus, the lower end of the resistor R22, the lower end of the resistor R21, the upper end of the resistor R23, and the upper end of the resistor R24 ​​are connected to the midpoint of the MOS tube circuit. The 0V midpoints of each group of busbars are connected together and then pass through the current sampling resistor to serve as the output negative terminal COM. The midpoints of each group of MOS tube circuits are connected together as the output positive terminal OUT.

[0050] Example 2

[0051] A novel bipolar linear power supply circuit control method is based on the above-mentioned novel bipolar linear power supply circuit, characterized in that a given generation circuit generates a total given signal and inputs it into a PI controller circuit. The PI controller circuit generates a drive signal via a CC outer loop controller and a CV outer loop controller based on the voltage sampling signal and current sampling signal output by the output voltage and current sampling circuit and the total given signal output by the given generation circuit. The drive conversion circuit performs voltage amplification, power amplification, and positive and negative drive conversion on the drive signal output by the PI controller, dividing the drive into two, with drive + and drive - serving as the drives of the upper MOSFET and lower MOSFET in the linear power amplifier circuit respectively. The bus voltage generation circuit outputs positive and negative bus voltages +Vs and -Vs to power part of the linear power amplifier circuit.

[0052] The reference generation circuit DSP is responsible for communicating with the screen and calculating the reference output according to user settings. The external RAM U7 is used to store user-defined waveforms. Users can use an oscilloscope or other device to capture the output voltage fluctuation waveform of the vehicle battery under various conditions. The measured waveform can then be input into the bipolar power supply through the host computer software to replicate the actual waveform. The FPGA U1 is responsible for driving DACs U2, U3, U4, and U5 to generate internal reference signals. The DC reference and fine-tuning reference are directly output from a single DAC. The AC reference uses DDS technology. The FPGA drives the parallel port DAC U4 to generate a fixed-amplitude AC waveform, which serves as the reference voltage for the next-level DAC U5. U5 adjusts the amplitude of the AC waveform to obtain the final AC reference. U2, U3, and U5 all communicate using the SPI interface to reduce the number of FPGA I / O devices. U4 is driven by the parallel port, which has a fast write rate and ensures smooth AC reference waveforms at high-frequency output. In addition to the internal reference, the present invention reserves an external reference input interface for connecting to other waveform generation devices such as an external signal source. The external reference can also be adjusted in amplitude via the DAC U5. R1, R2, R3, R4, R5, R6 and U6 form a summing circuit, and each given value is added to obtain a total given value, wherein the resistance value of R1 is set to 100K, and the resistance values ​​of the other resistors are all 10K. The fine-tuning given value is superimposed on the total given value at a rate of 0.1, so that the present invention can make more precise adjustments to the output amplitude through the fine-tuning given value.

[0053] The output voltage is divided by a resistor divider and then amplified by the first-stage op amp. The amplified result is fed back to the PI controller as output voltage. It also undergoes AC / DC switching and amplification by the second-stage op amp before entering the ADC. The ADC sampling result is transmitted to the FPGA via the SPI interface. A current sampling resistor is connected between the negative output terminal (COM) and the busbar midpoint (0V). Subsequent current sampling is performed in the same manner as voltage sampling.

[0054] The PI controller circuit generates a drive signal based on the voltage / current sampling and the total reference. The CV controller uses pure integral control, while the CC controller uses integral plus proportional control for faster response in CC mode. The controller's integral capacitors, C1 and C2, can be switched to different values ​​using a switch chip to achieve varying response speeds. The outputs of the CV and CC controllers are switched via a 2:1 selector, U9, to produce the final drive signal.

[0055] The drive conversion circuit is responsible for voltage amplification, power amplification, and positive-to-negative drive conversion of the drive output from the PI controller. It employs a totem-pole structure. The first-stage op amp controls the voltage gain, which is determined by the ratio of R14 and R16. The second-stage common-emitter amplifier circuit employs a push-pull structure, using a mirror current source as the collector resistor to achieve high gain. The third-stage emitter follower circuit utilizes a push-pull structure and a two-stage Darlington connection to increase current output capability. The fourth-stage positive-to-negative drive conversion circuit splits the drive into two. The relationship between Drive, Drive+, and Drive- is shown in the waveform diagram at the bottom of Figure 6. Drive+ and Drive- serve as the drivers for the top-side MOSFET and bottom-side MOSFET, respectively.

[0056] In the linear power amplifier circuit, the upper sampling resistor R22 samples the upper MOSFET current. The upper MOSFET current sampling and drive + passes through the current inner loop integration circuit to generate the upper MOSFET drive, which controls the conduction degree of the upper MOSFET Q23. At the same time, the voltage across R22 serves as the input of the upper MOSFET overcurrent protection circuit. When the current flowing through the upper MOSFET is too large, the voltage across R22 increases, the overcurrent detection circuit alarms, and the current inner loop integration circuit is turned off, so that the gate drive voltage of the upper MOSFET Q23 disappears and the impedance of Q23 increases, thereby reducing the upper MOSFET current. The lower sampling resistor R24 ​​samples the lower MOSFET current. The lower MOSFET current sampling and drive + passes through the lower current inner loop integration circuit to generate the lower MOSFET drive, which controls the conduction degree of the lower MOSFET Q24. At the same time, the voltage across R24 serves as the input of the lower MOSFET overcurrent protection circuit. When the current flowing through the lower MOSFET is too large, the voltage across R24 increases, the overcurrent detection circuit alarms, and the current inner loop integration circuit is turned off, so that the gate drive voltage of the lower MOSFET Q24 disappears and the impedance of Q24 increases, thereby reducing the current of the lower MOSFET.

[0057] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A novel bipolar linear power supply circuit control method, characterized in that: Based on a new bipolar linear power supply circuit, including a given generation circuit, a PI controller circuit, a drive conversion circuit, a linear power amplifier circuit, a bus voltage generation circuit and an output voltage and current sampling circuit, the given generation circuit is used to generate a given signal, the output end of the given generation circuit is connected to the input end of the PI controller circuit, the PI controller circuit is used to generate a drive signal, the output end of the PI controller circuit is connected to the input end of the drive conversion circuit, the output end of the drive conversion circuit is connected to the input end of the linear power amplifier circuit, the input end of the bus voltage generation circuit is connected to the mains, and the output end is connected to the linear power amplifier circuit, the input end of the output voltage and current sampling circuit is connected to the output end OUT of the linear power amplifier circuit, and the output end of the output voltage and current sampling circuit is connected to the PI controller circuit; The linear power amplifier circuit includes a plurality of MOS tube circuits connected in parallel and having the same structure, and each MOS tube circuit includes an upper MOS tube circuit and a lower MOS tube circuit that are symmetrically connected; The upper MOSFET circuit includes: an upper current inner loop integration circuit, an upper overcurrent detection circuit, an upper MOSFET, and an upper bus capacitor C3. The output drive + of the drive conversion circuit is connected to the upper current inner loop integration circuit and the left end of R19 after passing through R17. The right end of R19 is connected to the upper MOSFET source. The upper current inner loop integration circuit is also connected to the upper overcurrent detection circuit and the gate of the upper MOSFET respectively. The drain of the upper MOSFET is connected to the upper end of the upper bus capacitor C3, the source is connected to the upper end of the upper sampling resistor R22, and the lower end of R22 is connected to the upper overcurrent detection circuit. The lower MOSFET circuit includes: a lower current inner loop integration circuit, a lower overcurrent detection circuit, a lower MOSFET, and a lower bus capacitor C4. The output drive of the drive conversion circuit is connected to the lower current inner loop integration circuit and the left end of R26 after passing through R18. The right end of R26 is connected to the source of the lower MOSFET. The lower current inner loop integration circuit is also connected to the lower overcurrent detection circuit and the gate of the lower MOSFET respectively. The drain of the lower MOSFET is connected to the lower end of the lower bus capacitor C4, the source is connected to the lower end of the lower sampling resistor R24, and the upper end of R24 is connected to the lower overcurrent detection circuit. The lower end of the upper bus capacitor C3 and the upper end of the lower bus capacitor C4 are connected to the bus midpoint, the lower end of the resistor R22 and the upper end of the resistor R24 ​​are connected to the midpoint of the MOS tube circuit, and the 0V midpoints of each group of busbars are connected together and then pass through the current sampling resistor to serve as the output negative terminal COM. The midpoints of each group of MOS tube circuits are connected together as the output positive terminal OUT. The given generation circuit generates a total given signal and inputs it into the PI controller circuit. The PI controller circuit generates a drive signal through the CC outer loop controller and the CV outer loop controller based on the voltage sampling signal and current sampling signal output by the output voltage and current sampling circuit and the total given signal output by the given generation circuit. The drive conversion circuit performs voltage amplification, power amplification, and positive and negative drive conversion on the drive signal output by the PI controller, dividing the drive into two. The drive + and drive - serve as the drives of the upper MOSFET and the lower MOSFET in the linear power amplifier circuit respectively. The bus voltage generation circuit outputs positive and negative bus voltages +Vs and -Vs to power the linear power amplifier circuit. The DSP in the given generation circuit calculates the given output according to the user's settings, and the external RAM stores the user-defined waveform. The user collects the output voltage variation waveform of the vehicle battery under various environments, and then inputs the measured waveform into the bipolar power supply through the host computer software to reproduce the actual waveform; The FPGA drives the fine-tuning given DAC, DC given DAC, and AC given waveform DAC to generate givens, where the DC given and fine-tuning given are directly output by a single DAC. The AC given uses DDS technology to drive the FPGA-driven parallel port AC given waveform DAC to generate an AC waveform with a fixed amplitude, which serves as the reference voltage for the dual-channel amplitude adjustment DAC. The dual-channel amplitude adjustment DAC adjusts the amplitude of the AC waveform to obtain the final AC given. The FPGA drives the fine-tuning given DAC, DC given DAC, and dual-channel amplitude adjustment DAC all using the SPI interface for communication. The AC given waveform DAC is driven by the parallel port. The sum of each given is used to obtain the total given output.

2. The novel bipolar linear power supply circuit control method according to claim 1, characterized in that: The bus voltage generating circuit includes a power factor correction circuit and two LLC circuits. The mains power enters the power factor correction circuit to obtain a DC level, which is then connected to two LLC circuits with serial outputs to output positive and negative bus voltages +Vs and -Vs to power the linear power amplifier circuit.

3. The novel bipolar linear power supply circuit control method according to claim 1, characterized in that: The given generation circuit includes a DSP, an FPGA, a RAM and a plurality of DACs; the DSP is externally connected to the RAM, and the DSP is connected to the dual-port RAM inside the FPGA; The DAC includes a fine-tuning given DAC, a DC given DAC, an AC given waveform DAC, and a dual-channel amplitude adjustment DAC. The FPGA is connected to the fine-tuning given DAC, the DC given DAC, and the AC given waveform DAC respectively. The input end of the dual-channel amplitude adjustment DAC is connected to the AC given waveform DAC and the external given. The output end of the fine-tuning given DAC is connected to resistor R1, the output end of the DC given DAC is connected to resistor R2, the output end of the dual-channel amplitude adjustment DAC is connected to resistors R3 and R4, and the remote given is connected to resistor R5, and then connected to the inverting input end of the summing operational amplifier. A resistor R6 is connected in series between the inverting input and output ends of the summing operational amplifier, the non-inverting input end is grounded, and the output end of the operational amplifier outputs a total given signal that is connected to the input end of the PI controller.

4. The novel bipolar linear power supply circuit control method according to claim 1, characterized in that: The output voltage and current sampling circuit includes a first-stage operational amplifier proportional amplifier circuit, an AC / DC switching circuit, and a second-stage operational amplifier proportional amplifier circuit connected in sequence. The output end of the second-stage operational amplifier proportional amplifier circuit is connected to a dual-channel ADC, and the dual-channel ADC is connected to an FPGA via an SPI interface. The output end of the first-stage operational amplifier proportional amplifier circuit is also connected to a PI controller circuit. The first-stage op amp proportional amplification circuit includes a voltage first-stage op amp proportional amplification circuit and a current first-stage op amp proportional amplification circuit, the AC / DC switching circuit includes a voltage AC / DC switching circuit and a current AC / DC switching circuit, the second-stage op amp proportional amplification circuit includes a voltage second-stage op amp proportional amplification circuit and a current second-stage op amp proportional amplification circuit, the voltage first-stage op amp proportional amplification circuit, the voltage AC / DC switching circuit, and the voltage second-stage op amp proportional amplification circuit are connected in sequence, the current first-stage op amp proportional amplification circuit, the current AC / DC switching circuit, and the current second-stage op amp proportional amplification circuit are connected in sequence, the output ends of the voltage second-stage op amp proportional amplification circuit and the current second-stage op amp proportional amplification circuit are both connected to a dual-channel ADC, and the output ends of the voltage first-stage op amp proportional amplification circuit and the current first-stage op amp proportional amplification circuit are both connected to a PI controller circuit; The output voltage and current sampling circuit also includes a first voltage-dividing resistor, a second voltage-dividing resistor, and a current sampling resistor. The output voltage OUT is connected to the upper end of the first voltage-dividing resistor, the lower end of the first voltage-dividing resistor is respectively connected to the upper end of the second voltage-dividing resistor and the input end of the first-stage voltage operational amplifier proportional amplifier circuit, the lower end of the second voltage-dividing resistor is respectively connected to the output negative terminal COM and the upper end of the current sampling resistor, the lower end of the current sampling resistor is connected to the bus midpoint 0V, and the output negative terminal COM and the bus midpoint are respectively connected to the current first-stage operational amplifier proportional amplifier circuit.

5. The novel bipolar linear power supply circuit control method according to claim 1, characterized in that: The PI controller circuit includes a CV outer loop controller and a CC outer loop controller. The CV outer loop controller includes an integrator composed of an operational amplifier U6 and its peripheral circuits. The CC outer loop controller includes an integrator composed of an operational amplifier U7 and its peripheral circuits, and a proportional controller composed of an operational amplifier U8 and its peripheral circuits. The output end of the operational amplifier U7 is connected to the input end of U8.

6. The novel bipolar linear power supply circuit control method according to claim 1, characterized in that: The drive conversion circuit includes an amplifier circuit, a push-pull common emitter amplifier circuit, a push-pull emitter follower, and a positive-negative drive conversion circuit connected in sequence. The inverting input terminal of the amplifier circuit is connected to the drive signal. The push-pull common emitter amplifier circuit uses a mirror current source as a collector resistor. A resistor R16 is connected in series between the output terminal of the push-pull emitter follower and the inverting input terminal of the amplifier circuit. The positive-negative drive conversion circuit divides the drive into two and outputs two drive signals, drive + and drive -, which are used as the drive of the upper tube MOS and the lower tube MOS respectively.

7. The novel bipolar linear power supply circuit control method according to claim 1, characterized in that: In the linear power amplifier circuit, the upper sampling resistor R22 samples the upper MOSFET current. The upper MOSFET current sampling and drive + passes through the current inner loop integration circuit to generate the upper MOSFET drive, which controls the conduction degree of the upper MOSFET Q23. At the same time, the voltage across R22 serves as the input of the upper MOSFET overcurrent protection circuit. When the current flowing through the upper MOSFET is too large, the voltage across R22 increases, the overcurrent detection circuit alarms, and the current inner loop integration circuit is turned off, so that the gate drive voltage of the upper MOSFET Q23 disappears and the impedance of Q23 increases, thereby reducing the upper MOSFET current. The lower sampling resistor R24 ​​samples the lower MOSFET current. The lower MOSFET current sampling and drive + passes through the lower current inner loop integration circuit to generate the lower MOSFET drive, which controls the conduction degree of the lower MOSFET Q24. At the same time, the voltage across R24 serves as the input of the lower MOSFET overcurrent protection circuit. When the current flowing through the lower MOSFET is too large, the voltage across R24 increases, the overcurrent detection circuit alarms, and the current inner loop integration circuit is turned off, so that the gate drive voltage of the lower MOSFET Q24 disappears and the impedance of Q24 increases, thereby reducing the current of the lower MOSFET.

Images