A broadband gain, frequency tunable high-Q filter

Abstract

The application discloses a broadband gain and frequency tunable high-Q filter, which comprises a low-noise amplifier unit and a differential N-channel filter unit, wherein the low-noise amplifier unit is a load-balanced low-noise amplifier with tunable gain, single-end input and differential output; the differential N-channel filter unit is driven by a four-phase clock with a phase difference of 90 degrees, and the four-phase clock input is connected with an externally input signal with a phase difference of 90 degrees; the input end of the low-noise amplifier is connected with an input signal of an antenna end, the output positive end of the low-noise amplifier is connected with the input positive end of the differential N-channel filter, and the output negative end of the low-noise amplifier is connected with the input negative end of the differential N-channel filter. On the basis of the high-Q filter, the application realizes the characteristics of single-end to double-end signal receiving, gain adjustment, filter center frequency tuning, low noise, high bandwidth, output differential balance and strong load capacity.

Description

Technical Field

[0001] This invention belongs to the field of electronic information and relates to a filter, specifically a broadband gain, frequency-tunable high-Q filter. Background Technology

[0002] With the rapid development of wireless communication technology and the establishment and improvement of modern communication theory, the pursuit of speed and efficiency in wireless communication has led to different requirements for the operating frequency, data rate, and communication distance of different communication protocols. Therefore, the widespread coexistence of multi-band, multi-mode, and multi-standard wireless communication applications will become an important trend. As an important component of wireless transceiver systems, the filtering performance of filters is closely related to the performance of receivers. Therefore, wideband tunable high-Q filters are extremely important.

[0003] Compared to BAW and SAW filters with fixed passbands, N-channel filters can precisely adjust the passband position by controlling the center frequency with digital switches. They are also well-matched with the front-end single-ended to dual-ended low-noise amplifiers, offering advantages such as low noise figure, easy integration, high gain, tunable center frequency, and saving on external baluns. Therefore, they have extremely broad application prospects in multi-mode and multi-frequency radio communication systems. Summary of the Invention

[0004] The purpose of this invention is to provide a broadband, frequency-tunable, high-Q filter. This filter incorporates a low-noise single-ended to dual-ended amplifier as its input stage, reducing the area required for an off-chip balun, matching the antenna input signal, reducing noise, increasing gain, and adding tunable gain and linearity. It employs a differential N-channel filter to achieve a high Q value and tunable center frequency, while also exhibiting low power consumption and high linearity. An output stage buffer is used to balance the two output signals and perform output stage matching.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A broadband, frequency-tunable, high-Q filter includes a low-noise amplifier unit and a differential N-channel filter unit, wherein:

[0007] The low-noise amplifier unit is a load-balanced low-noise amplifier with gain tunable single-ended input and differential output.

[0008] The differential N-channel filter unit is driven by a four-phase clock with a phase difference of 90°. The four-phase clock input is connected to an externally input signal with a phase difference of 90°.

[0009] The input terminal of the low-noise amplifier is connected to the input signal of the antenna terminal. The positive output terminal of the low-noise amplifier is connected to the positive input terminal of the differential N-channel filter, and the negative output terminal of the low-noise amplifier is connected to the negative input terminal of the differential N-channel filter. The received signal from one antenna terminal is input-matched by the low-noise amplifier and converted into two fully differential signals. The two fully differential signals are simultaneously input to the differential N-channel filter. The two fully differential signals are respectively charged and discharged by four-phase clocks with a phase difference of 90°. The clocks of the two fully differential signals are 180° out of phase, thereby realizing differential output. The differential output is filtered by summing the positive and negative input signals, circuit output gain, and phase balance, and then outputs a balanced differential signal.

[0010] Compared with the prior art, the present invention has the following advantages:

[0011] 1. Compared with traditional SAW filters and BAW filters, the broadband tunable high-Q filter of the present invention can achieve tunability of the center frequency.

[0012] 2. Compared with traditional N-path filters, the broadband tunable high-Q filter of the present invention can achieve gain tunability and has the effects of output balance and output matching.

[0013] 3. Compared with traditional low-noise amplifiers, the low-noise amplifier in this invention can achieve good input matching, has differential output with balanced load, lower noise performance, and the effect of embedded balun.

[0014] 4. Based on a high-Q filter, this invention achieves the characteristics of single-ended to dual-ended signal reception, adjustable gain, tunable filter center frequency, low noise, high bandwidth, output differential balance, and strong load-carrying capacity. Attached Figure Description

[0015] Figure 1 This is a structural diagram of the broadband gain, frequency-tunable high-Q filter in this invention.

[0016] Figure 2 This is a circuit diagram of the low-noise amplifier unit in this invention.

[0017] Figure 3 This is a circuit diagram of the differential N-channel filter unit in this invention.

[0018] Figure 4 This is a graph showing the tunable center frequency of the filter.

[0019] Figure 5 This is a graph showing the tunable gain of the filter.

[0020] Figure 6 This is a graph showing the noise figure of the filter frequency tuning. Detailed Implementation

[0021] The technical solution of the present invention will be further described below with reference to the accompanying drawings, but it is not limited thereto. Any modifications or equivalent substitutions to the technical solution of the present invention that do not depart from the spirit and scope of the technical solution of the present invention should be covered within the protection scope of the present invention.

[0022] This invention provides a broadband, frequency-tunable, high-Q filter that can be used in the front end of an RF receiver. Figure 1 As shown, the broadband gain, frequency-tunable high-Q filter includes a low-noise amplifier unit and a differential N-channel filter unit, wherein:

[0023] The low-noise amplifier unit is a load-balanced low-noise amplifier with gain adjustable single-ended input and differential output. The gain of the low-noise amplifier is controlled by the bias voltage VB1 to achieve the gain tuning function.

[0024] The differential N-channel filter unit is driven by a four-phase clock with a 90° phase difference, which drives 16 switches composed of NMOS transistors to charge and discharge the capacitor, thereby realizing filtering and center frequency tuning functions. The clock signals driven between the differential connection positive and negative signals are 180° out of phase, thus forming a differential output signal. The two differential signals are filtered and have the gain and phase balanced after passing through the signal summing circuit of the positive and negative inputs.

[0025] The input terminal of the low-noise amplifier is connected to the input signal of the antenna terminal, the positive output terminal of the low-noise amplifier is connected to the positive input terminal of the differential N-channel filter, and the negative output terminal of the low-noise amplifier is connected to the negative input terminal of the differential N-channel filter. The low-noise amplifier converts the small signal from the single-ended antenna terminal into a differential signal through two paths and performs signal amplification and noise cancellation, while also having an adjustable gain function.

[0026] The four-phase clock input of the differential N-channel filter is connected to an externally input signal with a phase difference of 90°, and the differential N-channel filter outputs a balanced differential signal.

[0027] In this invention, the received signal from one antenna is input-matched by a low-noise amplifier and converted into two fully differential signals. The two fully differential signals are simultaneously input to a differential N-channel filter. The two fully differential signals charge and discharge four grounded capacitors through a four-phase clock with a phase difference of 90°. The clocks of the two fully differential signals are 180° out of phase, thereby achieving differential output. The differential output is then summed with the forward and reverse input signals to balance the gain and phase of the two output signals and perform output matching to drive a small output load.

[0028] In this invention, a choke is connected to the input terminal of the low-noise amplifier, thereby achieving a state where the DC signal is grounded and the AC signal is floating. The bias of the two input NMOS transistors of the low-noise amplifier is controlled by an external voltage signal, thereby adjusting the transconductance of the input stage to achieve adjustment of the gain and linearity.

[0029] In this invention, the four-phase clock signal of the differential N-channel filter is driven by a square wave signal with a variable frequency and a 90° phase difference, thereby achieving tuning of the filter's center frequency.

[0030] In this invention, the output of the differential N-channel filter is balanced in phase gain and matched, thereby enhancing its load-carrying capacity.

[0031] In this invention, such as Figure 2 As shown, the low-noise amplifier unit includes 7 NMOS transistors M1 to M7, 5 capacitors C1 to C5, 6 resistors R1 to R6, and one inductor L, wherein:

[0032] The drain of the NMOS transistor M5, one end of resistor R1, and one end of resistor R2 are all connected to VDD.

[0033] The source of NMOS transistor M2, the source of NMOS transistor M6, the source of NMOS transistor M7, and one end of inductor L are all connected to GND.

[0034] One end of the capacitor C1 serves as the input terminal of the low-noise amplifier;

[0035] The other end of capacitor C1, the source of NMOS transistor M1, the other end of inductor L, and one end of capacitor C2 are all connected to the source of NMOS transistor M5.

[0036] The other end of capacitor C2 and one end of resistor R6 are connected to the gate of NMOS transistor M2.

[0037] The drain of NMOS transistor M1 and the source of NMOS transistor M3 are both connected to one end of capacitor C3.

[0038] The other end of capacitor C3 and one end of resistor R3 are connected to the gate of NMOS transistor M6.

[0039] The drain of the NMOS transistor M2 and one end of the capacitor C4 are simultaneously connected to the source of the NMOS transistor M4.

[0040] The other end of capacitor C4 and one end of resistor R4 are connected to the gate of NMOS transistor M7.

[0041] The drain of the NMOS transistor M3, the other end of the resistor R1, and one end of the capacitor C5 are all connected to the drain of the NMOS transistor M7, and are used as the positive output terminal VO+ of the low noise amplifier.

[0042] The drain of the NMOS transistor M4 and the other end of the resistor R2 are simultaneously connected to the drain of the NMOS transistor M6, serving as the negative output terminal VO- of the low-noise amplifier;

[0043] The other end of capacitor C5 and one end of resistor R5 are connected to the gate of NMOS transistor.

[0044] The gate of the NMOS transistor M1 is connected to the other end of the resistor R6, which serves as the input bias voltage VB1.

[0045] The gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor M4, serving as the input bias voltage VB2.

[0046] The other end of resistor R3 is connected to the other end of resistor R4, serving as the input bias voltage VB3;

[0047] The other end of the resistor R5 serves as the input bias voltage VB4.

[0048] In this invention, such as Figure 3 As shown, the differential N-channel filter unit includes 12 capacitors C6-C17, 20 NMOS transistors M8-M27, and 4 resistors R7-R10, wherein:

[0049] The drain of NMOS transistor M24, the drain of NMOS transistor M26, one end of resistor R7, and one end of resistor R9 are all connected to VDD.

[0050] The source of NMOS transistor M25 and the source of NMOS transistor M27 are both connected to VSS.

[0051] One end of capacitors C6 to C13 and the source of NMOS transistors M25 and M27 are simultaneously connected to GND;

[0052] The sources of the NMOS transistors M8, M10, M12, and M14 are connected together to serve as the positive input terminal VIN+ of the differential N-channel filter.

[0053] The sources of the NMOS transistors M16, M18, M20, and M22 are connected together to serve as the negative input terminal VIN- of the differential N-channel filter.

[0054] The drains of the NMOS transistors M9, M11, M13, and M15 are simultaneously connected to one end of capacitors C14 and C17.

[0055] The drains of the NMOS transistors M17, M19, M21, and M23 are simultaneously connected to one end of capacitors C16 and C15;

[0056] The gates of the NMOS transistors M8, M9, M16, and M17 are connected to the input clock signal CLK3;

[0057] The gates of the NMOS transistors M10, M11, M18, and M19 are connected to the input clock signal CLK0;

[0058] The gates of the NMOS transistors M12, M13, M20, and M21 are connected to the input clock signal CLK1;

[0059] The gates of the NMOS transistors M14, M15, M22, and M23 are connected to the input clock signal CLK2;

[0060] The drain of NMOS transistor M8, the source of NMOS transistor M9, the drain of NMOS transistor M20, the source of NMOS transistor M21, and the other end of capacitor C6 are all connected to the other end of capacitor C12.

[0061] The drain of NMOS transistor M10, the source of NMOS transistor M11, the drain of NMOS transistor M22, the source of NMOS transistor M23, and the other end of capacitor C7 are all connected to the other end of capacitor C13.

[0062] The drain of NMOS transistor M12, the source of NMOS transistor M13, the drain of NMOS transistor M16, the source of NMOS transistor M17, and the other end of capacitor C8 are all connected to the other end of capacitor C10.

[0063] The drain of NMOS transistor M14, the source of NMOS transistor M15, the drain of NMOS transistor M18, the source of NMOS transistor M19, and the other end of capacitor C9 are all connected to the other end of capacitor C11.

[0064] One end of resistor R8 and one end of resistor R10 are connected to VCM at the same time;

[0065] The other end of capacitor C14 and the other end of resistor R7 are simultaneously connected to the gate of NMOS transistor M24.

[0066] The other end of capacitor C15 and the other end of resistor R8 are connected to the gate of NMOS transistor M25.

[0067] The other end of capacitor C16 and the other end of resistor R9 are simultaneously connected to the gate of NMOS transistor M26.

[0068] The other end of capacitor C17 and the other end of resistor R10 are simultaneously connected to the gate of NMOS transistor M27;

[0069] The source of the NMOS transistor M24 is connected to the drain of the NMOS transistor M25, serving as the positive output VOP;

[0070] The source of the NMOS transistor M26 is connected to the drain of the NMOS transistor M27, serving as the negative output VON.

[0071] The working principle is as follows:

[0072] like Figure 1 As shown, the small signal from the antenna is amplified by the common-source and common-gate paths at the input of the low-noise amplifier, and then split into two differential signals, which enter the positive and negative ports of the differential N-channel filter respectively. Each port signal is driven by a four-phase clock signal with a 90° phase difference, and the clock drive signals of the two port signals are 180° out of phase, thus realizing differential output. The differential output is balanced in terms of gain and phase by summing the positive and negative input signals, and output matching is performed to drive a small output load.

[0073] like Figure 2 As shown, the low-noise amplifier consists of NMOS transistors and resistors / capacitors. A small input signal is fed to the source of NMOS transistor M1, the source of NMOS transistor M5, and the gate of NMOS transistor M2. NMOS transistors M1 and M5 match the input signal to achieve a low input reflection coefficient. The input signal is amplified simultaneously via the common-gate stage of NMOS transistor M1 and the common-source stage of NMOS transistor M2. The two NMOS transistors have equal bias voltages and equal transconductances, forming two differential signals and eliminating noise. MOS transistors M3 and M4 improve input isolation and overall system stability. NMOS transistor M5 acts as positive feedback in the common-gate amplification path, increasing the gain of the common-gate amplification path to achieve the same gain as the common-source amplifier circuit, thus realizing differential output with symmetrical load. NMOS transistors M6 and M7 are biased in the weak inversion region, improving linearity and voltage gain. Inductor L is an external choke, placing the source of NMOS transistor M1 on DC ground. Gain and linearity are controlled by adjusting the voltage value of the DC bias signal VB1.

[0074] like Figure 3As shown, the differential N-channel filter unit consists of NMOS transistors, capacitors, and resistors. Each signal is controlled by a four-phase clock drive signal with a 90° phase difference, which controls the switching of the NMOS transistors. When the clock drive signal is high, the switch is closed, charging the filter capacitor; when the clock drive signal is low, the switch is closed, keeping the capacitor voltage constant. This allows the input signal to be transmitted at the drive signal frequency, while the input signal attenuates at frequencies deviating from the drive signal frequency. This achieves the effect of tuning the filter's center frequency by controlling the drive signal frequency. The two differential input signals of the differential N-channel filter have a 180° phase difference between their drive signals, thus achieving the same filtering effect. Furthermore, it improves the linearity of the filter; capacitors C14 to C17 couple the two input AC signals to the gates of NMOS transistors M24 to M27. The bias DC voltage is controlled by the resistor path and isolated from the DC voltage of the previous stage through capacitors C14 to C17. NMOS transistors M24 and M25 act as source followers and common-source amplifiers, respectively, to add the two signals. NMOS transistors M26 and M27 have the same function and their input signals are reversed, thereby generating a differential output signal with balanced gain and phase. At the same time, NMOS transistors M24 and M26 act as source followers, improving the system's load-driving capability.

[0075] Depend on Figures 4-6 As can be seen, this invention achieves the characteristics of tunable gain, tunable filter center frequency, low noise, differential balanced output, and strong load-carrying capacity based on a high-Q filter, thus meeting the needs of multi-mode multi-frequency wireless communication.

Claims

1. A broadband, frequency-tunable, high-Q filter, characterized in that... The filter includes a low-noise amplifier unit and a differential N-channel filter unit, wherein: The low-noise amplifier unit is a load-balanced low-noise amplifier with gain tunable single-ended input and differential output. The differential N-channel filter unit is driven by a four-phase clock with a phase difference of 90°. The four-phase clock input is connected to an externally input signal with a phase difference of 90°. The input terminal of the low-noise amplifier is connected to the input signal of the antenna terminal. The positive output terminal of the low-noise amplifier is connected to the positive input terminal of the differential N-channel filter, and the negative output terminal of the low-noise amplifier is connected to the negative input terminal of the differential N-channel filter. The received signal from one antenna terminal is input matched by the low-noise amplifier and converted into two fully differential signals. The two fully differential signals are simultaneously input to the differential N-channel filter. The two fully differential signals are respectively charged and discharged by four-phase clocks with a phase difference of 90°. The clocks of the two fully differential signals are 180° out of phase, thereby realizing differential output. The differential output is filtered by summing the positive and negative input signals, circuit output gain, and phase balance, and then outputs a balanced differential signal. The differential N-channel filter unit includes 12 capacitors C6~C17, 20 NMOS transistors M8~M27, and 4 resistors R7~R10, wherein: The drain of NMOS transistor M24, the drain of NMOS transistor M26, one end of resistor R7, and one end of resistor R9 are all connected to VDD. The source of NMOS transistor M25 and the source of NMOS transistor M27 are both connected to VSS. One end of capacitors C6~C13 and the source of NMOS transistors M25 and M27 are simultaneously connected to GND; The sources of the NMOS transistors M8, M10, M12, and M14 are connected together to serve as the positive input terminal VIN+ of the differential N-channel filter. The sources of the NMOS transistors M16, M18, M20, and M22 are connected together to serve as the negative input terminal VIN- of the differential N-channel filter. The drains of the NMOS transistors M9, M11, M13, and M15 are simultaneously connected to one end of capacitors C14 and C17. The drains of the NMOS transistors M17, M19, M21, and M23 are simultaneously connected to one end of capacitors C16 and C15; The gates of the NMOS transistors M8, M9, M16, and M17 are connected to the input clock signal CLK3; The gates of the NMOS transistors M10, M11, M18, and M19 are connected to the input clock signal CLK0; The gates of the NMOS transistors M12, M13, M20, and M21 are connected to the input clock signal CLK1; The gates of the NMOS transistors M14, M15, M22, and M23 are connected to the input clock signal CLK2; The drain of NMOS transistor M8, the source of NMOS transistor M9, the drain of NMOS transistor M20, the source of NMOS transistor M21, and the other end of capacitor C6 are all connected to the other end of capacitor C12. The drain of NMOS transistor M10, the source of NMOS transistor M11, the drain of NMOS transistor M22, the source of NMOS transistor M23, and the other end of capacitor C7 are all connected to the other end of capacitor C13. The drain of NMOS transistor M12, the source of NMOS transistor M13, the drain of NMOS transistor M16, the source of NMOS transistor M17, and the other end of capacitor C8 are all connected to the other end of capacitor C10. The drain of NMOS transistor M14, the source of NMOS transistor M15, the drain of NMOS transistor M18, the source of NMOS transistor M19, and the other end of capacitor C9 are all connected to the other end of capacitor C11. One end of resistor R8 and one end of resistor R10 are connected to VCM at the same time; The other end of capacitor C14 and the other end of resistor R7 are simultaneously connected to the gate of NMOS transistor M24. The other end of capacitor C15 and the other end of resistor R8 are connected to the gate of NMOS transistor M25. The other end of capacitor C16 and the other end of resistor R9 are simultaneously connected to the gate of NMOS transistor M26. The other end of capacitor C17 and the other end of resistor R10 are simultaneously connected to the gate of NMOS transistor M27; The source of the NMOS transistor M24 is connected to the drain of the NMOS transistor M25, serving as the positive output VOP; The source of the NMOS transistor M26 is connected to the drain of the NMOS transistor M27, serving as the negative output VON.

2. The broadband gain, frequency-tunable high-Q filter according to claim 1, characterized in that... The low-noise amplifier unit includes 7 NMOS transistors M1~M7, 5 capacitors C1~C5, 6 resistors R1~R6, and one inductor L, wherein: The drain of the NMOS transistor M5, one end of resistor R1, and one end of resistor R2 are all connected to VDD. The source of NMOS transistor M2, the source of NMOS transistor M6, the source of NMOS transistor M7, and one end of inductor L are all connected to GND. One end of the capacitor C1 serves as the input terminal of the low-noise amplifier; The other end of capacitor C1, the source of NMOS transistor M1, the other end of inductor L, and one end of capacitor C2 are all connected to the source of NMOS transistor M5. The other end of capacitor C2 and one end of resistor R6 are connected to the gate of NMOS transistor M2. The drain of NMOS transistor M1 and the source of NMOS transistor M3 are both connected to one end of capacitor C3. The other end of capacitor C3 and one end of resistor R3 are connected to the gate of NMOS transistor M6. The drain of the NMOS transistor M2 and one end of the capacitor C4 are simultaneously connected to the source of the NMOS transistor M4. The other end of capacitor C4 and one end of resistor R4 are connected to the gate of NMOS transistor M7. The drain of the NMOS transistor M3, the other end of the resistor R1, and one end of the capacitor C5 are all connected to the drain of the NMOS transistor M7, and are used as the positive output terminal VO+ of the low noise amplifier. The drain of the NMOS transistor M4 and the other end of the resistor R2 are simultaneously connected to the drain of the NMOS transistor M6, serving as the negative output terminal VO- of the low-noise amplifier; The other end of capacitor C5 and one end of resistor R5 are connected to the gate of NMOS transistor. The gate of the NMOS transistor M1 is connected to the other end of the resistor R6, which serves as the input bias voltage VB1. The gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor M4, serving as the input bias voltage VB2. The other end of resistor R3 is connected to the other end of resistor R4, serving as the input bias voltage VB3; The other end of the resistor R5 serves as the input bias voltage VB4.

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