MOS tube high-side output protection circuit, system and device

Abstract

The present application discloses a protection circuit, system and device for a high-side output of a MOS tube, wherein the protection circuit for the high-side output of the MOS tube comprises a current limiting protection resistor connected to a load, a bias delay circuit, a gate drive circuit, a control circuit, a NAND gate and a control signal terminal, the bias delay circuit comprises a second triode and a ninth resistor, the two ends of the ninth resistor are respectively connected to the emitter and the base of the second triode, the base of the second triode is connected to the load, the NAND gate comprises a first input terminal and a second input terminal, the first input terminal is connected to the collector of the second triode, the second input terminal is connected to the input terminal of the control signal terminal, the output terminal of the control signal terminal is connected to the gate drive circuit of the MOS tube, the output terminal of the NAND gate is connected to the control circuit, the control circuit is used to pull down the output terminal voltage of the control terminal to turn off the MOS tube, detect whether the load is short-circuited, and start current limiting of the MOS tube, thereby protecting the high-side output of the MOS tube and improving reliability.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular, to a protection circuit, system and device for high-side output of a MOS tube. Background Art

[0002] With the control of various lights on the car, the control of various electrical appliances, and the protection of various current outputs in the power control box, the current solution generally adopted is the intelligent MOS tube solution, but the intelligent MOS tube has the disadvantages of poor selectivity, high price, limited output power, etc. Before the adoption of intelligent MOS tubes, the traditional control method was relay plus fuse, which had the disadvantages of short switch action life and untimely protection.

[0003] The output mode of MOS tube as a switch is divided into low-side output and high-side output. Low-side output means that the power supply is connected to the load first, and the load is grounded through the MOS tube. High-side output means that the power supply is connected to the load through the MOS tube first, and the load is then grounded. For circuits with fixed power supply voltage and various loads, for example, when the load or load line is overloaded or directly grounded, the output is prone to short circuit. It is suitable to use a high-side switch that is easy to detect grounding to detect abnormal conditions, that is, the high-side output of the MOS tube. Therefore, it is necessary to design a short-circuit overcurrent protection circuit for the high-side output of the MOS tube. Summary of the invention

[0004] The purpose of the present application is to provide a protection circuit, system and device for a high-side output of a MOS tube, so as to solve the problem that the existing high-side output circuit of a MOS tube is prone to short circuit and overcurrent.

[0005] In order to solve the above problems, the present application adopts the following technical solutions:

[0006] A first aspect of the present application provides a protection circuit for a high-side output of a MOS tube, comprising a current limiting protection resistor connected to a load, a bias delay circuit, a gate drive circuit, a control circuit, an AND gate and a control signal terminal, wherein the bias delay circuit comprises a second triode and a ninth resistor, wherein the two ends of the ninth resistor are respectively connected to the emitter and the base of the second triode, and the base of the second triode is connected to the load, and the AND gate comprises a first input terminal and a second input terminal, wherein the first input terminal is connected to the collector of the second triode, and the second input terminal is connected to the input terminal of the control signal terminal, and the output terminal of the control signal terminal is connected to the gate drive circuit of the MOS tube, and the output terminal of the AND gate is connected to the control circuit, and the control circuit is used to pull down the output terminal voltage of the control terminal to turn off the MOS tube.

[0007] Furthermore, the bias delay circuit also includes an eighth resistor, one end of the eighth resistor is connected to the load, and the other end of the eighth resistor is connected to the ninth resistor.

[0008] Furthermore, the bias delay circuit also includes an adjusting resistor and a third capacitor, one end of the adjusting resistor is connected to the base of the second transistor, the other end of the adjusting resistor is grounded, and the third capacitor is connected in parallel with the adjusting resistor.

[0009] Furthermore, the protection circuit of the high-side output of the MOS tube includes a fourth resistor and a fifth resistor, one end of the fourth resistor is connected to the first input end, the other end of the fourth resistor is grounded, one end of the fifth resistor is connected to the first input end, and the other end of the fifth resistor is connected to the collector of the second transistor.

[0010] Furthermore, the protection circuit of the high-side output of the MOS tube includes a voltage regulator tube, and the voltage regulator tube is connected in parallel with the fourth resistor.

[0011] Furthermore, the protection circuit of the high-side output of the MOS tube includes a delay circuit, and two ends of the delay circuit are respectively connected to the input end of the control end and the power pin of the AND gate.

[0012] Furthermore, the protection circuit of the high-side output of the MOS tube includes a tenth resistor, and the tenth resistor is respectively connected to the output end of the control circuit and the output end of the AND gate.

[0013] Furthermore, the protection circuit of the high-side output of the MOS tube includes a second resistor and a first transistor, the second resistor is respectively connected to the base and emitter of the first transistor, the collector of the first transistor is connected to the gate drive switch circuit, and the power supply voltage of the AND gate is provided by a control signal.

[0014] A second aspect of the present application provides a MOS tube high-side output protection system, comprising: a shell having a receiving cavity formed therein, and a MOS tube high-side output protection circuit as described in any one of the above items, arranged in the shell.

[0015] A third aspect of the present application provides a protection device for a high-side output of a MOS tube, and the protection device for a high-side output of a MOS tube includes the above-mentioned system.

[0016] Compared with the prior art, the beneficial effect of the present application is that: since the two ends of the ninth resistor of the bias delay circuit are respectively connected to the emitter and base of the second triode, the base of the second triode is connected to the load, the first input end of the AND gate is connected to the collector of the second triode, the second input end is connected to the input end of the control end, the output end of the control signal end is connected to the gate drive circuit of the MOS tube, the output end of the AND gate is connected to the control circuit, and the control circuit is used to pull down the output end voltage of the control signal end to turn off the MOS tube. Through the current limiting protection resistor and the MOS tube conduction internal resistance, a large voltage drop is generated, thereby triggering the protection mechanism to turn off the MOS tube, the bias delay circuit can provide a stable bias voltage for the MOS tube, and the gate drive circuit can control the conduction and shutdown of the MOS tube according to the input signal of the control circuit. When the MOS output voltage is overcurrent or short-circuited, the short-circuit overcurrent protection circuit can protect the MOS from being damaged by short-circuit overcurrent in real time and lock the protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A circuit diagram of a protection circuit for a PMOS tube high-side output; and

[0018] Figure 2 This is the circuit diagram of the protection circuit for the high-side output of the NMOS tube.

[0019] Description of reference numerals:

[0020] 1. Gate drive circuit; 2. Voltage detection circuit; 3. Logic control circuit; 4. Control signal terminal;

[0021] K1, switch; R11, eleventh resistor; R12, twelfth resistor; VC, power supply voltage; T1, MOS tube; Q2, second transistor; R9, ninth resistor; R8, eighth resistor; RT, regulating resistor; C3, third capacitor; RL, current limiting protection resistor; Vout, output voltage of MOS tube; CON0, pre-control signal; CON1, first control signal; R1, first resistor; Q1, first transistor; R10, tenth resistor; R2, second resistor; R3, third resistor; C2, second capacitor; D1, voltage regulator; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; VG, driving voltage of MOS tube; U1, gate driving circuit unit; U2, AND gate. DETAILED DESCRIPTION

[0022] The specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0023] It should be noted that, in the absence of conflict, the embodiments and technical features in the embodiments of the present application can be combined with each other, and the detailed description in the specific implementation method should be understood as an explanation of the purpose of the present application and should not be regarded as an improper limitation on the present application.

[0024] It should be understood that the orientation or position relationship is based on the orientation or position relationship shown in the drawings. These orientation terms are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application.

[0025] Figure 1 This is the circuit diagram of the protection circuit for the high-side output of the PMOS tube. Figure 2 This is the circuit diagram of the protection circuit for the high-side output of the NMOS tube. Figure 1 and Figure 2 As shown, the embodiment of the present application provides a protection circuit for the high-side output of a MOS tube, including a current limiting protection resistor RL connected to a load, a bias delay circuit, a gate drive circuit 1, a control circuit, an AND gate U2, and a control signal terminal 4. Among them, the gate drive circuit 1 is respectively connected to the voltage detection circuit 2, the logic control circuit 3, and the control signal terminal 4. The logic control circuit 3 includes a control circuit and an AND gate U2, and the control circuit includes a second resistor R2 and a first transistor Q1. The voltage detection circuit 2 includes a second triode Q2, a current limiting protection resistor RL and a bias delay circuit. The bias delay circuit includes the second triode Q2 and a ninth resistor R9. The two ends of the ninth resistor R9 are respectively connected to the emitter and the base of the second triode Q2. The base of the second triode Q2 is connected to the load. The AND gate U2 includes a first input terminal B and a second input terminal A. The first input terminal B is connected to the collector of the second triode Q2. The second input terminal A is connected to the input terminal CON0 of the control signal terminal 4. The output terminal CON1 of the control signal terminal 4 is connected to the gate drive switch circuit of the MOS tube. The output terminal Y of the AND gate U2 is connected to the control circuit. The control circuit is used to pull down the output terminal voltage of the control terminal to turn off the MOS tube.

[0026] Specifically, a PNP transistor Q2 and a resistor R9 are selected in the bias delay circuit, and the two ends of the resistor R9 are respectively connected to the emitter and base of the transistor Q2, and the base of the transistor Q2 is connected to the load, and the output voltage Vout is provided by the MOS tube, and the collector of the second transistor Q2 is connected to the first input terminal B of the AND gate U2. The AND gate U2 includes a first input terminal B and a second input terminal A, the first input terminal B is connected to the collector of the transistor Q2, the second input terminal A is connected to the input terminal CON0 of the control signal terminal 4, and the output terminal Y of the AND gate U2 is connected to the control circuit. The control circuit receives an external signal and outputs a control signal to the second input terminal A of the AND gate U2. The control circuit can also be used to pull down the output terminal voltage of the control terminal to turn off the MOS tube, and the output terminal CON1 of the control signal terminal 4 is connected to the gate drive circuit 1 of the MOS tube.

[0027] It should be noted that in the gate drive circuit 1, the switch K1 can be any electronic switch, and the gate of the MOS tube is controlled through CON1 to control the on and off of the MOS. AND gate U2 and the delay circuit detect the voltage difference between the input voltage and the output voltage of the power output. If the voltage difference reaches a certain value, the second transistor Q2 is turned on. When the second transistor Q2 is a silicon material P-pole transistor, it will be turned on when the voltage difference reaches 0.6V (when there is no adjustment resistor RT), and at the same time, it has a delay control function for the level change of the B terminal of the non-gate U2. The control signal terminal 4 completes the logic control and controls the CON1 control signal. It only works when the CON0 control signal is at a high level, and has a delay control function for the level change of the A terminal of U2.

[0028] Since the two ends of the ninth resistor R9 of the bias delay circuit are respectively connected to the emitter and base of the second triode Q2, the base of the second triode Q2 is connected to the load, the first input end of the gate U2 is connected to the collector of the second triode Q2, the second input end is connected to the input end of the control signal end 4, the output end of the control signal end 4 is connected to the gate drive circuit 1 of the MOS tube, and the output end Y of the gate U2 is connected to the control circuit, and the control circuit is used to pull down the output end voltage of the control end to turn off the MOS tube. Through the current limiting protection resistor RL, a large voltage drop is generated, thereby triggering the protection mechanism to turn off the MOS tube, the bias delay circuit can provide a stable bias voltage for the MOS tube, and the gate drive circuit 1 can control the conduction and shutdown of the MOS tube according to the input signal of the control circuit. When the MOS output voltage is overcurrent or short-circuited, the short-circuit overcurrent protection circuit can protect the MOS from being damaged by the short-circuit overcurrent in real time, and lock the protection.

[0029] In some embodiments, the bias delay circuit further includes an eighth resistor R8, one end of the eighth resistor R8 is connected to the load, and the other end of the eighth resistor R8 is connected to a ninth resistor R9.

[0030] Specifically, one end of the eighth resistor R8 is connected to the load, and the other end is connected to the ninth resistor R9. The resistance value of the resistor R8 can be selected according to actual needs to provide an appropriate bias current. Through the series connection of the eighth resistor R8 and the ninth resistor R9, a stable bias current can be provided for the transistor Q2. During the bias delay process, the eighth resistor R8 provides a stable bias current for the bias delay circuit, ensuring the normal operation of the transistor Q2.

[0031] The eighth resistor R8 and the ninth resistor R9 are connected in series to provide a stable bias current for the second transistor Q2, which helps to ensure that the transistor Q2 can maintain a good on and off state throughout the entire working cycle, thereby improving the reliability and stability of the circuit. R9 can adjust the delay, and work together with R8 and C3 to adjust the protection current, so that the on and off of the transistor Q2 have a certain delay, avoiding instantaneous malfunction of the circuit.

[0032] In some embodiments, the bias delay circuit further includes an adjusting resistor RT and a third capacitor C3, one end of the adjusting resistor RT is connected to the base of the second transistor Q2, the other end of the adjusting resistor RT is grounded, and the third capacitor C3 is connected in parallel with the adjusting resistor RT.

[0033] Specifically, the resistance value of the regulating resistor RT can adjust the magnitude of the protection current of the protection circuit to adapt to different working conditions. For example, the regulating resistor RT selects a resistor adapted to the bias delay circuit, one end of which is connected to the base of the second triode Q2, and the other end is grounded. The third capacitor C3 is connected in parallel with the regulating resistor RT, and the third capacitor C3 has a delay effect on the bias voltage, thereby delaying the conduction and closing of the second triode Q2, thereby delaying the change of the logic level of the B end of the AND gate U2, and thereby delaying the protection time.

[0034] In some embodiments, the protection circuit of the high-side output of the MOS tube includes a fourth resistor R4 and a fifth resistor R5, one end of the fourth resistor R4 is connected to the first input terminal B, the other end of the fourth resistor R4 is grounded, one end of the fifth resistor R5 is connected to the first input terminal B, and the other end of the fifth resistor R5 is connected to the collector of the second transistor Q2.

[0035] Specifically, the fourth resistor R4 is a fixed resistor, one end of which is connected to the first input terminal B, and the other end is grounded, so as to perform voltage division protection. The fifth resistor R5 is a fixed resistor, one end of which is connected to the first input terminal B, and the other end is connected to the collector of the second transistor Q2. The output voltage of the second transistor Q2 may be 24V or higher, but the input voltage of the AND gate U2 generally cannot exceed 6V. Since R4 and R5 are provided, voltage division is achieved.

[0036] In some embodiments, the protection circuit of the high-side output of the MOS tube includes a voltage regulator tube D1 , and the voltage regulator tube D1 is connected in parallel with a fourth resistor R4 .

[0037] Specifically, the voltage regulator D1 is connected in parallel with the fourth resistor R4, one end of the voltage regulator D1 is grounded, and the other end of the voltage regulator D1 is connected to the first input terminal B. For example, the voltage regulator D1 selects a voltage regulator with a specific voltage rating, one end of which is grounded, and the other end is connected to the first input terminal B. The function of the voltage regulator D1 is to quickly start the protection mechanism when the voltage at the input terminal B exceeds its rated voltage to prevent overvoltage from causing damage to U2. By introducing the voltage regulator D1 to protect U2, the circuit can provide a stable voltage output.

[0038] In some embodiments, the protection circuit of the high-side output of the MOS tube includes a delay circuit, and two ends of the delay circuit are respectively connected to the input terminal CON0 of the control signal terminal 4 and the ground terminal.

[0039] Specifically, the two endpoints of the delay circuit are connected to the input terminal CON0 of the control signal terminal 4 and the ground terminal respectively. The delay circuit can be implemented by components such as capacitors, resistors and transistors. Its function is to delay the output signal for a period of time after detecting the change of the input signal, so that the MOS tube can be powered on normally, thereby reducing the circuit's sensitivity to instantaneous interference of the input signal. When the input terminal CON0 of the control signal terminal 4 changes, the delay circuit will generate a delayed output signal, which will perform a logical operation with the input signal of the AND gate U2 to control the high-side output of the MOS tube.

[0040] By introducing a delay circuit, the input signal has enough time to stabilize, thus avoiding unnecessary conduction or cutoff of the MOS tube.

[0041] In some embodiments, the protection circuit of the high-side output of the MOS tube includes a tenth resistor R10, and the tenth resistor R10 is respectively connected to the control circuit and the output terminal Y of the AND gate U2.

[0042] Specifically, the two ends of the tenth resistor R10 are connected to the control circuit and the output end Y of the AND gate U2 respectively. The tenth resistor R10 can be a variable resistor or other types of resistor elements, which is used to limit the current of the output signal. One end of the control circuit is connected to one end of the tenth resistor R10, and the control circuit can be a microcontroller or other logic circuit for generating a control signal to control the high-side output of the MOS tube. The other end of the tenth resistor R10 is connected to the output end Y of the AND gate U2, and the AND gate U2 is used to control the conduction and cutoff of the MOS tube according to the input signal and the control signal.

[0043] In some embodiments, the protection circuit of the MOS tube high-side output includes a second resistor R2 and a first transistor Q1 , the second resistor R2 is respectively connected to the base and emitter of the first transistor Q1 , and the collector of the first transistor Q1 is connected to the gate drive circuit 1 .

[0044] Specifically, the two endpoints of the second resistor R2 are respectively connected to the base and emitter of the first transistor Q1. The second resistor R2 can be a fixed resistor or other types of resistance elements. The collector of the first transistor Q1 is connected to the gate drive circuit 1. The first transistor Q1 can be an NPN transistor or a PNP transistor, which is used to control the high-side output of the MOS tube according to the control signal. The gate of the first transistor Q1 is connected to the gate drive circuit 1. The gate drive circuit 1 is used to generate a control signal according to the input signal to control the conduction and cutoff of the first transistor Q1.

[0045] By introducing the second resistor R2, the circuit can limit the base current passing through the first transistor Q1. When the base current exceeds the bearing capacity of the second resistor R2, it plays a current limiting role to prevent the first transistor Q1 from being damaged due to excessive current, thereby improving the stability and reliability of the entire system and reducing faults caused by overcurrent.

[0046] In order to better understand the protection circuit of the MOS tube high-side output in the embodiment of the present application, the protection process of the high-side output of the PMOS and NMOS tubes is specifically described below.

[0047] like Figure 2As shown, when CON1 is at a high level, the gate drive circuit unit U1 in the gate drive circuit 1 works, the VG voltage is turned on, and the T1 tube works. When CON1 is at a low level, the VG voltage is disconnected, and T1 turns off the output. Among them, VC is the power supply voltage, which can be a 12V system, a 24V system, or a 48V system. T1 is a MOS, Vout is the output voltage of the MOS tube, CON0 is the control signal output by the processing unit, and CON1 is the signal of CON0 after passing through the current limiting resistor R1. This signal and the Q1 control tube jointly control the switch of the gate switch circuit 2 to control the on and off of the MOS tube. VG is the driving voltage of NMOS, and the VG voltage is the VC voltage plus the NMOS conduction voltage. When NMOS is fully turned on, VG is generally 8V-12V higher than VC. R3 and C2 constitute the A-end delay circuit of U2, and Q1 and R2 constitute the pull-down control circuit of the CON1 signal. RL is a current limiting protection resistor, D1 is a voltage regulator, and the B-end of U1 is overvoltage protected. R4 and R5 are the voltage divider circuit after Q1 is turned on, and R7 is the driving current limiting resistor of T1. R6 is the gate discharge resistor when T1 is turned off. Q2 is a PNP tube, and R8, R9 and C3 constitute the bias circuit of Q2, and can also be a delay circuit for the change of Q2 base level. RT is the fine-tuning resistor of Q2 base voltage. When there is no RT, Q2 is a silicon material tube, and the on-voltage of Q2 is 0.6V. By adjusting RT, the on-voltage of Q2 can be reduced, and the on-voltage can be lower than 0.6V, so that the overcurrent short-circuit current of T1 can be adjusted.

[0048] It should be noted that the control logic of the protection circuit of the high-side output of the PMOS tube is the same as that of the NMOS tube, but the gate drive control of the PMOS is different. To control the NMOS to turn on, the gate voltage must be controlled to be higher than the input voltage VC, so that the NMOS turn-on threshold is within a reasonable range. To control the PMOS to turn on, the gate voltage must be controlled to be lower than the input voltage VC, so that the PMOS turn-on threshold is within a reasonable range. Among them, R12 is a pull-up resistor and R11 is a current limiting resistor. In order to avoid repetition, the following will be expanded based on the NMOS working process.

[0049] The power supply of AND gate U2 is provided by CON0 signal voltage. When the Y terminal of AND gate U2 outputs high level, the short-circuit overcurrent protection circuit plays a protective role, and Q1 pulls down the CON1 signal to turn off the MOS output. R3 and C2 are the delay circuit of the A input terminal of AND gate U2. The delay time is to cooperate with CON0 to start the control MOS tube T1 output normally. The delay power supply time of the A terminal of AND gate U2 is determined by C2 and R3, that is, RC delay. The delay time can be calculated by RC parameters. This delay time is greater than the time for the output voltage to rise and stabilize when the MOS is working normally.

[0050] When the Vout output current is too large or short-circuited, when the voltage drop through T1 and RL is higher than 0.6V, Q2 is turned on, making the B input of AND gate U2 high level, and the A input of AND gate U2 is also high level at this time, so that the Y end of AND gate U2 outputs high level, making the CON1 control signal low, turning off MOS tube T1, and playing the role of overcurrent short circuit protection. When T1 has no output, Q2 is also in the on state, and the B input of AND gate U2 is also high level, but CON0 is low level, and U2 does not work. When T1 is turned on and working normally, Q2 changes from on to off after a while, and the B input of AND gate U2 changes from high level to low level after a while. The A input of AND gate U2 changes from low level to high level after a while, so that the A input and B input of AND gate U2 cannot be high at the same time. The time when the A input terminal of the AND gate U2 changes from a low level to a high level, and the time when the B input terminal of the AND gate U2 changes from a high level to a low level, can change and adjust the maximum current allowed when the MOS tube starts, that is, the overcurrent or short-circuit current at startup. R8, R9, C3, R4 and R5 can adjust the time when the B input terminal of the AND gate U2 changes from a level, and can adjust the maximum startup current at startup. In the case of a short circuit after the MOS tube works normally, the size of the overcurrent protection current in this state can also be adjusted.

[0051] R3 and C2 can adjust the time for the A input terminal of AND gate U2 to change from level to level, and can adjust the maximum startup current at startup. In the case of a short circuit after the MOS tube works normally, the overcurrent protection current can also be adjusted in this state. The short-circuit overcurrent protection of MOS can also eliminate the need for RL resistors

[0052] It should be noted that the protection circuit of the high-side output of the MOS tube is a hardware short-circuit overcurrent protection circuit. When the MOS output voltage is overcurrent or short-circuited, the short-circuit overcurrent protection circuit can protect the MOS from damage due to short circuit in real time and lock the protection until the CON0 level changes again. Whether the MOS tube is short-circuited or overloaded before it is turned on, or short-circuited or overloaded after it works normally, it can be effectively protected; by adjusting the size of RL or changing the size of the internal resistance of T1, the size of the current limiting protection current can be changed; by adjusting the time of the logic change of the A end and the time of the logic change of the B end, the maximum current allowed when the MOS tube starts can be adjusted; by adjusting the time of the logic change of the A end and the time of the logic change of the B end, the size of the current limiting protection current of the MOS tube can be adjusted; the high-side power output devices controlled by the control end can use this circuit for short-circuit overcurrent protection, such as relay output, etc. Detect the voltage changes at both ends of the power device and the detection resistor (RL), and detect the voltage changes through the voltage detection circuit; then control the CON1 control signal through the logic circuit to achieve the purpose of short-circuit overcurrent protection. In addition, the voltage detection circuit part can be used, and the MCU can be used to sample and analyze the conduction signal of Q2, and the overcurrent and short-circuit protection can be completed by combining software and hardware. The voltage detection circuit part and the logic control circuit part can also be made into an integrated circuit, which will be smaller and more convenient.

[0053] An embodiment of the present application also provides a MOS tube high-side output protection system, comprising: a shell having a receiving cavity formed therein, and any of the above-mentioned MOS tube high-side output protection circuits, which are arranged in the shell.

[0054] An embodiment of the present application further provides a protection device for a high-side output of a MOS tube, and the protection device for a high-side output of a MOS tube includes the above-mentioned system.

[0055] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit the same. Although the present application has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to replace some of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions claimed to be protected by the present application.

Claims

1. A protection circuit for high-side output of a MOS tube, characterized in that: It includes a current limiting protection resistor connected to a load, a bias delay circuit, a gate drive circuit, a control circuit, an AND gate and a control signal terminal, the bias delay circuit includes a second triode and a ninth resistor, the two ends of the ninth resistor are respectively connected to the emitter and the base of the second triode, the base of the second triode is connected to the load, the AND gate includes a first input terminal and a second input terminal, the first input terminal is connected to the collector of the second triode, the second input terminal is connected to the input terminal of the control signal terminal, the output terminal of the control signal terminal is connected to the gate drive circuit of the MOS tube, the output terminal of the AND gate is connected to the control circuit, the control circuit is used to pull down the output terminal voltage of the control signal terminal to turn off the MOS tube, and the emitter of the second triode is connected to the VC terminal.

2. A protection circuit for high-side output of a MOS tube according to claim 1, characterized in that: The bias delay circuit also includes an eighth resistor, one end of the eighth resistor is connected to the load, and the other end of the eighth resistor is connected to the base of the second transistor.

3. A protection circuit for high-side output of a MOS tube according to claim 1, characterized in that: The bias delay circuit also includes an adjusting resistor and a third capacitor. One end of the adjusting resistor is connected to the base of the second transistor, the other end of the adjusting resistor is grounded, and the third capacitor is connected in parallel with the adjusting resistor.

4. A protection circuit for high-side output of a MOS tube according to claim 1, characterized in that: The protection circuit of the high-side output of the MOS tube includes a fourth resistor and a fifth resistor, one end of the fourth resistor is connected to the first input end, the other end of the fourth resistor is grounded, one end of the fifth resistor is connected to the first input end, and the other end of the fifth resistor is connected to the collector of the second transistor.

5. A protection circuit for high-side output of a MOS tube according to claim 4, characterized in that: The protection circuit of the high-side output of the MOS tube includes a voltage regulator tube, and the voltage regulator tube is connected in parallel with the fourth resistor.

6. A protection circuit for high-side output of a MOS tube according to claim 1, characterized in that: The protection circuit of the high-side output of the MOS tube comprises a delay circuit, and two ends of the delay circuit are respectively connected to the input end of the control signal end and the ground end.

7. A protection circuit for high-side output of a MOS tube according to claim 1, characterized in that: The protection circuit of the high-side output of the MOS tube includes a tenth resistor, and the tenth resistor is respectively connected to the output end of the control circuit and the output end of the AND gate.

8. The protection circuit for high-side output of a MOS tube according to claim 1, characterized in that: The control circuit of the MOS tube high-side output includes a second resistor and a first transistor, the second resistor is respectively connected to the base and emitter of the first transistor, the collector of the first transistor is connected to the gate drive switch circuit, and the power supply voltage of the AND gate is provided by the control signal.

9. A protection system for high-side output of a MOS tube, characterized in that: include: A shell having an accommodating cavity formed therein, and a protection circuit for the high-side output of the MOS tube according to any one of claims 1 to 8, are arranged in the shell.

10. A protection device for high-side output of a MOS tube, characterized in that: The protection device for the high-side output of the MOS tube includes the system described in claim 9.

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