Sampling circuit and device capable of offsetting dielectric absorption effect

Abstract

The present disclosure relates to a sampling circuit and device capable of offsetting dielectric absorption effect. The circuit includes two sampling and holding circuits containing multiple sampling units and a switch control module, wherein the sampling unit includes a first capacitor and a second capacitor, and at least some of the sampling units have the same target capacitance ratio; the switch control module controls the bottom plate of each capacitor in the first sampling and holding circuit to be connected to VIP, controls the bottom plate of each capacitor in the second sampling and holding circuit to be connected to VIN, controls the top plate of each first capacitor to be connected to VDD, and controls the top plate of each second capacitor to be grounded; controls the capacitor in the sampling and holding circuit to be disconnected from VIP and VIN in the conversion stage, and controls the connection between the top plate of the capacitor in the first sampling and holding circuit and the top plate of the capacitor in the second sampling and holding circuit and the positive and negative input terminals of the comparator to be turned on. The influence of dielectric absorption effect can be offset, the structure is simple, and the phenomenon of deterioration of THD and DNL / INL after long-term sampling of ADC can be effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of circuit design, and in particular to a sampling circuit and a device capable of offsetting dielectric absorption effect. Background Art

[0002] In some application scenarios, the SAR ADC circuit has a low-power working mode in which the ADC is turned off during the sampling phase to reduce the average power consumption of the system. The problem that often occurs is that when the ADC is in the low-power mode in which the ADC is turned off during the sampling phase for a long time, the total harmonic distortion (THD) and differential non-linearity (DNL) / integral non-linearity (INL) of the ADC will deteriorate significantly due to the influence of the dielectric absorption effect (Dielectric Absorption), and the high-temperature working environment will shorten the deterioration time. This problem needs to be solved urgently. Summary of the invention

[0003] In view of this, the present disclosure proposes a sampling circuit and a device capable of counteracting the dielectric absorption effect.

[0004] According to one aspect of the present disclosure, a sampling circuit capable of counteracting dielectric absorption effect is provided, the circuit comprising two sample-and-hold circuits and a switch control module.

[0005] Each of the sample-and-hold circuits comprises a plurality of sampling units, each of the sampling units comprises a first capacitor and a second capacitor, at least some of the sampling units in the plurality of sampling units correspond to the same target capacitance ratio, and the target capacitance ratio of each of the sampling units is the ratio of the capacitance values ​​of the first capacitor and the second capacitor in the sampling unit; the total capacitance value of the higher-order sampling unit in two adjacent sampling units is a preset multiple of the total capacitance value of the lower-order sampling unit, and the total capacitance value of each of the sampling units is the sum of the capacitance values ​​of the first capacitor and the second capacitor in the sampling unit;

[0006] The switch control module is used to control the connection between the bottom plate of each first capacitor in the first sampling and holding circuit of the sampling and holding circuit, the bottom plate of each second capacitor and the first input terminal of the positive input signal of the differential signal pair during the sampling phase, and control the connection between the bottom plate of each first capacitor in the second sampling and holding circuit of the sampling and holding circuit, the bottom plate of each second capacitor and the second input terminal of the negative input signal of the differential signal pair during the sampling phase, and control the top plate of each first capacitor to be connected to the power supply voltage and control the top plate of each second capacitor to be grounded; and

[0007] In the conversion phase, the connection between the bottom plate of each first capacitor and the bottom plate of each second capacitor in the first sampling and holding circuit and the first input terminal is controlled to be disconnected, and the connection between the bottom plate of each first capacitor and the bottom plate of each second capacitor in the second sampling and holding circuit and the second input terminal is controlled to be disconnected, and the connection between the top plate of each first capacitor and the top plate of each second capacitor in the first sampling and holding circuit and the positive input terminal of the comparator is controlled to be connected, and the connection between the top plate of each first capacitor and the top plate of each second capacitor in the second sampling and holding circuit and the negative input terminal of the comparator is controlled to be connected.

[0008] In a possible implementation, the switch control module includes a first sampling switch and a second sampling switch.

[0009] The first sampling switch is connected between the first sampling and holding circuit and the first input terminal, and is used to control the connection between the bottom plate of each first capacitor, the bottom plate of each second capacitor and the first input terminal in the first sampling and holding circuit during the sampling phase; and to control the connection between the bottom plate of each first capacitor, the bottom plate of each second capacitor and the first input terminal during the conversion phase;

[0010] The second sampling switch is connected between the second sampling and holding circuit and the second input terminal, and is used to control the connection between the bottom plate of each first capacitor, the bottom plate of each second capacitor and the second input terminal in the second sampling and holding circuit during the sampling phase; and to control the connection between the bottom plate of each first capacitor, the bottom plate of each second capacitor and the second input terminal in the second sampling and holding circuit during the conversion phase.

[0011] In a possible implementation, the switch control module includes a first switch unit and a second switch unit.

[0012] The first switch unit is connected between the power supply voltage and the top plate of each of the first capacitors, and is used to control the top plate of each of the first capacitors to be connected to the power supply voltage during the sampling phase, and to disconnect the top plate of each of the first capacitors from the power supply voltage during the conversion phase;

[0013] The top plate of each second capacitor is grounded through the second switch unit, and the second switch unit is used to be turned on in the sampling phase to ground the top plate of each second capacitor, and turned off in the conversion phase to disconnect the top plate of each second capacitor from the ground.

[0014] In a possible implementation, the switch control module further includes a third switch unit and a fourth switch unit.

[0015] The third switch unit is connected between the top plates of the first capacitors and the top plates of the second capacitors in the first sample-and-hold circuit, and the third switch unit is used to disconnect in a sampling phase to disconnect the connection between the top plates of the first capacitors and the second capacitors in the first sample-and-hold circuit, and to conduct in a conversion phase to conduct the connection between the top plates of the first capacitors and the second capacitors in the first sample-and-hold circuit;

[0016] The fourth switch unit is connected between the top plate of each of the second capacitors in the first sampling and holding circuit and the positive input terminal of the comparator. The fourth switch unit is used to disconnect in the sampling phase to disconnect the connection between the top plate of each of the second capacitors in the first sampling and holding circuit and the positive input terminal of the comparator, and to connect in the conversion phase to connect the connection between the top plate of each of the second capacitors in the first sampling and holding circuit and the positive input terminal of the comparator.

[0017] In a possible implementation, the switch control module further includes a fifth switch unit and a sixth switch unit.

[0018] The fifth switch unit is connected between the top plates of the first capacitors and the top plates of the second capacitors in the second sample-and-hold circuit, and the fifth switch unit is used to disconnect in the sampling phase to disconnect the connection between the top plates of the first capacitors and the second capacitors in the second sample-and-hold circuit, and to conduct in the conversion phase to conduct the connection between the top plates of the first capacitors and the second capacitors in the second sample-and-hold circuit;

[0019] The sixth switch unit is connected between the top plate of each of the second capacitors in the second sampling and holding circuit and the negative input terminal of the comparator. The sixth switch unit is used to be disconnected in the sampling phase to disconnect the connection between the top plate of each of the second capacitors in the second sampling and holding circuit and the negative input terminal of the comparator, and to be turned on in the conversion phase to connect the connection between the top plate of the second capacitor in the second sampling and holding circuit and the negative input terminal of the comparator.

[0020] In a possible implementation manner, the target capacitance value ratios corresponding to the sampling units other than the sampling unit corresponding to the lowest bit in the plurality of sampling units are the same.

[0021] In a possible implementation manner, the target capacitance ratio corresponding to the sampling unit corresponding to the lowest bit is a set value.

[0022] In a possible implementation, the target capacitance ratio is determined according to parameters of a circuit environment in which the sampling circuit is located during a sampling process;

[0023] The parameters of the circuit environment include at least one of the following: a numerical range of a positive input signal of a differential signal pair, a numerical range of a negative input signal of a differential signal pair, and a voltage value of a comparator power supply voltage.

[0024] According to another aspect of the present disclosure, a sampling device capable of counteracting dielectric absorption effect is provided, the device comprising: the sampling circuit capable of counteracting dielectric absorption effect and a comparator as described above,

[0025] Each of the sample-and-hold circuits comprises a plurality of sampling units, each of the sampling units comprises a first capacitor and a second capacitor, at least some of the target sampling units in the plurality of sampling units have the same target capacitance ratio, and the target capacitance ratio of each of the sampling units is the ratio of the capacitance values ​​of the first capacitor and the second capacitor in the sampling unit; the total capacitance value of the higher-order sampling unit in two adjacent sampling units is a preset multiple of the total capacitance value of the lower-order sampling unit, and the total capacitance value of each of the sampling units is the sum of the capacitance values ​​of the first capacitor and the second capacitor in the sampling unit;

[0026] The switch control module is used to control the connection between the bottom plate of each first capacitor in the first sampling and holding circuit of the sampling and holding circuit, the bottom plate of each second capacitor and the first input terminal of the positive input signal of the differential signal pair in the sampling phase, and control the connection between the bottom plate of each first capacitor in the second sampling and holding circuit of the sampling and holding circuit, the bottom plate of each second capacitor and the second input terminal of the negative input signal of the differential signal pair in the sampling phase, and control the top plate of each first capacitor to be connected to the power supply voltage and control the top plate of each second capacitor to be grounded; and

[0027] Controlling the disconnection between the bottom plate of each first capacitor and the bottom plate of each second capacitor in the first sampling and holding circuit and the first input terminal in the conversion phase, and controlling the disconnection between the bottom plate of each first capacitor and the bottom plate of each second capacitor in the second sampling and holding circuit and the second input terminal in the conversion phase, and controlling the connection between the top plate of each first capacitor and the top plate of each second capacitor in the first sampling and holding circuit and the positive input terminal of the comparator, and controlling the connection between the top plate of each first capacitor and the top plate of each second capacitor in the second sampling and holding circuit and the negative input terminal of the comparator;

[0028] The comparator is used to compare the signals input to the positive input terminal and the negative input terminal during the conversion phase, and output the comparison result through the output terminal.

[0029] In a possible implementation manner, the device further includes:

[0030] The successive approximation register is used to receive the comparison result output by the comparator, and perform sampling control and result output of the device according to the comparison result.

[0031] The embodiments of the present disclosure provide a sampling circuit and device capable of offsetting the dielectric absorption effect, which can offset the influence of the dielectric absorption effect, have a simple structure, and can effectively improve the phenomenon of THD and DNL / INL deterioration after long-term sampling of the ADC.

[0032] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0034] Figure 1 A schematic diagram showing the equivalent circuit of a capacitor.

[0035] Figure 2 This is a structural diagram of a traditional 5-bit differential SAR ADC baseboard sampling circuit.

[0036] Figure 3 This is the clock signal timing diagram.

[0037] Figure 4 A structural diagram of a sampling circuit capable of counteracting dielectric absorption effect according to an embodiment of the present disclosure is shown.

[0038] Figure 5 A structural diagram of a sampling circuit capable of counteracting dielectric absorption effect according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0040] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0041] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0042] The dielectric absorption effect, sometimes also called the battery effect or dielectric delay, is a phenomenon caused by the reorientation of dipoles in dielectric materials after the charge and discharge process. This phenomenon is particularly evident in the charge and discharge process of capacitors, and refers to a phenomenon in which a capacitor that has been charged for a long time will not be fully discharged after only a short reset; an ideal capacitor will maintain a voltage difference of zero volts after the positive and negative terminals are short-circuited, but a real capacitor will generate a small voltage through time-delayed dipole discharge.

[0043] The mechanism of this dielectric absorption effect is that when charging the two ends of a capacitor for a long time, it will lead to directional polarization of the charge, and the orientation of the charge will not change immediately when the electric field disappears, but will be delayed by a time constant dependent on the material, and will not immediately return to the initial undirected state. When this phenomenon occurs, it will cause dielectric loss, causing the equivalent capacitance value to change, and high temperature will accelerate the occurrence of this phenomenon. When considering the dielectric absorption effect of the capacitor, the capacitance equivalent circuit of a capacitor with a capacitance of C is as follows Figure 1 As shown, the R and ΔC values ​​are related to the dielectric material and the voltage difference across the capacitor.

[0044] Among them, the potential impact of dielectric absorption effect on high-precision ADC (Analog-to-Digital Converter) is very large and is not easy to be discovered in the early stage of use. Figure 2 This is a traditional 5-bit differential SAR (Successive Approximation Register) ADC backplane sampling circuit diagram. Figure 2 Only the P-terminal circuit is schematically shown, and the N-terminal circuit is symmetrical with the P-terminal circuit and is not shown. Among them, in the P-terminal circuit, C1, C2, C3, and C4 are the capacitors in the DAC, arranged from high to low. Generally speaking, C1=8C4, C2=4C4, and C3=2C4. In the sampling stage, switch F1 is closed and switch F2 is open. Figure 3 for Figure 2The timing diagram of each clock signal corresponding to the sampling circuit. In order to reduce the circuit generation of the intermediate level and reduce the circuit complexity, a common method is to connect all the bottom plates of the capacitors to the input signal, the top plate of the highest capacitor to VDD, and the top plates of the remaining capacitors to GND during the sampling phase. This is equivalent to connecting the top plates of the capacitors to VDD / 2 during the sampling phase, and also avoids the circuit that generates the VDD / 2 voltage. A typical application scenario of the SAR ADC circuit is to control the ADC startup and conversion process through a pulse signal. When the rising edge of the pulse signal arrives, the ADC enters the conversion phase. After the conversion is completed, the ADC automatically enters the sampling phase. The ADC can be turned off during the sampling phase, so that it is in a low-power working mode and reduces the average power consumption of the system. A common problem in such application scenarios is that when the ADC is in low-power mode for a long time, the total harmonic distortion (THD), differential non-linearity (DNL) / integral non-linearity (INL) of the ADC will deteriorate significantly, and the high-temperature working environment will shorten the deterioration time. This may be caused by the dielectric absorption effect. The reason is that when the ADC is in the sampling stage for a long time, the voltage difference across C1 is different from the voltage difference across C2 to C4, and the capacitance change caused by the dielectric absorption effect will also be different, resulting in a mismatch between C1 and the low-segment capacitor, thereby causing deterioration of THD, DNL / INL performance.

[0045] The dielectric absorption effect will cause the THD and DNL / INL performance of the chip to deteriorate after long-term use. Essentially, when the chip is in the sampling stage for a long time, the DAC capacitor value will change, and the capacitance change ratio of each bit is different, which leads to the deterioration of indicators such as THD and DNL / INL, and high temperature will accelerate the rate of deterioration.

[0046] To solve the above technical problems, the embodiments of the present disclosure provide a sampling circuit and device capable of offsetting the dielectric absorption effect, which can offset the influence of the dielectric absorption effect, has a simple structure, and can effectively improve the phenomenon of THD and DNL / INL deterioration after long-term ADC sampling.

[0047] like Figure 4 As described above, the sampling circuit provided by the embodiment of the present disclosure is capable of counteracting the dielectric absorption effect. The sampling circuit includes two sample-and-hold circuits 10 and a switch control module 20 .

[0048] Each of the sample-and-hold circuits 10 includes a plurality of sampling units, each of which includes a first capacitor (such as Figure 4 C1, C2, C3...Cn shown) and the second capacitor (such as Figure 4C1', C2', C3'...Cn' shown in the figure), the target capacitance ratio corresponding to at least some of the multiple sampling units is the same, and the target capacitance ratio of each sampling unit is the ratio of the capacitance values ​​of the first capacitor and the second capacitor in the sampling unit; the total capacitance value of the high-order sampling unit in the two adjacent sampling units is a preset multiple of the total capacitance value of the low-order sampling unit, and the total capacitance value of each sampling unit is the sum of the capacitance values ​​of the first capacitor and the second capacitor in the sampling unit. The preset multiple can be set according to the actual sampling needs, for example, the preset multiple can be 2, 1, 1.5, etc., and the present disclosure does not limit this.

[0049] The switch control module 20 is used to control the connection and conduction between the bottom plate of each first capacitor in the first sampling and holding circuit in the sampling and holding circuit, the bottom plate of each second capacitor and the first input end of the positive input signal VIP of the differential signal pair during the sampling phase, and to control the connection and conduction between the bottom plate of each first capacitor in the second sampling and holding circuit in the sampling and holding circuit, the bottom plate of each second capacitor and the second input end of the negative input signal VIN of the differential signal pair during the sampling phase, and to control the top plate of each first capacitor to be connected to the power supply voltage VDD and to control the top plate of each second capacitor to be grounded GND.

[0050] The switch control module 20 is also used to control the disconnection between the bottom plate of each first capacitor, the bottom plate of each second capacitor and the first input terminal in the first sampling and holding circuit during the conversion stage, and to control the disconnection between the bottom plate of each first capacitor, the bottom plate of each second capacitor and the second input terminal in the second sampling and holding circuit during the conversion stage, and to control the connection between the top plate of each first capacitor, the top plate of each second capacitor and the positive input terminal of the comparator 30, and to control the connection between the top plate of each first capacitor, the top plate of each second capacitor in the second sampling and holding circuit and the negative input terminal of the comparator 30.

[0051] In one possible implementation, Figure 5 As shown, the switch control module 20 may include a first sampling switch F1D and a second sampling switch F2D.

[0052] The first sampling switch F1D is connected between the first sampling and holding circuit and the first input end of the positive input signal VIP of the differential signal pair, and is used to control the connection between the bottom plate of each first capacitor, the bottom plate of each second capacitor in the first sampling and holding circuit and the first input end of the positive input signal VIP of the differential signal pair during the sampling phase; and to control the connection between the bottom plate of each first capacitor, the bottom plate of each second capacitor in the first sampling and holding circuit and the first input end of the positive input signal VIP of the differential signal pair during the conversion phase.

[0053] The second sampling switch F2D is connected between the second sampling and holding circuit and the second input end of the negative input signal VIN of the differential signal pair, and is used to control the connection between the bottom plate of each first capacitor, the bottom plate of each second capacitor in the second sampling and holding circuit and the second input end of the negative input signal VIN of the differential signal pair in the sampling phase; and to control the connection between the bottom plate of each first capacitor, the bottom plate of each second capacitor in the second sampling and holding circuit and the second input end of the negative input signal VIN of the differential signal pair in the conversion phase.

[0054] In this way, the first sampling switch F1D and the second sampling switch F2D are synchronously turned on and off in the sampling phase and the conversion phase to realize the connection control of the first capacitor and the second capacitor bottom plate connected to VIP in the first sampling and holding circuit and the first capacitor and the second capacitor bottom plate connected to VIN in the second sampling and holding circuit.

[0055] In one possible implementation, Figure 5 As shown, the switch control module 20 may include a first switch unit F1 and a second switch unit F2.

[0056] The first switch unit F1 is connected between the power supply voltage VDD and the top plate of each of the first capacitors, and is used to control the connection of the top plate of each of the first capacitors to the power supply voltage VDD during the sampling phase, and to disconnect the connection between the top plate of each of the first capacitors and the power supply voltage VDD during the conversion phase.

[0057] The top plate of each second capacitor is grounded GND through the second switch unit F2, and the second switch unit F2 is used to be turned on in the sampling phase to connect the top plate of each second capacitor to the ground GND, and to be turned off in the conversion phase to disconnect the top plate of each second capacitor from the ground GND.

[0058] In this way, the connection control of connecting the top plates of each first capacitor to the power supply voltage and connecting the top plates of each second capacitor to the ground is achieved by synchronously switching on and off the first switch unit F1 and the second switch unit F2 in the sampling phase and the conversion phase.

[0059] In one possible implementation, Figure 5 As shown, the switch control module 20 may include a third switch unit F3 and a fourth switch unit F4.

[0060] The third switch unit F3 is connected between the top plate of each of the first capacitors and the top plate of each of the second capacitors in the first sampling and holding circuit. The third switch unit F3 is used to disconnect in the sampling phase to disconnect the connection between the top plate of the first capacitor and the top plate of the second capacitor in the first sampling and holding circuit, and to turn on in the conversion phase to connect the connection between the top plate of the first capacitor and the top plate of the second capacitor in the first sampling and holding circuit.

[0061] The fourth switch unit F4 is connected between the top plate of each second capacitor in the first sampling and holding circuit and the positive input terminal of the comparator 30. The fourth switch unit F4 is used to disconnect in the sampling phase to disconnect the connection between the top plate of each second capacitor in the first sampling and holding circuit and the positive input terminal of the comparator, and to connect in the conversion phase to connect the connection between the top plate of each second capacitor in the first sampling and holding circuit and the positive input terminal of the comparator 30.

[0062] In this way, the connection control of the top plates of each first capacitor and each second capacitor in the first sample and hold circuit is achieved by synchronously switching the third switch unit F3 and the fourth switch unit F4 in the sampling phase and the conversion phase.

[0063] In one possible implementation, Figure 5 As shown, the switch control module 20 may further include a fifth switch unit F5 and a sixth switch unit F6.

[0064] The fifth switch unit F5 is connected between the top plate of each of the first capacitors and the top plate of each of the second capacitors in the second sampling and holding circuit. The fifth switch unit F5 is used to disconnect in the sampling phase to disconnect the connection between the top plate of the first capacitor and the top plate of the second capacitor in the second sampling and holding circuit, and to turn on in the conversion phase to connect the connection between the top plate of the first capacitor and the top plate of the second capacitor in the second sampling and holding circuit.

[0065] The sixth switch unit F6 is connected between the top plate of each second capacitor in the second sampling and holding circuit and the negative input terminal of the comparator 30. The sixth switch unit F6 is used to be disconnected in the sampling phase to disconnect the connection between the top plate of each second capacitor in the second sampling and holding circuit and the negative input terminal of the comparator, and to be turned on in the conversion phase to connect the connection between the top plate of the second capacitor in the second sampling and holding circuit and the negative input terminal of the comparator 30.

[0066] In this way, the connection control of each first capacitor and each second capacitor top plate in the second sample and hold circuit is realized by synchronously switching on and off the fifth switch unit F5 and the sixth switch unit F6 in the sampling phase and the conversion phase.

[0067] In a possible implementation, the target capacitance ratios corresponding to the remaining sampling units except the sampling unit corresponding to the lowest bit in the plurality of sampling units are the same. In some embodiments, the target capacitance ratio corresponding to the sampling unit corresponding to the lowest bit may be a set value, for example, the set value may be 1. In this way, during the sampling phase, the capacitance changes caused by the dielectric effect between each capacitance unit are proportional, which will not cause the deterioration of THD and DNL / INL.

[0068] For example, the capacitance of the first capacitor and the second capacitor can be αiCi and (1-αi)Cni' respectively, i represents the position, i can be 1, 2...n, the larger the value of i is, the lower the order of the number of bits corresponding to the corresponding sampling unit is, and the target capacitance ratio of each sampling unit is αi / (1-αi). Then, the target capacitance ratios corresponding to the remaining sampling units except the sampling unit corresponding to the lowest bit in the multiple sampling units are the same, and the target capacitance ratio corresponding to the sampling unit corresponding to the lowest bit is 1, that is: α1=α2=α(n-1)≠1 and αn=1.

[0069] In a possible implementation, the target capacitance ratio is determined according to the parameters of the circuit environment in which the sampling circuit is located during the sampling process; wherein the parameters of the circuit environment include at least one of the following: the value range of the positive input signal VIP of the differential signal pair, the value range of the negative input signal VIN of the differential signal pair, and the voltage value of the comparator power supply voltage VDD. The circuit environment in which the sampling circuit is located can be represented by the voltage, current, etc. of the circuit to which the sampling circuit is connected.

[0070] In this embodiment, each switch unit can select a corresponding switch device according to actual needs, and the present disclosure does not limit this.

[0071] The present disclosure also provides a sampling device capable of counteracting the dielectric absorption effect. Figure 5 As shown, the device includes the above-mentioned sampling circuit capable of counteracting the dielectric absorption effect and a comparator 30.

[0072] The comparator 30 is used to compare the signals inputted from the positive input terminal and the negative input terminal during the conversion phase, and output the comparison result through the output terminal.

[0073] In a possible implementation, the device may further include: a successive approximation register, configured to receive a comparison result output by the comparator, and perform sampling control and result output of the device according to the comparison result.

[0074] It should be noted that although the above embodiments are used as examples to introduce the sampling method and device capable of offsetting the dielectric absorption effect, those skilled in the art will appreciate that the present disclosure should not be limited thereto. In fact, the user can flexibly set the circuit structure according to personal preferences and / or actual application scenarios, as long as it complies with the technical solution of the present disclosure.

[0075] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A sampling circuit capable of counteracting dielectric absorption effect, characterized in that: The circuit includes two sample-and-hold circuits and a switch control module. Each of the sample-and-hold circuits comprises a plurality of sampling units, each of the sampling units comprises a first capacitor and a second capacitor, at least some of the sampling units in the plurality of sampling units correspond to the same target capacitance ratio, and the target capacitance ratio of each of the sampling units is a ratio of capacitance values ​​of the first capacitor and the second capacitor in the sampling unit; The total capacitance value of the higher-order sampling unit in two adjacent sampling units is a preset multiple of the total capacitance value of the lower-order sampling unit, and the total capacitance value of each sampling unit is the sum of the capacitance values ​​of the first capacitor and the second capacitor in the sampling unit; The switch control module is used to control the connection and conduction between the bottom plate of each first capacitor in the first sampling and holding circuit of the sampling and holding circuit, the bottom plate of each second capacitor and the first input terminal of the positive input signal of the differential signal pair in the sampling and holding circuit in the sampling and holding circuit, and control the connection and conduction between the bottom plate of each first capacitor in the second sampling and holding circuit of the sampling and holding circuit, the bottom plate of each second capacitor and the second input terminal of the negative input signal of the differential signal pair in the sampling and holding circuit in the sampling and holding circuit, and control the top plate of each first capacitor to be connected to the power supply voltage and control the top plate of each second capacitor to be grounded; as well as Controlling the disconnection between the bottom plate of each first capacitor and the bottom plate of each second capacitor in the first sampling and holding circuit and the first input terminal in the conversion phase, and controlling the disconnection between the bottom plate of each first capacitor and the bottom plate of each second capacitor in the second sampling and holding circuit and the second input terminal in the conversion phase, and controlling the connection between the top plate of each first capacitor and the top plate of each second capacitor in the first sampling and holding circuit and the positive input terminal of the comparator, and controlling the connection between the top plate of each first capacitor and the top plate of each second capacitor in the second sampling and holding circuit and the negative input terminal of the comparator; The switch control module includes a first switch unit and a second switch unit. The first switch unit is connected between the power supply voltage and the top plate of each of the first capacitors, and is used to control the top plate of each of the first capacitors to be connected to the power supply voltage during the sampling phase, and to disconnect the top plate of each of the first capacitors from the power supply voltage during the conversion phase; The top plate of each second capacitor is grounded through the second switch unit, and the second switch unit is used to be turned on in the sampling phase to ground the top plate of each second capacitor, and turned off in the conversion phase to disconnect the top plate of each second capacitor from the ground.

2. The circuit according to claim 1, characterized in that The switch control module includes a first sampling switch and a second sampling switch. The first sampling switch is connected between the first sampling and holding circuit and the first input terminal, and is used to control the connection between the bottom plates of each first capacitor, the bottom plates of each second capacitor and the first input terminal in the first sampling and holding circuit during the sampling phase; and controlling the connection between the bottom plates of each first capacitor, the bottom plates of each second capacitor and the first input terminal in the first sampling and holding circuit to be disconnected during the conversion phase; The second sampling switch is connected between the second sampling and holding circuit and the second input terminal, and is used to control the connection between the bottom plates of each first capacitor, the bottom plates of each second capacitor and the second input terminal in the second sampling and holding circuit during the sampling phase; And in the conversion stage, the connection between the bottom plates of the first capacitors, the bottom plates of the second capacitors and the second input terminal in the second sampling and holding circuit is controlled to be disconnected.

3. The circuit according to claim 2, characterized in that The switch control module further includes a third switch unit and a fourth switch unit. The third switch unit is connected between the top plates of the first capacitors and the top plates of the second capacitors in the first sample-and-hold circuit, and the third switch unit is used to disconnect in a sampling phase to disconnect the connection between the top plates of the first capacitors and the second capacitors in the first sample-and-hold circuit, and to conduct in a conversion phase to conduct the connection between the top plates of the first capacitors and the second capacitors in the first sample-and-hold circuit; The fourth switch unit is connected between the top plate of each of the second capacitors in the first sampling and holding circuit and the positive input terminal of the comparator. The fourth switch unit is used to disconnect in the sampling phase to disconnect the connection between the top plate of each of the second capacitors in the first sampling and holding circuit and the positive input terminal of the comparator, and to connect in the conversion phase to connect the connection between the top plate of each of the second capacitors in the first sampling and holding circuit and the positive input terminal of the comparator.

4. The circuit according to claim 3, characterized in that The switch control module further includes a fifth switch unit and a sixth switch unit. The fifth switch unit is connected between the top plates of the first capacitors and the top plates of the second capacitors in the second sample-and-hold circuit, and the fifth switch unit is used to disconnect in the sampling phase to disconnect the connection between the top plates of the first capacitors and the second capacitors in the second sample-and-hold circuit, and to conduct in the conversion phase to conduct the connection between the top plates of the first capacitors and the second capacitors in the second sample-and-hold circuit; The sixth switch unit is connected between the top plate of each of the second capacitors in the second sampling and holding circuit and the negative input terminal of the comparator. The sixth switch unit is used to be disconnected in the sampling phase to disconnect the connection between the top plate of each of the second capacitors in the second sampling and holding circuit and the negative input terminal of the comparator, and to be turned on in the conversion phase to connect the connection between the top plate of the second capacitor in the second sampling and holding circuit and the negative input terminal of the comparator.

5. The circuit according to claim 1, characterized in that The target capacitance ratios corresponding to the remaining sampling units among the plurality of sampling units except the sampling unit corresponding to the lowest bit are the same.

6. The circuit according to claim 1, characterized in that The target capacitance ratio is determined according to parameters of the circuit environment in which the sampling circuit is located during the sampling process; The parameters of the circuit environment include at least one of the following: a numerical range of a positive input signal of a differential signal pair, a numerical range of a negative input signal of a differential signal pair, and a voltage value of a comparator power supply voltage.

7. A sampling device capable of counteracting dielectric absorption effect, characterized in that: The device comprises: a sampling circuit and a comparator capable of offsetting dielectric absorption effect as claimed in any one of claims 1 to 6, Each of the sample-and-hold circuits comprises a plurality of sampling units, each of the sampling units comprises a first capacitor and a second capacitor, at least some of the target sampling units in the plurality of sampling units have the same target capacitance ratio, and the target capacitance ratio of each of the sampling units is the ratio of the capacitance values ​​of the first capacitor and the second capacitor in the sampling unit; the total capacitance value of the higher-order sampling unit in two adjacent sampling units is a preset multiple of the total capacitance value of the lower-order sampling unit, and the total capacitance value of each of the sampling units is the sum of the capacitance values ​​of the first capacitor and the second capacitor in the sampling unit; The switch control module is used to control the connection between the bottom plate of each first capacitor in the first sampling and holding circuit of the sampling and holding circuit, the bottom plate of each second capacitor and the first input terminal of the positive input signal of the differential signal pair in the sampling phase, and control the connection between the bottom plate of each first capacitor in the second sampling and holding circuit of the sampling and holding circuit, the bottom plate of each second capacitor and the second input terminal of the negative input signal of the differential signal pair in the sampling phase, and control the top plate of each first capacitor to be connected to the power supply voltage and control the top plate of each second capacitor to be grounded; and Controlling the disconnection between the bottom plate of each first capacitor and the bottom plate of each second capacitor in the first sampling and holding circuit and the first input terminal in the conversion phase, and controlling the disconnection between the bottom plate of each first capacitor and the bottom plate of each second capacitor in the second sampling and holding circuit and the second input terminal in the conversion phase, and controlling the connection between the top plate of each first capacitor and the top plate of each second capacitor in the first sampling and holding circuit and the positive input terminal of the comparator, and controlling the connection between the top plate of each first capacitor and the top plate of each second capacitor in the second sampling and holding circuit and the negative input terminal of the comparator; The comparator is used to compare the signals inputted from the positive input terminal and the negative input terminal in the conversion phase, and output the comparison result through the output terminal; The switch control module includes a first switch unit and a second switch unit. The first switch unit is connected between the power supply voltage and the top plate of each of the first capacitors, and is used to control the top plate of each of the first capacitors to be connected to the power supply voltage during the sampling phase, and to disconnect the top plate of each of the first capacitors from the power supply voltage during the conversion phase; The top plate of each second capacitor is grounded through the second switch unit, and the second switch unit is used to be turned on in the sampling phase to ground the top plate of each second capacitor, and turned off in the conversion phase to disconnect the top plate of each second capacitor from the ground.

8. The device according to claim 7, characterized in that The device also includes: The successive approximation register is used to receive the comparison result output by the comparator, and perform sampling control and result output of the device according to the comparison result.

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