An Ethernet encoding method and apparatus

Abstract

The present application discloses an encoding method and apparatus for Ethernet, in order to adapt to the scenario of greater transmission error codes brought by high bandwidth. The method is as follows: the sending end encodes first information to be encoded by using a first forward error correction (FEC) codeword to obtain first encoded data, and the first FEC codeword is a Reed-Solomon forward error correction (RS-FEC) code; the sending end encodes the first encoded data by using a second FEC codeword to obtain second encoded data; the code length N and the information bit length K of the second FEC codeword satisfy the following formula: where M1 is the throughput rate of the first encoded data, and M2 is the throughput rate of the second encoded data.

Description

[0001] This application is a divisional application of the application filed with the China National Intellectual Property Administration on October 29, 2020, with the application number 202011183088.7 and the invention title "An Encoding Method and Device for Ethernet". Technical Field

[0002] The embodiments of this application relate to the field of encoding technologies, and in particular, to an encoding method and device for Ethernet. Background Art

[0003] With the rapid growth of the network service throughput rate, the service bandwidth of communication devices has also increased rapidly. The International Organization for Standardization has defined the IEEE802.3 Ethernet protocol, and the interface protocols for 100GE, 200GE, and 400GE have been defined in the IEEE 802.3 Ethernet protocol. Big data transmission has a higher demand for high bandwidth, which brings pressure to the data center architecture and underlying interconnection. Considering this, the standardization work of the next-generation Ethernet 800G has begun to be promoted.

[0004] Although Ethernet 800G can provide a higher transmission bandwidth, it will bring the problem of increased transmission error codes. How to provide an encoding method with higher error correction performance is an urgent problem to be solved. Summary of the Invention

[0005] The embodiments of this application provide an encoding method and device for Ethernet, aiming to provide an encoding method with higher error correction performance to adapt to the scenario of larger transmission error codes brought by high bandwidth.

[0006] In a first aspect, an encoding method for Ethernet is provided. The execution entity of this method can be a sending end, or also referred to as an encoding device. The steps of this method include: the sending end encodes first information to be encoded using a first FEC codeword to obtain first encoded data, where the first FEC codeword is a Reed-Solomon forward error correction code RS-FEC, and the sending end encodes the first encoded data using a second FEC codeword to obtain second encoded data. The code length N and the information bit length K of the second FEC codeword satisfy the following formula: Among them, M1 is the throughput of the first encoded data, and M2 is the throughput of the second encoded data. It can be seen that by adopting the encoding scheme of cascading two FEC codewords, the throughput requirements of Ethernet 800G or even higher can be supported. Through the design of the second FEC codeword, the error correction performance is increased by increasing the overhead (OH) of the system FEC encoding. Ethernet 800G uses a higher baud rate for transmission, and the bit error rate before error correction is higher. By adopting the encoding scheme of cascading two FEC codewords, the error correction performance of Ethernet can be improved to meet the error correction performance index of Ethernet 800G. By setting constraint conditions The bandwidth and transmission performance limitations of optical devices can be met. On the premise of meeting the requirements of next-generation Ethernet technical indicators, it flexibly supports and is compatible with most interface protocols of 100GE, 200GE, and 400GE in the IEEE 802.3 standard.

[0007] In a possible design, the sending end performs FEC encoding on the first information to be encoded using the first FEC codeword to obtain the first encoded data, which is achieved by the following method: the sending end performs FEC encoding on the first information to be encoded using y first FEC codewords to obtain y groups of encoded data, where y is an even number greater than or equal to 2; the sending end performs first interleaving on the y groups of encoded data to obtain the first encoded data; the first interleaving conforms to an interleaving matrix with row and column numbers L and P respectively, and L and P are even numbers greater than or equal to 2, and P is the number of physical medium attachment sublayer PMA channels. This can make the encoded data after the first FEC codeword encoding more fully interleaved and improve the error correction performance. The interleaving between the first FEC codeword (RS codeword) and the second FEC codeword (Inner-FEC) is such that the residual bit errors after Inner-FEC can be aggregated into a symbol (10-bit) of an RS, minimizing the Hamming distance at the symbol level between RS and Inner-FEC and improving the error correction efficiency of RS.

[0008] In a possible design, the row elements in a row of the interleaving matrix respectively correspond to the data obtained by polling from the y groups of encoded data. Such an interleaving method can make the symbols of different RSs in the PCS layer be more randomly and evenly distributed to the second FEC codeword (Inner-FEC) codewords, which can improve the burst error resistance ability of the system. Such an interleaving can be compatible with the number of RSs in each PCS layer, without distinguishing the symbols of the RS codewords from the PCS layer data stream, and can reduce the operation of identifying the RS symbol boundary.

[0009] In a possible design, each row of the L rows adopts the same polling rule; or, the polling rules of every consecutive y rows in the L rows are all different.

[0010] In a possible design, the transmitting end encodes the first encoded data using a second FEC codeword, which is achieved in the following manner: the transmitting end transmits the first encoded data through P PMA channels; and encodes the first encoded data transmitted through the P PMA channels.

[0011] In a possible design, the transmitting end transmits the second encoded data through P PMA channels and processes the second encoded data transmitted through the P PMA channels.

[0012] In a possible design, the transmitting end performs a first interleaving on the y groups of encoded data, which is achieved in the following manner: the transmitting end transmits the y groups of encoded data through P PMA channels; and performs the first interleaving on the y groups of encoded data transmitted through the P PMA channels.

[0013] In a possible design, the P PMA channels correspond to the sequence numbers from 0 to (P - 1), and the P columns of the interleaving matrix respectively correspond one-to-one to the encoded data from the P PMA channels; the row elements with odd column sequence numbers in one row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with the sequence numbers from 0 to (P / 2 - 1); the row elements with even column sequence numbers in one row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with the sequence numbers from P / 2 to P. Such a design of the interleaving method can avoid identifying the boundaries of symbols (symbols), enabling the PMA layer to directly perform multiplexing and 10-bit granularity distribution on the data stream received by the PMA layer without knowing the format of the PCS layer data frame. The 10-bit (10-bits) granularity exactly matches the size of the symbols of the second FEC codeword, improving the system's ability to resist burst errors (burst errors), and the implementation method is simple.

[0014] In a possible design, the value of P can be a power of 2, for example, it can be 16 or 32.

[0015] In a possible design, K also satisfies the following conditions: is a positive integer, and N1 is the code length of the first FEC codeword. In this way, the output of the first FEC codeword (i.e., the input of the second FEC codeword) can be equally divided into integer parts, each part being K, and each part of the input does not require padding bits. This makes the concatenated coding scheme of the first FEC codeword and the second FEC codeword simpler and easier to implement, with lower complexity.

[0016] In a possible design, N and K also satisfy the following conditions: W is a positive integer. The Ethernet encoding scheme corresponding to the second FEC codeword can make the implementation of Ethernet clock extraction and synchronization simpler. When W is an integer, the PLL can be adjusted at integer grid points, and the clock extraction and synchronization are simply implemented, so that the phase locking of the PLL can be completed more quickly, and it is easy to implement with low complexity.

[0017] Among them, W can be 4 times the reference clock multiplication factor RCM.

[0018] In a possible design, M1 = 106.25 Gbps and M2 = 114 Gbps.

[0019] In a possible design,

[0020] In a possible design, the second FEC codeword is constructed as (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, K is the number of bits included in the information bits, and m is the order of the Galois field where the second FEC codeword is located; the second FEC codeword includes any one of the following codewords, or includes a spatially coupled code constructed with any one of the following codewords as sub - codes, or includes a multi - layer code constructed with any one of the following codewords as sub - codes: Hamming(144, 136, 8), Hamming(180, 170, 10), extended Hamming code eHamming(180, 170, 9), double - extended Hamming code DE - Hamming(180, 170, 8), BCH(360, 340, 10), double - extended BCH code DE - BCH(360, 340, 9), DE - BCH(576, 544, 10), or BCH(594, 561, 11), or Hamming(180, 170, 10).

[0021] In a possible design, the second FEC codeword is constructed as (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, K is the number of bits included in the information bits, and m is the order of the Galois field where this FEC codeword is located; the second FEC codeword includes any one of the following codewords, or includes a spatially coupled code constructed with any one of the following codewords as sub - codes, or includes a multi - layer code constructed with any one of the following codewords as sub - codes: Hamming(126,119,7), Hamming(127,119,8), Hamming(145,136,9), Hamming(179,170,9), eHamming(127,119,7), eHamming(145,136,8), eHamming(179,170,8), eHamming(181,170,10), BCH(290,272,9), BCH(358,340,9), BCH(574,544,10), extended BCH code eBCH(291,272,9), eBCH(359,340,9), eBCH(361,340,10), eBCH(575,544,10), or DE - BCH(362,340,10).

[0022] In a possible design, the sending end performs one or more of the following processes on the second encoded data: transmitting through P PMA channels, second interleaving, data modulation, or optoelectronic conversion; P is an even number greater than or equal to 2; the sending end sends the processed data to the receiving device.

[0023] In a possible design, N = x * n, K = x * k, where x, n, and k are positive integers.

[0024] The Ethernet encoding method provided by the embodiments of this application, through the concatenated coding scheme of the first FEC codeword and the second FEC codeword, the outer code of the concatenated code follows the original standard RS codeword, and the inner code of the concatenated code uses the second FEC codeword, that is, the Inner - FEC codeword. This encoding method can be compatible with the 100GE, 200GE, 400GE Ethernet RS(544,514,10) encoding, and increases the overhead (OH) of the entire FEC encoding through the encoding method of the RS(544,514,10) concatenated with the Inner - FEC codeword. The OH of the system link FEC encoding increases, improving the error - correction performance of the system, meeting both the performance indicators of the next - generation high - speed Ethernet and the delay requirements of the next - generation Ethernet with a small implementation cost.

[0025] The encoder component of this Inner-FEC codeword can be placed in the PCS layer or the PMA layer. When the encoder component of the Inner-FEC codeword is placed in the PMA layer, the RS coding in the PCS layer and the Inner-FEC coding in the PMA layer are decoupled, and the Inner-FEC coding in the PMA layer can be completed in the case of containing the bit errors inherent in the C2M optical-electric interface. When the encoder component of the Inner-FEC codeword is cascaded in the PCS layer, the cascade coding scheme can also be completed.

[0026] In a second aspect, an encoding device for Ethernet is provided, and the device has a function of implementing the method described in the above first aspect and any possible design of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. In one design, the device may include an obtaining module and a processing module. Exemplarily: the obtaining module is configured to obtain first information to be encoded; the processing module is configured to encode the first information to be encoded by using a first forward error correction code (FEC) codeword to obtain first encoded data, and the first forward error correction code (FEC) codeword is a Reed-Solomon forward error correction code (RS-FEC); the processing module is further configured to encode the first encoded data by using a second FEC codeword to obtain second encoded data; the code length N and the information bit length K of the second FEC codeword satisfy the following formula: where M1 is the throughput rate of the first encoded data, and M2 is the throughput rate of the second encoded data.

[0027] In a possible design, when encoding the first information to be encoded by using the first FEC codeword to obtain the first encoded data, the processing module is configured to: encode the first information to be encoded by using y first FEC codewords to obtain y groups of encoded data, where y is an even number greater than or equal to 2; perform first interleaving on the y groups of encoded data to obtain the first encoded data; the first interleaving conforms to an interleaving matrix with row and column numbers L and P respectively, and L and P are even numbers greater than or equal to 2, and P is the number of physical medium attachment (PMA) channels.

[0028] In a possible design, the row elements in a row of the interleaving matrix respectively correspond to the data obtained by polling from the y groups of encoded data.

[0029] In a possible design, each of the L rows adopts the same polling rule; or, the polling rules of every consecutive y rows in the L rows are different.

[0030] In a possible design, when encoding the first encoded data with the second FEC codeword, the processing module is configured to: transmit the first encoded data through P PMA channels; and encode the first encoded data transmitted through the P PMA channels.

[0031] In a possible design, the processing module is further configured to: transmit the second encoded data through P PMA channels, and process the second encoded data transmitted through the P PMA channels.

[0032] In a possible design, when performing the first interleaving on the y groups of encoded data, the processing module is configured to: transmit the y groups of encoded data through P PMA channels; and perform the first interleaving on the y groups of encoded data transmitted through the P PMA channels.

[0033] In a possible design, the P PMA channels correspond to serial numbers from 0 to (P - 1), and the P columns of the interleaving matrix respectively correspond one-to-one to the encoded data from the P PMA channels; the row elements with odd column serial numbers in a row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with serial numbers from 0 to (P / 2 - 1); and the row elements with even column serial numbers in a row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with serial numbers from P / 2 to P.

[0034] In a possible design, the value of P includes 16 or 32.

[0035] In a possible design, K further satisfies the following condition: is a positive integer, and N1 is the code length of the first FEC codeword.

[0036] In a possible design, N and K further satisfy the following condition: W is a positive integer.

[0037] In a possible design, W = 4 * reference clock multiplication factor RCM.

[0038] In a possible design, M1 = 106.25 Gbps and M2 = 114 Gbps.

[0039] In a possible design,

[0040] In a possible design, the second FEC codeword is constructed as (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, K is the number of bits included in the information bits, and m is the order of the Galois field where the second FEC codeword is located; the second FEC codeword includes any one of the following codewords, or includes a spatially coupled code constructed with any one of the following codewords as sub - codes, or includes a multi - layer code constructed with any one of the following codewords as sub - codes: Hamming(144, 136, 8), Hamming(180, 170, 10), extended Hamming code eHamming(180, 170, 9), double - extended Hamming code DE - Hamming(180, 170, 8), BCH(360, 340, 10), double - extended BCH code DE - BCH(360, 340, 9), DE - BCH(576, 544, 10), or BCH(594, 561, 11), or Hamming(180, 170, 10).

[0041] In a possible design, the second FEC codeword is constructed as (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, K is the number of bits included in the information bits, and m is the order of the Galois field where the FEC codeword is located; the second FEC codeword includes any one of the following codewords, or includes a spatially coupled code constructed with any one of the following codewords as sub - codes, or includes a multi - layer code constructed with any one of the following codewords as sub - codes: Hamming(126, 119, 7), Hamming(127, 119, 8), Hamming(145, 136, 9), Hamming(179, 170, 9), eHamming(127, 119, 7), eHamming(145, 136, 8), eHamming(179, 170, 8), eHamming(181, 170, 10), BCH(290, 272, 9), BCH(358, 340, 9), BCH(574, 544, 10), extended BCH code eBCH(291, 272, 9), eBCH(359, 340, 9), eBCH(361, 340, 10), eBCH(575, 544, 10), or DE - BCH(362, 340, 10).

[0042] In a possible design, the processing module is further configured to: perform one or more of the following operations on the second encoded data: transmit through P PMA channels, second interleaving, data modulation, or optoelectronic conversion; P is an even number greater than or equal to 2; the apparatus further includes a communication module for sending the processed data to a receiving device.

[0043] In a possible design, N = x * n, K = x * k, where x, n, and k are positive integers.

[0044] For the beneficial effects of the second aspect, reference can be made to the corresponding description of the first aspect, which will not be elaborated here.

[0045] In a third aspect, an Ethernet encoding device is provided, and the device has the function of implementing the method described in the above first aspect and any possible design of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0046] In a possible design, when part or all of the function is implemented by hardware, the Ethernet encoding device includes: an input interface circuit for obtaining first information to be encoded; a logic circuit for performing the actions described in the above first aspect and any possible design of the first aspect based on the obtained first information to be encoded; and an output interface circuit for outputting second encoded data.

[0047] Optionally, the Ethernet encoding device may be a chip or an integrated circuit.

[0048] In a possible design, when part or all of the function is implemented by software, the Ethernet encoding device includes: a memory for storing programs or instructions; a processor for executing the programs or instructions stored in the memory, and when the programs or instructions are executed, the method described in the above first aspect and any possible design of the first aspect is implemented.

[0049] Optionally, the above memory may be a physically independent unit or integrated with the processor.

[0050] In a possible design, when part or all of the function is implemented by software, the Ethernet encoding device includes a processor. The memory for storing programs is located outside the encoding device, and the processor is connected to the memory through a circuit / wire for reading and executing the programs stored in the memory.

[0051] In a fourth aspect, a computer-readable storage medium is provided, storing computer-readable instructions, and when the computer-readable instructions are run on a computer, the method described in any of the first aspect and any possible design of the first aspect is executed.

[0052] In a fifth aspect, an embodiment of the present application provides a computer program product containing instructions, and when it runs on a computer, the method described in the above first aspect and any possible design of the first aspect is executed.

[0053] In a sixth aspect, an embodiment of the present application provides a chip system. The chip system includes a processor and may further include a memory, and is used to implement the method described in the first aspect or any possible design in the first aspect. The chip system may be composed of chips or may include chips and other discrete devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1a It is a schematic structural diagram of a communication system in an embodiment of the present application;

[0055] Figure 1b It is a schematic diagram of an Ethernet architecture in an embodiment of the present application;

[0056] Figure 2 It is a schematic diagram of RS-FEC encoding of 100GE Ethernet in an embodiment of the present application;

[0057] Figure 3 It is a schematic diagram of RS-FEC encoding of 200GE Ethernet in an embodiment of the present application;

[0058] Figure 4 It is a schematic diagram of RS-FEC encoding of 400GE Ethernet in an embodiment of the present application;

[0059] Figure 5 It is one of the schematic flowcharts of the encoding method of Ethernet in an embodiment of the present application;

[0060] Figure 6a It is a schematic diagram of an Ethernet layer architecture one in an embodiment of the present application;

[0061] Figure 6b It is a schematic diagram of an Ethernet layer architecture two in an embodiment of the present application;

[0062] Figure 7a It is a schematic diagram of the processing process of the data stream corresponding to architecture one in an embodiment of the present application;

[0063] Figure 7b It is a schematic diagram of the processing process of the data stream corresponding to architecture two in an embodiment of the present application;

[0064] Figure 8 It is a schematic diagram of an 800G Ethernet layer architecture in an embodiment of the present application;

[0065] Figure 9 It is one of the schematic flowcharts of the data processing in an embodiment of the present application;

[0066] Figure 10 It is two of the schematic flowcharts of the data processing in an embodiment of the present application;

[0067] Figure 11 It is three of the schematic flowcharts of the data processing in an embodiment of the present application;

[0068] Figure 12 This is the second flowchart diagram of the encoding method for Ethernet in the embodiments of the present application;

[0069] Figure 13 This is the first structural diagram of the encoding device for Ethernet in the embodiments of the present application;

[0070] Figure 14 This is the second structural diagram of the encoding device for Ethernet in the embodiments of the present application;

[0071] Figure 15 This is the third structural diagram of the encoding device for Ethernet in the embodiments of the present application. Detailed implementation manners

[0072] The embodiments of the present application provide an encoding method and device for Ethernet, aiming to improve the error correction performance of Ethernet encoding. Among them, the method and the device are based on the same technical concept. Since the principles of the method and the device for solving problems are similar, the implementation of the device and the method can be referred to each other, and the repeated parts will not be described again.

[0073] In the description of the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The plurality involved in the present application refers to two or more. In addition, it should be understood that in the description of the present application, terms such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0074] The communication method provided by the embodiments of the present application can be applied to Ethernet, and can also be applied to other networks using forward error correction (FEC) encoding. The embodiments of the present application can be applied to application scenarios with large traffic and short delay, such as short-distance interconnection in data centers, cloud storage, cloud computing, and the backbone network of 5th generation (5G) base stations.

[0075] Next, the embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0076] Figure 1aSchematic diagram of a communication system applicable to an embodiment of the present application. The communication system includes a transmitting end 101 and a receiving end 102. Among them, the transmitting end can also be called a transmitting device, and the receiving end can also be called a receiving device. The transmitting end can also be called a transmitting apparatus, and the receiving end can also be called a receiving apparatus. An embodiment of the present application is described by taking the transmitting end and the receiving end as examples. When an embodiment of the present application is applied to Ethernet, both the transmitting end and the receiving end support the IEEE802.3 Ethernet protocol. As Figure 1b shown, it is a schematic diagram of an Ethernet architecture applicable to an embodiment of the present application. It includes switches and servers in a data center. The switches can be connected to each other, and the switches can also be connected to the servers. It can be understood that Figure 1b it is a schematic diagram. In an actual Ethernet network, there may be more or fewer switches and more or fewer servers. The connection method between switches and the connection method between switches and servers are for illustration.

[0077] In Ethernet, the transmitting end 101 is a switch, and the receiving end 102 is a switch; the transmitting end 101 is a switch, and the receiving end 102 is a server; the transmitting end 101 is a server, and the receiving end 102 is a switch.

[0078] The method provided by the embodiment of the present application can be applicable to multiple fields, for example, augmented reality / virtual reality (AR / VR), artificial intelligence (AI), 5G applications or cloud applications, etc. More and more applications in various fields will generate more and more throughput. The explosive growth of throughput requires higher bandwidth. Therefore, the standard work of 800G Ethernet has begun to be promoted. The increase in the transmission bandwidth of Ethernet will inevitably lead to an increase in transmission error codes. The embodiment of the present application provides an encoding method for Ethernet in order to adapt to a higher Ethernet transmission bandwidth.

[0079] To better understand the solution provided by the embodiment of the present application, the encoding schemes of 100GE, 200GE, and 400GE in the IEEE 802.3 standard, as well as some related concepts and terms, will be introduced below.

[0080] 1. 100GE

[0081] In the 100GE Ethernet 4-channel physical media dependent (PMD), that is, in the KP4 application scenario, the encoding scheme uses Reed-Solomon (RS) (544, 514, 10) codewords. The code length n of the RS codeword RS = 544, and the length k of the information symbol bitsRS = 514, and the Galois field is GF(2 10 ). The schematic flow diagram of the encoding scheme for 100GE KP4 Ethernet is as Figure 2 shown. Data from the client of the medium access control (MAC) and higher layers will pass through the reconciliation sublayer. The reconciliation sublayer translates the data from the MAC and higher layers of the client and sends it to the physical coding sublayer (PCS) layer of 100GBASE-R through the 100 Gigabit per second (bps, b / s) media independent interface (100Gb / s media independent interface, CGMII) interface. The PCS layer transcodes, scrambles, inserts AM, etc. into the data and sends it to the Reed-Solomon forward error correction (RS-FEC) codeword for encoding. The RS-FEC encoding for 100GE Ethernet uses an RS(544, 514, 10) codeword. The encoded codeword will enter the physical medium attachment sublayer (PMA) layer for operations such as multiplexing (Mux), and the data stream after the operation is transmitted to the PMA of the next layer through a four-lane attachment unit interface (CAUI-4) chip-to-module (C2M) interface. After the data stream passes through the PMA, the PMD modulates and performs optoelectronic conversion on the data stream. The medium dependent interface (MDI) interface transmits the modulated and optoelectronically converted optical signal through a medium such as an optical fiber to the receiving end.

[0082] 2. 200GE, 400GE

[0083] For the encoding schemes of 200GE and 400GE Ethernet, the RS(544, 514, 10) codeword is also used. The code length n of the RS codeword RS = 544, and the length of the information symbol bit k RS = 514, and the Galois field is GF(2 10 ).

[0084] The schematic flow diagram of the encoding scheme for 200GE Ethernet is as Figure 3As shown in the figure. The data from the clients of the MAC and higher layers will pass through the coordination sublayer. The coordination sublayer translates the data from the clients of the MAC and higher layers and sends it to the PCS layer of 200GBASE-R through the 200GMII interface. The PCS layer performs operations such as transcoding, scrambling, and inserting AM on the data and sends it to the RS-FEC module for encoding. The RS-FEC encoding of 200GE Ethernet uses two RS(544,514,10) codewords. The data stream from the PCS layer is sent to the two RS codewords in a 10-bit polling distribution manner. The encoded codewords of the two RS codewords respectively will enter the PMA layer for operations such as Mux. The data stream after the operation is transmitted to the PMA of the next layer through a 200G four-lane attachment unit interface (CAUI-4) C2M interface. After the data stream passes through the PMA, the PMD modulates and performs optoelectronic conversion on the data stream. The MDI interface transmits the optically modulated and optoelectronically converted optical signal to the receiving end through a medium such as an optical fiber.

[0085] The flow schematic diagram of the encoding scheme of 400GE Ethernet is as Figure 4 As shown in the figure. The data from the clients of the MAC and higher layers will pass through the coordination sublayer. The coordination sublayer translates the data from the clients of the MAC and higher layers and sends it to the PCS layer of 400GBASE-R through the 400GMII interface. The PCS layer performs operations such as transcoding, scrambling, and inserting AM on the data and sends it to the RS-FEC module for encoding. The RS-FEC encoding of 400GE Ethernet uses two RS(544,514,10) codewords. The data stream from the PCS layer is sent to the two RS codewords in a 10-bit polling distribution manner. The encoded codewords of the two RS codewords respectively, after passing through Mux and 10-bit symbol distribution, enter the PMA layer. The data stream output by the PMA layer is transmitted to the PMA of the next layer through a 400GAUI-4 C2M interface. After the data stream passes through the PMA, the PMD modulates and performs optoelectronic conversion on the data stream. The MDI interface transmits the optically modulated and optoelectronically converted optical signal to the receiving end through a medium such as an optical fiber.

[0086] The encoding schemes of 100GE, 200GE, and 400GE Ethernet all perform RS encoding at the PCS layer. The data stream after RS encoding runs end-to-end. The errors caused by the noise of the optical link and the electrical layer interface are all corrected by the RS code. However, when Ethernet evolves to 800G, the single-wavelength rate increases from 100Gbps of 400GE to 200Gbps. Due to device constraints, the bit error rate level before correction increases. Therefore, an Ethernet encoding method with stronger error correction ability is required, which needs to be maximally compatible and docked with the data stream of the original scheme.

[0087] Based on this, an embodiment of the present application provides an encoding method for Ethernet. As Figure 5 shown, the specific process of the Ethernet encoding method provided by the embodiment of the present application is described as follows. The execution subject of this method can be a sending device, a sending end, or a sending apparatus.

[0088] S501. The sending end encodes the first information to be encoded with a first codeword to obtain first encoded data.

[0089] Among them, the first codeword can be a forward error correction (FEC) codeword, denoted as the first FEC codeword. For example, the first codeword can be an RS-FEC codeword, which can also be called an RS codeword, or an RS code.

[0090] S502. The sending end encodes the first encoded data with a second codeword to obtain second encoded data.

[0091] The second codeword can be an FEC codeword, denoted as the second FEC codeword.

[0092] It can be seen that the encoding scheme of cascading two FEC codewords adopted in the embodiment of the present application can support the throughput requirements of Ethernet 800G or even higher. Ethernet 800G uses a higher baud rate for transmission, and the pre-error correction rate is higher. By adopting the encoding scheme of cascading two FEC codewords, the error correction performance of Ethernet can be improved to meet the error correction performance index of Ethernet 800G.

[0093] The sending device can also process the second encoded data and send the processed data to the receiving device. Correspondingly, the receiving device receives the processed data.

[0094] Among them, the processing process can include: transmission through P PMA channels, second interleaving, data modulation, or optoelectronic conversion. The processing process can also include some of the above processes. Among them, P is an even number greater than or equal to 2, or P is an integer power of 2. For example, P can take values of 4, 8, 16, 32.

[0095] Combined with the above description, some optional implementation manners of the embodiment of the present application will be described below.

[0096] In the embodiment of the present application, it can be assumed that the construction of the first FEC codeword, that is, the RS codeword, is (544, 514, 10), where 514 is the length K1 of the information symbol bits of the first FEC codeword, and 544 is the code length N1 of the first FEC codeword. K1 is 514 symbols, N1 is 544 symbols, and 10 indicates that one symbol is 10 bits. That is, N1 = 5440 bits and K1 = 5140 bits.

[0097] When Ethernet adopts an encoding scheme with two concatenated FEC codewords, the architecture of the Ethernet layer can have the following examples. The architectures of several examples of the Ethernet layer can be applied to Ethernet networks with a bandwidth of 800G or even higher. The first FEC codeword is an RS-FEC codeword, and the second FEC codeword can be denoted as an Inner-FEC codeword. The architecture of the Ethernet layer can include a MAC layer, a PCS layer, a PMA layer, and a PMD layer. Among them, the MAC layer and the PCS layer can be considered to be on the device side, and the PMA layer and the PMD layer can be considered to be on the module side. The device refers to the device at the sending end, such as a switch or a server. The module refers to an optical module for optical communication. In the embodiments of the present application, the encoder component of the first FEC codeword is used to complete the encoding of the first FEC codeword, and the encoder component of the second FEC codeword is used to complete the encoding of the second FEC codeword. The encoder component of the first FEC codeword can also be denoted as the encoder of the first FEC codeword, the encoding module of the first FEC, the RS-FEC encoder, or the RS-FEC encoding module. The encoder component of the second FEC codeword can also be denoted as the encoder of the second FEC codeword, the encoding module of the second FEC, the Inner-FEC encoder, or the Inner-FEC encoding module. When the second FEC codeword is a Hamming code, the encoder component of the second FEC codeword can also be called a Hamming code encoder or a Hamming code encoding module. When the second FEC codeword is a BCH code, the encoder component of the second FEC codeword can also be called a BCH code encoder or a BCH code encoding module. The BCH code is the (Bose, Ray-Chaudhuri, and Hocquenghem) code.

[0098] Architecture 1:

[0099] As Figure 6a shown, the encoder component of the second FEC codeword can be located in the PCS layer.

[0100] An encoder component for the Inner-FEC codeword is added to the PCS layer on the device side. The data stream passes through the 64B / 66B encoding, 256B / 257B transcoding, scrambling, insertion of AM, and 10-bit granularity polling distribution in the PCS layer on the device side in sequence, and then RS-FEC encoding is performed. Among them, 64B / 66B encoding can refer to expanding a 64-bit data block into a 66-bit information block. 256B / 257B transcoding can refer to: sorting and splitting a 66-bit data block. Taking a 25G service as an example, the data to be sent is split into multiple 66-bit data blocks, and every 4 66-bit data blocks are divided into a data block group (data segment), and each data block group is a 257-bit data block.

[0101] The data stream after RS-FEC encoding enters the encoder component of the Inner-FEC codeword. After the data stream is encoded in the encoder component of the Inner-FEC codeword, it enters the module side through the AUI C2M interface. After the operations of PMA and PMD are completed on the module side, the data stream on the module side is transmitted to the media layer through the MDI interface to complete the data stream transmission.

[0102] Architecture Two:

[0103] As Figure 6b shown, the encoder component of the second FEC codeword can be located in the PMA layer.

[0104] The encoder component of the Inner-FEC codeword is added on the module side. The data stream passes through the 64B / 66B encoding, 256B / 257B transcoding, scrambling, insertion of AM, and 10-bit granularity polling distribution of the MAC layer and PCS layer in sequence on the device side, and then RS-FEC encoding is performed. The processes of 64B / 66B encoding and 256B / 257B transcoding can refer to the description of Architecture One.

[0105] The data stream after RS-FEC encoding enters the module side through the AUI C2M interface. On the module side, the data stream enters the encoder component of the Inner-FEC codeword. After the data stream is encoded in the encoder component of the Inner-FEC codeword, the operations of PMA and PMD are performed, and then the data stream on the module side is transmitted to the media layer through the MDI interface to complete the data stream transmission.

[0106] It can be understood that the encoder component of the second FEC codeword can also be located in other parts of the Ethernet. The above Architecture One and Architecture Two are only illustrative examples.

[0107] Next, based on Architecture One and Architecture Two, the processing flow of the data stream is described.

[0108] In Figure 6a the shown Architecture One, the encoder component of the second FEC codeword can be located in the PCS layer. As Figure 7a shown, the processing process of the data stream is as follows. The data output from the MAC layer will pass through the PCS layer, and the second FEC codeword encoding, that is, Inner-FEC encoding, will be completed in the PCS layer. The two PCS layer data streams after Inner-FEC encoding are independently distributed to the PMA layer, and then combined into an 800G data stream in the PMA layer. The 800G data stream is sent to the receiving end through the communication medium.

[0109] The processing process of the data stream is as follows. The processing process of the data stream includes the processing process of the data stream at the sending end from top to bottom and the processing process of the data stream at the receiving end from bottom to top.

[0110] The data stream at the sending end arrives at the PCS layer from the MII interface. The PCS layer is compatible with 100GE, 200GE, and 400GE standard protocols. At the sending end, after passing through 10 main operation steps in sequence, namely encode and rate matching, 256B / 257B transcode, scramble, alignment insertion, Pre-FEC distribution, RS Encode, distribution and interleave, PMA layer processing, and PMD layer, it is sent to the receiving end through the communication medium.

[0111] Among them, Encode and rate matching is a 64B / 66B module that completes 64B / 66B encoding for the TXD<63:0> data block after translation at the MII interface and adjusts the throughput rate according to TXC<7:0> at the MII interface. 256B / 257B Transcode is the transcoding from 256 bits to 257 bits. Scramble is the scrambling operation. Alignment insertion is the alignment mark insertion operation. Pre-FEC distribution is the 10-bit polling distribution operation before RS encoding. RS Encode is the RS(544,514,10) encoding operation. Distribution and interleave is the symbol distribution and symbol interleaving with a 10-bit granularity after RS encoding. The data stream after symbol distribution and symbol interleaving undergoes the second FEC codeword encoding, that is, the Inner-FEC Encode step operation. After completing the Inner-FEC Encode operation, the data stream passes through the operations of PMA and PMD.

[0112] The receiving end receives a data stream from the communication medium and sequentially goes through 11 main steps at the receiving end, namely PMD, PMA, Alignment lock and lane deskew, Inner-FEC Decode, Lane reorder and de-interleave, RS Decode, Post-FEC interleave, Alignment removal, Descramble, Reverse Transcode, Decode and rate matching. These 11 steps passed through by the receiving end are the reverse operations of the corresponding operation steps at the sending end. Inner-FEC Decode is the decoding operation of Inner-FEC. These 11 steps passed through by the receiving end are the reverse operations of the corresponding operation steps at the sending end. Inner-FEC Decode is the decoding operation of Inner-FEC. Alignment lock and lane deskew are the alignment mark locking and lane alignment operations. Lane reorder and de-interleave are the lane rearrangement and de-interleaving operations. RS Decode is the decoding operation of RS(544,514,10). Post-FEC interleave is the reverse operation of Pre-FEC distribution after RS decoding. Alignment removal is the operation of removing the alignment marks added at the encoding end. Descramble is the descrambling operation. Reverse Transcode is the reverse operation of 256B / 257B transcoding, which reversely converts 257 bits into 256 bits. Decode and rate matching is the reverse operation of 64B / 66B and the throughput rate matching operation.

[0113] Based on the architecture two shown in Figure 6b Figure, the encoder component of the second FEC codeword can be located in the PMA layer, as Figure 7b shown. The processing process of the data stream is as described below. The processing process of the data stream includes the processing process of the data stream at the sending end from top to bottom and the processing process of the data stream at the receiving end from bottom to top.

[0114] The data stream at the sending end arrives at the PCS layer from the MII interface, and the PCS layer is compatible with the 100GE, 200GE, and 400GE standard protocols. At the sending end, it successively undergoes 10 operation steps including encode and rate matching, 256B / 257B transcode, scramble, alignment insertion, Pre-FEC distribution, RS Encode, distribution and interleave, PMA layer processing, Inner-FEC Encode, and PMD layer processing, and then is sent to the receiving end through the communication medium.

[0115] Among them, Encode and rate matching is a 64B / 66B module that completes 64B / 66B encoding for the TXD<63:0> data block after translation at the MII interface and adjusts the throughput rate according to TXC<7:0> at the MII interface. 256B / 257B Transcode is the transcoding from 256 bits to 257 bits. Scramble is the scrambling operation. Alignment insertion is the alignment mark insertion operation. Pre-FEC distribution is the 10-bit polling distribution operation before RS encoding. RS Encode is the RS(544,514,10) encoding operation. Distribution and Interleave is the symbol distribution and symbol interleaving with a 10-bit granularity after RS encoding. PMA is the next layer after the data stream undergoes the PCS layer operations. The data stream will perform the encoding operation of the second FEC codeword at the PMA layer, that is, the Inner-FEC Encode operation.

[0116] The receiving end receives a data stream from the communication medium and successively goes through 11 main steps at the receiving end, namely PMD, Inner-FEC Decode, PMA, Alignment lock and lane deskew, Lane reorder and de-interleave, RS Decode, Post-FEC interleave, Alignment removal, Descramble, Reverse Transcode, and Decode and rate matching. These 11 steps passed through by the receiving end are the inverse operations of the corresponding operation steps at the sending end. Inner-FEC Decode is the decoding operation of Inner-FEC. Alignment lock and lane deskew are the alignment mark locking and lane alignment operations. Lane reorder and de-interleave are the lane rearrangement and de-interleaving operations. RS Decode is the decoding operation of RS(544,514,10). Post-FEC interleave is the inverse operation of Pre-FEC distribution after RS decoding. Alignment removal is the operation of removing the alignment marks added at the encoding end. Descramble is the descrambling operation. Reverse Transcode is the inverse operation of 256B / 257B transcoding, which inversely converts 257 bits into 256 bits. Decode and rate matching is the inverse operation of 64B / 66B and the throughput rate matching operation.

[0117] It can be seen that for the Ethernet encoding method provided in the embodiment of the present application, through the concatenated coding scheme of the first FEC codeword and the second FEC codeword, the outer code of the concatenated code uses the original standard RS codeword, and the inner code of the concatenated code uses the second FEC codeword, that is, the Inner-FEC codeword. This encoding method can be compatible with the RS(544,514,10) encoding of 100GE, 200GE, and 400GE Ethernet, and increases the overhead (OH) of the entire FEC encoding through the encoding method of concatenating the RS(544,514,10) codeword with the Inner-FEC codeword. The OH of the system link FEC encoding increases, improving the error correction performance of the system, meeting both the performance indicators of the next-generation high-speed Ethernet and the delay requirements of the next-generation Ethernet, and with a small implementation cost.

[0118] The encoder component of this Inner-FEC codeword can be placed in the PCS layer or the PMA layer. When the encoder component of the Inner-FEC codeword is placed in the PMA layer, the RS coding in the PCS layer is decoupled from the Inner-FEC coding in the PMA layer, and the Inner-FEC coding in the PMA layer can be completed in the case of containing the bit errors inherent in the C2M optical-electric interface. When the encoder component of the Inner-FEC codeword is cascaded in the PCS layer, the cascaded coding scheme can also be completed.

[0119] Under the limitations of the device transmission rate and the system link budget, the second FEC codeword needs to meet some constraints. In addition, aiming to flexibly support and be compatible with most interface protocols of 100GE, 200GE, and 400GE in the IEEE 802.3 standard on the premise of meeting the requirements of the next-generation Ethernet technical indicators, the second FEC codeword also needs to meet some constraints. In the embodiments of this application, the code length of the second FEC codeword is represented by N, and the information bit length of the second FEC codeword is represented by K. Among them, N = x * n, K = x * k, where x, n, and k are positive integers, and x is the common factor of N and K. The code length of the first FEC codeword is represented by N1, and the information bit length of the first FEC codeword is represented by K1. In a possible implementation, the length of the FEC codeword may be relatively long. When limiting the construction parameters of the codeword, more fine-grained parameters of the codeword construction can be limited. For example, N = x * n, K = x * k. When limiting the parameters N and K of the second FEC codeword, n and k can be limited. The number of RS codewords used for RS-FEC coding in the PCS layer of Ethernet is represented by y. For example, Figure 2 As shown, the 100GE Ethernet RS-FEC coding uses 1 RS, that is, y = 1. For example, Figure 3 As shown, the 200GE Ethernet RS-FEC coding uses 2 RSs, that is, y = 2. For example, Figure 4 As shown, the 400GE Ethernet RS-FEC coding uses 2 RSs, that is, y = 2. The 800G Ethernet RS-FEC coding can use 4 RSs.

[0120] Among them, the meaning of using RS is to use the encoder component of RS.

[0121] Suppose the construction of the first FEC codeword, that is, the RS codeword, is (544, 514, 10). Among them, 514 is the information bit length K1 of the first FEC codeword, and 544 is the code length N1 of the first FEC codeword. K1 is 514 symbols, N1 is 544 symbols, and 10 means that one symbol is 10 bits. That is, N1 = 5440 bits, K1 = 5140 bits.

[0122] Some implementation forms related to the second FEC codeword will be described below.

[0123] The second FEC codeword meets any one or more of the following conditions 1 to 3.

[0124] Condition 1: The code length N and the information bit length K of the second FEC codeword satisfy the following formula (1).

[0125]

[0126] Among them, M1 is the throughput of the first encoded data, and M2 is the throughput of the second encoded data.

[0127] Formula (1) can have various deformed formulas. For example, For another example,

[0128] K is the information bit length, and N is the code length. It can be considered that K is the input before encoding, and N is the output after encoding. The K-bit information bit is encoded by the second FEC codeword to obtain the N-bit encoded data. M1 is the throughput of the first encoded data. The throughput of the first encoded data is used as the input of the second FEC codeword, and the output of the second FEC codeword cannot exceed M2.

[0129] M2 is a value determined based on one or more of the factors such as the transceiver rate, optical device bandwidth, and transmission performance limitations in Ethernet, and can be considered as the throughput of the second encoded data. M2 can also be considered as the output data throughput of the PMD layer.

[0130] The units of M1 and M2 can be Gbps. The values of M1 and M2 can be: M1 = 106.25 Gbps, M2 = 114 Gbps. That is, formula (1) becomes Among them, 106.25 Gbps is the throughput of the single-channel (lane) output data stream of the PCS layer.

[0131] Ethernet is based on a reference clock of 156.25 MHz, and uses a PLL for clock extraction and clock recovery. The lock and synchronization process of the PLL is adjusted with the reference clock multiplier (RCM) as the grid point. The data stream at the MAC layer will be transmitted to the PCS layer through the PCS physical channel with a bit width of 64 bits. The data stream first completes 64B / 66B encoding at the PCS layer, and then completes 256B / 257B transcoding based on 4 64B / 66B encodings. 20 transcoded data blocks are subjected to RS(544,514,10) FEC encoding. For each 100 Gbps data throughput rate input from the MAC layer to the PCS layer, after 64B / 66B encoding, 256B / 257B transcoding, and RS encoding are completed at the PCS layer, the single-lane output data throughput rate at the PCS layer is 106.25 Gbps. Limited by the bandwidth and transmission performance of the optical device, the output data throughput rate of the PMD layer cannot exceed M2 Gbps. Optionally, M2 = 114 Gbps.

[0132] Condition 2: K also satisfies the following conditions: is a positive integer, and N1 is the code length of the first FEC codeword.

[0133] Through Figure 5 It can be seen from the cascaded coding scheme of the embodiment that the output of the first FEC codeword is used as the input of the second FEC codeword. N1 is the code length of the first FEC codeword, which can be regarded as the output of the first FEC codeword. The second FEC codeword is input and encoded in units of K. Therefore, setting N2 as a positive integer multiple of K can equally divide the output of the first FEC codeword (i.e., the input of the second FEC codeword) into integer parts, each part being K, and each input does not require padding bits. This makes the cascaded coding scheme of the first FEC codeword and the second FEC codeword simpler and easier to implement, with lower complexity.

[0134] When N1 = 5440 bits, Condition 2 can be transformed into is a positive integer.

[0135] Substituting K = x*k, we get is a positive integer. When N1 = 5440 bits, it is transformed into is a positive integer.

[0136] The number of RS codewords used for RS-FEC encoding in the PCS layer of Ethernet is y. Among them, the output codeword length of one RS codeword is N1, so the output codeword length of y RS codewords is y * N1. In fact, the output of y RS codewords is the input of the second FEC codeword, that is, the input of the second FEC codeword is y * N1. If it is necessary to satisfy that the input of the second FEC codeword can be divided by K, in fact, it is necessary to satisfy that y * N1 can be divided by K, that is is a positive integer, or, is a positive integer.

[0137] If y is taken as 1, then is a positive integer. When y is taken as 1, that is, when one RS codeword is used for RS-FEC encoding in the PCS layer of Ethernet, if it can be satisfied that the output of the RS codeword (that is, the input of the second FEC codeword) can be divided by K, then when y is taken as 2 or any other integer value, the output of y RS codewords (that is, the input of the second FEC codeword) can be divided by K. Therefore, in the embodiments of the present application, y is taken as 1 to obtain Constraint Condition 2 is a positive integer.

[0138] Taking y as 1 means that the PCS layer divides data blocks in units of 1 RS(544,514,10). If the information bit length of Inner-FEC can divide 1 RS(544,514,10) codeword, then no matter how many RSs there are, they are all integer multiples of the length of 1 RS(544,514,10). Since the number of RSs in the PCS layer of 100GE is 1, and the number of RSs in the PCS layer of 200GE and 400GE is 2, for the PCS layer of Ethernet with a 100Gbps granularity, y is taken as 1 in the codeword constraint. For the next-generation 800G Ethernet, y can take y = 4.

[0139] Condition 3: N and K also satisfy the following conditions: L is a positive integer. For example, L = 4 * RCM.

[0140] When the architecture of Ethernet is Architecture 1, the encoder component of the second FEC codeword can be located in the PCS layer, and the second FEC codeword also needs to satisfy Condition 3.

[0141] For example, during the transmission of each 100Gbps data stream, each 100Gbps data stream will perform serial-to-parallel conversion by adjusting with a grid point of 156.25MHz RCM, and 4 data streams will be merged into one and transmitted in a serial manner in one transmission channel. Therefore, the second FEC codeword, that is, the Inner-FEC codeword, needs to satisfy: W is a positive integer. Or satisfy: W is a positive integer.

[0142] For the Ethernet coding scheme corresponding to the second FEC codeword that meets Condition 3, the implementation of Ethernet clock extraction and synchronization can be made simpler. When W is an integer, the PLL can be adjusted at integer grid points, which can complete the phase locking of the PLL more quickly, is easy to implement, and has a lower complexity.

[0143] Optionally, when the encoder component of the second FEC codeword is placed in the PMA layer, the second FEC codeword can meet at least one of Condition 1 and Condition 2, and it does not need to meet Condition 3 either. When the encoder component of the second FEC codeword is placed in the PCS layer, the second FEC codeword can meet at least one of Condition 1, Condition 2, and Condition 3.

[0144] In a possible design, the embodiment of the present application also sets Condition 4 for the second FEC codeword.

[0145] Condition 4: Or Or some other variants, for example, That is Or,

[0146] The following gives some possible specific second FEC codewords.

[0147] The structure of the second FEC codeword is (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, K is the number of bits included in the information bits, and m is the order of the Galois field where this FEC codeword is located.

[0148] When meeting Condition 4, The second FEC codeword includes any one of the following codewords, or a spatially coupled code constructed with any one of the following codewords as a subcode, or a multilevel coding (MLC) constructed with any one of the following codewords as a subcode:

[0149] (1) The codeword is Hamming(144, 136, 8). Where x = 8, N = 144, K = 136, OH = 5.88%.

[0150] (2) The codeword is Hamming(180, 170, 10). Where x = 10, N = 180, K = 170, OH = 5.88%.

[0151] (3) The codeword is extended Hamming (eHamming)(180, 170, 9). Where x = 10, N = 180, K = 170, OH = 5.88%.

[0152] (4) The codeword is a Double Extended Hamming (DE-Hamming) code (180, 170, 8). Among them, x = 10, N = 180, K = 170, and OH = 5.88%.

[0153] (5) The codeword is a BCH(360, 340, 10). Among them, x = 20, N = 360, K = 340, and OH = 5.88%.

[0154] (6) The codeword is a DE-BCH(360, 340, 9). Among them, x = 20, N = 360, K = 340, and OH = 5.88%.

[0155] (7) The codeword is a DE-BCH(576, 544, 10). Among them, x = 32, N = 576, K = 544, and OH = 5.88%.

[0156] (8) The codeword is a BCH(594, 561, 11). Among them, x = 33, N = 594, K = 561, and OH = 5.88%.

[0157] Among them, based on the determination of the codeword construction parameters N, K, and m, OH can be determined.

[0158] The codewords (1) to (8) meet Condition 1, Condition 2, Condition 3, and Condition 4.

[0159] Optionally, the second FEC codeword may further include any one of the following codewords, or a spatially coupled code constructed with any one of the following codewords as a subcode, or a multi-layer code constructed with any one of the following codewords as a subcode:

[0160] 1) Hamming(126, 119, 7). Among them, x = 7, OH = 5.88%, N = 126, K = 119.

[0161] 2) Hamming(127, 119, 8). Among them, x = 7, OH = 6.72%, N = 127, K = 119.

[0162] 3) Hamming(145, 136, 9). Among them, x = 8, OH = 6.62%, N = 144, K = 136.

[0163] 4) Hamming(179, 170, 9). Among them, x = 10, OH = 5.29%, N = 179, K = 170.

[0164] 5) eHamming(127, 119, 7). Among them, x = 7, OH = 6.72%, N = 127, K = 119.

[0165] 6) eHamming(145, 136, 8). Among them, x = 8, OH = 6.62%, N = 145, K = 136.

[0166] 7) eHamming(179, 170, 8). Among them, x = 10, OH = 5.29%, N = 179, K = 170.

[0167] 8) eHamming(181, 170, 10). Among them, x = 10, OH = 6.47%, N = 181, K = 170.

[0168] 9) BCH(290, 272, 9). Among them, x = 16, OH = 6.62%, N = 290, K = 272.

[0169] 10) BCH(358, 340, 9). Among them, x = 20, OH = 5.29%, N = 358, K = 340.

[0170] 11) BCH(574, 544, 10). Among them, x = 32, OH = 5.51%, N = 574, K = 544.

[0171] 12) Extended BCH code eBCH(291, 272, 9). Among them, x = 16, OH = 6.99%, N = 291, K = 272.

[0172] 13) eBCH(359, 340, 9). Among them, x = 20, OH = 5.59%, N = 359, K = 340.

[0173] 14) eBCH(361, 340, 10). Among them, x = 20, OH = 6.18%, N = 361, K = 340.

[0174] 15) eBCH(575, 544, 10). Among them, x = 32, OH = 5.70%, N = 575, K = 544.

[0175] 16) DE - BCH(362, 340, 10). Among them, x = 20, OH = 6.47%, N = 362, K = 340.

[0176] Codewords 1) to 16) meet Condition 1 and Condition 2.

[0177] The above-mentioned codewords are just examples, and there may be more eligible codewords in actual applications. Through the design of the second FEC codeword, the error correction performance is increased by improving the overhead (OH) of the system FEC encoding. If Ethernet continues to evolve to 1.6 Tbps, the concatenated coding scheme provided by the embodiments of the present application and the above-mentioned various constraints of the inner code under the concatenated scheme still apply.

[0178] Combined with Figure 2 , Figure 3 and Figure 4 the Ethernet layer architectures of 100GE, 200GE, and 400GE respectively given below, several possible examples of the Ethernet layer architecture of 800G (or 800GE) are given.

[0179] Example 1: As Figure 8 shown, the 800G Ethernet layer can be formed by juxtaposing and splicing two 400GE Ethernet layer architectures. From the 400GE Ethernet layer architecture shown in Figure 4 , it can be seen that the RS-FEC encoding of the 400GE Ethernet PCS layer uses 2 RS codewords. Thus, the RS-FEC encoding of the 800GE Ethernet PCS layer uses 4 RS codewords.

[0180] Example 2: It can also be formed by juxtaposing and splicing four 200GE Ethernet layer architectures to form the 800G Ethernet layer. From the 200GE Ethernet layer architecture shown in Figure 3 , it can be seen that the RS-FEC encoding of the 200GE Ethernet PCS layer uses 2 RS codewords, and the RS-FEC encoding of the 800GE Ethernet PCS layer uses 8 RS codewords.

[0181] Example 3: It can also be formed by juxtaposing and splicing eight 100GE Ethernet layer architectures to form the 800G Ethernet layer. From the 100GE Ethernet layer architecture shown in Figure 2 , it can be seen that the RS-FEC encoding of the 100GE Ethernet PCS layer uses 1 RS codeword. Thus, the RS-FEC encoding of the 800GE Ethernet PCS layer uses 8 RS codewords.

[0182] Example 4: It can also be formed by juxtaposing and splicing four 100GE Ethernet layer architectures and one 400GE Ethernet layer architecture to form the 800G Ethernet layer. From the 100GE Ethernet layer architecture shown in Figure 2 and the 400GE Ethernet layer architecture shown in Figure 4 , it can be seen that the RS-FEC encoding of the 100GE Ethernet PCS layer uses 1 RS codeword, and the RS-FEC encoding of the 400GE Ethernet PCS layer uses 2 RS codewords. Thus, the RS-FEC encoding of the 800GE Ethernet PCS layer uses 6 RS codewords.

[0183] Example 5: It is also possible to juxtapose and splice 2 architectures of 200GE Ethernet layer and 1 architecture of 400GE Ethernet layer to form an 800G Ethernet layer. From Figure 3 the 200GE Ethernet layer architecture shown in Figure 4 and the 400GE Ethernet layer architecture shown in

[0184] it can be seen that the RS-FEC encoding of the 200GE Ethernet PCS layer uses 2 RS codewords, and the RS-FEC encoding of the 400GE Ethernet PCS layer uses 2 RS codewords. In this way, the RS-FEC encoding of the 800GE Ethernet PCS layer uses 6 RS codewords. Figure 2 Example 6: It is also possible to juxtapose and splice 6 architectures of 100GE Ethernet layer and 1 architecture of 200GE Ethernet layer to form an 800G Ethernet layer. From Figure 4 the 100GE Ethernet layer architecture shown in

[0185] and the 400GE Ethernet layer architecture shown in

[0186] it can be seen that the RS-FEC encoding of the 100GE Ethernet PCS layer uses 1 RS codeword, and the RS-FEC encoding of the 400GE Ethernet PCS layer uses 2 RS codewords. In this way, the RS-FEC encoding of the 800GE Ethernet PCS layer uses 8 RS codewords.

[0187] It can be understood that with the evolution of the system, the solution of the embodiment of the present application can also be applicable to being composed of 1 architecture of 800G Ethernet layer, rather than being juxtaposed and spliced by multiple architectures.

[0188] Taking Example 1 as an example below, based on Figure 6a the Architecture 1 shown in Figure 7a and the process shown in

[0189] the 800G Ethernet PCS layer is composed of two 400GE PCS layers, and the encoder component of the second FEC codeword (Inner-FEC codeword) can be located in the PCS layer. The 800G data stream is divided into two 400G data streams in the PCS layer, and each 400G data stream is combined with Figure 7aSimilar to the data stream operation process of the 400GE PCS layer shown, after completing AM insertion, two-way RS encoding, multiplexing of two RS(544,514,10), and 10-bit symbol distribution, the data stream enters the encoder of the Inner-FEC codeword (abbreviated as Inner-FEC encoder) for encoding. The data stream is divided into data blocks with a length of K bits, and the data blocks after entering the Inner-FEC encoder are N bits. The Inner-FEC encoder encodes the data blocks of K bits into N bits. After completing the encoding by the Inner-FEC encoder, the data stream enters the PMA. The data stream entering the PMA layer will perform another multiplexing and 10-bit symbol distribution operation. Here, the multiplexing and 10-bit symbol distribution operations are 4 RS(544,514,10). Multiplexing and 10-bit symbol distribution in the PMA layer. Interleaving of 2-bit granules is implemented in the PMA layer. The interleaved data stream is distributed by bit to the PMD, and modulation and electro-optical conversion are completed on the PMD.

[0190] Taking Example 1 as an example below, based on Figure 6b the architecture two shown and Figure 7b the process shown, the processing process of the data stream will be further described in detail.

[0191] The 800G Ethernet PCS layer is composed of two 400GE PCS layers. The encoder component of the second FEC codeword can be located in the PMA layer. The 800G data stream is divided into two 400G data streams at the PCS layer. Each 400G data stream is the same as the 400GE PCS layer data stream operation process Figure 7b described. After completing AM insertion, two-way RS encoding, multiplexing of two RS(544,514,10), and 10-bit symbol distribution, the data stream enters the PMA. The data stream entering the PMA layer will perform another multiplexing and 10-bit symbol distribution operation. Here, the multiplexing and 10-bit symbol distribution operations are 4 RS(544,514,10). After the multiplexing and 10-bit symbol distribution operations in the PMA layer, the data stream enters the encoder of the Inner-FEC codeword (abbreviated as Inner-FEC encoder) for encoding. The data stream is divided into data blocks with a length of K bits, and the data blocks after entering the Inner-FEC encoder are N bits. The Inner-FEC encoder encodes the data blocks of K bits into N bits. After completing the encoding by the Inner-FEC encoder, the data stream performs interleaving of 2-bit granules in the PMA layer. The interleaved data stream is distributed by bit to the PMD, and modulation and electro-optical conversion are completed on the PMD.

[0192] In the embodiments of the present application, a cascaded coding scheme of a first FEC codeword and a second FEC codeword is adopted, where the first FEC codeword is the outer code and the second FEC codeword is the inner code. As Figure 5As described in the embodiments, the sending end first encodes the first information to be encoded using the first FEC codeword, and then encodes the encoded first encoded data using the second FEC codeword. Considering the sufficient mixing of the data input to the second FEC codeword, the embodiments of the present application provide a method to add an interleaving step in the concatenated coding scheme.

[0193] After adding the interleaving step, Figure 5 S501 in the embodiments can be described as: In S501, the sending end performs FEC encoding on the first information to be encoded using y first FEC codewords to obtain y groups of encoded data, where y is an even number greater than or equal to 2; the sending end performs first interleaving on the y groups of encoded data to obtain the first encoded data.

[0194] Alternatively, after adding the interleaving step, Figure 5 S501 and S502 in the embodiments can be described as: In S501, the sending end encodes the first information to be encoded using the first FEC codeword to obtain the first encoded data, including the following steps: The sending end performs FEC encoding on the first information to be encoded using y first FEC codewords to obtain y groups of first encoded data. In S502, the sending end encodes the first encoded data using the second FEC codeword, which actually includes the following steps: The sending end performs first interleaving on the y groups of first encoded data, and encodes the first encoded data after the first interleaving using the second FEC codeword.

[0195] The descriptions of S501 and S502 after adding interleaving are actually the same in the operation process, only the literal expressions are different.

[0196] Among them, the first interleaving conforms to an interleaving matrix with row and column numbers L and P respectively, that is, the sending end interleaves the y groups of encoded data using the interleaving matrix. The interleaving matrix can also be called an interleaving pattern, which means that during the interleaving of the y groups of encoded data, interleaving is performed according to the interleaving matrix or interleaving pattern. Among them, L and P are even numbers greater than or equal to 2, and P is the number of PMA channels. The PMA channel can be a real channel or a virtual channel. For example, the value of P can be a power of 2, such as P can take values of 4, 8, 16, 32.

[0197] After being encoded by the first FEC codeword, it needs to be output through the PMA channel and enter the encoder of the second FEC codeword for encoding. After adding the interleaving operation, the processes of encoding, interleaving, and output through the PMA channel can be implemented by the following several processes. The several processes have changed in the order of encoding, interleaving, and output through the PMA channel.

[0198] Process 1:

[0199] The transmitting end encodes the first information to be encoded using the first FEC codeword to obtain y groups of encoded data; the transmitting end performs first interleaving on the y groups of encoded data to obtain first encoded data; the transmitting end transmits the first encoded data through P PMA channels; the first encoded data transmitted through the P PMA channels is encoded using the second FEC codeword to obtain second encoded data.

[0200] Process Two:

[0201] The transmitting end encodes the first information to be encoded using the first FEC codeword to obtain y groups of encoded data; the transmitting end transmits the y groups of encoded data through P PMA channels; the y groups of encoded data transmitted through the P PMA channels are subjected to first interleaving to obtain first encoded data; the transmitting end encodes the first encoded data transmitted through the P PMA channels using the second FEC codeword to obtain second encoded data.

[0202] Process Three: The transmitting end encodes the first information to be encoded using the first FEC codeword to obtain y groups of encoded data; the transmitting end performs first interleaving on the y groups of encoded data to obtain first encoded data; the transmitting end encodes the first encoded data using the second FEC codeword to obtain second encoded data; the transmitting end transmits the second encoded data through P PMA channels and processes the second encoded data transmitted through the P PMA channels. The processed data can also be sent to the receiving end.

[0203] The interleaver for the first interleaving can be represented by π e The interleaver π e for the first interleaving can be an interleaver composed of a multiplexer (Mux) and a 10-bit symbol distribution.

[0204] The above Process One can be applicable to an Ethernet architecture where the encoder component of the second FEC codeword is located in the PMA layer and the interleaver π e for the first interleaving is located in the PCS layer. Process Two can be applicable to an Ethernet architecture where the encoder component of the second FEC codeword is located in the PMA layer and the interleaver π e for the first interleaving is located in the PMA layer. Process Three can be applicable to an Ethernet architecture where the encoder component of the second FEC codeword is located in the PCS layer and the interleaver π e for the first interleaving is located in the PCS layer.

[0205] The first interleaving in the above Process One and Process Three conforms to the following rules:

[0206] The row elements in a row of the interleaving matrix respectively correspond to the data polled from y groups of encoded data from left to right. For example, when y = 4, the group numbers of the 4 groups of encoded data are a, b, c, d respectively. The row elements in a row of the interleaving matrix respectively correspond to the data obtained from a, b, c, d, a, b, c, d...

[0207] Each row of the L rows follows the same polling rule; for example, the row elements in each row of the interleaving matrix respectively correspond to the data obtained from a, b, c, d, a, b, c, d... from left to right.

[0208] Alternatively, the polling rules for every consecutive y rows in the L rows are all different. Assume y = 4. For example, the polling rule for the first row in the L rows is: the row elements in the first row of the interleaving matrix respectively correspond to the data obtained from a, b, c, d, a, b, c, d... from left to right; the polling rule for the second row in the L rows is: the row elements in the second row of the interleaving matrix respectively correspond to the data obtained from d, c, b, a, d, c, b, a... from left to right; the polling rule for the third row in the L rows is: the row elements in the third row of the interleaving matrix respectively correspond to the data obtained from b, a, d, c, b, a, d, c... from left to right; the polling rule for the fourth row in the L rows is: the row elements in the fourth row of the interleaving matrix respectively correspond to the data obtained from c, d, a, b, c, d, a, b... from left to right. Then, the polling rules for the consecutive 4 rows from the first row to the fourth row in the L rows are all different. The polling rules for the fifth row to the eighth row in the L rows can be the same as those for the first row to the fourth row respectively. Then, the polling rules for every consecutive 4 rows in the L rows are all different. For example, the polling rules for the fifth row to the eighth row in the L rows are different, and for another example, the polling rules for the third row to the sixth row in the L rows are also different.

[0209] The first interleaving in the above process two conforms to the following rules:

[0210] The P PMA channels correspond to the serial numbers 0 to (P - 1). The P columns of the interleaving matrix respectively correspond one-to-one to the encoded data from the P PMA channels; the row elements with odd column serial numbers in a row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with serial numbers 0 to (P / 2 - 1); the row elements with even column serial numbers in a row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with serial numbers P / 2 to P. Of course, it can also be that the row elements with even column serial numbers in a row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with serial numbers 0 to (P / 2 - 1); the row elements with odd column serial numbers in a row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with serial numbers P / 2 to P.

[0211] To better understand the above processes 1, 2, and 3, and to better understand the interleaving rules that each process conforms to, the following takes Figure 8 Example 1 shown below, that is, the architecture of two 400GE Ethernet layers juxtaposed and spliced into an 800G Ethernet layer as an example, to describe the above processes 1-3 and the interleaving rules in detail.

[0212] Combined with the description of Process 1, as Figure 9 shown, the data processing process is described as follows.

[0213] Two 400Gbps data streams enter the alignment marker insertion (AM Insertion) module. After the alignment markers are inserted into the data streams, they are polled and distributed in 10-bit granularity (10-bit round robin distribution) to the information symbols of the RS codeword. At Figure 9There are four RS codewords, denoted as codeword A, codeword B, codeword C, and codeword D respectively. The low 0-bit information symbol (symbol to be encoded) of codeword A is denoted as mA0, the low 1-bit information symbol is denoted as mA1, the high 512-bit information symbol is denoted as mA512, and the high 513-bit information symbol is denoted as mA513. Similarly, the low 0-bit information symbol of codeword B is denoted as mB0, the low 1-bit information symbol is denoted as mB1, the high 512-bit information symbol is denoted as mB512, and the high 513-bit information symbol is denoted as mB513. The low 0-bit information symbol of codeword C is denoted as mC0, the low 1-bit information symbol is denoted as mC1, the high 512-bit information symbol is denoted as mC512, and the high 513-bit information symbol is denoted as mC513. The low 0-bit information symbol of codeword D is denoted as mD0, the low 1-bit information symbol is denoted as mD1, the high 512-bit information symbol is denoted as mD512, and the high 513-bit information symbol is denoted as mD513. After the information symbols of codewords A, B, C, and D are distributed, they are respectively sent into the corresponding encoders, namely RS encoder A, RS encoder B, RS encoder C, and RS encoder D. The low 0-bit after codeword A is encoded is denoted as cA0, and cA0 is also the parity symbol bit pA0, that is, cA0 = pA0. The low 1-bit after codeword A is encoded is denoted as cA1, and cA1 is also the parity symbol bit pA1, that is, cA1 = pA1. The low 29-bit after codeword A is encoded is denoted as cA29, and cA29 is also the parity symbol bit pA29, that is, cA29 = pA29. The low 30-bit after codeword A is encoded is denoted as cA30, and cA30 is also the information symbol bit mA0, that is, cA30 = mA0. The low 31-bit after codeword A is encoded is denoted as cA31, and cA31 is also the information symbol bit mA1, that is, cA31 = mA1. The high 543-bit after codeword A is encoded is denoted as cA543, and cA543 is also the information symbol bit mA513, that is, cA543 = mA513. The low 0-bit after codeword B is encoded is denoted as cB0, and cB0 is also the parity symbol bit pB0, that is, cB0 = pB0. The low 1-bit after codeword B is encoded is denoted as cB1, and cB1 is also the parity symbol bit pB1, that is, cB1 = pB1. The low 29-bit after codeword B is encoded is denoted as cB29, and cB29 is also the parity symbol bit pB29, that is, cB29 = pB29. The low 30-bit after codeword B is encoded is denoted as cB30, and cB30 is also the information symbol bit mB0, that is, cB30 = mB0. The low 31-bit after codeword B is encoded is denoted as cB31, and cB31 is also the information symbol bit mB1, that is, cB31 = mB1. The high 543-bit after codeword B is encoded is denoted as cB543, and cB543 is also the information symbol bit mB513, that is, cB543 = mB513. The low 0-bit after codeword C is encoded is denoted as cC0, and cC0 is also the parity symbol bit pC0, that is, cC0 = pC0.The least significant bit of the codeword C after encoding is denoted as cC1, and cC1 is also the parity symbol bit pC1, i.e., cC1 = pC1. The least significant 29 bits of the codeword C after encoding are denoted as cC29, and cC29 is also the parity symbol bit pC29, i.e., cC29 = pC29. The least significant 30 bits of the codeword C after encoding are denoted as cC30, and cC30 is also the information symbol bit mC0, i.e., cC30 = mC0. The least significant 31 bits of the codeword C after encoding are denoted as cC31, and cC31 is also the information symbol bit mC1, i.e., cC31 = mC1. The most significant 543 bits of the codeword C after encoding are denoted as cC543, and cC543 is also the information symbol bit mC513, i.e., cC543 = mC513. The least significant bit of the codeword D after encoding is denoted as cD0, and cD0 is also the parity symbol bit pD0, i.e., cD0 = pD0. The least significant bit of the codeword D after encoding is denoted as cD1, and cD1 is also the parity symbol bit pD1, i.e., cD1 = pD1. The least significant 29 bits of the codeword D after encoding are denoted as cD29, and cD29 is also the parity symbol bit pD29, i.e., cD29 = pD29. The least significant 30 bits of the codeword D after encoding are denoted as cD30, and cD30 is also the information symbol bit mD0, i.e., cD30 = mD0. The least significant 31 bits of the codeword D after encoding are denoted as cD31, and cD31 is also the information symbol bit mD1, i.e., cD31 = mD1. The most significant 543 bits of the codeword D after encoding are denoted as cD543, and cD543 is also the information symbol bit mD513, i.e., cD543 = mD513. The encoding processes of the codewords A, B, C, and D can correspond to. Figure 5 In the embodiment, y pieces of information to be encoded are encoded using the first FEC codeword to obtain y groups of encoded data. The value of y is 4.

[0214] At the PCS layer, an interleaver π is used for the 4 groups of encoded data e After interleaving, through the optical-electric interface C2M or through P PMA channels, the data stream completes the concatenated encoding of the second FEC codeword at the PMA layer. The encoded codeword is the second FEC codeword, i.e., the Inner-FEC codeword.

[0215] Figure 9 Under the shown architecture, there are P PMA channels (PMALane), P = 32, that is, 32 columns of PMA Lane. j represents the number of symbols of each RS in each row of each PMAlane, and L represents the number of rows of the PMA Lane. Among them, cA<543 - 8L - j> represents Figure 9 the 543 - 8L - j-th symbol bit of the left RS codeword A, cB<543 - 8L - j> represents Figure 9 the 543 - 8L - j-th symbol bit of the left RS codeword B, cC<543 - 8L - j> represents Figure 9The 543 - 8L - j - th symbol position of the RS codeword C on the right, cD<543 - 8L - j> represents Figure 9 The 543 - 8L - j - th symbol position of the RS codeword D on the right. tx_out represents the output data stream of the interleaver in symbol granularity. tx_out<32L + 4j> represents the 32L + 4j - th symbol of the interleaver output data stream, tx_out<32L + 4j + 1> represents the 32L + 4j + 1 - th symbol of the interleaver output data stream, tx_out<32L + 4j + 2> represents the 32L + 4j + 2 - th symbol of the interleaver output data stream, and tx_out<32L + 4j + 3> represents the 32L + 4 + 2j + 3 - th symbol of the interleaver output data stream.

[0216] Interleaver π e The interleaving rules adopted can be, for example, the following interleaving rule one, interleaving rule two, interleaving rule three, and interleaving rule four.

[0217] Interleaving rule one is: For the 32 symbols in the first row on 32 PMA channels, they are sequentially polled and distributed by 4 RS codewords A, B, C, D; for the 32 symbols in the second row, they are sequentially polled and distributed by 4 RS codewords D, C, B, A; for the 32 symbols in the third row, they are sequentially polled and distributed by 4 RS codewords B, A, D, C; for the 32 symbols in the fourth row, they are sequentially polled and distributed by 4 RS codewords C, D, A, B. After that, each subsequent row is distributed in 10 - bit granularity according to this rule.

[0218] Interleaver π e The interleaving rule one of can be expressed in pseudo - code form as:

[0219] For all k = 0 to 67

[0220] For all j = 0 to 7

[0221] if(k % 4 == 0)

[0222] tx_out<32k + 4j> = cA<543 - 8k - j>

[0223] tx_out<32k + 4j + 1> = cB<543 - 8k - j>

[0224] tx_out<32k + 4j + 2> = cC<543 - 8k - j>

[0225] tx_out<32k + 4j + 3> = cD<543 - 8k - j>

[0226] else if(k % 4 == 1)

[0227] tx_out<32k + 4j> = cD<543 - 8k - j>

[0228] tx_out<32k + 4j + 1> = cC<543 - 8k - j>

[0229] tx_out<32k + 4j + 2> = cB<543 - 8k - j>

[0230] tx_out<32k + 4j + 3> = cA<543 - 8k - j>

[0231] else if (k % 4 == 2)

[0232] tx_out<32k + 4j> = cB<543 - 8k - j>

[0233] tx_out<32k + 4j + 1> = cA<543 - 8k - j>

[0234] tx_out<32k + 4j + 2> = cD<543 - 8k - j>

[0235] tx_out<32k + 4j + 3> = cC<543 - 8k - j>

[0236] else

[0237] tx_out<32k + 4j> = cC<543 - 8k - j>

[0238] tx_out<32k + 4j + 1> = cD<543 - 8k - j>

[0239] tx_out<32k + 4j + 2> = cA<543 - 8k - j>

[0240] tx_out<32k + 4j + 3> = cB<543 - 8k - j>

[0241] The interleaving rule two is as follows:

[0242] The 32 symbols in the first row on 32 PMA channels are sequentially polled and distributed by 4 RS codewords A, B, C, D; the 32 symbols in the second row are sequentially polled and distributed by 4 RS codewords B, A, D, C; the 32 symbols in the third row are sequentially polled and distributed by 4 RS codewords C, D, A, B; the 32 symbols in the fourth row are sequentially polled and distributed by 4 RS codewords D, C, B, A. Each subsequent row is distributed in 10 - bit granularity according to this rule. The interleaving rule of the interleaver can be expressed in pseudo - code form as:

[0243] For all k = 0 to 67

[0244] For all j from 0 to 7

[0245] if (k % 4 == 0)

[0246] tx_out<32k + 4j> = cA<543 - 8k - j>

[0247] tx_out<32k + 4j + 1> = cB<543 - 8k - j>

[0248] tx_out<32k + 4j + 2> = cC<543 - 8k - j>

[0249] tx_out<32k + 4j + 3> = cD<543 - 8k - j>

[0250] else if (k % 4 == 1)

[0251] tx_out<32k + 4j> = cB<543 - 8k - j>

[0252] tx_out<32k + 4j + 1> = cA<543 - 8k - j>

[0253] tx_out<32k + 4j + 2> = cD<543 - 8k - j>

[0254] tx_out<32k + 4j + 3> = cC<543 - 8k - j>

[0255] else if (k % 4 == 2)

[0256] tx_out<32k + 4j> = cC<543 - 8k - j>

[0257] tx_out<32k + 4j + 1> = cD<543 - 8k - j>

[0258] tx_out<32k + 4j + 2> = cA<543 - 8k - j>

[0259] tx_out<32k + 4j + 3> = cB<543 - 8k - j>

[0260] else

[0261] tx_out<32k + 4j> = cD<543 - 8k - j>

[0262] tx_out<32k + 4j + 1> = cC<543 - 8k - j>

[0263] tx_out<32k + 4j + 2> = cB<543 - 8k - j>

[0264] tx_out<32k + 4j + 3> = cA<543 - 8k - j>

[0265] The third interleaving rule is as follows: For the 32 symbols in the first row on 32 PMA channels, they are sequentially polled and distributed by 4 RS codewords A, B, C, and D; for the 32 symbols in the second row, they are sequentially polled and distributed by 4 RS codewords C, D, A, and B; for the 32 symbols in the third row, they are sequentially polled and distributed by 4 RS codewords B, A, D, and C; for the 32 symbols in the fourth row, they are sequentially polled and distributed by 4 RS codewords D, C, B, and A. After that, each subsequent row is distributed in 10-bit granularity according to this rule.

[0266] The third interleaving rule of the interleaver can be expressed in pseudocode form as:

[0267] For all k = 0 to 67

[0268] For all j = 0 to 7

[0269] if (k % 4 == 0)

[0270] tx_out<32k + 4j> = cA<543 - 8k - j>

[0271] tx_out<32k + 4j + 1> = cB<543 - 8k - j>

[0272] tx_out<32k + 4j + 2> = cC<543 - 8k - j>

[0273] tx_out<32k + 4j + 3> = cD<543 - 8k - j>

[0274] else if (k % 4 == 1)

[0275] tx_out<32k + 4j> = cC<543 - 8k - j>

[0276] tx_out<32k + 4j + 1> = cD<543 - 8k - j>

[0277] tx_out<32k + 4j + 2> = cA<543 - 8k - j>

[0278] tx_out<32k + 4j + 3> = cB<543 - 8k - j>

[0279] else if (k % 4 == 2)

[0280] tx_out<32k + 4j> = cB<543 - 8k - j>

[0281] tx_out<32k + 4j + 1> = cA<543 - 8k - j>

[0282] tx_out<32k + 4j + 2> = cD<543 - 8k - j>

[0283] tx_out<32k + 4j + 3> = cC<543 - 8k - j>

[0284] else

[0285] tx_out<32k + 4j> = cD<543 - 8k - j>

[0286] tx_out<32k + 4j + 1> = cC<543 - 8k - j>

[0287] tx_out<32k + 4j + 2> = cB<543 - 8k - j>

[0288] tx_out<32k + 4j + 3> = cA<543 - 8k - j>

[0289] The fourth interleaving rule is as follows: For the 32 symbols in the first row on 32 PMA channels, they are sequentially polled and distributed by 4 RS codewords A, B, C, and D; for the 32 symbols in the second row, they are sequentially polled and distributed by 4 RS codewords D, C, B, and A; for the 32 symbols in the third row, they are sequentially polled and distributed by 4 RS codewords A, B, C, and D; for the 32 symbols in the fourth row, they are sequentially polled and distributed by 4 RS codewords D, C, B, and A. After that, each subsequent row is distributed in 10-bit granularity according to this rule.

[0290] The fourth interleaving rule of the interleaver can be expressed in pseudocode as:

[0291] For all k = 0 to 67

[0292] For all j = 0 to 7

[0293] if even(k)

[0294] tx_out<32k + 4j> = cA<543 - 8k - j>

[0295] tx_out<32k + 4j + 1> = cB<543 - 8k - j>

[0296] tx_out<32k + 4j + 2> = cC<543 - 8k - j>

[0297] tx_out<32k + 4j + 3> = cD<543 - 8k - j>

[0298] else

[0299] tx_out<32k + 4j> = cD<543 - 8k - j>

[0300] tx_out<32k + 4j + 1> = cC<543 - 8k - j>

[0301] tx_out<32k + 4j + 2> = cB<543 - 8k - j>

[0302] tx_out<32k + 4j + 3> = cA<543 - 8k - j>

[0303] The above interleaver π e After the interleaving is completed, the data stream is sent to the Inner-FEC module through the PMA channel for inner code encoding operation. After the inner code encoding is completed, the original data interleaving of the PMA is directly multiplexed for π O interleaving. Finally, the data is modulated and photoelectrically converted at the PMD and sent to the communication medium through the MDI interface to complete the data transmission.

[0304] In interleaving rules one to four, during the symbol distribution process of each row, codeword A and codeword B are always adjacent, and codeword C and codeword D are always adjacent. Therefore, there is no need to distinguish adjacent codeword A and codeword B, and there is no need to distinguish adjacent codeword C and codeword D, reducing the complexity. Making π e The interleaving depth is increased from the symbol distribution of 2 RSs to the symbol distribution of 4 RSs, and the distribution pattern is changed from the original parity distribution pattern in the standard to the new distribution pattern. However, it is necessary that the symbols of each RS codeword in the PCS layer are adjacent, that is, to ensure Figure 9 the symbols of RS codewords A and B in are adjacent, and the symbols of C and D are adjacent. Such an interleaver design can identify the boundaries of symbols (symbols), and the 10-bits granularity exactly matches the size of the RS symbols. Such an interleaver enables different RS symbols to be more randomly and evenly distributed to the Inner-FEC codewords, can be compatible with the number of RSs in each PCS layer, does not need to distinguish the symbols of the RS codewords from the data stream of the PCS layer, can reduce the operation of identifying the RS symbol boundaries, and can improve the system's ability to resist Burst Error.

[0305] Combined with the description of process two, as Figure 10 shown, the data processing process is as described below.

[0306] Two 400Gbps data streams enter the alignment marker insertion (AM Insertion) module. After inserting the alignment markers, the data streams are distributed in a 10-bit granularity round robin to the information symbols of the RS codewords (RS codeword). In Figure 10 There are four RS codewords, denoted as codeword A, codeword B, codeword C, and codeword D respectively. The encoding methods of codeword A, codeword B, codeword C, and codeword D can refer to Figure 9 the relevant descriptions, which will not be elaborated here.

[0307] The encoding processes of codeword A, codeword B, codeword C, and codeword D can correspond to Figure 5 In the embodiment, the first FEC codeword is used to encode y information to be encoded, and y groups of encoded data are obtained. The value of y is 4.

[0308] The two groups of encoded data after encoding codeword A and codeword B are interleaved through a Mux and an interleaver of 10-bit symbol distribution, which can be denoted as the third interleaving. The two groups of encoded data after encoding codeword C and codeword D are interleaved through a Mux and an interleaver of 10-bit symbol distribution for the third interleaving.

[0309] The 4 groups of encoded data respectively interleaved through a Mux and an interleaver of 10-bit symbol distribution are input into P PMA channels (PMA Lane), where P = 32, that is, 32 columns of PMA Lane. j represents the number of symbols of each RS in one row of each PMA lane, and L represents the number of rows of the PMA Lane. Among them, cA<543 - 8L - j> represents Figure 10 the 543 - 8L - j-th symbol bit of the left RS codeword A, cB<543 - 8L - j> represents Figure 10 the 543 - 8L - j-th symbol bit of the left RS codeword B, cC<543 - 8L - j> represents Figure 10 the 543 - 8L - j-th symbol bit of the right RS codeword C, cD<543 - 8L - j> represents Figure 10 the 543 - 8L - j-th symbol bit of the right RS codeword D.

[0310] The data stream output from the 32 PMA channels enters the interleaver π e for interleaving. The interleaver π e The data stream after interleaving completes the concatenated encoding of the second FEC codeword at the PMA layer. The encoded codeword is the second FEC codeword, that is, the Inner-FEC codeword.

[0311] The interleaver πe It is equivalent to performing secondary Mux and 10-bit symbol distribution on the data output from 32 PMA channels, and completing a more sufficient interleaving of the data streams of two 400G PCS layers at the PMA layer. The data stream is transmitted to the PMA layer through the optoelectronic interface C2M. Therefore, the bit errors caused at the optoelectronic interface are at the interleaver π e Before this, it is also impossible to know which symbols belong to which RS codewords unless deinterleaving is completed at the PMA layer, which will require a relatively high cost. Therefore, if the interleaver π e is placed at the PMA layer and the interleaver π is designed in blind mode e , the interleaver design only needs to be related to the PMA Lane. The interleaver π e The interleaving rule adopted can be, for example, the following interleaving rule five.

[0312] The interleaving rule five is as follows:

[0313] For 32 PMA Lanes, the symbol output from the j-th PMA Lane from left to right is S <j>, j = 1, 2, …, 31, 32. The symbol size is 10 bits. tx_out represents the output data stream of the interleaver in symbol granularity.

[0314] The 32 PMA channels correspond to the sequence numbers from 0 to (32 - 1). The 32 columns of the interleaving matrix respectively correspond one-to-one with the encoded data from 32 PMA channels; among the row elements with odd column numbers in a row of the interleaving matrix, they respectively correspond to the encoded data of the PMA channels with sequence numbers from 0 to (32 / 2 - 1); among the row elements with even column numbers in a row of the interleaving matrix, they respectively correspond to the encoded data of the PMA channels with sequence numbers from 32 / 2 to 32. Of course, it can also be that among the row elements with even column numbers in a row of the interleaving matrix, they respectively correspond to the encoded data of the PMA channels with sequence numbers from 0 to (32 / 2 - 1); among the row elements with odd column numbers in a row of the interleaving matrix, they respectively correspond to the encoded data of the PMA channels with sequence numbers from 32 / 2 to 32.

[0315] Interleaver π e The interleaving rule five of it can be expressed in the form of pseudocode as:

[0316] For all k = 0 to 67

[0317] For all j = 0 to 16

[0318] If even(j)

[0319] tx_out<32k + j> = S <j>

[0320] else

[0321] tx_out<32k+j>=S<16+j>

[0322] This interleaving method design does not need to identify symbol boundaries, so that the PMA layer does not need to know the format of the PCS layer data frame, and directly multiplexes and distributes the 10-bit granularity on the data stream received by the PMA layer. The 10-bit granularity just matches the size of the symbol of the second FEC codeword, improves the system's ability to resist burst errors, and is simple to implement.

[0323] Combined with the description of process three, such as Figure 11 As shown, the data processing flow is as follows.

[0324] Figure 11 The process can be referred to Figure 9 The process shown is different in that Figure 9 When the four groups of coded data are interleaved using e After interleaving, the first coded data obtained is transmitted through 32 PMA channels, and the first coded data transmitted through the 32 PMA channels is encoded using a second FEC codeword to obtain second coded data. Figure 11 It is to use interleaver π on 4 sets of coded data. e After interleaving, first coded data is obtained, the first coded data is encoded using a second FEC codeword to obtain second coded data, the second coded data is transmitted through 32 PMA channels, and the second coded data transmitted through the 32 PMA channels is processed.

[0325] visible Figure 11 and Figure 9 The difference is the location of the second FEC encoding. Other than that, the details of each step can be referred to Figure 9 The interleaving rules can also be referred to in Figure 9 The description will not be repeated here.

[0326] Understandably, Figures 9 - 11 So Figure 8 Example 1 is taken as an example, that is, the architecture of two 400GE Ethernet layers is spliced ​​in parallel to form an 800G Ethernet layer. When the Ethernet architecture is composed of other methods, the data processing process is similar. The following takes Example 2 as an example, that is, the architecture of four 200GE Ethernet layers is spliced ​​in parallel to form an 800G Ethernet layer, to describe the data processing process.

[0327] Four 200Gbps data streams enter the alignment marker insertion (AM Insertion) module. After the alignment markers are inserted into the data streams, they are distributed in a 10-bit granularity round robin manner to a 10-bit granularity round robin distribution. There will be eight RS codewords, denoted as codeword A, codeword B, codeword C, codeword D, codeword E, codeword F, codeword G, and codeword H respectively. The RS encoding method for each codeword can refer to Figure 9 The description related to the embodiment.

[0328] At the PCS layer, an interleaver π is used for the 4 groups of encoded data e After interleaving, the data stream is cascaded and encoded at the PMA layer through the optoelectronic interface C2M. The encoded codeword is Inner-FEC.

[0329] There are P PMA channels (PMA Lanes), P = 32, that is, 32 columns of PMA Lanes. j represents the number of symbols of each RS in one row of each PMA lane, and L represents the number of rows of the PMA Lanes.

[0330] where cA<543 - 4L - j> represents the (543 - 4L - j)-th symbol bit of RS codeword A, cB<543 - 4L - j> represents the (543 - 4L - j)-th symbol bit of RS codeword B, cC<543 - 4L - j> represents the (543 - 4L - j)-th symbol bit of RS codeword C, cD<543 - 4L - j> represents the (543 - 4L - j)-th symbol bit of RS codeword D, cE<543 - 4L - j> represents the (543 - 4L - j)-th symbol bit of RS codeword E, cF<543 - 4L - j> represents the (543 - 4L - j)-th symbol bit of RS codeword F, cG<543 - 4L - j> represents the (543 - 4L - j)-th symbol bit of RS codeword G, cH<543 - 4L - j> represents the (543 - 4L - j)-th symbol bit of RS codeword H. tx_out represents the output data stream of the interleaver in symbol granularity. tx_out<32L + 8j> represents the (32L + 8j)-th symbol of the interleaver output data stream, tx_out<32L + 8j + 1> represents the (32L + 8j + 1)-th symbol of the interleaver output data stream, tx_out<32L + 8j + 2> represents the (32L + 8j + 2)-th symbol of the interleaver output data stream, tx_out<32L + 8j + 3> represents the (32k + 8j + 3)-th symbol of the interleaver output data stream, tx_out<32k + 8j + 4> represents the (32L + 8j + 4)-th symbol of the interleaver output data stream, tx_out<32L + 8j + 5> represents the (32L + 8j + 5)-th symbol of the interleaver output data stream, tx_out<32L + 8j + 6> represents the (32L + 8j + 6)-th symbol of the interleaver output data stream, tx_out<32L + 8j + 7> represents the (32L + 8j + 7)-th symbol of the interleaver output data stream.

[0331] Interleaver π e The interleaving rule adopted can be interleaving rule six.

[0332] The interleaving rule six is as follows: For the 32 symbols in the first row on 32 PMA channels, they are sequentially polled and distributed by 8 RS codewords A, B, C, D, E, F, G, H; for the 32 symbols in the second row, they are sequentially polled and distributed by 8 RS codewords C, D, E, F, G, H, A, B; for the 32 symbols in the third row, they are sequentially polled and distributed by 8 RS codewords E, F, G, H, A, B, C, D; for the 32 symbols in the fourth row, they are sequentially polled and distributed by 8 RS codewords G, H, A, B, C, D, E, F; for the 32 symbols in the fifth row, they are sequentially polled and distributed by 8 RS codewords H, G, F, E, D, C, B, A; for the 32 symbols in the sixth row, they are sequentially polled and distributed by 8 RS codewords B, A, H, G, F, E, D, C; for the 32 symbols in the seventh row, they are sequentially polled and distributed by 8 RS codewords D, C, B, A, H, G, F, E; for the 32 symbols in the eighth row, they are sequentially polled and distributed by 8 RS codewords F, E, D, C, B, A, H, G. For each subsequent row, the distribution is performed in 10-bit granularity according to this rule. In fact, as long as it is ensured that the polling rules for every consecutive 8 rows are different, the polling rule of rule six is just an example.

[0333] Interleaver π e The interleaving rule six of it can be expressed in pseudo-code form as:

[0334] For all k = 0 to 67

[0335] For all j = 0 to 4

[0336] if(k % 8 == 0)

[0337] tx_out<32k + 8j> = cA<543 - 4k - j>

[0338] tx_out<32k + 8j + 1> = cB<543 - 4k - j>

[0339] tx_out<32k + 8j + 2> = cC<543 - 4k - j>

[0340] tx_out<32k + 8j + 3> = cD<543 - 4k - j>

[0341] tx_out<32k + 8j + 4> = cE<543 - 4k - j>

[0342] tx_out<32k + 8j + 5> = cF<543 - 4k - j>

[0343] tx_out<32k + 8j + 6> = cG<543 - 4k - j>

[0344] tx_out<32k + 8j + 7> = cH<543 - 4k - j> else if (k % 8 == 1)

[0345] tx_out<32k + 8j> = cC<543 - 4k - j> tx_out<32k + 8j + 1> = cD<543 - 4k - j> tx_out<32k + 8j + 2> = cE<543 - 4k - j> tx_out<32k + 8j + 3> = cF<543 - 4k - j> tx_out<32k + 8j + 4> = cG<543 - 4k - j> tx_out<32k + 8j + 5> = cH<543 - 4k - j> tx_out<32k + 8j + 6> = cA<543 - 4k - j> tx_out<32k + 8j + 7> = cB<543 - 4k - j> else if (k % 8 == 2)

[0346] tx_out<32k + 8j> = cE<543 - 4k - j> tx_out<32k + 8j + 1> = cF<543 - 4k - j> tx_out<32k + 8j + 2> = cG<543 - 4k - j> tx_out<32k + 8j + 3> = cH<543 - 4k - j> tx_out<32k + 8j + 4> = cA<543 - 4k - j> tx_out<32k + 8j + 5> = cB<543 - 4k - j> tx_out<32k + 8j + 6> = cC<543 - 4k - j> tx_out<32k + 8j + 7> = cD<543 - 4k - j> else if (k % 8 == 3)

[0347] tx_out<32k + 8j> = cG<543 - 4k - j> tx_out<32k + 8j + 1> = cH<543 - 4k - j> tx_out<32k + 8j + 2> = cA<543 - 4k - j> tx_out<32k + 8j + 3> = cB<543 - 4k - j> tx_out<32k + 8j + 4> = cC<543 - 4k - j> tx_out<32k + 8j + 5> = cD<543 - 4k - j> tx_out<32k + 8j + 6> = cE<543 - 4k - j> tx_out<32k + 8j + 7> = cF<543 - 4k - j> if (k % 8 == 4)

[0348] tx_out<32k + 8j> = cH<543 - 4k - j> tx_out<32k + 8j + 1> = cG<543 - 4k - j> tx_out<32k + 8j + 2> = cF<543 - 4k - j> tx_out<32k + 8j + 3> = cE<543 - 4k - j> tx_out<32k + 8j + 4> = cD<543 - 4k - j> tx_out<32k + 8j + 5> = cC<543 - 4k - j> tx_out<32k + 8j + 6> = cB<543 - 4k - j> tx_out<32k + 8j + 7> = cA<543 - 4k - j> else if (k % 8 == 5)

[0349] tx_out<32k + 8j> = cB<543 - 4k - j> tx_out<32k + 8j + 1> = cA<543 - 4k - j> tx_out<32k + 8j + 2> = cH<543 - 4k - j> tx_out<32k + 8j + 3> = cG<543 - 4k - j> tx_out<32k + 8j + 4> = cF<543 - 4k - j> tx_out<32k + 8j + 5> = cE<543 - 4k - j> tx_out<32k + 8j + 6> = cD<543 - 4k - j>

[0350] tx_out<32k + 8j + 7> = cC<543 - 4k - j>

[0351] else if (k % 8 == 6)

[0352] tx_out<32k + 8j> = cD<543 - 4k - j>

[0353] tx_out<32k + 8j + 1> = cC<543 - 4k - j>

[0354] tx_out<32k + 8j + 2> = cB<543 - 4k - j>

[0355] tx_out<32k + 8j + 3> = cA<543 - 4k - j>

[0356] tx_out<32k + 8j + 4> = cH<543 - 4k - j>

[0357] tx_out<32k + 8j + 5> = cG<543 - 4k - j>

[0358] tx_out<32k + 8j + 6> = cF<543 - 4k - j>

[0359] tx_out<32k + 8j + 7> = cE<543 - 4k - j>

[0360] else if (k % 8 == 7)

[0361] tx_out<32k + 8j> = cF<543 - 4k - j>

[0362] tx_out<32k + 8j + 1> = cE<543 - 4k - j>

[0363] tx_out<32k + 8j + 2> = cD<543 - 4k - j>

[0364] tx_out<32k + 8j + 3> = cC<543 - 4k - j>

[0365] tx_out<32k + 8j + 4> = cB<543 - 4k - j>

[0366] tx_out<32k + 8j + 5> = cA<543 - 4k - j>

[0367] tx_out<32k + 8j + 6> = cH<543 - 4k - j>

[0368] tx_out<32k + 8j + 7> = cG<543 - 4k - j>

[0369] The symbol distribution method can make π e The interleaving depth is increased from the symbol distribution of 2 RSs to the symbol distribution of 8 RSs, and the distribution pattern is changed from the original parity distribution pattern in the standard to the new distribution pattern. However, it is required that the symbols of each PCS layer's RS codeword are adjacent, that is, to ensure that the symbols of RS codewords A and B are adjacent, the symbols of C and D are adjacent, the symbols of E and F are adjacent, and the symbols of G and H are adjacent.

[0370] After the above interleaving is completed, the data stream is sent to the Inner-FEC module through the PMA channel for inner code encoding operation. After the inner code encoding is completed, the original data interleaving of PMA is directly multiplexed for π O interleaving. Finally, the data is modulated and optoelectronically converted in PMD and sent to the communication medium through the MDI interface to complete data transmission.

[0371] Based on the above description, in a possible design, the flow diagram of the encoding method of the Ethernet provided by the embodiments of the present application can be as Figure 12 shown. The main processes include that the data stream to be encoded is encoded by the RS encoder, interleaved by the interleaver π e interleaved, encoded by the Inner-FEC encoder, and interleaved by the interleaver π o interleaved. π e The original polling distribution can be adopted, or other distribution or interleaving methods can be used. Of course, the order between each step can be changed. For details, reference can be made to the descriptions of each embodiment above. Figure 12 It is a schematic diagram of one way.

[0372] In summary, due to the limited error correction performance of RS codewords in 100GE, 200GE, and 400GE Ethernet technologies, even if the 10-bit RS symbol distribution technology of 200GE and 400GE Ethernet is applied to the next-generation Ethernet coding scheme, this symbol distribution is essentially a weak interleaver, and the performance still cannot meet the requirements of the next-generation Ethernet BER performance technical indicators. It is necessary to adopt the method of increasing the OH of the system to improve the error correction performance. Through designing a concatenated Inner-FEC codeword in the embodiments of the present application, on the basis of being compatible with most protocol layers of IEEE 802.3bj and IEEE 802.3bs, the OH of the system is increased. Through the joint optimization design of the architecture and coding, the PCS layer coding and the PMA layer coding are decoupled, and each layer of coding is responsible for different error types and error distributions, having an optimal coding gain as a whole in the system, and the implementation complexity is the lowest, and the latency and resource consumption levels are both an optimal solution.

[0373] In addition, the method provided in the embodiments of the present application solves the problem that the error code type and error distribution do not match the error correction efficiency of the designed Inner-FEC codeword. The interleaving between the first FEC codeword (RS codeword) and the second FEC codeword (Inner-FEC) is to gather the remaining error codes after Inner-FEC into a RS symbol (10-bit), so that the Hamming distance at the symbol level between RS and Inner-FEC is minimized, improving the error correction efficiency of RS; and the interleaving between the channel and Inner-FEC is to reduce the Burst Error of the channel to a certain extent, so that the length of the Burst Error is within the correctable range of Inner-FEC, improving the error correction efficiency of Inner-FEC.

[0374] Therefore, the solution provided in the embodiments of the present application can achieve an overall optimal effect in terms of various technical indicators such as latency, computational complexity, resource consumption, and system compatibility on the premise of meeting the next-generation Ethernet performance indicators.

[0375] Based on the same technical concept as the above-mentioned Ethernet coding method, such as Figure 13 As shown in the figure, an encoding device 1300 for Ethernet is further provided in an embodiment of the present application. The device 1300 has the function of implementing the above-mentioned Ethernet encoding method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. In one design, the device 1300 may include an acquisition module 1301 and a processing module 1302.

[0376] Exemplarily:

[0377] The acquisition module 1301 is used to acquire the first information to be encoded; the processing module 1302 is used to encode the first information to be encoded with the first forward error correction code FEC codeword to obtain the first encoded data, and the first forward error correction code FEC codeword is the Reed-Solomon forward error correction code RS-FEC; the processing module 1302 is further used to encode the first encoded data with the second FEC codeword to obtain the second encoded data; the code length N and the information bit length K of the second FEC codeword meet the following formula: where M1 is the throughput rate of the first encoded data and M2 is the throughput rate of the second encoded data.

[0378] Optionally, when encoding the first information to be encoded with the first FEC codeword to obtain the first encoded data, the processing module 1302 is used to: encode the first information to be encoded with y first FEC codewords to obtain y groups of encoded data, where y is an even number greater than or equal to 2; perform a first interleaving on the y groups of encoded data to obtain the first encoded data; the first interleaving conforms to an interleaving matrix with row and column numbers L and P respectively, and L and P are even numbers greater than or equal to 2, and P is the number of physical medium attachment sublayer PMA channels.

[0379] Optionally, the row elements in a row of the interleaving matrix respectively correspond to the data obtained by polling from y groups of encoded data.

[0380] Optionally, each of the L rows adopts the same polling rule; or, the polling rules of every consecutive y rows in the L rows are all different.

[0381] Optionally, when encoding the first encoded data with the second FEC codeword, the processing module 1302 is used to: transmit the first encoded data through P PMA channels; encode the first encoded data transmitted through the P PMA channels.

[0382] Optionally, the processing module 1302 is further used to: transmit the second encoded data through P PMA channels and process the second encoded data transmitted through the P PMA channels.

[0383] Optionally, when performing the first interleaving on y groups of encoded data, the processing module 1302 is configured to: transmit the y groups of encoded data through P PMA channels; and perform the first interleaving on the y groups of encoded data transmitted through the P PMA channels.

[0384] Optionally, the P PMA channels correspond to serial numbers from 0 to (P - 1), and the P columns of the interleaving matrix respectively correspond one-to-one to the encoded data from the P PMA channels; the row elements with odd column serial numbers in a row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with serial numbers from 0 to (P / 2 - 1); and the row elements with even column serial numbers in a row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with serial numbers from P / 2 to P.

[0385] Optionally, the value of P includes 16 or 32.

[0386] Optionally, K also satisfies the following condition: is a positive integer, and N1 is the code length of the first FEC codeword.

[0387] Optionally, N and K also satisfy the following condition: W is a positive integer.

[0388] Optionally, W = 4 * reference clock multiplication factor RCM.

[0389] Optionally, M1 = 106.25 Gbps, M2 = 114 Gbps.

[0390] Optionally,

[0391] The second FEC codeword is constructed as (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, K is the number of bits included in the information bits, and m is the order of the Galois field where the second FEC codeword is located; the second FEC codeword includes any one of the following codewords, or includes a spatially coupled code constructed with any one of the following codewords as sub - codes, or includes a multi - layer code constructed with any one of the following codewords as sub - codes: Hamming(144, 136, 8), Hamming(180, 170, 10), extended Hamming code eHamming(180, 170, 9), double - extended Hamming code DE - Hamming(180, 170, 8), BCH(360, 340, 10), double - extended BCH code DE - BCH(360, 340, 9), DE - BCH(576, 544, 10), or BCH(594, 561, 11), or Hamming(180, 170, 10).

[0392] Optionally, the second FEC codeword is constructed as (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, K is the number of bits included in the information bits, and m is the order of the Galois field where the FEC codeword is located; the second FEC codeword includes any one of the following codewords, or a spatially coupled code constructed with any one of the following codewords as sub - codes, or a multi - layer code constructed with any one of the following codewords as sub - codes: Hamming(126,119,7), Hamming(127,119,8), Hamming(145,136,9), Hamming(179,170,9), eHamming(127,119,7), eHamming(145,136,8), eHamming(179,170,8), eHamming(181,170,10), BCH(290,272,9), BCH(358,340,9), BCH(574,544,10), extended BCH code eBCH(291,272,9), eBCH(359,340,9), eBCH(361,340,10), eBCH(575,544,10), or DE - BCH(362,340,10).

[0393] Optionally, the processing module 1302 is further configured to perform one or more of the following on the second encoded data: transmit through P PMA channels, second interleaving, data modulation, or optoelectronic conversion; P is an even number greater than or equal to 2; the apparatus further includes a communication module 1303, configured to send the processed data to a receiving device.

[0394] Optionally, N = x * n, K = x * k, where x, n, and k are positive integers.

[0395] As Figure 14 shown, an Ethernet encoding apparatus 1400 is further provided in an embodiment of the present application. The Ethernet encoding apparatus 1400 can be used to execute the above - mentioned Ethernet encoding method. Part or all of the above - mentioned Ethernet encoding method can be implemented by hardware or by software. When implemented by hardware, the Ethernet encoding apparatus 1400 includes: an input interface circuit 1401, configured to obtain first information to be encoded; a logic circuit 1402, configured to execute the above - mentioned Ethernet encoding method, for details, please refer to the description in the previous method embodiment and will not be elaborated here; an output interface circuit 1403, configured to output second encoded data.

[0396] Optionally, the Ethernet encoding apparatus 1400 can be a chip or an integrated circuit in specific implementation.

[0397] Optionally, when part or all of the Ethernet encoding method in the above embodiments is implemented by software, as Figure 15 shown, the Ethernet encoding device 1400 includes: a memory 1501 for storing programs; a processor 1502 for executing the programs stored in the memory 1501, and when the programs are executed, the Ethernet encoding device 900 can implement the Ethernet encoding method provided in the above embodiments.

[0398] Optionally, the above memory 1501 can be a physically independent unit, or the memory 1501 can be integrated with the processor 1502.

[0399] Optionally, when part or all of the above Ethernet encoding method is implemented by software, the Ethernet encoding device 1400 may also only include the processor 1502. The memory 1501 for storing programs is located outside the Ethernet encoding device 1400, and the processor 1502 is connected to the memory 1501 through a circuit / wire for reading and executing the programs stored in the memory 1501.

[0400] The processor 1502 can be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.

[0401] The processor 1502 may further include a hardware chip. The above hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The above PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0402] The memory 1501 may include a volatile memory, such as a random-access memory (RAM); the memory 1501 may also include a non-volatile memory, such as a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); the memory 1501 may further include a combination of the above types of memories.

[0403] The encoding device 1400 of Ethernet may also be a chip, an integrated circuit, or a chip system.

[0404] An embodiment of this application may further provide a chip, including a processor, for supporting the encoding device 1400 of the Ethernet to implement the functions involved in the above method embodiments. In a possible design, the chip is connected to a memory or the chip includes a memory, and the memory is used to store the necessary program instructions and data of the encoding device 1400 of the Ethernet.

[0405] An embodiment of this application provides a computer-readable storage medium, storing a computer program, and the computer program includes instructions for executing the above method embodiments.

[0406] An embodiment of this application provides a computer program product containing instructions, which, when running on a computer, enables the above method embodiments to be implemented.

[0407] Those skilled in the art should understand that the embodiments of this application can be provided as a method, a system, or a computer program product. Therefore, this application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0408] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing device produce means for implementing the functions specified in one or more flows of the flowchart and / or one or more blocks of the block diagram.

[0409] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufacture including instruction means that implement the functions specified in one or more flows of the flowchart and / or one or more blocks of the block diagram.

[0410] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more flows of the flowchart and / or one or more blocks of the block diagram.

[0411] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0412] Obviously, those skilled in the art can make various changes and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and variations.< / j> < / j>

Claims

1. A coding method for Ethernet, characterized in that, it includes: The sending end encodes the first information to be encoded by using a first forward error correction code FEC codeword to obtain first encoded data, and the first FEC codeword is a Reed-Solomon forward error correction code RS-FEC; The sending end encodes the first encoded data by using a second FEC codeword to obtain second encoded data; the code length N and the information bit length K of the second FEC codeword satisfy the following formula: where M1 is the throughput of the first encoded data, and M2 is the throughput of the output data of the physical medium dependent (PMD) layer; The sending end performs FEC encoding on the first information to be encoded by using the first FEC codeword to obtain first encoded data, including: The sending end performs FEC encoding on the first information to be encoded by using y first FEC codewords to obtain y groups of encoded data, where y is an even number greater than or equal to 2; The sending end performs first interleaving on the y groups of encoded data to obtain the first encoded data; the first interleaving conforms to an interleaving matrix with row and column numbers of L and P respectively, where L and P are even numbers greater than or equal to 2, and the value of P includes 8, 16 or 32.

2. The method according to claim 1, characterized in that, The row elements in one row of the interleaving matrix respectively correspond to the data obtained by polling from the y groups of encoded data.

3. The method according to claim 2, characterized in that, Each row of the L rows adopts the same polling rule; or, the polling rules of every consecutive y rows in the L rows are all different.

4. The method according to any one of claims 1 to 3, characterized in that, The sending end encodes the first encoded data by using a second FEC codeword, including: The sending end transmits the first encoded data through P physical medium sublayer PMA channels; Encode the first encoded data transmitted through the P PMA channels.

5. The method according to any one of claims 1 to 3, characterized in that, The method further includes: The sending end transmits the second encoded data through P PMA channels and processes the second encoded data transmitted through the P PMA channels.

6. The method according to any one of claims 1 to 3, characterized in that, The sending end performs first interleaving on the y groups of encoded data, including: The sending end transmits the y groups of encoded data through P PMA channels; Perform the first interleaving on the y groups of encoded data transmitted through the P PMA channels.

7. The method according to claim 6, characterized in that, The P PMA channels correspond to serial numbers 0 to (P - 1), and the P columns of the interleaving matrix respectively correspond one-to-one to the encoded data from the P PMA channels; the row elements with odd column numbers in one row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with serial numbers 0 to (P / 2 - 1); the row elements with even column numbers in one row of the interleaving matrix respectively correspond to the encoded data of the PMA channels with serial numbers P / 2 to P.

8. The method according to any one of claims 1 to 3, characterized in that, K also satisfies the following conditions: is a positive integer, and N1 is the code length of the first FEC codeword.

9. The method according to any one of claims 1 to 3, characterized in that, The N and the K also satisfy the following conditions: W is a positive integer.

10. The method according to any one of claims 1 to 3, characterized in that, M1 = 106.25 Gbps, M2 = 114 Gbps.

11. The method according to any one of claims 1 to 3, characterized in that, When the Ethernet PCS layer is 800GE, the value of y is 4.

12. The method according to any one of claims 1 to 3, characterized in that the construction of the second FEC codeword is (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, K is the number of bits included in the information bits, and m is the order of the Galois field where the second FEC codeword is located; the second FEC codeword includes any one of the following codewords, or a spatially coupled code constructed with any one of the following codewords as sub - codes, or a multi - layer code constructed with any one of the following codewords as sub - codes: Hamming(144, 136, 8), Hamming(180, 170, 10), extended Hamming code eHamming(180, 170, 9), double - extended Hamming code DE - Hamming(180, 170, 8), BCH(360, 340, 10), double - extended BCH code DE - BCH(360, 340, 9), DE - BCH(576, 544, 10), or BCH(594, 561, 11), or Hamming(180, 170, 10).

13. The method according to any one of claims 1 to 3, characterized in that the construction of the second FEC codeword is (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, K is the number of bits included in the information bits, and m is the order of the Galois field where the FEC codeword is located; the second FEC codeword includes any one of the following codewords, or a spatially coupled code constructed with any one of the following codewords as sub - codes, or a multi - layer code constructed with any one of the following codewords as sub - codes: Hamming(126, 119, 7), Hamming(127, 119, 8), Hamming(145, 136, 9), Hamming(179, 170, 9), eHamming(127, 119, 7), eHamming(145, 136, 8), eHamming(179, 170, 8), eHamming(181, 170, 10), BCH(290, 272, 9), BCH(358, 340, 9), BCH(574, 544, 10), extended BCH code eBCH(291, 272, 9), eBCH(359, 340, 9), eBCH(361, 340, 10), eBCH(575, 544, 10), or DE - BCH(362, 340, 10).

14. The method according to any one of claims 1 to 3, characterized in that the method further includes: the sending end performs one or more of the following processes on the second encoded data: transmitting through P PMA channels, second interleaving, data modulation, or optoelectronic conversion; P is an even number greater than or equal to 2; the sending end sends the processed data to the receiving device.

15. The method according to any one of claims 1 to 3, characterized in that, N = x * n, K = x * k, where x, n, and k are positive integers and x is greater than 1.

16. The method according to claim 15, characterized in that, x is 8.

17. The method according to any one of claims 1 to 3, characterized in that, the second FEC codeword is a Hamming code or a BCH code.

18. An encoding device for an Ethernet, characterized in that, the device is configured to perform the method according to any one of claims 1 to 17.

19. A communication system, characterized in that, comprising a sending end and a receiving end, the sending end is configured to perform the method according to any one of claims 1 to 17, and the receiving end is configured to receive the data processed by the sending end.

20. A computer-readable storage medium, characterized in that, the computer-readable storage medium stores computer-readable instructions, and when the computer-readable instructions run on an encoding device for an Ethernet, the encoding device for the Ethernet is caused to perform the method according to any one of claims 1 to 17.

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