A method for characterizing degradation of an igbt epitaxial layer

Abstract

This invention discloses a degradation characterization method for IGBT epitaxial layers, comprising: applying a constant bias voltage to the device gate and superimposing a small signal; performing a voltage scan between the collector and emitter of the device; and detecting the capacitance C between the gate and collector at multiple collector and emitter bias voltage points. gc ; Calculate each V ce Substrate capacitance C at value sub And draw C sub -V ce Curve and 1 / C 2 sub -V ce Curve, extracting the surface MOS capacitance C of the junction field-effect region. oj With V ce Variation curve; calculate the substrate capacitance C after the device degrades due to stress. sub Value and draw C sub -V ce Curve and 1 / C 2 sub -V ce The curves are compared to analyze and calculate the types, locations, and densities of defect charges by comparing the drift of the curves before and after device degradation. The method of this invention is simple and easy to implement, and can accurately and quickly determine the defect charges of the epitaxial layer of the device.

Description

Technical Field

[0001] This invention relates to the field of power device reliability testing, and specifically to a method for characterizing the degradation of IGBT epitaxial layers. Background Technology

[0002] IGBT transistors, as important power semiconductor devices, offer higher power density and output capabilities, as well as faster switching speeds, and are widely used in high-voltage, high-power-density applications such as power systems, industrial automation, and new energy vehicles. However, due to the long-term operation of IGBTs under high temperature, high pressure, and radiation, defects can develop in the drift region, especially in silicon carbide-based IGBTs, where the propagation of dislocations in the drift region leads to more severe degradation.

[0003] Currently, the most widely used methods for testing defects in power semiconductor devices are the capacitance (CV) method and the charge pump method. However, neither of these methods can characterize defects in the epitaxial layer of IGBTs. This invention provides a testing method that can characterize the charge of defects in the epitaxial layer. Summary of the Invention

[0004] The purpose of this invention is to provide a degradation characterization method for IGBT epitaxial layers, which can characterize the defect charge of the epitaxial layer of IGBT devices.

[0005] To achieve the above functions, this invention designs a degradation characterization method for IGBT epitaxial layers, performing the following steps S1-S5 to characterize the damage type, density, and location of the IGBT device epitaxial layer:

[0006] Step S1: Set up the test circuit. For the IGBT device under test, apply a constant bias voltage to the gate of the IGBT device under test using a voltage source and superimpose a small AC signal. Perform a 0V-V test between the collector and emitter of the IGBT device under test. ce1 Negative voltage scan;

[0007] Step S2: For the IGBT device under test, apply multiple bias voltages V to its collector and emitter. ce Extracted at 0V-V ce1 The capacitance C between the gate and collector gc ;

[0008] Step S3: Calculate each bias voltage V ce Substrate capacitance C at value sub And draw C sub -V ce Curve and 1 / C 2 sub -V ce The curve is used to extract the surface MOS capacitance C of the junction field-effect region through calculation.oj with the bias voltage V ce curve.

[0009] Step S4: apply stress to the IGBT device under test, when the IGBT device under test degrades due to the stress, repeat steps S1-S2, based on the capacitance C gc between the gate and the collector of the IGBT device under test, calculate the capacitance C oj of the substrate of the IGBT device under test after stress, and plot the C sub -V sub curve and the 1 / C ce -V 2 sub -V ce curve.

[0010] Step S5: compare the drift of the C sub -V ce curve and the 1 / C 2 sub -V ce curve before and after the degradation of the IGBT device under test, determine the type of defect charge of the epitaxial layer of the IGBT device under test, calculate the density of the defect charge, and characterize the location of the defect charge.

[0011] As a preferred technical solution of the present application: the AC small signal voltage amplitude in step S1 is between 1mV and 1V, and the frequency is between 1KHz and 1MHz.

[0012] As a preferred technical solution of the present application: the constant bias voltage applied to the gate of the IGBT device under test in step S1 is between 0V and 10V.

[0013] As a preferred technical solution of the present application: the maximum bias voltage V ce1 between the collector and the emitter in step S1 is determined by the maximum reverse voltage that the device can withstand, and the typical value is between -5V and -1000V.

[0014] As a preferred technical solution of the present application: the calculation of the MOS capacitance C oj of the surface of the junction field effect region in step S3 is as follows:

[0015]

[0016] The MOS capacitance C ce of the surface of the junction field effect region under different bias voltage V oj is obtained from the above formula.

[0017] As a preferred technical solution of the present application: the stress applied to the IGBT device under test in step S4 includes all stresses that can cause defects in the epitaxial layer of the IGBT device under test.

[0018] As a preferred technical solution of the present application: the substrate capacitance C sub As follows:

[0019]

[0020] The different bias voltages V ce The lower substrate capacitance C sub value.

[0021] As a preferred technical solution of the present application: the method for judging the type of defect charge in step S5 is as follows:

[0022] As the bias voltage V ce value increases, the PN junction depletion region of the substrate and the epitaxial layer of the IGBT device under test gradually expands, and when the depletion region expands to a position containing defect charge: if compared with the epitaxial layer without defects, if C sub -V ce curve drifts upward, 1 / C 2 sub -V ce curve drifts along 1 / C 2 sub axis, then the defect polarity is positive, and the type of defect charge is donor-type defect.

[0023] If compared with the epitaxial layer without defects, C sub -V ce curve drifts downward, 1 / C 2 sub -V ce curve drifts along 1 / C 2 sub axis, then the defect polarity is negative, and the type of defect charge is acceptor-type defect.

[0024] As a preferred technical solution of the present application: the method for calculating the position and density of defect charge in step S5 is as follows:

[0025] The substrate capacitance C sub and the width W of the depletion layer of the substrate PN junction are related as follows:

[0026]

[0027] wherein ε is the dielectric constant of the semiconductor, and A is the area of the substrate PN junction.

[0028] The width W of the depletion layer is a function of the collector and the emitter, and the specific relationship is:

[0029]

[0030] wherein, N d is the effective doping concentration of the substrate PN junction depletion region, is the built-in potential difference of the substrate PN junction, V ce is the bias voltage, q is the electronic charge amount;

[0031] Substituting equation (4) into equation (3), the relationship between the substrate capacitance C sub and the bias voltage V ce is obtained, and the specific relationship is:

[0032]

[0033] The effective doping concentration before and after stress is obtained by extracting the slope of equation (5) before and after stress, and the defect charge density introduced by the epitaxial layer due to stress is calculated by the following equation:

[0034] Conc Trap = ΔN d (6)

[0035] wherein, Conc Trap is the defect density of the epitaxial layer, and ΔN d is the difference between the effective doping concentrations calculated using equation (5) before and after stress.

[0036] As a preferred technical solution of the present application, the method for characterizing the position of defect charges in step S5 is as follows:

[0037] The depletion layer position under the bias voltage V sub when the substrate capacitance C ce begins to drift is extracted, and the depletion layer position under the bias voltage V sub when the substrate capacitance C ce drifts to the maximum is extracted, to obtain the region containing defect charges in the epitaxial layer.

[0038] Advantages: Compared with the prior art, the advantages of the present application include:

[0039] 1. The test method designed by the present application can analyze and extract the defect position, polarity, and density in the IGBT epitaxial layer. The traditional C-V method and charge pump method can only solve the problem of interface state generated at the gate oxide interface of the device, and cannot solve the extraction of IGBT epitaxial layer defects. The advantage of the IGBT epitaxial layer degradation characterization method of the present application is that the MOS capacitance C oj of the junction field effect region surface remains unchanged before and after the degradation of the device by fixing the gate voltage, and the capacitance C gc after degradation is detected, and the difference between C gc and Coj The substrate capacitance C after the device is degraded can be obtained by operation sub The substrate capacitance C before and after the device is degraded is compared and analyzed sub The epitaxial layer defects can be characterized

[0040] 2. The test method designed in the application compares and analyzes C sub -V ce curve and 1 / C 2 sub -V ce curve, the polarity of the epitaxial layer defects can be obtained by the upward or downward drift of C sub -V ce curve, if C sub -V ce curve drifts upward, the defect polarity is positive, which is a donor type defect, and vice versa. Meanwhile, the region containing defects in the epitaxial layer can be detected according to the depletion layer position under V sub when the drift starts to V ce and the depletion layer position under V sub when the drift is the largest ce The method is simple and easy to operate, and has high accuracy

[0041] 3. The test method designed in the application is simple and clear in the calculation process of the epitaxial layer defect density, 1 / C 2 sub -V ce curve is in a linear relationship, and the slope is related to the effective doping quality in the epitaxial layer, and only the drift of the curve slope of 1 / C 2 sub -V ce curve before and after the degradation is drawn and the drift of the curve slope is extracted, the epitaxial layer defect density can be calculated. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a structure of an IGBT transistor and a capacitor composition diagram provided according to an embodiment of the application;

[0043] Figure 2 is a flowchart of a degradation characterization method for an IGBT epitaxial layer provided according to an embodiment of the application;

[0044] Figure 3 is a test circuit diagram provided according to an embodiment of the application;

[0045] Figure 4 is a C sub -V ce curve diagram before stress provided according to an embodiment of the application;

[0046] Figure 5The stress before and after C sub -V ce curve and 1 / C 2 sub -V ce curve. DETAILED DESCRIPTION

[0047] The application will be further described below with reference to the drawings. The following examples are only used to more clearly illustrate the technical solutions of the application, and cannot be used to limit the protection scope of the application.

[0048] IGBT (Isulated-Gate-Bipolar-Transistor) is a high-power electronic device, which combines the characteristics of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and BJT (Bipolar Transistor), and realizes low switching loss while having high current density.

[0049] The structure and capacitor composition of the IGBT transistor are shown in Figure 1 The gate capacitor composition mainly has two parts between the gate and the collector capacitor C gc , and the capacitor C ge between the gate and the emitter. The capacitor C gc is composed of four capacitors through series and parallel connection, which are the channel region surface MOS capacitor C oc , the junction field effect region surface MOS capacitor C oj , the PN junction capacitor C j , and the substrate capacitor C sub , wherein the junction field effect region surface MOS capacitor C oj and the substrate capacitor C sub are in series connection. The capacitor C ge is composed of three capacitors through series and parallel connection, which are the channel region surface MOS capacitor C oc , the junction field effect region surface MOS capacitor C oj , and the PN junction capacitor C j , wherein C ge is mainly affected by C oc . When the emitter and the collector are short-circuited, the PN junction capacitor C j effect is shielded, and the gate capacitor C g is formed by the capacitor C gc and the capacitor C ge in parallel.

[0050] When the bias voltage applied to the gate of the IGBT continues to increase, the channel region under the gate electrode goes through from depletion to inversion, and carrier accumulation occurs in the junction field effect region, forming an inversion layer channel connecting the N+ emitter region and the N base region.

[0051] The semiconductor surface inversion refers to that after the gate voltage is applied, the electrons or holes are attracted to the semiconductor surface, causing the semiconductor surface to be converted from the original n-type to the p-type or from the original p-type to the n-type; the semiconductor surface depletion refers to that after the gate voltage is applied, the electrons or holes are repelled, and the original donor atoms or acceptor atoms lose electrons or holes, and a space charge region is formed in part of the semiconductor surface; and the semiconductor surface accumulation refers to that after the gate voltage is applied, the electrons or holes are accumulated on the semiconductor surface, so that the electron concentration of the n-type region or the hole concentration of the p-type region of the semiconductor surface is higher than that of the n-type region or the p-type region inside the semiconductor.

[0052] Due to the working scene of the IGBT involving high temperature, large current, irradiation and other factors, defects are introduced in the gate oxide and the epitaxial layer of the IGBT, defect charges are introduced in the gate oxide, which seriously affects the gate control ability of the device, and defects exist in the substrate, which seriously affects the current capacity of the device.

[0053] The embodiment of the present application provides a method for characterizing the degradation of the epitaxial layer of the IGBT, referring to Figure 2 , the following steps S1-S5 are performed to characterize the damage type, density and position of the epitaxial layer of the IGBT device:

[0054] Step S1: build a test circuit, referring to Figure 3 , for the IGBT device to be tested, a constant bias voltage is applied to the gate of the IGBT device to be tested by using a voltage source and superimposing an AC small signal, and a negative voltage scanning of 0V-V ce1 is performed between the collector and the emitter of the IGBT device to be tested.

[0055] In step S1, the direct current voltage scanning is performed between the collector and the emitter, and the scanning range is large enough to make the substrate PN junction space charge region extend deep enough in the N-drift region, and during the scanning, an appropriate step size is set, considering the test rate and test accuracy; and the voltage scanning range between the collector and the emitter should make the substrate PN junction depletion region extend to the position containing defects, and the voltage scanning range of the collector and the emitter should be determined by the voltage withstanding capacity of the device.

[0056] Maximum bias voltage V between collector and emitter ce1 To maximize the extent of the substrate PN junction, allowing for the detection of deeper stress-induced damage without exceeding the device's forward blocking voltage, therefore V ce1 The range is between -5V and -1000V.

[0057] The amplitude of the AC small-signal voltage is between 1mV and 1V, and the frequency is between 1KHz and 1MHz.

[0058] A constant bias voltage is applied to the gate of the IGBT device under test between 0V and 10V.

[0059] In one embodiment, a constant bias voltage of 2V is applied to the gate of the IGBT device under test and a small AC signal with an amplitude of 1mV and a frequency of 1KHz is superimposed to perform a voltage scan between the collector and emitter of the IGBT device under test.

[0060] Step S2: For the IGBT device under test, apply multiple bias voltages V to its collector and emitter. ce Extracted at 0V-V ce1 The capacitance C between the gate and collector gc ;

[0061] Step S3: Calculate each bias voltage V ce Substrate capacitance C at value sub And draw C sub -V ce Curve and 1 / C 2 sub -V ce Curve, reference Figure 4 The surface MOS capacitance C of the junction field-effect region is extracted through calculation. oj With bias voltage V ce Change curve;

[0062] Due to capacitance C gc The surface MOS capacitance and substrate capacitance C of the junction field-effect region sub Formed in series, therefore the surface MOS capacitor C of the junction field-effect region oj The calculation is as follows:

[0063]

[0064] The above formula yields different bias voltages V. ce Surface-mount MOS capacitor C in lower junction field-effect region oj value.

[0065] Step S4: Apply stress to the IGBT device under test. When the IGBT device degrades due to stress, repeat steps S1-S2, i.e., set the same voltage bias as before the degradation of the IGBT device, based on the capacitance C between the gate and collector. gc With the surface MOS capacitor C of the junction field-effect region oj The gate voltage of the IGBT device under test remains unchanged before and after degradation, and the capacitance C oj Keeping it constant, the substrate capacitance C after stress is calculated. sub The value was calculated, and the C value of the IGBT device under test after degradation was plotted. sub -V ce Curve and 1 / C 2 sub -V ce curve;

[0066] C before and after stress sub -V ce Curve and 1 / C 2 sub -V ce Curve reference Figure 5 ;

[0067] The stress applied to the IGBT device under test includes any stress that can cause defects in the epitaxial layer, such as radiation stress. Radiation stress refers to the situation where the device's operating environment is frequently injected with high-energy particles, causing defects in the epitaxial layer, severely affecting device performance, and leading to device degradation or failure.

[0068] Due to capacitance C gc The surface MOS capacitance and substrate capacitance C of the junction field-effect region sub Series formation, substrate capacitance C after stress in step S4 sub As shown in the following formula:

[0069]

[0070] The above formula yields different bias voltages V. ce Lower substrate capacitance C sub value.

[0071] Step S5: Compare C values ​​of the IGBT device before and after degradation. sub -V ce Curve and 1 / C 2 sub -V ce The drift of the curve is used to determine the type of defect charge in the epitaxial layer of the IGBT device under test, calculate the defect charge density, and characterize the location of the defect charge.

[0072] Under a small positive gate voltage, the gate oxide interface capacitance of the junction field effect region is large, and the substrate capacitance is small. Since the capacitance C gc is composed of the two in series, the capacitance value C gc between the gate and the collector is approximately the substrate capacitance. As the value of V ce increases, the depletion region of the PN junction between the substrate and the epitaxial layer gradually expands. When the depletion region expands to a location containing defect charges: if the defect charges are donor-type defects, the substrate capacitance value will decrease compared to the epitaxial layer without defects; if the defect charges are acceptor-type defects, the substrate capacitance value will increase compared to the epitaxial layer without defects. Therefore, the method for determining the type of defect charges in step S5 is as follows:

[0073] As the bias voltage V ce increases, the depletion region of the PN junction between the substrate and the epitaxial layer of the IGBT device under test gradually expands, and when the depletion region expands to a location containing defect charges: if compared to the epitaxial layer without defects, if C sub -V ce curve shifts upward, 1 / C 2 sub -V ce curve shifts along the 1 / C 2 sub axis in the negative direction, then the defect polarity is positive, and the type of defect charges is donor-type defects;

[0074] if compared to the epitaxial layer without defects, C sub -V ce curve shifts downward, 1 / C 2 sub -V ce curve shifts along the 1 / C 2 sub axis in the positive direction, then the defect polarity is negative, and the type of defect charges is acceptor-type defects.

[0075] The method for calculating the density of defect charges in step S5 is as follows:

[0076] The relationship between the substrate capacitance C sub and the width W of the depletion layer of the substrate PN junction is:

[0077]

[0078] where ε is the dielectric constant of the semiconductor, and A is the area of the substrate PN junction;

[0079] The width W of the depletion layer is a function of the collector and the emitter, and the specific relationship is:

[0080]

[0081] where N dThe effective doping concentration of the depletion region of the substrate PN junction, The built-in potential difference of the substrate PN junction, V ce The bias voltage;

[0082] Substituting equation (4) into equation (3) can obtain the relationship between the substrate capacitance C sub and the bias voltage V ce , and the specific relationship is:

[0083]

[0084] From the formula, 1 / C 2 sub and V ce is a linear relationship, and the slope is related to the doping concentration of the depletion region of the PN junction. When the device introduces defects in the epitaxial layer due to stress, the effective doping concentration of the PN junction epitaxial layer part region changes, and as V ce increases, the depletion region expands to the region containing defects, and the actual effective doping concentration of the depletion layer changes.

[0085] By extracting the slope of equation (5) before and after stress, the effective doping concentration before and after stress is obtained, and the defect charge density introduced in the epitaxial layer due to stress is calculated by the following formula:

[0086] Conc Trap = ΔN d (6)

[0087] Where, Conc Trap is the defect density of the epitaxial layer, and ΔN d is the difference between the effective doping concentrations calculated using equation (5) before and after stress.

[0088] The position method of defect charge in step S5 is as follows:

[0089] By extracting the depletion layer position under the bias voltage V sub when the substrate capacitance C ce begins to drift, to the depletion layer position under the bias voltage V sub when the substrate capacitance C ce drifts to the maximum, the region containing defect charges in the epitaxial layer is obtained. As shown in the defect region in Figure 5 , it is defined as the region containing defect charges in the epitaxial layer. The depletion layer position under the corresponding voltage can be calculated by equation (4).

[0090] Specifically, by equations (3) and (4), the substrate capacitance C ce under each V sub value is calculated, and the capacitance C gc measured before stress and C subThe surface MOS capacitance C of the junction field-effect region is obtained by calculation. oj With the gate voltage constant, the MOS capacitor C oj Almost unchanged. After extracting stress, at different V... ce Capacitance C at value gc With MOS capacitor C oj The substrate capacitance C after stress can be obtained by performing calculations. sub And can draw 1 / C 2 sub -V ce Curve, curve.

[0091] In summary, the method designed in this invention extracts 1 / C before and after stress. 2 sub -V ce The drift of the curve slope can be used to calculate the density of defect charge in the epitaxial layer.

[0092] When the gate voltage is at a fixed bias, changing V ce Value, substrate capacitance C sub Changes to the surface MOS capacitance C in the junction field-effect region. oj C remains unchanged. gc Primarily affected by substrate capacitance. With a fixed bias voltage between the gate and collector, a voltage scan is performed between the collector and emitter to obtain C. gc -V ce Curves Figure 4 As shown. Due to capacitance C oj Stable and constant, each V is calculated before stress. ce Substrate capacitance C under value sub and the measured C gc -V ce The curve corresponds to V ce C under value gc The capacitance C can be obtained by performing calculations. oj Capacitance C before and after stress oj Stable and unchanged. After stress, the measured capacitance C gc With C oj The calculation yields C sub -V ce The curve, and plot 1 / C 2 sub -V ce curve.

[0093] From formulas (3), (4), and (5), we can see that 1 / C 2 sub With V cebetween them is a linear relationship, the slope of which is related to the effective doping concentration of the PN junction depletion region. When the device introduces defects in the epitaxial layer due to stress, the effective doping concentration of the PN junction epitaxial layer part region changes, and as V ce increases, the depletion region expands to the region containing defects, the actual effective doping concentration of the depletion layer changes, the slope of the linear relationship of equation (5) changes as shown in FIG. 5. By extracting the slope of equation (5) before and after stress, the effective doping concentration before and after stress can be obtained, and the defect charge density introduced in the epitaxial layer due to stress can be calculated by equation (6). Figure 5

[0094] The position of the depletion layer at the time when the capacitance value starts to drift is defined as V ce , and the position of the depletion layer at the time when the capacitance value drifts the most is defined as V ce , as shown in FIG. 4. Figure 5 Figure 5 The defect region in equation (4) is defined as the region containing defects in the epitaxial layer. The position of the depletion layer at the corresponding voltage can be calculated by equation (4).

[0095] The embodiments of the present application are described in detail above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present application.​​

Claims

1. A method of characterizing degradation with respect to an IGBT epitaxial layer, comprising: The following steps S1-S5 are performed to characterize the type, density and location of the damage of the IGBT device epitaxial layer: Step S1: build a test circuit, for the IGBT device to be tested, a constant bias voltage is applied to the gate of the IGBT device to be tested by a voltage source and an AC small signal is superimposed, and a 0V-V ce1 negative voltage scanning is performed between the collector and the emitter of the IGBT device to be tested; Step S2: for the IGBT device under test, a plurality of bias voltages V are applied to its collector and emitter ce , extracting the capacitance C between the gate and collector between 0V-V ce1 ; gc ; Step S3: Calculate each bias voltage V ce substrate capacitance C at the value sub and plot C sub -V ce curve and 1 / C 2 sub -V ce curve, by the operation of extracting the junction field effect region surface MOS capacitance C oj with the bias voltage V ce change curve; Step S4: applying stress to the IGBT device under test, and repeating steps S1-S2 after the IGBT device under test degrades due to the stress, based on the capacitance C gc between the gate and the collector of the IGBT device under test oj , calculating the capacitance C sub of the substrate after the stress, and plotting the C sub -V ce curve and the 1 / C 2 sub -V ce curve after the IGBT device under test degrades; Step S5: comparing C sub -V ce curves and 1 / C 2 sub -V ce the shift of the curves, judging the type of the defect charge of the epitaxial layer of the IGBT device under test, calculating the density of the defect charge, and representing the position of the defect charge. The method for calculating the location and density of the defect charge in step S5 is as follows: Substrate capacitance C sub The relationship with the substrate PN junction depletion layer width W is: wherein, the dielectric constant of the semiconductor, the area of the substrate PN junction; The depletion layer width W is a function between the collector and the emitter, and the specific relationship is: wherein, is an effective doping concentration of a substrate PN junction depletion region, is a built-in potential difference of a substrate PN junction, V ce is a bias voltage, q is an electronic charge amount; Substituting (4) into (3) gives the relationship between the substrate capacitance C sub and the bias voltage V ce , which is specifically: The effective doping concentration before and after stress is obtained by extracting the slope of formula (5) before and after stress, and the defect charge density of the epitaxial layer due to stress is calculated by the following formula: wherein, is the defect density of the epitaxial layer, Δ N d is the difference of effective doping concentration before and after stress calculated using formula (5).

2. The method of claim 1, wherein the method is characterized by: The AC small signal voltage amplitude in step S1 is between 1mV and 1V, and the frequency is between 1KHz and 1MHz.

3. The method of claim 1, wherein the method is characterized by: The constant bias voltage applied to the gate of the IGBT device to be measured in step S1 is between 0V and 10V.

4. The method of claim 1, wherein the method is characterized by: The maximum bias voltage V between the collector and the emitter in step S1 ce1 The range is determined by the maximum reverse voltage that the device can withstand, which has a typical value between -5 V and -1000 V.

5. The method of claim 1, wherein the method is characterized by: The surface MOS capacitance C of the junction field effect region in step S3 oj is calculated as follows: Different bias voltages V are obtained from the above equation ce The surface MOS capacitance C of the junction field effect region oj value.

6. The method of claim 1, wherein the method is performed on an epitaxial layer of an IGBT. The stress applied to the IGBT device to be measured in step S4 includes all stresses that cause defects in the epitaxial layer of the IGBT device to be measured.

7. The method of claim 1, wherein the method is performed on an epitaxial layer of an IGBT. The substrate capacitance C after stress in step S4 sub The following equation: Different bias voltages V are obtained from the above equation ce Lower substrate capacitance C sub Values.

8. The method of claim 1, wherein the method is used for characterizing the degradation of an IGBT epitaxial layer. The method for judging the type of defect charge in step S5 is as follows: As the bias voltage V ce increases, the PN junction depletion region of the substrate and the epitaxial layer of the IGBT device under test gradually expands, and when the depletion region expands to a location containing defect charges: if compared to the epitaxial layer without defects, if C sub -V ce the curve drifts upwards, 1 / C 2 sub -V ce the curve along 1 / C 2 sub drifts negatively, then the defect polarity is positive, and the type of defect charge is a donor-type defect. If the curve drifts downward, 1 / C sub -V ce If the curve drifts downward, 1 / C 2 sub -V ce If the curve drifts downward, 1 / C 2 sub If the curve drifts upward, 1 / C If the curve drifts upward, 1 / C 9. The method of claim 1, wherein the method is used for characterizing the degradation of an IGBT epitaxial layer. The method for characterizing the location of the defect charge in step S5 is as follows: The method for characterizing the location of the defect charge in step S5 is as follows: By extracting substrate capacitance C sub Bias voltage V at the start of drift ce The depletion layer location below, to the substrate capacitance C sub Bias voltage V at maximum drift ce The location of the depletion layer is determined to obtain the region containing defect charges in the epitaxial layer.

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