FPGA synthesis tool logic optimization method, storage medium and electronic device

Abstract

The present invention provides a method for optimizing logic of an FPGA synthesis tool, including traversing each trigger unit d in a circuit netlist, storing a mapping relationship between a D input port signal of the trigger unit d and the trigger unit d in a trigger input set; performing a static variable check on each multiplexer output port signal o that can be found in the trigger input set; performing a dynamic variable check on each multiplexer output port signal o after the static variable check, and optimizing the multiplexer unit according to the variable range after the dynamic variable check. The present invention determines the variable range of a part of the signal after the dynamic variable check, thereby optimizing the multiplexer unit according to the variable range of the signal, removing some logic branches that are not within the variable range, thereby reducing the number of logic resources used and improving the performance after circuit synthesis.

Description

Technical Field

[0001] The present invention belongs to the technical field of programmable logic devices, and in particular relates to an FPGA synthesis tool logic optimization method, a storage medium and an electronic device. Background Art

[0002] Logic synthesis is one of the key steps in the FPGA EDA (Electronic Design Automation) software design process. It is responsible for converting the Verilog or VHDL code described by the user at the behavioral level or register transfer level (RTL) into a netlist file consisting of the basic logic units of the FPGA, such as lookup tables (LUTs) and flip-flops (FFs). This process is divided into two main stages: synthesis and mapping. The synthesis stage converts the high-level description into a logic netlist consisting of basic gate circuits, while the mapping stage further converts these gate circuits into logic units suitable for the FPGA hardware structure.

[0003] In the process of FPGA logic synthesis, reducing the number of occupied resources is an important optimization goal. This is because the reduction of resources not only helps to improve the success rate of routing, but also improves the overall timing performance. In practical applications, the values ​​of certain signals can be determined through static analysis and dynamic semantic analysis to determine their effective range. Using this information, the conditional branches or multiplexers (MUX) involving these signals can be logically optimized. However, traditional synthesis tools often ignore the consideration of the range of signal variables, resulting in redundant generated logic resources.

[0004] Therefore, it is necessary to significantly reduce the number of required resources during the logic synthesis stage by accurately determining the valid range of signals and optimizing logic components such as multiplexers accordingly. Summary of the invention

[0005] The present invention provides a method for optimizing logic of an FPGA synthesis tool, which effectively reduces the number of resources required in the logic synthesis stage by determining the effective range of a signal and optimizing logic components such as a multiplexer accordingly, significantly reduces the synthesis area of ​​the FPGA, and improves the use efficiency of the circuit.

[0006] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0007] In order to achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a method for optimizing logic of an FPGA synthesis tool, characterized in that it includes traversing each trigger unit d in the circuit netlist, storing the mapping relationship between the D input port signal of the trigger unit d and the trigger unit d in the trigger input set; performing a static variable check on each multiplexer output port signal o that can be found in the trigger input set; performing a dynamic variable check on each multiplexer output port signal o after the static variable check, and optimizing the multiplexer unit according to the variable range after the dynamic variable check. The beneficial effect of this technical solution is that the variable range of a part of the signal is determined after the dynamic variable check, so as to optimize the multiplexer unit according to the variable range of the signal, remove some logic branches that are not within the variable range, thereby reducing the number of logic resources used and improving the performance after circuit synthesis.

[0008] The FPGA synthesis tool logic optimization method further includes performing filtering of a selection signal according to a variable range of a selection dependent signal for each parallel multiplexer unit in the circuit netlist.

[0009] The static variable checking method is to traverse each multiplexer unit in the circuit netlist, obtain the A-end input signal and the B-end input signal of the multiplexer in the trigger set of the multiplexer output port signal o, and when the A-end input signal or the B-end input signal of the multiplexer is a constant signal, insert the constant value of the A-end input signal or the B-end input signal of the multiplexer into the variable range of the multiplexer output port signal o.

[0010] When the input signal at the A end or the input signal at the B end of the multiplexer is not a constant signal, determine whether the input signal at the A end or the input signal at the B end of the multiplexer is the output signal of another multiplexer; when the judgment result is yes, recursively perform a static variable check on the input signal at the A end or the input signal at the B end of the multiplexer, and insert the variable range of the input signal at the A end or the input signal at the B end of the multiplexer obtained by the check into the variable range of the multiplexer output port signal o; when the judgment result is no, delete the multiplexer output port signal o from the multiplexer output port variable range set.

[0011] The dynamic variable checking method is to analyze the input signal of the S end of each multiplexer where the output port signal o of each multiplexer is located, and obtain the signal set on which the input signal of the S end of the multiplexer depends; determine whether each signal in the signal set on which the input signal of the S end of the multiplexer depends is a constant or is found in the variable range set of the multiplexer output port; if the judgment result is yes, count the combinations of all signal values ​​in the signal set on which the input signal of the S end of the multiplexer depends, and according to each signal value combination, perform statement analysis on the input signal statement of the S end of the multiplexer, and when the statement analysis result is true, recursively perform the dynamic variable check of the input signal of the B end of the multiplexer, and insert the variable range of the input signal of the B end of the multiplexer into the variable range of the output port signal o of the multiplexer.

[0012] When the statement analysis result of the input signal at the S end of the multiplexer is false, the dynamic variable check of the input signal at the A end of the multiplexer is recursively executed, and the variable range of the input signal at the A end of the multiplexer is inserted into the variable range of the output port signal o of the multiplexer.

[0013] The multiplexer unit is optimized according to the variable range after the dynamic variable check, including traversing each multiplexer unit in the circuit netlist, analyzing the input signal at the S end of the multiplexer, obtaining the signal set on which the input signal at the S end of the multiplexer depends, and when each signal in the signal set on which the input signal at the S end of the multiplexer depends is a constant or within the variable range set of the multiplexer output port, counting the combination of all signal values ​​in the signal set on which the input signal at the S end of the multiplexer depends; according to each combination of signal values ​​in the signal set on which the input signal at the S end of the multiplexer depends, when the analysis results of the input signal statement at the S end of the multiplexer are all true, deleting the input signal at the A end of the multiplexer, and replacing the output signal of the multiplexer unit with the input signal at the B end of the multiplexer.

[0014] According to each combination of signal values ​​in the signal set on which the input signal at the S end of the multiplexer depends, when the analysis results of the statement of the input signal at the S end of the multiplexer are all false, the input signal at the B end of the multiplexer is deleted, and the output signal of the multiplexer unit is replaced by the input signal at the A end of the multiplexer.

[0015] The method for processing each parallel multiplexer unit in the circuit netlist includes: traversing each parallel multiplexer unit in the circuit netlist, obtaining the signal of the parallel multiplexer S input end, and obtaining the logic unit of the source of each bit signal of the parallel multiplexer S input end; judging the type of the logic unit of the source of each bit signal of the parallel multiplexer S input end, and when the logic unit operation type is an equal comparison operation, obtaining the A-end input signal and the B-end input signal of the logic unit, judging whether the A-end input signal of the logic unit exists in the variable range set of the multiplexer output port, and whether the B-end input signal of the logic unit exists in the variable range of the A-end input signal of the logic unit; when the judgment results are all yes, continue to execute the logic unit type judgment of the source of each bit signal of the parallel multiplexer S input end, and repeat the above steps; when any judgment result is no, delete the S input end signal of the parallel multiplexer unit and the signal corresponding to the B input end.

[0016] If the logic unit operation type is not an equal comparison operation, the logic unit type determination of the next signal source of the parallel multiplexer S input terminal is continued.

[0017] A technical solution of the present invention provides a computer-readable storage medium, in which program code is stored. The program code is called by a processor to execute the above-mentioned FPGA synthesis tool logic optimization method.

[0018] An electronic device provided by a technical solution of the present invention includes one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more programs are configured to execute the above-mentioned FPGA synthesis tool logic optimization method.

[0019] Compared with the prior art, the beneficial effects of the present invention mainly include: determining the variable range of a part of the signal after dynamic variable inspection, thereby optimizing the parallel multiplexer unit and the multiplexer unit according to the variable range of the signal, removing some logic branches that are not within the variable range, thereby reducing the number of logic resources used and improving the performance after circuit synthesis.

[0020] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 The present invention is a flow chart of the FPGA synthesis tool logic optimization method.

[0023] Figure 2 The present invention is a flow chart of a method for performing static variable checking on a multiplexer unit output signal.

[0024] Figure 3 The present invention is a flow chart of a method for performing dynamic variable checking on a multiplexer unit output signal.

[0025] Figure 4 The present invention is a flowchart of a method for optimizing a multiplexer unit after dynamic variable checking.

[0026] Figure 5 The present invention is a flow chart of a method for optimizing a parallel multiplexer after dynamic variable checking. DETAILED DESCRIPTION

[0027] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0028] Embodiment 1

[0029] Embodiment 1 provides a method for optimizing logic of an FPGA synthesis tool. Figure 1-5 , including traversing each trigger (DFF) unit d in the circuit netlist, storing the mapping relationship between the D input port signal of the trigger unit d and the trigger unit d in the trigger input set input_dff; traversing each multiplexer (Mux) unit c in the circuit netlist, judging whether the output port signal o of the multiplexer unit c exists in the trigger input set input_dff, if so, performing a static variable check on the output port signal o of the multiplexer unit c, if not, continue to traverse other multiplexer units in the circuit netlist. For the static variable check process, see Figure 2The specific method is to recursively traverse the A-end input signal i1 and the B-end input signal i2 of the multiplexer output port signal o in the trigger set. If the A-end input signal i1 or the B-end input signal i2 of the multiplexer is a constant signal, insert the constant value of the A-end input signal i1 or the B-end input signal i2 of the multiplexer into the variable range scopes[o] of the multiplexer output port signal o. If the A-end input signal i1 or the B-end input signal i2 of the multiplexer is not a constant signal, determine whether the A-end input of the multiplexer is a constant signal. Whether the signal i1 or the B-end input signal i2 is the output signal of another multiplexer Mux unit; when the judgment result is yes, recursively perform a static variable check on the A-end input signal i1 or the B-end input signal i2 of the multiplexer, and insert the variable scope of the A-end input signal i1 or the B-end input signal i2 of the multiplexer obtained by the check into the multiplexer output port signal o variable scope scopes[o]; when the judgment result is no, delete the multiplexer output port signal o from the multiplexer output port variable scope set scopes.

[0030] After performing a static variable check on the output port signal o of the multiplexer unit c, perform a dynamic variable check on the output port signal o of the multiplexer unit c. For the steps of the dynamic variable check, refer to Figure 3 , traverse each multiplexer Mux unit c in the circuit netlist, if the output port signal o of the multiplexer Mux unit c can be found in the trigger input set input_dff, analyze the multiplexer S-end input signal i3 where each multiplexer output port signal o is located, obtain the multiplexer S-end input signal i3 dependent signal set V (where the dependent signal refers to the signal that directly affects the value of signal i3, such as logical operation), and determine whether each signal in the signal set V that the multiplexer S-end input signal i3 depends on is a constant or in the multiplexer output port variable The result of the judgment is yes, the combination N of all signal values ​​in the signal set on which the input signal at the S end of the multiplexer depends is counted, and according to each combination of signal values, statement analysis is performed on the statement of the input signal i3 at the S end of the multiplexer, and when the result of the statement analysis of the i3 signal is true, the dynamic variable check of the input signal i2 at the B end of the multiplexer is recursively performed, and the variable scope scopes[i2] of the input signal at the B end of the multiplexer is inserted into the variable scope scopes[o] of the output port signal o of the multiplexer.

[0031] If the statement analysis result of the input signal i3 at the S end of the multiplexer is false, the dynamic variable check of the input signal i1 at the A end of the multiplexer is recursively performed, and the variable scope scopes[i1] of the input signal i1 at the A end of the multiplexer is inserted into the variable scope scopes[o] of the output port signal o of the multiplexer.

[0032] Optimize multiplexer units based on variable ranges after dynamic variable checking, see Figure 4 , the specific process includes traversing each multiplexer Mux unit c in the circuit netlist, analyzing the S-end input signal i3 of the multiplexer Mux unit c, obtaining the dependent signal set V of the S-end input signal i3 of the multiplexer Mux unit c, if each signal of the dependent signal set V is a constant or can be found in the multiplexer output port variable range set scopes, counting the combination N of all signal values ​​in the dependent signal set V, according to each combination of signal values ​​in the signal set V that the multiplexer S-end input signal i3 depends on, when the statement analysis results of the multiplexer S-end input signal i3 are all true, deleting the A-end input signal of the multiplexer, and replacing the output signal of the multiplexer unit with the B-end input signal of the multiplexer. If according to each combination of signal values ​​in the signal set V that the multiplexer S-end input signal i3 depends on, when the statement analysis results of the multiplexer S-end input signal i3 are all false, deleting the B-end input signal of the multiplexer, and replacing the output signal of the multiplexer unit with the A-end input signal of the multiplexer.

[0033] After the optimization of the multiplexer Mux unit is completed, the selection signal is filtered for each parallel multiplexer pmux unit p in the circuit netlist according to the variable range of the selection dependent signal. Figure 5 , including, for each parallel multiplexer pmux unit p in the circuit netlist, the processing method includes, traversing each parallel multiplexer pmux unit p in the circuit netlist, obtaining each bit signal i4 of the S input end of the parallel multiplexer pmux unit p, and obtaining the logic unit lc from which each bit signal i4 of the S input end of each parallel multiplexer is derived;

[0034] Determine the type of the logic unit lc from which each bit signal i4 at the input end of the parallel multiplexer S comes, and when the logic operation type of the logic unit lc is an equal comparison operation (i.e. Figure 5The type eq in the formula (type eq is the abbreviation of equation, which means the equality comparison operation performed by the logic unit) obtains the A-end input signal i5 and the B-end input signal i6 of the logic unit lc, and determines whether the A-end input signal i5 of the logic unit lc exists in the multiplexer output port variable scope set scopes, and whether the B-end input signal i6 of the logic unit lc exists in the variable scope scopes[i5] of the A-end input signal of the logic unit lc;

[0035] If the judgment results are all yes, continue to perform the logic unit lc type judgment of the next signal i4 source of the input end of the parallel multiplexer S, and repeat the above steps;

[0036] In the case where any of the judgment results is negative, the S input terminal signal i4 and the signal corresponding to the B input terminal of the parallel multiplexer unit p are deleted.

[0037] If the logic operation type of the logic unit 1c is not an equal comparison operation (ie, the type of the logic unit 1c is not eq), the logic unit type determination of the next signal i4 source at the input end of the parallel multiplexer S is continued.

[0038] Embodiment 2

[0039] Embodiment 2 provides a computer-readable storage medium, in which program codes are stored. The program codes are called by a processor to execute the FPGA synthesis tool logic optimization method in embodiment 1.

[0040] Embodiment 3

[0041] Embodiment three provides an electronic device, comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more programs are configured to execute the FPGA synthesis tool logic optimization method in embodiment one.

[0042] The above is a detailed introduction to a FPGA synthesis tool logic optimization method, storage medium and electronic device provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for optimizing logic of an FPGA synthesis tool, characterized in that: The method comprises traversing each trigger unit d in the circuit netlist, and storing a mapping relationship between a D input port signal of the trigger unit d and the trigger unit d in a trigger input set; For each multiplexer output port signal o that can be found in the trigger input set, a static variable check is performed; the static variable check method is to traverse each multiplexer unit in the circuit netlist, obtain the A-end input signal and the B-end input signal of the multiplexer in the trigger set of the multiplexer output port signal o, and when the A-end input signal or the B-end input signal of the multiplexer is a constant signal, insert the constant value of the A-end input signal or the B-end input signal of the multiplexer into the variable range of the multiplexer output port signal o; A dynamic variable check is performed on each multiplexer output port signal o after the static variable check is performed, and the multiplexer unit is optimized according to the variable range after the dynamic variable check.

2. The FPGA synthesis tool logic optimization method according to claim 1, characterized in that: The FPGA synthesis tool logic optimization method further includes performing filtering of a selection signal according to a variable range of a selection dependent signal for each parallel multiplexer unit in the circuit netlist.

3. The FPGA synthesis tool logic optimization method according to claim 1, characterized in that: When the input signal at the A end or the input signal at the B end of the multiplexer is not a constant signal, determining whether the input signal at the A end or the input signal at the B end of the multiplexer is an output signal of another multiplexer; When the judgment result is yes, recursively perform a static variable check on the input signal at the A end or the input signal at the B end of the multiplexer, and insert the variable range of the input signal at the A end or the input signal at the B end of the multiplexer obtained by the check into the variable range of the output port signal o of the multiplexer; When the judgment result is no, the multiplexer output port signal o is deleted from the multiplexer output port variable range set.

4. The FPGA synthesis tool logic optimization method according to claim 1, characterized in that: The dynamic variable checking method is to analyze the input signal of the multiplexer S terminal where each multiplexer output port signal o is located, and obtain the signal set on which the multiplexer S terminal input signal depends; Determine whether each signal in the signal set on which the input signal at the S end of the multiplexer depends is a constant or is found in the variable range set of the output port of the multiplexer; When the judgment result is yes, count all the combinations of signal values ​​in the signal set that the input signal at the S end of the multiplexer depends on, perform statement analysis on the input signal statement at the S end of the multiplexer according to each signal value combination, and when the statement analysis result is true, recursively perform the dynamic variable check of the input signal at the B end of the multiplexer, and insert the variable range of the input signal at the B end of the multiplexer into the variable range of the multiplexer output port signal o.

5. The FPGA synthesis tool logic optimization method according to claim 4, characterized in that: When the statement analysis result of the input signal at the S end of the multiplexer is false, the dynamic variable check of the input signal at the A end of the multiplexer is recursively executed, and the variable range of the input signal at the A end of the multiplexer is inserted into the variable range of the output port signal o of the multiplexer.

6. The FPGA synthesis tool logic optimization method according to claim 4, characterized in that: Optimizing the multiplexer unit according to the variable range after the dynamic variable check, including traversing each multiplexer unit in the circuit netlist, analyzing the input signal at the S end of the multiplexer, obtaining the signal set on which the input signal at the S end of the multiplexer depends, and when each signal in the signal set on which the input signal at the S end of the multiplexer depends is a constant or within the variable range set of the output port of the multiplexer, counting the combination of all signal values ​​in the signal set on which the input signal at the S end of the multiplexer depends; According to each combination of signal values ​​in the signal set on which the input signal at the S end of the multiplexer depends, when the analysis results of the statement of the input signal at the S end of the multiplexer are all true, the input signal at the A end of the multiplexer is deleted, and the output signal of the multiplexer unit is replaced by the input signal at the B end of the multiplexer.

7. The FPGA synthesis tool logic optimization method according to claim 6, characterized in that: According to each combination of signal values ​​in the signal set on which the input signal at the S end of the multiplexer depends, when the analysis results of the statement of the input signal at the S end of the multiplexer are all false, the input signal at the B end of the multiplexer is deleted, and the output signal of the multiplexer unit is replaced by the input signal at the A end of the multiplexer.

8. The FPGA synthesis tool logic optimization method according to claim 2, characterized in that: The method for processing each parallel multiplexer unit in the circuit netlist includes traversing each parallel multiplexer unit in the circuit netlist, obtaining a signal at an input end of the parallel multiplexer S, and obtaining a logic unit of a source of each bit signal at the input end of each parallel multiplexer S; Determine the type of logic unit of the source of each bit signal of the input end S of the parallel multiplexer, and when the operation type of the logic unit is an equal comparison operation, obtain the input signal of the A end and the input signal of the B end of the logic unit, and determine whether the input signal of the A end of the logic unit exists in the variable range set of the multiplexer output port, and whether the input signal of the B end of the logic unit exists in the variable range of the input signal of the A end of the logic unit; If the judgment results are all yes, continue to judge the logic unit type of the next signal source of the input end of the parallel multiplexer S, and repeat the above steps; In the case where any judgment result is negative, the signal at the S input terminal and the signal corresponding to the B input terminal of the parallel multiplexer unit are deleted.

9. The FPGA synthesis tool logic optimization method according to claim 8, characterized in that: If the logic unit operation type is not an equal comparison operation, the logic unit type determination of the next signal source of the parallel multiplexer S input terminal is continued.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code is called by a processor to execute the method according to any one of claims 1 to 9.

11. An electronic device, characterized in that: comprising one or more processors; Memory; One or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs are configured to execute the method according to any one of claims 1-9.

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