A wafer-level three-dimensional packaging integration and heat flow control method

Abstract

The present invention discloses a wafer-level three-dimensional packaging integration and heat flow control method, comprising providing a chip stacking structure, wherein each electronic chip comprises at least one thermal sensor; arranging a thermal interface material containing a high thermal conductivity material between the electronic chips, configuring a thermal management unit, the thermal management unit being connected to the thermal sensor of each electronic chip, and setting a key hot spot area of ​​the chip stacking structure; utilizing microfluidic technology to embed a micro cooling channel in the chip stacking structure, and dynamically adjusting the temperature of the electronic chip by changing the flow rate and path of the cooling medium in the micro cooling channel; by real-time temperature monitoring and dynamically adjusting the cooling strategy, timely responding to chip heat changes, and simultaneously using high thermal conductivity materials and micro cooling channels, the entire thermal management system is not only highly efficient but also compact in structure, thereby improving the thermal efficiency and reliability of the chip and meeting the high requirements for heat dissipation during operation of high-performance chips.

Description

Technical Field

[0001] The present invention relates to the field of wafer processing technology, and in particular to a wafer-level three-dimensional packaging integration and heat flow control method. Background Art

[0002] With the rapid development of semiconductor technology, electronic devices are increasingly evolving towards high performance and high integration. Especially in data centers, high-performance computing and large-scale storage devices, wafer-level three-dimensional integrated packaging technology has attracted attention because it can significantly improve circuit density and signal transmission efficiency. This technology not only saves space by vertically stacking multiple chips, but also improves processing speed and energy efficiency. However, this dense integration also brings significant thermal management challenges, because if the heat generated by the chip operation cannot be effectively dissipated, it will seriously affect the performance and life of the chip.

[0003] At present, the existing stacked chip heat dissipation technology mainly relies on passive heat dissipation methods such as heat sinks, fans or liquid cooling systems; although these methods are reliable when dealing with single chips or low-density packages, they face many limitations when dealing with wafer-level three-dimensional integrated packages. For example, heat sinks and fans cannot effectively and precisely control tiny hot spots inside or between chips, resulting in uneven distribution of heat in the chip stack, increasing the risk of overheating and thermal stress. In addition, traditional heat dissipation technologies are often bulky and are not suitable for high-performance chip integration environments with limited space. They are also difficult to meet the requirements of modern electronic devices for compact design.

[0004] In view of this, it is necessary to improve the stacked chip heat dissipation management technology in the prior art to solve the technical problems of low heat dissipation accuracy and inability to achieve precise control. Summary of the invention

[0005] The purpose of the present invention is to provide a wafer-level three-dimensional packaging integration and heat flow control method to solve the above technical problems.

[0006] To achieve this object, the present invention adopts the following technical solutions:

[0007] A wafer-level three-dimensional packaging integration and heat flow control method, comprising:

[0008] A chip stacking structure having at least two electronic chips is provided, wherein each electronic chip comprises at least one thermal sensor for real-time monitoring of temperature data of the corresponding electronic chip;

[0009] Disposing a thermal interface material containing a high thermal conductivity material between the electronic chips, and optimizing the thermal path in the chip stacking structure through the thermal interface material;

[0010] A thermal management unit is configured, wherein the thermal management unit is connected to a thermal sensor of each electronic chip and sets a critical hot spot area of ​​the chip stack structure;

[0011] Using microfluidics technology, micro cooling channels are embedded in the chip stacking structure, and the micro cooling channels are distributed in the key hot spot areas of the chip stacking structure;

[0012] The thermal management unit implements a regulation mechanism according to the temperature data monitored in real time, and dynamically regulates the temperature of the electronic chip by changing the flow rate and path of the cooling medium in the micro cooling channel.

[0013] Optionally, the high thermal conductivity material is selected from graphene, diamond or modified copper-based composite materials.

[0014] Optionally, a thermal interface material containing a high thermal conductivity material is provided between the electronic chips, and the thermal interface material is used to optimize the thermal path in the chip stacking structure, specifically comprising:

[0015] Selecting a high thermal conductivity material suitable for packaging according to the model of the electronic chip as a thermal interface material;

[0016] Design the thickness and shape of the thermal interface material according to the size and thermal characteristics of the chip stacking structure;

[0017] Using coating technology, the thermal interface material coating is evenly applied on the contact surface of each electronic chip according to the set thickness and shape of the thermal interface material.

[0018] Optionally, a thermal interface material coating is uniformly applied on the contact surface of each electronic chip, and then the method further includes:

[0019] The coated thermal interface material is subjected to a thermal curing process so that the thermal interface material is bonded to the surface of the electronic chip;

[0020] After the thermal interface material is set, a thermal characteristic test is performed on the chip stacking structure to verify the thermal conductivity of the thermal interface material.

[0021] Optionally, the configuration of a thermal management unit, wherein the thermal management unit is connected to a thermal sensor of each electronic chip and sets a key hot spot area of ​​the chip stacking structure, specifically includes:

[0022] configuring a thermal management unit, and connecting the thermal management unit to a thermal sensor of each electronic chip;

[0023] Conducting a test run on a chip stack structure coated with thermal interface material to receive and analyze real-time temperature data collected from thermal sensors on each electronic chip;

[0024] The temperature distribution pattern is analyzed by the hot spot management algorithm of the thermal management unit, and the development trend of the hot spot is predicted to identify the key hot spot area in the chip stacking structure.

[0025] Optionally, the temperature distribution pattern is analyzed by a hot spot management algorithm of the thermal management unit, and a development trend of hot spots is predicted to identify key hot spot areas in the chip stacking structure, and then the method further includes:

[0026] According to the identified key hotspot areas, the thermal management unit sets a priority for each key hotspot area.

[0027] Optionally, the micro cooling channel includes:

[0028] A flexible bonding body, used to be bonded to the surface of the chip stacking structure;

[0029] A plurality of micro cooling pipes are built into the flexible conformable body, wherein the plurality of micro cooling pipes are evenly distributed in different areas of the flexible conformable body;

[0030] A controllable flow rate valve, which is arranged at the intersection of a plurality of the micro-cooling pipelines and is used to control the flow rate and path of the cooling medium in the micro-cooling pipelines;

[0031] An interface integrated module is used to connect with the chip stacking structure to realize input and output control of the cooling liquid and signal connection with the thermal management unit.

[0032] Optionally, the thermal management unit implements a regulation mechanism according to the temperature data monitored in real time, and dynamically adjusts the temperature of the electronic chip by changing the flow rate and path of the cooling medium in the micro cooling channel, specifically including:

[0033] The thermal management unit receives real-time temperature data monitored by the thermal sensors of each electronic chip;

[0034] The thermal management unit analyzes the real-time temperature data to identify hot chip areas where the current temperature is higher than a preset temperature threshold;

[0035] The thermal management unit implements a regulation mechanism on the identified hot spot chip area and calculates the required regulation parameters; the regulation parameters include the optimal flow rate and path change of the cooling medium.

[0036] Optionally, the thermal management unit implements a regulation mechanism on the identified hotspot chip area and calculates required regulation parameters, and then further includes:

[0037] Adjusting the adjustment parameters in the corresponding micro cooling channel to change the flow rate and path of the cooling medium;

[0038] The thermal management unit optimizes the adjustment parameters according to the difference between the temperature feedback data of the thermal sensor after parameter adjustment and the preset temperature threshold, and dynamically adjusts the temperature of the electronic chip according to the optimized adjustment parameters.

[0039] The present invention also provides a wafer-level three-dimensional packaging integration and heat flow control system, which uses the wafer-level three-dimensional packaging integration and heat flow control method as described above to achieve control, and the control system includes:

[0040] A thermal sensor module, comprising at least one thermal sensor installed on each electronic chip, for real-time monitoring of temperature data of the corresponding electronic chip;

[0041] A data processing module, used for preprocessing the received real-time temperature data;

[0042] A regulating mechanism unit, comprising micro cooling channels, the micro cooling channels being distributed in key hot spots of the chip stacking structure and being used to dynamically regulate the temperature of the electronic chip;

[0043] A thermal management unit connected to the thermal sensor of each electronic chip, used to implement a regulation mechanism based on the real-time monitored temperature data, and dynamically adjust the temperature of the electronic chip by changing the flow rate and path of the cooling medium in the micro cooling channel;

[0044] The communication module is used for data exchange during the heat dissipation control process.

[0045] Compared with the prior art, the present invention has the following beneficial effects: when working, by configuring an electronic chip stacking structure containing at least one thermal sensor, the temperature of each electronic chip is monitored in real time, and the high thermal conductivity thermal interface material serves as a thermal bridge between chips to effectively conduct and disperse heat. By setting micro-cooling channels in key hot spots, the flow of cooling medium is accurately controlled by microfluidic technology, so that heat can be effectively taken away from the chip surface. The thermal management unit adjusts the flow rate and path of the cooling medium according to real-time temperature data, dynamically controls the chip temperature, and realizes temperature management. The method can respond to chip heat changes in a timely manner through real-time temperature monitoring and dynamic adjustment of cooling strategies. At the same time, the use of high thermal conductivity materials and micro-cooling channels makes the entire thermal management system not only efficient but also compact in structure, thereby improving the thermal efficiency and reliability of the chip, adapting to the high requirements for heat dissipation during the operation of high-performance chips, extending the service life of the product, and reducing maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0047] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size shall still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0048] Figure 1 This is one of the flow diagrams of the wafer-level three-dimensional packaging integration and heat flow control method of the first embodiment;

[0049] Figure 2 This is a second flow chart of the wafer-level three-dimensional packaging integration and heat flow control method of the first embodiment;

[0050] Figure 3 This is the third flow chart of the wafer-level three-dimensional packaging integration and heat flow control method of the first embodiment. DETAILED DESCRIPTION

[0051] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] In the description of the present invention, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0053] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0054] Embodiment 1:

[0055] Combination Figures 1 to 3 As shown, an embodiment of the present invention provides a wafer-level three-dimensional packaging integration and heat flow control method, including:

[0056] S1, providing a chip stacking structure having at least two electronic chips, wherein each electronic chip comprises at least one thermal sensor for real-time monitoring of temperature data of the corresponding electronic chip.

[0057] By providing a set of stacked electronic chips and equipping each chip with at least one thermal sensor, the temperature data of each chip can be monitored in real time. This is the basis of the entire thermal management process, ensuring the accuracy and real-time nature of the data. Real-time monitoring can quickly respond to chip temperature changes, provide necessary data support for subsequent thermal management and regulation, and ensure the thermal stability and performance optimization of the entire system.

[0058] S2, a thermal interface material containing a high thermal conductivity material is disposed between the electronic chips, and the thermal interface material is used to optimize the thermal path in the chip stacking structure.

[0059] By placing thermal interface materials (TIMs) with high thermal conductivity between electronic chips, the thermal path can be significantly optimized to effectively conduct and disperse the heat accumulated during chip operation. High thermal conductivity materials such as graphene and diamond can quickly transfer heat and reduce local overheating. This improvement is particularly critical in chip stacking environments because stacking structures are prone to heat concentration problems, which affects chip performance and service life.

[0060] S3, configuring a thermal management unit, the thermal management unit being connected to a thermal sensor of each electronic chip and setting a key hot spot area of ​​the chip stacking structure;

[0061] The thermal management unit is set up to connect and exchange data in real time with the thermal sensors of each electronic chip, so as to accurately identify and locate the key hot spots in the chip stacking structure. This process includes data analysis and hot spot identification to determine which areas are hot and need more cooling resources. This provides a basis for subsequent cooling strategy adjustments and effective heat dissipation, ensuring that the thermal management unit is more accurate and effective.

[0062] S4, using microfluidics technology, embeds micro cooling channels in the chip stacking structure, and the micro cooling channels are distributed in the key hot spots of the chip stacking structure;

[0063] Microfluidics technology is used to design and embed micro cooling channels in the chip stacking structure, so that these cooling channels can be precisely distributed in the identified key hot spots, significantly improving the heat dissipation efficiency. Microfluidics technology allows the creation of precise and controllable cooling channels, which not only improves the heat dissipation effect, but also maintains the structural integrity of the chip. This step combines precision manufacturing and cooling design to ensure efficient local cooling without damaging the chip structure.

[0064] S5, the thermal management unit implements a regulation mechanism based on the real-time monitored temperature data, and dynamically adjusts the temperature of the electronic chip by changing the flow rate and path of the cooling medium in the micro cooling channel. Through the implemented regulation mechanism, it ensures that the electronic chip operates within the optimal temperature range to maximize thermal efficiency and prevent performance degradation and failure rate caused by overheating.

[0065] The working principle of the present invention is as follows: when working, by configuring an electronic chip stacking structure containing at least one thermal sensor, the temperature of each electronic chip is monitored in real time, and the thermal interface material with high thermal conductivity serves as a thermal bridge between chips to effectively conduct and disperse heat. By setting micro-cooling channels in key hot spots, the flow of cooling medium is accurately controlled using microfluidic technology, so that heat can be effectively taken away from the chip surface. The thermal management unit adjusts the flow rate and path of the cooling medium according to real-time temperature data, dynamically controls the chip temperature, and realizes temperature management. The method can respond to chip heat changes in a timely manner through real-time temperature monitoring and dynamic adjustment of cooling strategies. At the same time, the use of high thermal conductivity materials and micro-cooling channels makes the entire thermal management system not only efficient but also compact in structure, thereby improving the thermal efficiency and reliability of the chip, adapting to the high requirements for heat dissipation during the operation of high-performance chips, extending the service life of the product, and reducing maintenance costs.

[0066] In this embodiment, as a preferred implementation, the high thermal conductivity material is selected from graphene, diamond or modified copper-based composite materials.

[0067] The reason for choosing graphene, diamond or modified copper-based composites as high thermal conductivity materials is that these materials have excellent thermal conductivity. Graphene is an ideal choice because of its abnormal thermal and electrical conductivity, as well as extremely low weight and high mechanical strength. Diamond has the highest thermal conductivity known in nature and is suitable for heat dissipation in complex environments. Modified copper-based composites provide a more cost-effective option by improving the thermal conductivity and mechanical stability of copper. The application of these materials can significantly optimize the thermal management of electronic devices and improve performance and reliability.

[0068] In this embodiment, it is specifically described that step S2 specifically includes:

[0069] S21, selecting a high thermal conductivity material suitable for packaging as a thermal interface material according to the model of the electronic chip.

[0070] According to the model of the electronic chip, select suitable high thermal conductivity materials as thermal interface materials to match the thermal characteristics of the materials with the operating requirements and heat dissipation requirements of the electronic chip, ensuring that the materials can effectively absorb and conduct the heat generated by the chip. Material selection needs to take into account the operating temperature, thermal expansion coefficient and heat resistance of the chip to ensure the stability and efficiency of the thermal interface material during the chip operation process.

[0071] S22, designing the thickness and shape of the thermal interface material according to the size and thermal characteristics of the chip stacking structure; to ensure that the material can form a uniform and effective heat conduction layer between the electronic chips.

[0072] S23, using coating technology, according to the set thickness and shape of the thermal interface material, evenly applies the thermal interface material coating on the contact surface of each electronic chip to ensure the integrity and heat conduction efficiency of the thermal interface material.

[0073] This step requires a precise coating process to ensure uniform distribution of the thermal interface material to avoid hot spots. The choice of coating technique, such as spraying, brushing or rolling, should be determined based on the physical properties of the material and the required coverage area to ensure continuity and uniformity of the coating.

[0074] In this embodiment, it is further explained that after step S23, the following steps are further performed:

[0075] S24, subjecting the coated thermal interface material to a thermal curing process to bond the thermal interface material to the surface of the electronic chip; during this process, it is necessary to control appropriate pressure and temperature to optimize the performance and durability of the thermal interface material.

[0076] The thermal interface material is heated to form a solid, continuous coating on the chip surface, which helps improve thermal conductivity and material adhesion. The temperature and time of the curing process must be precisely controlled according to the chemical and thermal properties of the material to avoid damaging the chip or reducing the effectiveness of the coating.

[0077] S25, after completing the setting of the thermal interface material, a thermal characteristic test is performed on the chip stacking structure to verify the thermal conductivity of the thermal interface material; the thermal characteristic test verifies whether the thermal interface material effectively reduces the thermal resistance between chips and ensures the uniformity and stability of heat distribution.

[0078] By using thermal imagers, thermocouples and other measuring equipment to check heat distribution, we can evaluate whether the thermal interface material can disperse heat evenly and effectively, thereby ensuring that the chip maintains the optimal temperature during operation. This test is the key to evaluating the success of thermal management system design, helping to identify deficiencies in the design and providing data support for subsequent optimization.

[0079] In this embodiment, it is specifically described that step S3 specifically includes:

[0080] S31, configure a thermal management unit, connect the thermal management unit to the thermal sensor of each electronic chip; the thermal management unit includes a central processor and related software for real-time data processing and decision making.

[0081] S32, testing the chip stack structure coated with thermal interface material to receive and analyze real-time temperature data collected from thermal sensors of each electronic chip.

[0082] During the test run, the thermal management unit begins to receive and analyze real-time temperature data collected from the thermal sensors of each electronic chip. This step allows the thermal management system to evaluate the effectiveness of the thermal interface material and its performance in actual operation, while verifying the system's overall temperature monitoring and response capabilities.

[0083] S33, analyzes the temperature distribution pattern through the hotspot management algorithm of the thermal management unit and predicts the development trend of the hotspot to identify the key hotspot areas in the chip stacking structure. The hotspot management algorithm can analyze the temperature distribution pattern and predict the development trend of the hotspot to determine which areas need special attention. Through this analysis, the system can manage thermal issues more proactively instead of just reacting to the current status, thereby optimizing the overall thermal management strategy.

[0084] S34, based on the identified key hotspot areas, the thermal management unit sets the priority of each key hotspot area. Thermal intervention measures include setting priorities, that is, deciding which hotspot areas should be handled first, and predicting areas that may form hotspots in the future for preventive management. Priority is set based on the severity of the hotspot and the potential impact on system performance, so that the thermal management unit can effectively allocate cooling resources to ensure that the system operates in optimal conditions.

[0085] In this embodiment, it is specifically described that the micro cooling channel includes:

[0086] A flexible bonding body is used to bond to the surface of the chip stacking structure; a flexible or semi-flexible patch body, the material of the flexible patch body has high thermal conductivity and good mechanical compatibility, so that it can be closely bonded to the surface of the chip stacking structure without damaging the structure of the chip itself.

[0087] Multiple micro-cooling pipes are built into the flexible conformable body, and multiple micro-cooling pipes are evenly distributed in different areas of the flexible conformable body; these micro-cooling pipes are evenly distributed in different areas of the patch through precise design and production to specifically cover and cool the identified hot spot areas.

[0088] Controllable flow rate valve, the controllable flow rate valve is set at the intersection of multiple micro cooling pipelines, and is used to control the flow rate and path of the cooling medium in the micro cooling pipeline. These controllable flow rate valves are connected to the thermal management unit to adjust the flow rate and direction of the coolant in the channel according to the real-time temperature data to dynamically respond to the temperature changes of the chip.

[0089] The interface integration module is used to connect with the chip stacking structure to realize the input and output control of the cooling liquid and the signal connection with the thermal management unit.

[0090] In this embodiment, it is specifically described that step S5 specifically includes:

[0091] S51, receiving the real-time temperature data monitored by the thermal sensors of each electronic chip through the thermal management unit; ensuring that the thermal management unit can obtain real-time and accurate temperature information, which is the basis for effective thermal management and control.

[0092] S52, the thermal management unit analyzes the real-time temperature data to identify hotspot chip areas whose current temperatures are higher than a preset temperature threshold; after identifying these areas, the thermal management unit can start planning how to effectively reduce the temperatures of these hotspots.

[0093] S53, the thermal management unit implements a regulation mechanism for the identified hotspot chip area and calculates the required regulation parameters; the regulation parameters include the optimal flow rate and path change of the cooling medium. The regulation parameters are calculated based on real-time data and prediction models in order to maximize the heat dissipation efficiency and quickly respond to temperature changes in the hotspot area.

[0094] S54, adjusting the adjustment parameters in the corresponding micro cooling channel to change the flow rate and path of the cooling medium; this step is a key link in the actual implementation of the thermal management strategy, ensuring that the cooling medium can flow according to the predetermined optimal path and speed to achieve the best cooling effect.

[0095] S55, the thermal management unit optimizes the adjustment parameters according to the difference between the temperature feedback data of the thermal sensor after the parameter adjustment and the preset temperature threshold, and dynamically adjusts the temperature of the electronic chip according to the optimized adjustment parameters.

[0096] The thermal management unit optimizes the adjustment parameters based on the difference between the temperature feedback data of the thermal sensor after parameter adjustment and the preset temperature threshold. This is a continuous feedback and optimization process to ensure that the temperature control strategy can dynamically adapt to the thermal characteristics of the chip and environmental changes. The optimized adjustment parameters will be used to dynamically adjust the temperature of the electronic chip to ensure that the entire system maintains an ideal working state.

[0097] Embodiment 2:

[0098] The present invention also provides a wafer-level three-dimensional packaging integration and heat flow control system, which uses the wafer-level three-dimensional packaging integration and heat flow control method of the first embodiment to achieve control, and the control system includes:

[0099] A thermal sensor module, comprising at least one thermal sensor installed on each electronic chip, for real-time monitoring of temperature data of the corresponding electronic chip;

[0100] A data processing module, used for preprocessing the received real-time temperature data;

[0101] A regulating mechanism unit, comprising micro cooling channels, the micro cooling channels being distributed in key hot spots of the chip stacking structure and being used to dynamically regulate the temperature of the electronic chip;

[0102] A thermal management unit connected to the thermal sensor of each electronic chip, used to implement a regulation mechanism based on the real-time monitored temperature data, and dynamically adjust the temperature of the electronic chip by changing the flow rate and path of the cooling medium in the micro cooling channel;

[0103] The communication module is used for data exchange during the heat dissipation control process.

[0104] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wafer-level three-dimensional packaging integration and heat flow control method, characterized in that: include: A chip stacking structure having at least two electronic chips is provided, wherein each electronic chip comprises at least one thermal sensor for real-time monitoring of temperature data of the corresponding electronic chip; Disposing a thermal interface material containing a high thermal conductivity material between the electronic chips, and optimizing the thermal path in the chip stacking structure through the thermal interface material; A thermal management unit is configured, wherein the thermal management unit is connected to a thermal sensor of each electronic chip and sets a critical hot spot area of ​​the chip stack structure; Using microfluidics technology, micro cooling channels are embedded in the chip stacking structure, and the micro cooling channels are distributed in the key hot spot areas of the chip stacking structure; The thermal management unit implements a regulation mechanism based on the temperature data monitored in real time, and dynamically regulates the temperature of the electronic chip by changing the flow rate and path of the cooling medium in the micro cooling channel; Wherein, the micro cooling channel comprises: A flexible bonding body, used to be bonded to the surface of the chip stacking structure; A plurality of micro cooling pipes are built into the flexible conformable body, wherein the plurality of micro cooling pipes are evenly distributed in different areas of the flexible conformable body; A controllable flow rate valve, which is arranged at the intersection of a plurality of the micro-cooling pipelines and is used to control the flow rate and path of the cooling medium in the micro-cooling pipelines; An interface integrated module is used to connect with the chip stacking structure to realize input and output control of the cooling liquid and signal connection with the thermal management unit.

2. The wafer-level three-dimensional packaging integration and heat flow control method according to claim 1, characterized in that: The high thermal conductivity material is selected from graphene, diamond or modified copper-based composite material.

3. The wafer-level three-dimensional packaging integration and heat flow control method according to claim 1, characterized in that: A thermal interface material containing a high thermal conductivity material is arranged between the electronic chips, and the thermal interface material is used to optimize the thermal path in the chip stacking structure, specifically comprising: Selecting a high thermal conductivity material suitable for packaging according to the model of the electronic chip as a thermal interface material; Design the thickness and shape of the thermal interface material according to the size and thermal characteristics of the chip stacking structure; Using coating technology, the thermal interface material coating is evenly applied on the contact surface of each electronic chip according to the set thickness and shape of the thermal interface material.

4. The wafer-level three-dimensional packaging integration and heat flow control method according to claim 3, characterized in that: The thermal interface material coating is evenly applied on the contact surface of each electronic chip, followed by: The coated thermal interface material is subjected to a thermal curing process so that the thermal interface material is bonded to the surface of the electronic chip; After the thermal interface material is set, a thermal characteristic test is performed on the chip stacking structure to verify the thermal conductivity of the thermal interface material.

5. The wafer-level three-dimensional packaging integration and heat flow control method according to claim 1, characterized in that: The configuration of the thermal management unit, which is connected to the thermal sensor of each electronic chip and sets the key hot spot area of ​​the chip stacking structure, specifically includes: configuring a thermal management unit, and connecting the thermal management unit to a thermal sensor of each electronic chip; Conducting a test run on a chip stack structure coated with thermal interface material to receive and analyze real-time temperature data collected from thermal sensors on each electronic chip; The temperature distribution pattern is analyzed by the hot spot management algorithm of the thermal management unit, and the development trend of the hot spot is predicted to identify the key hot spot area in the chip stacking structure.

6. The wafer-level three-dimensional packaging integration and heat flow control method according to claim 5, characterized in that: Analyzing the temperature distribution pattern through the hot spot management algorithm of the thermal management unit and predicting the development trend of the hot spot to identify the key hot spot area in the chip stacking structure, and then further comprising: According to the identified key hotspot areas, the thermal management unit sets a priority for each key hotspot area.

7. The wafer-level three-dimensional packaging integration and heat flow control method according to claim 1, characterized in that: The thermal management unit implements a regulation mechanism according to the temperature data monitored in real time, and dynamically adjusts the temperature of the electronic chip by changing the flow rate and path of the cooling medium in the micro cooling channel, specifically including: The thermal management unit receives real-time temperature data monitored by the thermal sensors of each electronic chip; The thermal management unit analyzes the real-time temperature data to identify hot chip areas where the current temperature is higher than a preset temperature threshold; The thermal management unit implements a regulation mechanism on the identified hot spot chip area and calculates the required regulation parameters; the regulation parameters include the optimal flow rate and path change of the cooling medium.

8. The wafer-level three-dimensional packaging integration and heat flow control method according to claim 7, characterized in that: The thermal management unit implements a regulation mechanism on the identified hotspot chip area and calculates the required regulation parameters, and then further includes: Adjusting the adjustment parameters in the corresponding micro cooling channel to change the flow rate and path of the cooling medium; The thermal management unit optimizes the adjustment parameters according to the difference between the temperature feedback data of the thermal sensor after parameter adjustment and the preset temperature threshold, and dynamically adjusts the temperature of the electronic chip according to the optimized adjustment parameters.

9. A wafer-level three-dimensional packaging integration and thermal flow control system, characterized in that: The control is implemented by using the wafer-level three-dimensional packaging integration and heat flow control method according to any one of claims 1 to 8, wherein the control system comprises: A thermal sensor module, comprising at least one thermal sensor installed on each electronic chip, for real-time monitoring of temperature data of the corresponding electronic chip; A data processing module, used for preprocessing the received real-time temperature data; A regulating mechanism unit, comprising micro cooling channels, the micro cooling channels being distributed in key hot spots of the chip stacking structure and being used to dynamically regulate the temperature of the electronic chip; A thermal management unit connected to the thermal sensor of each electronic chip, used to implement a regulation mechanism based on the real-time monitored temperature data, and dynamically adjust the temperature of the electronic chip by changing the flow rate and path of the cooling medium in the micro cooling channel; The communication module is used for data exchange during the heat dissipation control process.

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