A multi-modal nitride semiconductor CMOS array and its preparation method

Abstract

The present invention discloses a multimodal nitride semiconductor CMOS array and a method for fabricating the same. The array comprises a plurality of longitudinally distributed first nanopillar structures; an insulating dielectric is filled between adjacent first nanopillar structures; each first nanopillar structure comprises: a first N-type epitaxial structure comprising a first barrier layer; a first P-type epitaxial structure comprising a second channel layer located above the first N-type epitaxial structure; a first source electrode annularly surrounding the first barrier layer; and a second source electrode annularly surrounding the second channel layer; a first gate electrode and a second gate electrode located on the surfaces of the first barrier layer and the second barrier layer, respectively, with the first and second gate electrodes sharing a common gate via metal interconnection; and a first drain electrode and a second drain electrode located on the surfaces of the first barrier layer and the second barrier layer, respectively, with an insulating dielectric filled between the first drain electrode and the first gate electrode, and between the second drain electrode and the second gate electrode, with the first and second drain electrodes sharing a common drain via metal interconnection. This invention improves the integration level of nitride semiconductor CMOS arrays.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a multi-modal nitride semiconductor CMOS array and a preparation method thereof. Background Art

[0002] CMOS (Complementary Metal Oxide Semiconductor) integrated circuits play a vital role in modern electronic devices. CMOS technology has been the dominant technology in the microelectronics industry since the 1960s and is widely used in digital logic circuits, microprocessors, memory, and other digital integrated circuits.

[0003] CMOS technology is based on complementary N-type and P-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). In CMOS circuits, the two types of transistors are designed to operate in a complementary manner. The main advantage of this design is that power is consumed only when the circuit switches states, greatly reducing power consumption and thus extending the device's standby time. With the continuous improvement and development of process technology, the size of CMOS integrated arrays has continued to shrink and the integration level has continued to increase. Today's CMOS integrated arrays can integrate billions of transistors, making the computing power, storage capacity, and functions of microelectronic devices increasingly powerful. Moreover, because the CMOS production process is relatively simple and the production cost is relatively low, this technology has been widely used in the microelectronics industry.

[0004] Current CMOS integrated array technology mainly includes the following solutions:

[0005] 1. Standard digital CMOS process: This is the most commonly used solution for the production of a large number of general-purpose digital logic circuits. This process uses P-type silicon as the substrate and prepares N-type and P-type MOSFETs through ion implantation and thermal diffusion processes.

[0006] 2. Bipolar CMOS process: This process combines the advantages of CMOS and bipolar transistors. By integrating two types of transistors on the same silicon wafer, it can realize both high oscillation frequency digital circuits and analog circuits at the same time.

[0007] 3. SOI (Silicon On Insulator) CMOS process: An insulating layer is added between the silicon substrate and the silicon layer to prevent charge interaction between the substrate and the source / drain, which can effectively reduce the short channel effect and improve device performance.

[0008] 4. FinFET (Fin Field-Effect Transistor) CMOS process: It overcomes the problem of traditional silicon-based planar MOSFET reaching its limit by adding vertical "fins" between the source and drain to form a three-dimensional structure to achieve a smaller characteristic length, improve integration, and continue to maintain low power consumption.

[0009] However, existing silicon-based CMOS devices require a doping process, which increases process complexity and produces suboptimal carrier electrical properties. Furthermore, existing silicon-based CMOS arrays and FinFET CMOS arrays, constructed by laterally connecting multiple conventional CMOS devices, occupy a significant footprint and hinder integration. Therefore, improving the electrical performance of CMOS devices and increasing the integration density of CMOS arrays remain key challenges in the current technology. Summary of the Invention

[0010] In order to solve the above problems existing in the prior art, the present invention provides a multi-modal nitride semiconductor CMOS array and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0011] In a first aspect, an embodiment of the present invention provides a multi-modal nitride semiconductor CMOS array, wherein the array comprises a plurality of longitudinally distributed nano-pillar structures; an insulating medium is filled between adjacent longitudinally distributed nano-pillar structures; wherein,

[0012] Each longitudinally distributed nanocolumn structure includes:

[0013] A first N-type epitaxial structure is located on the substrate layer; the first N-type epitaxial structure includes, from bottom to top, a first back barrier layer, a first channel layer, and a first barrier layer;

[0014] a first P-type epitaxial structure located above the first N-type epitaxial structure, the first N-type epitaxial structure and the first P-type epitaxial structure being isolated by an insulating medium; the first P-type epitaxial structure including, from bottom to top, a second barrier layer and a second channel layer;

[0015] a first source electrode and a second source electrode, wherein the first source electrode is located on a side of the first barrier layer and surrounds the first barrier layer in a ring shape, and the second source electrode is located on a side of the second channel layer and surrounds the second channel layer in a ring shape;

[0016] The first gate and the second gate each include a T-shaped electrode connection portion and an electrode main portion, the electrode connection portion of the first gate being located on a surface of one end of the first barrier layer, the electrode main portion of the first gate being located above the first barrier layer and an insulating medium being filled between the first barrier layer and the electrode connection portion of the second gate being located on a surface of one end of the second channel layer on the same side as the first gate, the electrode main portion of the second gate being located above the second channel layer and an insulating medium being filled between the second channel layer, and the electrode main portions of the first gate and the second gate being connected by an interconnecting metal to realize a common gate;

[0017] The first drain and the second drain each include a T-shaped electrode connection portion and an electrode main portion. The electrode connection portion of the first drain is located on the surface of the other end of the first barrier layer. The electrode main portion of the first drain is located above the first gate and an insulating medium is filled between the first gate and the first barrier layer. The electrode connection portion of the second drain is located on the surface of the other end of the second channel layer. The electrode main portion of the second drain is located above the second gate and an insulating medium is filled between the second gate and the second channel layer. The electrode main portions of the first drain and the second drain are connected to a common drain through interconnected metal.

[0018] In one embodiment of the present invention, the array further comprises a plurality of laterally distributed nanocolumn structures, and an insulating medium is filled between adjacent laterally distributed nanocolumn structures; wherein,

[0019] Each laterally distributed nanocolumn structure includes:

[0020] a second N-type epitaxial structure located on the substrate layer; the second N-type epitaxial structure comprises, from bottom to top, a second back barrier layer, a third channel layer, and a third barrier layer;

[0021] a second P-type epitaxial structure located on one side of the second N-type epitaxial structure, with an insulating dielectric filled between the second P-type epitaxial structure and the second N-type epitaxial structure; the second P-type epitaxial structure includes, from bottom to top, a fourth barrier layer and a fourth channel layer; wherein the fourth barrier layer and the back barrier layer are made of the same material, and the third channel layer and the fourth channel layer are made of the same material;

[0022] a third source electrode and a fourth source electrode, the third source electrode being located on an upper surface of one end of the third barrier layer, and the fourth source electrode being located on an upper surface of one end of the fourth channel layer;

[0023] a third drain and a fourth drain, the third drain being located on an upper surface at the other end of the third barrier layer, and the fourth drain being located on an upper surface at the other end of the fourth channel layer; the third drain and the fourth drain being connected to each other via an interconnecting metal to realize a common drain;

[0024] The third gate and the fourth gate, the third gate is located on the upper surface of the third barrier layer between the third source and the third drain, the fourth gate is located on the upper surface of the fourth channel layer between the fourth source and the fourth drain, and the third gate and the fourth gate are connected to each other through interconnected metal to realize a common gate.

[0025] In a second aspect, an embodiment of the present invention provides a method for preparing a multimodal nitride semiconductor CMOS array, the method comprising:

[0026] Growing a first N-type epitaxial structure on the substrate layer; the first N-type epitaxial structure includes a first back barrier layer, a first channel layer and a first barrier layer from bottom to top;

[0027] growing a first insulating dielectric on the first barrier layer;

[0028] Etching a plurality of first grooves on the surface of the first insulating medium until reaching the upper surface of the first barrier layer, and depositing gate metal in each first groove and around the first groove to form an electrode connection portion and an electrode main portion corresponding to the first gate;

[0029] Continuing to grow a second insulating medium on the first insulating medium and the electrode main body portions of all the first gates;

[0030] Etching a plurality of second grooves on the surface of the second insulating medium until reaching the upper surface of the first barrier layer, and depositing drain metal in each second groove and around the second groove to respectively form an electrode connection portion and an electrode main portion corresponding to the first drain; wherein the electrode main portion of each first drain is located above the electrode main portion corresponding to the first gate;

[0031] Continuing to grow a third insulating medium on the electrode main body portions of all first drain electrodes to prepare a first partial structure;

[0032] Obtaining a first P-type epitaxial structure; the first P-type epitaxial structure includes, from bottom to top, a second barrier layer and a second channel layer;

[0033] Growing a fourth insulating medium on the lower surface of the second barrier layer and the upper surface of the second channel layer respectively;

[0034] Etching a plurality of third grooves on the surface of the fourth insulating medium until reaching the upper surface of the second barrier layer, and depositing gate metal in and around each third groove to form an electrode connection portion and an electrode main portion corresponding to the second gate;

[0035] Continue growing a fifth insulating medium on the fourth insulating medium and the electrode main body portions of all the second gates;

[0036] Etching a plurality of fourth grooves on the surface of the fifth insulating medium until reaching the upper surface of the second barrier layer, and depositing drain metal in and around each of the fourth grooves to form an electrode connection portion and an electrode main portion corresponding to the second drain, respectively; wherein the electrode main portion of each second drain is located above the electrode main portion corresponding to the second gate;

[0037] Continuing to grow a sixth insulating dielectric on the electrode main body portions of all second drain electrodes to prepare a second partial structure;

[0038] Bonding the top end of the first structure and the bottom end of the second structure together to prepare a third structure;

[0039] Etching the third portion of the structure into a plurality of first nanorod structures perpendicular to the substrate layer; wherein each first nanorod structure includes a first N-type epitaxial structure, a first P-type epitaxial structure, a first drain and a first gate located on the first N-type epitaxial structure, and a second drain and a second gate located on the first P-type epitaxial structure;

[0040] An insulating medium is grown between adjacent first nanocolumn structures until the insulating medium grown between the adjacent first nanocolumn structures is flush with the upper surface of the sixth insulating medium, completing the preparation and forming a nitride semiconductor CMOS array including a plurality of longitudinally distributed nanocolumn structures; wherein, in the process of growing the insulating medium between the adjacent first nanocolumn structures, a first source and a second source are formed, and an interconnecting metal is deposited so that the main electrode parts of the first gate and the second gate are connected through the interconnecting metal to realize a common gate, and the main electrode parts of the first drain and the second drain are connected through the interconnecting metal to realize a common drain.

[0041] In one embodiment of the present invention, the preparation method further comprises:

[0042] growing a second P-type epitaxial structure on the substrate layer; the second P-type epitaxial structure includes a fourth barrier layer and a fourth channel layer from bottom to top;

[0043] Etching a plurality of third deep trenches on the surface of the second P-type epitaxial structure until reaching the surface of the fourth barrier layer;

[0044] Depositing a third barrier layer on the fourth channel layer on one side of each third deep trench, forming a second N-type epitaxial structure by the fourth barrier layer, the fourth channel layer and the third barrier layer from bottom to top;

[0045] forming a third source electrode, a third gate electrode and a third drain electrode in sequence on the third barrier layer on one side of each third deep trench;

[0046] forming a fourth source electrode, a fourth gate electrode, and a fourth drain electrode in sequence on the fourth channel layer on one side of each third deep trench to obtain a fourth partial structure;

[0047] Etching the fourth portion of the structure into a plurality of second nanorod structures perpendicular to the substrate layer; wherein each second nanorod structure includes a second P-type epitaxial structure, a second N-type epitaxial structure, a third source, a third gate, and a third drain located on the second N-type epitaxial structure, and a fourth source, a fourth gate, and a fourth drain located on the second P-type epitaxial structure;

[0048] depositing an insulating dielectric between adjacent second nanorod structures and within each third deep trench;

[0049] Depositing interconnect metal on the third gate and the fourth gate of each second nanorod structure respectively, so that the third gate and the fourth gate are connected through the interconnect metal to realize a common gate;

[0050] Interconnect metal is deposited on the third drain and the fourth drain of each second nano-pillar structure respectively, so that the third drain and the fourth drain are connected to each other through the interconnect metal to realize a common drain, and the preparation is completed to form a nitride semiconductor CMOS array including several laterally distributed nano-pillar structures.

[0051] Beneficial effects of the present invention:

[0052] The multimodal nitride semiconductor CMOS array proposed in the present invention nanopillars the entire CMOS and stacks it vertically. During the vertical stacking, the nMOS and pMOS are arranged vertically and separated by an insulating dielectric. Compared with traditional Si-based CMOS arrays and FinFET CMOS arrays, the use of a nanopillar structure and vertical stacking can significantly reduce the size of traditional CMOS devices and improve the integration of the CMOS array. During the vertical stacking process, the source, drain and gate electrodes are reconfigured. To maintain the nanopillar structure of the CMOS array and facilitate lead-out, the source and gate are arranged in the form of metal layers and separated by an insulating dielectric. The source is isolated and ring-shaped around the barrier layer in the nMOS and the upper part of the channel layer in the pMOS. This utilizes the vertical distance, thereby increasing the gate-drain spacing and the source-drain spacing, ensuring the stability and reliability of the device. At the same time, because both the pMOS and nMOS use a heterojunction structure, the doping step of traditional CMOS devices is eliminated. The polarized two-dimensional electron gas and two-dimensional hole gas have better performance, thereby achieving a higher-precision CMOS device.

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 1 is a schematic structural diagram of a multi-modal nitride semiconductor CMOS array provided by an embodiment of the present invention;

[0055] Figure 2 is a schematic diagram of an adjacent longitudinally distributed nanocolumn structure provided by an embodiment of the present invention;

[0056] Figure 3 is a schematic diagram of a single longitudinally distributed nanocolumn structure provided by an embodiment of the present invention;

[0057] Figure 4 1 is a schematic structural diagram of another multi-modal nitride semiconductor CMOS array provided by an embodiment of the present invention;

[0058] Figure 5 is a schematic diagram of a single laterally distributed nanopillar structure provided by an embodiment of the present invention;

[0059] Figure 6 This is a schematic flow chart of a method for preparing a multi-modal nitride semiconductor CMOS array provided by an embodiment of the present invention;

[0060] Figure 7 is a schematic diagram of a process for growing an insulating medium between adjacent longitudinally distributed nanorod structures provided by an embodiment of the present invention;

[0061] Figure 8(a) to Figure 8(t) 1 is a schematic structural diagram corresponding to the preparation process of a multi-modal nitride semiconductor CMOS array provided by an embodiment of the present invention;

[0062] Figure 9 It is a flow chart of another method for preparing a multi-modal nitride semiconductor CMOS array provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0063] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0064] Traditional CMOS devices are made based on Si (silicon) transistors, and the way to achieve pMOS and nMOS is through doping, which increases the complexity of the process, and the electrical characteristics of the carriers formed by doping are not ideal. At the same time, traditional Si-based CMOS devices are composed of a pMOS and an nMOS connected horizontally, which occupies a large layout area and is not conducive to improving the integration. In recent years, the FinFET CMOS process has indeed been proposed. Since the gate of FinFET is three-dimensional, it can greatly reduce the layout area, improve the integration, and can use nano-processing to further reduce the layout size, but this only optimizes the device structure. In essence, the connection method of nMOS and pMOS is still a horizontal connection, and the layout area occupied is still large, which is not conducive to improving the integration. Based on the above analysis, the embodiment of the present invention proposes a solution to nano-pillar CMOS and stack it vertically, which greatly reduces the layout occupancy and thus improves the integration. However, when stacking vertically, since the entire CMOS adopts a nanopillar structure, the electrode arrangement of the pMOS and nMOS becomes very critical. If the gate, source, and drain electrodes are all arranged on the surface of the barrier layer according to the traditional arrangement method, the gate-drain spacing and the source-drain spacing will be limited. Excessively small source-drain spacing will make it difficult to increase the breakdown voltage of the device and affect the output transfer characteristics of the device. Therefore, the embodiment of the present invention re-arranges the position of the gate, source, and drain electrodes while nanopillarizing and stacking the CMOS vertically. Specifically:

[0065] In a first aspect, an embodiment of the present invention provides a multi-modal nitride semiconductor CMOS array, the array comprising a plurality of longitudinally distributed nanorod structures Figure 1 As shown, Figure 1 It only shows the N-type epitaxial structure in multiple longitudinally distributed nanopillar structures. More detailed structures are shown in the figure. Figure 2 As shown; the adjacent longitudinally distributed nanocolumn structures are filled with insulating medium ( Figure 1 and Figure 2 (not shown) to achieve electrical isolation between the longitudinally distributed nanocolumn structures, the material of the insulating medium may be SiO2 (silicon dioxide), but is not limited to SiO2; wherein,

[0066] Each longitudinally distributed nanopillar structure is as follows Figure 3 Shown, including:

[0067] A first N-type epitaxial structure is located on the substrate layer; the first N-type epitaxial structure includes, from bottom to top, a first back barrier layer, a first channel layer, and a first barrier layer;

[0068] a first P-type epitaxial structure located above the first N-type epitaxial structure, the first N-type epitaxial structure and the first P-type epitaxial structure being isolated by an insulating medium; the first P-type epitaxial structure including, from bottom to top, a second barrier layer and a second channel layer;

[0069] a first source electrode and a second source electrode, wherein the first source electrode is located on a side of the first barrier layer and surrounds the first barrier layer in a ring shape, and the second source electrode is located on a side of the second channel layer and surrounds the second channel layer in a ring shape;

[0070] The first gate and the second gate each include a T-shaped electrode connection portion and an electrode main portion, the electrode connection portion of the first gate being located on a surface of one end of the first barrier layer, the electrode main portion of the first gate being located above the first barrier layer and an insulating medium being filled between the first barrier layer and the electrode connection portion of the second gate being located on a surface of one end of the second channel layer on the same side as the first gate, the electrode main portion of the second gate being located above the second channel layer and an insulating medium being filled between the second channel layer, and the electrode main portions of the first gate and the second gate being connected by an interconnecting metal to realize a common gate;

[0071] The first drain and the second drain each include a T-shaped electrode connection portion and an electrode main portion. The electrode connection portion of the first drain is located on the surface of the other end of the first barrier layer. The electrode main portion of the first drain is located above the first gate and an insulating medium is filled between the first gate and the first barrier layer. The electrode connection portion of the second drain is located on the surface of the other end of the second channel layer. The electrode main portion of the second drain is located above the second gate and an insulating medium is filled between the second gate and the second channel layer. The electrode main portions of the first drain and the second drain are connected to a common drain through interconnected metal.

[0072] The substrate layer of the embodiment of the present invention can be SiC, but is not limited to SiC. The material of the first back barrier layer is AlN; the material of the first channel layer and the second channel layer is one of GaN, InGaN, and AlGaN; the material of the first barrier layer and the second barrier layer is one of AlGaN, AlInN, AlN, ScAlN, and AlInGaN. Among them, the materials of the first barrier layer and the second barrier layer are: the Al component of AlGaN ranges from 25% to 85%, the Al component of AlInN is fixed at 83%, the Sc component of ScAlN is fixed at 18%, the Al component of AlInGaN is greater than 25%, the In component is greater than 20%, and the Ga component is greater than 25%; the materials of the first channel layer and the second channel layer are: the In component of InGaN is 5% to 45%, and the Al component of AlGaN is 15% to 45%. The materials mentioned subsequently all use the same components as those here.

[0073] The first N-type epitaxial structure and the first P-type epitaxial structure can be selected from existing structures, or they can be prepared using a MOCVD (Metal-organic Chemical Vapor Deposition) process. In the embodiment of the present invention, it is preferred that the first N-type epitaxial structure is AlN / GaN / AlN, and the first P-type epitaxial structure is GaN / AlN. GaN-based heterostructures have high electron mobility and two-dimensional electron gas density as well as low sheet resistance; AlN has a large lattice parameter and can serve as a stable anti-relaxation layer, which has a pressure buffering effect in the heterojunction and helps to reduce the lattice mismatch caused by lattice mismatch; the lattice constants of AlN and GaN are very close, so that there is a good lattice match between them, which helps to reduce the generation of lattice stress and defects, and is conducive to the growth of high-quality heterojunctions and improve the quality and performance of the material; the thermal expansion coefficient of AlN is close to that of GaN. This anti-thermal expansion property makes the AlN / GaN heterojunction suitable for devices in high-temperature working environments and helps to maintain the lattice stability of the material under high temperature conditions. In addition, signal transmission is very important in CMOS arrays, and AlN is an excellent insulating material that can play an insulating isolation role in devices. The insulating performance of the AlN / GaN heterojunction can effectively reduce crosstalk and electron tunneling effects between devices, thereby improving device reliability.

[0074] In the first N-type epitaxial structure of the embodiment of the present invention, the thickness of the first barrier layer should be 5nm to 30nm. Considering that an excessively thick first barrier layer will bring about a more serious leakage problem, a first barrier layer of 20nm is more preferred. As the channel layer of the first N-type epitaxial structure, the thickness of the first channel layer should not be too thin, otherwise it will be easily interfered by alloy scattering from the upper and lower barrier layers. The thickness of the first channel layer should be 10nm to 50nm, and a first channel layer of 30nm is more preferred. As the back barrier of the first N-type epitaxial structure, the first back barrier layer and the first barrier layer form an opposite polarization field to enhance the confinement of carriers and should not be too thick. The thickness of the first back barrier layer should be 3nm to 15nm, and a first back barrier layer of 10nm is more preferred. Similarly, as the channel layer of the first P-type epitaxial structure, the thickness of the second channel layer should not be too thin, otherwise it will be easily interfered by the alloy scattering from the barrier layer below. The thickness of the second channel layer should be 10nm~50nm, and a second channel layer of 30nm is more preferred; as a barrier layer for exciting two-dimensional hole gas (2DHG), the thickness of the second barrier layer should be 10nm~30nm, and a second barrier layer of 20nm is more preferred.

[0075] In the embodiment of the present invention, each longitudinally distributed nanopillar structure is cylindrical, with a diameter of 10 nm to 40 nm and an aspect ratio of 20:1 to 50:1. Furthermore, each longitudinally distributed nanopillar structure has a slightly tapered characteristic, which is advantageous because it has higher mechanical rigidity to withstand further processing steps.

[0076] The gate material used for the first and second gates in the embodiments of the present invention should have good interface properties, enabling good Schottky contact between the gate material and the semiconductor material. It should also have high conductivity to ensure effective control of the gate over the device channel switching. It should also ensure good stability and workability, possess chemical stability and corrosion resistance, effectively resist stress and deformation caused by thermal expansion, and adapt to more complex operating environments. The material for the first and second gates in the embodiments of the present invention is preferably Au, with a thickness of 8nm to 12nm, more preferably 10nm. This metal has a mature process for use as an electrode and can form good contact.

[0077] The drain material for the first and second drain electrodes in the present embodiment should have high conductivity to ensure efficient current transmission and reduce resistance and power consumption. The drain material should have good contact with the GaN material, with low contact resistance and high interface quality to ensure smooth electron transfer and improve device performance. The drain material for the first and second drain electrodes in the present embodiment is preferably Ti, with a thickness of 16nm to 24nm, more preferably 20nm. This metal has a mature process for use as an electrode and can form good contact.

[0078] In the embodiment of the present invention, the first source and the second source are ring-shaped and surround the corresponding nano-pillar structure. The source material is similar to the drain material, preferably Ti, and the thickness should be 5nm to 20nm, more preferably 10nm.

[0079] In the embodiment of the present invention, the interconnection metal between the first gate and the second gate, and between the first drain and the second drain, is preferably made of W (tungsten) as the interconnection material. W has high electrical conductivity, can efficiently conduct current, and has good resistance to micro-arc corrosion, which can avoid damage to the equipment caused by the generation of micro-arcs.

[0080] Furthermore, the multi-modal nitride semiconductor CMOS array proposed in the embodiment of the present invention further includes a plurality of laterally distributed nano-pillar structures such as Figure 4 As shown, the adjacent laterally distributed nanocolumn structures are filled with insulating medium; wherein,

[0081] Each laterally distributed nanopillar structure is shown in Figure 5 and includes:

[0082] a second N-type epitaxial structure located on the substrate layer; the second N-type epitaxial structure comprises, from bottom to top, a second back barrier layer, a third channel layer, and a third barrier layer;

[0083] a second P-type epitaxial structure located on one side of the second N-type epitaxial structure, with an insulating dielectric filled between the second P-type epitaxial structure and the second N-type epitaxial structure; the second P-type epitaxial structure includes, from bottom to top, a fourth barrier layer and a fourth channel layer; wherein the fourth barrier layer and the back barrier layer are made of the same material, and the third channel layer and the fourth channel layer are made of the same material;

[0084] a third source electrode and a fourth source electrode, the third source electrode being located on an upper surface of one end of the third barrier layer, and the fourth source electrode being located on an upper surface of one end of the fourth channel layer;

[0085] a third drain and a fourth drain, the third drain being located on an upper surface at the other end of the third barrier layer, and the fourth drain being located on an upper surface at the other end of the fourth channel layer; the third drain and the fourth drain being connected to each other via an interconnecting metal to realize a common drain;

[0086] The third gate and the fourth gate, the third gate is located on the upper surface of the third barrier layer between the third source and the third drain, the fourth gate is located on the upper surface of the fourth channel layer between the fourth source and the fourth drain, and the third gate and the fourth gate are connected to each other through interconnected metal to realize a common gate.

[0087] In this embodiment of the present invention, the second back barrier layer is made of AlN; the third and fourth channel layers are made of one of GaN, InGaN, and AlGaN; and the third and fourth barrier layers are made of one of AlGaN, AlInN, AlN, ScAlN, and AlInGaN. The drain material of the third and fourth source electrodes, and the third and fourth drain electrodes is preferably Ti, and the gate material of the third and fourth gate electrodes is preferably Au.

[0088] In the embodiment of the present invention, the thickness of the second back barrier layer is 10nm to 30nm, more preferably 15nm; the thickness of the third barrier layer is 5nm to 30nm, more preferably 20nm; the thickness of the third channel layer and the fourth channel layer is 10nm to 50nm, more preferably 30nm; the thickness of the fourth barrier layer is 10nm to 30nm, more preferably 15nm. The diameter of the horizontally distributed nanopillar structure in the embodiment of the present invention is slightly larger than that of the vertically distributed nanopillar structure, ranging from 30nm to 60nm, and the aspect ratio is also smaller than that of the vertical device, resulting in a lower degree of integration than the vertical device.

[0089] In summary, the multi-modal nitride semiconductor CMOS array proposed in the embodiment of the present invention nano-pillars the entire CMOS and stacks it vertically. When stacking vertically, nMOS and pMOS are arranged in a vertical direction and separated by an insulating medium in the middle. Compared with CMOS arrays, the use of nanopillar structure and vertical stacking can significantly reduce the volume of traditional CMOS devices and improve the integration of CMOS arrays. During the vertical stacking process, the source, drain and gate electrodes were reset. In order not to change the nanopillar structure of the CMOS array and to facilitate lead-out, the source and gate were set in the form of metal layers and separated by an insulating medium in the middle. The source was separated and the barrier layer in nMOS and the upper part of the channel layer in pMOS were surrounded in a ring shape, thereby utilizing the vertical distance, thereby increasing the gate-drain spacing and the source-drain spacing, and ensuring the stability and reliability of the device. At the same time, since both pMOS and nMOS use heterojunction structures, the doping steps of traditional CMOS devices are eliminated, and the polarized two-dimensional electron gas and two-dimensional hole gas have better performance, thereby obtaining higher-precision CMOS devices. Integrating CMOS devices of different modes, namely the longitudinally distributed nanopillar structure and the transversely distributed nanopillar structure, in the same CMOS array increases the scalability of the integrated CMOS array.

[0090] In a second aspect, an embodiment of the present invention provides a method for preparing a multi-modal nitride semiconductor CMOS array, see Figure 6 , the preparation method comprises:

[0091] S10, growing a first N-type epitaxial structure on the substrate layer as shown in FIG8( a ); the first N-type epitaxial structure includes, from bottom to top, a first back barrier layer, a first channel layer, and a first barrier layer;

[0092] S20, growing a first insulating dielectric on the first barrier layer as shown in FIG8(b);

[0093] S30, etching a plurality of first grooves on the surface of the first insulating medium until reaching the upper surface of the first barrier layer, and depositing gate metal in each first groove and around the first groove to form an electrode connection portion and an electrode main portion corresponding to the first gate, as shown in FIG8( c ). The first grooves are not shown in FIG8( c );

[0094] S40, continuing to grow a second insulating medium on the first insulating medium and the electrode main body portions of all the first gates as described in FIG8(d);

[0095] S50, etching a plurality of second grooves on the surface of the second insulating medium until reaching the upper surface of the first barrier layer, and depositing drain metal in each second groove and around the second groove to respectively form an electrode connection portion and an electrode main portion corresponding to the first drain, as shown in FIG8( e ). The second grooves are not shown in FIG8( e ); wherein the electrode main portion of each first drain is located above the electrode main portion corresponding to the first gate;

[0096] S60, continuing to grow a third insulating dielectric on the main electrode portion of all first drain electrodes to obtain a first partial structure as shown in FIG8(f);

[0097] S70, obtaining a first P-type epitaxial structure as shown in FIG8(g); the first P-type epitaxial structure includes a second barrier layer and a second channel layer from bottom to top;

[0098] S80, growing a fourth insulating dielectric on the lower surface of the second barrier layer and the upper surface of the second channel layer, respectively, as shown in FIG8(h);

[0099] S90, etching a plurality of third grooves on the surface of one end of the fourth insulating medium until reaching the upper surface of the second barrier layer, and depositing gate metal in and around each third groove to form an electrode connection portion and an electrode main portion corresponding to the second gate, as shown in FIG8( i ). The third grooves are not shown in FIG8( i );

[0100] S100, continuing to grow a fifth insulating medium on the fourth insulating medium and the main electrode parts of all second gate electrodes as shown in FIG8(j);

[0101] S101, etching a plurality of fourth grooves on the surface of the end of the fifth insulating dielectric away from the second gate until reaching the upper surface of the second barrier layer, and depositing drain metal in and around each fourth groove to form an electrode connection portion and an electrode main portion corresponding to the second drain, as shown in FIG8( k ). The fourth groove is not shown in FIG8( k ); wherein the electrode main portion of each second drain is located above the electrode main portion of the corresponding second gate;

[0102] S102, continuing to grow a sixth insulating dielectric on the main electrode portion of all second drain electrodes to obtain a second partial structure as shown in FIG8(1);

[0103] S103, bonding the top end of the first partial structure and the bottom end of the second partial structure together to prepare a third partial structure as shown in FIG8(m); In the embodiment of the present invention, bonding the top end of the first partial structure and the bottom end of the second partial structure together includes:

[0104] A low-temperature vacuum bonding process is used to bond the top of the first part structure to the bottom of the second part structure; wherein the low-temperature vacuum bonding process includes: annealing treatment at a temperature of 150°C to 200°C, more preferably at a temperature of 180°C and in a vacuum environment, so that the third insulating medium at the top of the first part structure and the fourth insulating medium at the bottom of the second part structure are bonded and grown together.

[0105] S104, etching the third portion of the structure into a plurality of first nanorod structures perpendicular to the substrate layer; wherein each first nanorod structure includes a first N-type epitaxial structure, a first P-type epitaxial structure, a first drain and a first gate located on the first N-type epitaxial structure, and a second drain and a second gate located on the first P-type epitaxial structure;

[0106] S105. Growing an insulating medium between adjacent first nanocolumn structures until the insulating medium grown between the adjacent first nanocolumn structures is flush with the upper surface of the sixth insulating medium, completing the preparation and forming a nitride semiconductor CMOS array including a plurality of longitudinally distributed nanocolumn structures; wherein, in the process of growing the insulating medium between the adjacent first nanocolumn structures, forming a first source and a second source, and depositing an interconnecting metal so that the main electrode parts of the first gate and the second gate are connected through the interconnecting metal to realize a common gate, and the main electrode parts of the first drain and the second drain are connected through the interconnecting metal to realize a common drain.

[0107] For S105, the embodiment of the present invention provides a process of growing an insulating medium between first adjacent nanorod structures until the insulating medium grown between the adjacent first nanorod structures is flush with the upper surface of the sixth insulating medium. Figure 7 ,include:

[0108] S1051, growing a seventh insulating dielectric between adjacent first nanorod structures until it is at a certain distance from the lower surface of the first barrier layer, for example, 3 nm to 10 nm from the upper and lower surfaces of the first barrier layer, and depositing a circle of source metal on the exposed side of the second barrier layer to form a first source electrode as shown in FIG8(n);

[0109] S1052, continuing to grow an eighth insulating dielectric between adjacent first nanorod structures until it is flush with the lower surface of the electrode main portion of the first gate, and depositing a first portion of interconnect metal on one side of the exposed electrode main portion of the first gate. The first portion of interconnect metal is in contact with the first gate, as shown in FIG8(o);

[0110] S1053, continuing to grow a ninth insulating dielectric between adjacent first nanorod structures until it is flush with the lower surface of the main portion of the electrode of the first drain electrode, and depositing a second portion of interconnecting metal on one side of the exposed main portion of the electrode of the first drain electrode. The second portion of interconnecting metal is in contact with the first drain electrode, as shown in FIG8(p);

[0111] S1054, continue growing a tenth insulating dielectric between adjacent first nanorod structures until it reaches a certain distance from the lower surface of the second channel layer, for example, 5 nm to 10 nm from the upper surface of the second channel layer, and deposit a circle of source metal on the exposed side of the second channel layer to form a second source electrode, as shown in FIG8(q);

[0112] S1055, continuing to grow an eleventh insulating dielectric between adjacent first nanorod structures until it is flush with the lower surface of the electrode main portion of the second gate, etching away a portion of the eleventh insulating dielectric until a first deep trench is formed on the surface of the first portion of the interconnection metal, depositing a third portion of the interconnection metal in and around the first deep trench, the third portion of the interconnection metal in contact with the electrode main portion of the second gate as shown in FIG8(r), so that the electrode main portions of the first gate and the second gate are connected through the third portion of the interconnection metal to achieve a common gate;

[0113] S1056, continuing to grow a twelfth insulating dielectric between adjacent first nanorod structures until it is flush with the lower surface of the electrode main portion of the second drain, etching away a portion of the twelfth insulating dielectric until a second deep trench is formed on the surface of the second portion of the interconnect metal, depositing a fourth portion of the interconnect metal in and around the second deep trench, the fourth portion of the interconnect metal in contact with the electrode main portion of the second drain as shown in FIG8(s), so that the electrode main portions of the first drain and the second drain are connected through the fourth portion of the interconnect metal to realize a common drain;

[0114] S1057 , continue growing the thirteenth insulating medium between adjacent first nanorod structures until it is flush with the upper surface of the sixth insulating medium, as shown in FIG8( t ).

[0115] In the embodiments S10 to S105 and S1051 to S1057 of the present invention, S10 and S70 can be prepared by MOCVD process; S30, S50, S90, S101, S1051 to S1056 can be prepared by electron beam evaporation technology to deposit the corresponding source material, drain material and gate material, as well as the interconnection metal of each part; S20, S40, S60, S80, S100, S102, S1051 to S1057 can be prepared by PECVD (Plasma Enhanced Chemical Vapor The insulating medium is deposited by plasma enhanced chemical vapor deposition (Phase Enhanced Chemical Vapor Deposition) process. The deposited insulating medium is preferably SiO2. SiO2 has excellent electrical insulation properties. It can effectively prevent electrons from shuttling between layers and prevent short circuits between circuits. The chemical and thermal stability of SiO2 is very high. It can maintain its properties for a long time under various harsh environments. In addition, due to the high stability of SiO2 itself, the uniformity and quality of the film thickness can be guaranteed. S30, S50, S90, S101, S104, S1055, and S1056 can be produced by ICP (Inductively Coupled Plasma (inductively coupled plasma) process is used for dry etching. ICP is a commonly used micro-nano processing technology that can achieve highly precise pattern definition and two-dimensional / three-dimensional structure processing, and can prepare micro-nanoscale devices and structures. Moreover, this technology has high selectivity and can perform precise etching between different materials while avoiding the impact on other areas or layers, which helps to realize the processing of complex structures and can be applied to a variety of materials, including silicon, nitrides, oxides, metals, etc., with good versatility and applicability. The high directionality of ICP etching helps to form the anisotropic profile required for smooth vertical sidewalls, as well as a high aspect ratio. It is advantageous for the first nanocolumn structure to have a slight taper because they allow higher mechanical rigidity to withstand further processing steps. S109 and S110 utilize TSV (Through Silicon) Through-silicon-via (Through-silicon-via) technology is used to achieve vertical electrical interconnection. Since CMOS devices require a common-gate and common-drain structure for simultaneous input and output, the gate and drain of pMOS and nMOS devices need to be connected. Specifically, as shown in Figures 8(r) and 8(s), etching is started from the eleventh and twelfth insulating dielectrics at the top to form corresponding through-holes that can contact the gate and drain of nMOS, namely the first deep trench and the second deep trench. Since the nanopillars are separated by insulating dielectrics, electrical isolation has been achieved. Therefore, as long as W or Cu is filled in the through-holes as interconnecting metal, the common gate and common drain of pMOS and nMOS can be achieved.Insulating dielectrics between the longitudinally distributed nanopillar structures S1051-S1057 need to be deposited in multiple steps. During the deposition of the insulating dielectric, source metal is deposited simultaneously to form the first source and the second source, and interconnect metal is deposited to form a common drain and a common gate through the interconnect metal.

[0116] It should be noted that S10~S105, and S1051~S1057 correspond to Figure 8(a) to Figure 8(t) Only a single longitudinally distributed nanopillar structure is shown in the fabrication process. The fabrication process of each longitudinally distributed nanopillar structure in the entire CMOS device can be seen in the following figure. Figure 8(a) to Figure 8(t) .

[0117] Furthermore, the method for preparing a multi-modal nitride semiconductor CMOS array provided by an embodiment of the present invention is as follows: Figure 9 As shown, it also includes:

[0118] S10-1, growing a second P-type epitaxial structure on the substrate layer; the second P-type epitaxial structure includes a fourth barrier layer and a fourth channel layer from bottom to top;

[0119] S10-2, etching a plurality of third deep trenches on the surface of the second P-type epitaxial structure until reaching the surface of the fourth barrier layer;

[0120] S10-3. Deposit a third barrier layer on the fourth channel layer on one side of each third deep trench, and form a second N-type epitaxial structure by the fourth barrier layer, the fourth channel layer and the third barrier layer from bottom to top; here, for the sake of simplicity of process, the fourth barrier layer is used as the first back barrier in the second N-type epitaxial structure, and the fourth channel layer is used as the third channel layer in the second N-type epitaxial structure, that is, the fourth barrier layer is made of the same material as the second back barrier layer, and the third channel layer is made of the same material as the fourth channel layer.

[0121] S10-4, forming a third source, a third gate, and a third drain in sequence on the third barrier layer on one side of each third deep trench;

[0122] S10-5, sequentially forming a fourth source electrode, a fourth gate electrode, and a fourth drain electrode on the fourth channel layer on one side of each third deep trench to obtain a fourth partial structure;

[0123] S10-6, etching the fourth portion of the structure into a plurality of second nanorod structures perpendicular to the substrate layer; wherein each second nanorod structure includes a second P-type epitaxial structure, a second N-type epitaxial structure, a third source, a third gate, and a third drain located on the second N-type epitaxial structure, and a fourth source, a fourth gate, and a fourth drain located on the second P-type epitaxial structure;

[0124] S10-7, depositing an insulating dielectric between adjacent second nanorod structures and in each third deep trench;

[0125] S10-8, depositing interconnect metal on the third gate and the fourth gate of each second nanorod structure, so that the third gate and the fourth gate are connected through the interconnect metal to realize a common gate;

[0126] S10-9. Deposit interconnect metal on the third drain and the fourth drain of each second nano-pillar structure respectively, so that the third drain and the fourth drain are connected to a common drain through the interconnect metal, and complete the preparation to form a nitride semiconductor CMOS array including several laterally distributed nano-pillar structures.

[0127] In embodiments S10-1 to S10-9 of the present invention, S10-1 and S10-3 are fabricated using an MOCVD process; S10-40, S10-5, S10-8, and S10-9 can utilize electron beam evaporation to deposit the corresponding source, drain, and gate materials, as well as interconnect metal; S10-7 can utilize PECVD to deposit the insulating dielectric; and S10-2 and S10-6 can utilize dry etching using an ICP process. Unlike a longitudinally distributed nanopillar structure, a transversely distributed nanopillar structure can simultaneously achieve shared gate and drain interconnection, requiring only the gate and drain electrodes to be connected and led out using interconnect metal.

[0128] Finally, Figure 6 and Figure 7 The prepared longitudinally distributed nanocolumn structure, Figure 9 The prepared laterally distributed nanocolumn structure is bonded to the same substrate to complete the preparation of a multimodal nitride semiconductor CMOS array that supports both lateral and longitudinal modes.

[0129] Since the longitudinally distributed CMOS device proposed in the present invention adopts the nanopillar process as a whole, the setting of the gate, source, and drain electrodes of nMOS and pMOS becomes very critical. The setting of the gate, source, and drain electrodes of traditional nMOS and pMOS needs to consider a series of factors, such as breakdown voltage, transfer output characteristics of the device, etc. Therefore, when nMOS and pMOS are made into nanopillar structures and stacked vertically, the gate, source, and drain electrodes need to be reset. In order not to change the nanopillar structure of the CMOS array and to facilitate the extraction, the embodiment of the present invention makes the gate and drain electrodes of nMOS and pMOS in the form of metal layers, which are separated by an insulating medium in the middle. Unlike conventional MOS processes, the gate, source, and drain of nMOS and pMOS in the embodiment of the present invention are manufactured separately. Specifically, first, a layer of insulating dielectric is grown on the N-type epitaxial structure and the P-type epitaxial structure, respectively. Then, the gate opening area is defined by photolithography, the insulating dielectric on the surface is etched away, and then the gate area is defined by photolithography, the gate metal is sputtered, and then the process is stripped to complete the gate manufacturing. Then, a layer of insulating dielectric is grown and planarized. Then, the drain is manufactured by first photolithography defining the drain opening area, etching away the insulating dielectric on the surface, and then photolithography defining the drain area, sputtering the drain metal, and then stripping to complete the drain manufacturing. As for the source, when the insulating dielectric is deposited between the nano-pillar structures after bonding is completed, when the insulating dielectric is deposited to the corresponding barrier layer in nMOS and the upper part of the channel layer in pMOS, the source area is defined by photolithography, and the source metal is deposited to complete the manufacturing. Because traditional Si-based MOS introduces charge through doping, the doping area is uniform within a certain range, so there are not many restrictions on electrode settings. In the embodiments of the present invention, since the CMOS device is etched into a nanopillar structure, if the electrodes are set on the surface of the barrier layer and channel layer according to the traditional electrode setting method, the gate-drain spacing and the source-drain spacing will be limited. Excessively small source-drain spacing will make it difficult to increase the breakdown voltage of the device and affect the output transfer characteristics of the device. By isolating the source and surrounding the barrier layer in nMOS and the upper part of the channel layer in pMOS in a ring shape, the vertical distance is utilized, thereby improving the gate-drain spacing and the source-drain spacing, ensuring the stability and reliability of the device.

[0130] As for the method embodiment of the second aspect, since it is basically similar to the structural embodiment of the first aspect, the description is relatively simple, and the relevant parts can be referred to the partial description of the structural embodiment of the first aspect.

[0131] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0132] Although the present invention is described herein in conjunction with various embodiments, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the specification and accompanying drawings in the process of implementing the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components or steps. The fact that certain measures are described in different embodiments does not mean that these measures cannot be combined to produce good results.

[0133] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A multi-mode nitride semiconductor CMOS array, characterized in that: The array includes a plurality of longitudinally distributed nanocolumn structures; an insulating medium is filled between adjacent longitudinally distributed nanocolumn structures; wherein, Each longitudinally distributed nanocolumn structure includes: A first N-type epitaxial structure is located on the substrate layer; the first N-type epitaxial structure includes, from bottom to top, a first back barrier layer, a first channel layer, and a first barrier layer; a first P-type epitaxial structure located above the first N-type epitaxial structure, the first N-type epitaxial structure and the first P-type epitaxial structure being isolated by an insulating medium; the first P-type epitaxial structure including, from bottom to top, a second barrier layer and a second channel layer; a first source electrode and a second source electrode, wherein the first source electrode is located on a side of the first barrier layer and surrounds the first barrier layer in a ring shape, and the second source electrode is located on a side of the second channel layer and surrounds the second channel layer in a ring shape; The first gate and the second gate each include a T-shaped electrode connection portion and an electrode main portion, the electrode connection portion of the first gate being located on a surface of one end of the first barrier layer, the electrode main portion of the first gate being located above the first barrier layer and an insulating medium being filled between the first barrier layer and the electrode connection portion of the second gate being located on a surface of one end of the second channel layer on the same side as the first gate, the electrode main portion of the second gate being located above the second channel layer and an insulating medium being filled between the second channel layer, and the electrode main portions of the first gate and the second gate being connected by an interconnecting metal to realize a common gate; The first drain and the second drain each include a T-shaped electrode connection portion and an electrode main portion. The electrode connection portion of the first drain is located on the surface of the other end of the first barrier layer. The electrode main portion of the first drain is located above the first gate and an insulating medium is filled between the first gate and the first barrier layer. The electrode connection portion of the second drain is located on the surface of the other end of the second channel layer. The electrode main portion of the second drain is located above the second gate and an insulating medium is filled between the second gate and the second channel layer. The electrode main portions of the first drain and the second drain are connected to a common drain through interconnected metal.

2. The multi-mode nitride semiconductor CMOS array according to claim 1, wherein: The material of the first back barrier layer is AlN; the material of the first channel layer and the second channel layer is one of GaN, InGaN, and AlGaN; the material of the first barrier layer and the second barrier layer is one of AlGaN, AlInN, AlN, ScAlN, and AlInGaN.

3. The multi-mode nitride semiconductor CMOS array according to claim 1, wherein: In the first N-type epitaxial structure, the thickness of the first back barrier layer is 3nm to 15nm, the thickness of the first channel layer is 10nm to 50nm, and the thickness of the first barrier layer is 5nm to 30nm; In the first P-type epitaxial structure, the thickness of the second barrier layer is 10 nm to 30 nm, and the thickness of the second channel layer is 10 nm to 50 nm.

4. The multi-mode nitride semiconductor CMOS array according to claim 1, wherein: The diameter of each longitudinally distributed nanocolumn structure is 10nm to 40nm, and the aspect ratio is 20:1 to 50:

1.

5. The multi-mode nitride semiconductor CMOS array according to claim 1, wherein: The array further includes a plurality of laterally distributed nanocolumn structures, and an insulating medium is filled between adjacent laterally distributed nanocolumn structures; wherein, Each laterally distributed nanocolumn structure includes: a second N-type epitaxial structure located on the substrate layer; the second N-type epitaxial structure comprises, from bottom to top, a second back barrier layer, a third channel layer, and a third barrier layer; a second P-type epitaxial structure located on one side of the second N-type epitaxial structure, with an insulating dielectric filled between the second P-type epitaxial structure and the second N-type epitaxial structure; the second P-type epitaxial structure includes, from bottom to top, a fourth barrier layer and a fourth channel layer; wherein the fourth barrier layer and the second back barrier layer are made of the same material, and the third channel layer and the fourth channel layer are made of the same material; a third source electrode and a fourth source electrode, the third source electrode being located on an upper surface of one end of the third barrier layer, and the fourth source electrode being located on an upper surface of one end of the fourth channel layer; a third drain and a fourth drain, the third drain being located on an upper surface at the other end of the third barrier layer, and the fourth drain being located on an upper surface at the other end of the fourth channel layer; the third drain and the fourth drain being connected to each other via an interconnecting metal to realize a common drain; The third gate and the fourth gate, the third gate is located on the upper surface of the third barrier layer between the third source and the third drain, the fourth gate is located on the upper surface of the fourth channel layer between the fourth source and the fourth drain, and the third gate and the fourth gate are connected to each other through interconnected metal to realize a common gate.

6. The multi-mode nitride semiconductor CMOS array according to claim 5, characterized in that: The material of the two back barrier layers is AlN; the material of the third channel layer and the fourth channel layer is one of GaN, InGaN, and AlGaN; the material of the third barrier layer and the fourth barrier layer is one of AlGaN, AlInN, AlN, ScAlN, and AlInGaN.

7. A method for preparing a multimodal nitride semiconductor CMOS array, characterized in that: The preparation method comprises: Growing a first N-type epitaxial structure on the substrate layer; the first N-type epitaxial structure includes a first back barrier layer, a first channel layer and a first barrier layer from bottom to top; growing a first insulating dielectric on the first barrier layer; Etching a plurality of first grooves on the surface of the first insulating medium until reaching the upper surface of the first barrier layer, and depositing gate metal in each first groove and around the first groove to form an electrode connection portion and an electrode main portion corresponding to the first gate; Continuing to grow a second insulating medium on the first insulating medium and the electrode main body portions of all the first gates; Etching a plurality of second grooves on the surface of the second insulating medium until reaching the upper surface of the first barrier layer, and depositing drain metal in each second groove and around the second groove to respectively form an electrode connection portion and an electrode main portion corresponding to the first drain; wherein the electrode main portion of each first drain is located above the electrode main portion corresponding to the first gate; Continuing to grow a third insulating medium on the electrode main body portions of all first drain electrodes to prepare a first partial structure; Obtaining a first P-type epitaxial structure; the first P-type epitaxial structure includes, from bottom to top, a second barrier layer and a second channel layer; Growing a fourth insulating medium on the lower surface of the second barrier layer and the upper surface of the second channel layer respectively; Etching a plurality of third grooves on the surface of the fourth insulating medium until reaching the upper surface of the second barrier layer, and depositing gate metal in and around each third groove to form an electrode connection portion and an electrode main portion corresponding to the second gate; Continue growing a fifth insulating medium on the fourth insulating medium and the electrode main body portions of all the second gates; Etching a plurality of fourth grooves on the surface of the fifth insulating medium until reaching the upper surface of the second barrier layer, and depositing drain metal in and around each of the fourth grooves to form an electrode connection portion and an electrode main portion corresponding to the second drain, respectively; wherein the electrode main portion of each second drain is located above the electrode main portion corresponding to the second gate; Continuing to grow a sixth insulating dielectric on the electrode main body portions of all second drain electrodes to prepare a second partial structure; Bonding the top end of the first structure and the bottom end of the second structure together to prepare a third structure; Etching the third portion of the structure into a plurality of first nanorod structures perpendicular to the substrate layer; wherein each first nanorod structure includes a first N-type epitaxial structure, a first P-type epitaxial structure, a first drain and a first gate located on the first N-type epitaxial structure, and a second drain and a second gate located on the first P-type epitaxial structure; An insulating medium is grown between adjacent first nanocolumn structures until the insulating medium grown between the adjacent first nanocolumn structures is flush with the upper surface of the sixth insulating medium, completing the preparation and forming a nitride semiconductor CMOS array including a plurality of longitudinally distributed nanocolumn structures; wherein, in the process of growing the insulating medium between the adjacent first nanocolumn structures, a first source and a second source are formed, and an interconnecting metal is deposited so that the main electrode parts of the first gate and the second gate are connected through the interconnecting metal to realize a common gate, and the main electrode parts of the first drain and the second drain are connected through the interconnecting metal to realize a common drain.

8. The method for preparing a multi-modal nitride semiconductor CMOS array according to claim 7, wherein: The process of growing an insulating medium between adjacent first nanocolumn structures until the insulating medium grown between the adjacent first nanocolumn structures is flush with an upper surface of a sixth insulating medium includes: Growing a seventh insulating medium between adjacent first nanorod structures until it is a certain distance from the lower surface of the first barrier layer, and depositing a circle of source metal on the exposed side of the first barrier layer to form a first source electrode; Continue growing an eighth insulating medium between adjacent first nanorod structures until it is flush with the lower surface of the electrode main portion of the first gate, and deposit a first portion of interconnect metal on one side of the exposed electrode main portion of the first gate, wherein the first portion of interconnect metal contacts the electrode main portion of the first gate; Continue growing a ninth insulating dielectric between adjacent first nanorod structures until it is flush with the lower surface of the main portion of the electrode of the first drain electrode, and deposit a second portion of interconnecting metal on one side of the exposed main portion of the electrode of the first drain electrode, so that the second portion of interconnecting metal contacts the main portion of the electrode of the first drain electrode; Continue growing a tenth insulating medium between adjacent first nanorod structures until it is a certain distance from the lower surface of the second channel layer, and deposit a circle of source metal on the exposed side of the second channel layer to form a second source electrode; Continuing to grow an eleventh insulating dielectric between adjacent first nanopillar structures until it is flush with the lower surface of the electrode main portion of the second gate, etching away a portion of the eleventh insulating dielectric until a first deep trench is formed on the surface of the first portion of the interconnection metal, depositing a third portion of the interconnection metal within and around the first deep trench, the third portion of the interconnection metal contacting the electrode main portion of the second gate, so that the electrode main portions of the first gate and the second gate are connected via the third portion of the interconnection metal to achieve a common gate; Continue growing a twelfth insulating dielectric between adjacent first nanorod structures until it is flush with the lower surface of the electrode main portion of the second drain electrode, etch away a portion of the twelfth insulating dielectric until a second deep trench is formed on the surface of the second portion of the interconnection metal, and deposit a fourth portion of the interconnection metal in and around the second deep trench, the fourth portion of the interconnection metal being in contact with the electrode main portion of the second drain electrode, so that the electrode main portions of the first drain electrode and the second drain electrode are connected via the fourth portion of the interconnection metal to achieve a common drain; The thirteenth insulating medium continues to grow between adjacent first nanorod structures until it is flush with the upper surface of the sixth insulating medium.

9. The method for preparing a multi-modal nitride semiconductor CMOS array according to claim 7, wherein: Bonding the top end of the first structure and the bottom end of the second structure together, comprising: The top end of the first structure and the bottom end of the second structure are bonded together using a low-temperature vacuum bonding process. The low-temperature vacuum bonding process includes: Annealing is performed at a temperature of 150° C. to 200° C. in a vacuum environment, so that the third insulating medium at the top of the first part structure and the fourth insulating medium at the bottom of the second part structure are bonded and grown together.

10. The method for preparing a multi-modal nitride semiconductor CMOS array according to claim 7, wherein: The preparation method further comprises: growing a second P-type epitaxial structure on the substrate layer; the second P-type epitaxial structure includes a fourth barrier layer and a fourth channel layer from bottom to top; Etching a plurality of third deep trenches on the surface of the second P-type epitaxial structure until reaching the surface of the fourth barrier layer; Depositing a third barrier layer on the fourth channel layer on one side of each third deep trench, forming a second N-type epitaxial structure by the fourth barrier layer, the fourth channel layer and the third barrier layer from bottom to top; forming a third source electrode, a third gate electrode and a third drain electrode in sequence on the third barrier layer on one side of each third deep trench; forming a fourth source electrode, a fourth gate electrode, and a fourth drain electrode in sequence on the fourth channel layer on one side of each third deep trench to obtain a fourth partial structure; Etching the fourth portion of the structure into a plurality of second nanorod structures perpendicular to the substrate layer; wherein each second nanorod structure includes a second P-type epitaxial structure, a second N-type epitaxial structure, a third source, a third gate, and a third drain located on the second N-type epitaxial structure, and a fourth source, a fourth gate, and a fourth drain located on the second P-type epitaxial structure; depositing an insulating dielectric between adjacent second nanorod structures and within each third deep trench; Depositing interconnect metal on the third gate and the fourth gate of each second nanorod structure respectively, so that the third gate and the fourth gate are connected through the interconnect metal to realize a common gate; Interconnect metal is deposited on the third drain and the fourth drain of each second nano-pillar structure respectively, so that the third drain and the fourth drain are connected to each other through the interconnect metal to realize a common drain, and the preparation is completed to form a nitride semiconductor CMOS array including several laterally distributed nano-pillar structures.

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