A seven-level inverter circuit and control method thereof

Abstract

The present invention discloses a seven-level inverter circuit and a control method thereof. The seven-level inverter circuit comprises: an input DC power supply, a low-frequency pole-changing bridge arm, a high-frequency level selection bridge arm, an inverter-side inductor and a filter capacitor; by controlling the on-off of a switch tube, the inverter bridge arm composed of two bridge arms can output 0, V dc / 4, V dc / 2, V dc ,‑V dc / 4, ‑V dc / 2, ‑V dc Seven levels; the present invention controls the amount of charge to make the seven-level inverter circuit work in a mixed conduction mode (CCM and TPCM). The seven-level inverter circuit works at a fixed frequency and works in fixed-frequency critical continuous conduction in TPCM, which can significantly reduce the amplitude of the inductor current on the inverter side, that is, reduce the conduction loss of the seven-level inverter circuit, and effectively improve the low-frequency distortion of the output current.

Description

Technical Field

[0001] The present invention relates to the technical field of seven-level inverter circuit control, and in particular to a seven-level inverter circuit and a control method thereof. Background Art

[0002] With the continuous development of industry, the performance requirements for power supplies are also increasing, and the research on seven-level inverter circuits is becoming more and more in-depth. The discontinuous conduction mode (DCM) and boundary conduction mode (BCM) of the seven-level inverter circuit do not require auxiliary circuits to achieve soft switching of the switch tube, and the inductance required on the inverter side is smaller than that of the continuous conduction mode (CCM). However, the switching frequency of BCM is not fixed, which is difficult to control, low-frequency harmonics are difficult to filter, and the current stress is large; the DCM frequency is fixed but the current stress is greater, which will cause greater conduction losses. Summary of the invention

[0003] Technical purpose: In view of the shortcomings of the existing seven-level inverter circuit working mode, the present invention discloses a seven-level inverter circuit and a control method thereof, which can select a reasonable working mode according to the expected working state of the seven-level inverter circuit, work in DCM when light load, and work in trapezium conduction mode (TPCM) when heavy load, realize fixed frequency operation, and a control method combining DCM and TPCM, which effectively reduces current stress and reduces low-frequency harmonics.

[0004] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution:

[0005] A seven-level inverter circuit, comprising:

[0006] Input DC power supply, used to provide DC voltage V dc ;

[0007] The high-frequency level selection bridge arm has a positive input terminal connected to the positive pole of the input DC power supply, a negative input terminal connected to the negative pole of the input DC power supply, and an output terminal connected to the positive pole of the inverter side inductor, which is used to output 0, V dc / 4, V dc / 2, V dc Four voltage levels;

[0008] The low-frequency polarity changing bridge arm, the positive input end is connected to the positive input end of the high-frequency level selection bridge arm, the negative input end is connected to the negative input end of the high-frequency level selection bridge arm, and the midpoint of the bridge arm is connected to the negative electrode of the filter capacitor. It is used for single power supply bipolar inversion. The low-frequency polarity changing bridge arm and the high-frequency level selection bridge arm constitute the inverter bridge arm, which is used to output 0, V dc / 4, V dc / 2, V dc , -V dc / 4, -V dc / 2, -V dc Seven voltage levels;

[0009] The inverter side inductor L has a negative electrode connected to the positive electrode of the filter capacitor C0, and a positive electrode connected to the output end of the high frequency level selection bridge arm;

[0010] The filter capacitor C0, with its positive electrode connected to the positive electrode of the load and its negative electrode connected to the negative electrode of the load, is used to filter out the harmonics of the high-frequency level selection bridge arm operating frequency and output the output voltage V of the desired frequency. g .

[0011] The present invention further provides a control method for a seven-level inverter circuit, which is used to control the above-mentioned seven-level inverter circuit, comprising:

[0012] Sample output voltage V g and output current I g , and the output current I g The reference current I ref By comparison, an error signal is obtained;

[0013] The error signal is input to the PID regulator, and the desired inverter bridge arm output charge Q is calculated through the PID algorithm. b ;

[0014] According to the desired inverter bridge arm output charge Q b , inverter side inductor L and current output voltage V g , select the working mode;

[0015] According to the selected working mode, calculate the duty cycle of each power switch tube;

[0016] The duty cycle of each power switch tube controls the amount of charge output by the inverter bridge arm, and the desired voltage and current are output through the filter capacitor.

[0017] Beneficial effects: The seven-level inverter circuit and control method provided by the present invention have the following beneficial effects:

[0018] The high-frequency level selection bridge arm and the low-frequency polarity change bridge arm in the seven-level inverter circuit of the present invention together constitute the inverter bridge arm. By adjusting the switch of the power switch tube in the high-frequency level selection bridge arm, the high-frequency level selection bridge arm can output different levels. At the same time, by controlling the switch of the power switch tube in the low-frequency polarity change bridge arm, the output polarity of different levels can be selected. The combination of the two enables the inverter bridge arm to output 0, V dc / 4, V dc / 2, V dc , -V dc / 4, -V dc / 2, -V dc The seven levels enable the seven-level inverter circuit to control the output voltage more finely, meet the needs of different application scenarios, and improve the applicability and flexibility of the system.

[0019] The present invention can select the working mode of the seven-level inverter circuit through charge quantity control, so that the seven-level inverter circuit works in a mixed conduction mode (DCM and TPCM), so that the seven-level inverter circuit can optimize the current waveform under different load conditions, work in DCM when light load, and work in TPCM when heavy load. In particular, when working in TPCM when heavy load, a critical continuous conduction mode can be realized at a fixed frequency, and the current amplitude of the inverter side inductor is effectively reduced, the current stress is reduced, and the low-frequency harmonics are reduced, thereby improving the efficiency and reliability of the seven-level inverter circuit.

[0020] The present invention calculates the duty cycle of each switch tube according to the working mode, so that the switch tube performs on-off operation at the most appropriate time point, thereby reducing switching loss and conduction loss, being able to quickly respond to load changes, and maintaining the stability of output voltage and current. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0022] Figure 1 Schematic diagram of a seven-level inverter circuit of the present invention;

[0023] FIG2 (a) to (j) are circuit structure diagrams of the seven-level inverter circuit of the present invention in ten different working modes;

[0024] Figure 3 It is a flow chart for distinguishing eight working modes of the seven-level inverter circuit of the present invention;

[0025] 4 (a) to (h) are schematic diagrams of the waveforms of the switch tube voltage and the inverter-side inductor current of the seven-level inverter circuit of the present invention in eight working modes;

[0026] Figure 5The figure is a working flow chart of the control method of the seven-level inverter of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be described more clearly and completely below by way of a preferred embodiment in conjunction with the accompanying drawings, but the present invention is not limited to the scope of the embodiment.

[0028] like Figure 1 As shown, a seven-level inverter circuit includes:

[0029] Input DC power supply, used to provide DC voltage V dc ;

[0030] The high-frequency level selection bridge arm has a positive input terminal connected to the positive pole of the input DC power supply, a negative input terminal connected to the negative pole of the input DC power supply, and an output terminal connected to the positive pole of the inverter side inductor, which is used to output 0, V dc / 4, V dc / 2, V dc Four voltage levels;

[0031] The low-frequency polarity changing bridge arm, the positive input end is connected to the positive input end of the high-frequency level selection bridge arm, the negative input end is connected to the negative input end of the high-frequency level selection bridge arm, and the midpoint of the bridge arm is connected to the negative electrode of the filter capacitor. It is used for single power supply bipolar inversion. The low-frequency polarity changing bridge arm and the high-frequency level selection bridge arm constitute the inverter bridge arm, which is used to output 0, V dc / 4, V dc / 2, V dc , -V dc / 4, -V dc / 2, -V dc Seven voltage levels;

[0032] The inverter side inductor L has a negative electrode connected to the positive electrode of the filter capacitor, and a positive electrode connected to the output end of the high frequency level selection bridge arm;

[0033] The filter capacitor C0, with its positive electrode connected to the positive electrode of the load and its negative electrode connected to the negative electrode of the load, is used to filter out the harmonics of the high-frequency level selection bridge arm operating frequency and output the output voltage V of the desired frequency. g .

[0034] The high-frequency level selection bridge arm is composed of a first energy storage capacitor C1, a second energy storage capacitor C2, a third energy storage capacitor C3, a fourth energy storage capacitor C4, a first power switch tube Q1, a second power switch tube Q2, a fifth power switch tube Q5, a sixth power switch tube Q6, a seventh power switch tube Q7, an eighth power switch tube Q8, a first power diode D1 and a second power diode D2;

[0035] The first energy storage capacitor C1, the second energy storage capacitor C2, the third energy storage capacitor C3 and the fourth energy storage capacitor C4 are sequentially connected in series and then connected in parallel on both sides of the input DC power supply, wherein the positive electrode of the first energy storage capacitor C1 is connected to the positive electrode of the input DC power supply, the negative electrode of the fourth energy storage capacitor C4 is connected to the negative electrode of the input DC power supply, and the voltages of the four energy storage capacitors are equal;

[0036] The drain of the first power switch tube Q1 is connected to the positive electrode of the input DC power supply, and the source of the first power switch tube Q1 is connected to the anode of the second power diode D2, the drain of the sixth power switch tube Q6, the cathode of the first power diode D1, the drain of the second power switch tube Q2 and the positive electrode of the inverter side inductor; the anode of the second power switch tube Q2 is connected to the negative electrode of the input DC power supply; the drain of the fifth power switch tube Q5 is connected to the positive electrode of the third energy storage capacitor C3, and the source of the fifth power switch tube Q5 is connected to the source of the sixth power switch tube Q6; the drain of the seventh power switch tube Q7 is connected to the negative electrode of the fourth energy storage capacitor C4, and the source of the seventh power switch tube Q7 is connected to the anode of the first power diode D1; the source of the eighth power switch tube Q8 is connected to the positive electrode of the second energy storage capacitor C2, and the drain of the eighth power switch tube Q8 is connected to the cathode of the second power diode D2.

[0037] The low-frequency polarity conversion bridge arm is a power polarity conversion bridge composed of a third power switch tube Q3 and a fourth power switch tube Q4 connected in series. The drain of the third power switch tube Q3 is connected to the positive polarity input end of the high-frequency level selection bridge arm, the source of the third power switch tube Q3 is connected to the drain of the fourth power switch tube Q4, and the source of the fourth power switch tube Q4 is connected to the negative polarity input end of the high-frequency level selection bridge arm.

[0038] The specific working principle and all working modes of the seven-level inverter circuit of the present invention are described below in conjunction with Figures 2(a) to 2(j).

[0039] In working mode 1, as shown in FIG2 (a), the fourth power switch tube Q4 is turned on, the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3, the fifth power switch tube Q5, the sixth power switch tube Q6, the seventh power switch tube Q7 and the eighth power switch tube Q8 are turned off, and the output voltage V g The polarity is positive, the output level of the inverter bridge arm is 0, and the voltage on the inverter side inductor is -V g However, the second power switch tube Q2 is turned off, and the current is clamped by the body diode of the second power switch tube Q2 and has no path. The inverter side inductor and the parasitic capacitance of the second power switch tube Q2 resonate, but the amplitude is very low and can be ignored here. The inverter side inductor current is 0.

[0040] In working mode 2, as shown in FIG2( b), the second power switch tube Q2 and the fourth power switch tube Q4 are turned on, the first power switch tube Q1, the third power switch tube Q3, the fifth power switch tube Q5, the sixth power switch tube Q6, the seventh power switch tube Q7 and the eighth power switch tube Q8 are turned off, and the output voltage V g The polarity is positive, the output level of the inverter bridge arm is 0, and the voltage on the inverter side inductor is -V g , the inverter side inductor current flows through the fourth power switch tube Q4, the second power switch tube Q2, and the inverter side inductor.

[0041] In working mode 3, as shown in FIG2(c), the fourth power switch tube Q4 and the seventh power switch tube Q7 are turned on, the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3, the fifth power switch tube Q5, the sixth power switch tube Q6 and the eighth power switch tube Q8 are turned off, and the output voltage V g The output level of the inverter bridge arm is V dc / 4, the voltage on the inverter side inductor is V dc / 4-V g , the inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the seventh power switch tube Q7, the first power diode D1, and the inverter side inductor, V g Less than V dc / 4, the inductor current amplitude on the inverter side increases linearly, V g Greater than V dc / 4, the amplitude of the inverter side inductor current decreases linearly.

[0042] In working mode 4, as shown in FIG2(d), the fourth power switch tube Q4 and the fifth power switch tube Q5 are turned on, the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3, the sixth power switch tube Q6, the seventh power switch tube Q7 and the eighth power switch tube Q8 are turned off, and the output voltage V g The output level of the inverter bridge arm is V dc / 2, the voltage on the inverter side inductor is V dc / 2-V g , the inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the fifth power switch tube Q5, the body diode of the sixth power switch tube Q6, and the inverter side inductor, V g Less than V dc / 2, the inductor current amplitude on the inverter side increases linearly, V g Greater than V dc / 2, the amplitude of the inverter side inductor current decreases linearly.

[0043] In working mode 5, as shown in FIG2( e ), the first power switch tube Q1 and the fourth power switch tube Q4 are turned on, the second power switch tube Q2, the third power switch tube Q3, the fifth power switch tube Q5, the sixth power switch tube Q6, the seventh power switch tube Q7 and the eighth power switch tube Q8 are turned off, and the output voltage V g The output level of the inverter bridge arm is V dc , the voltage on the inverter side inductor is V dc -V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the second energy storage capacitor C2, the first energy storage capacitor C1, the first power switch tube Q1, and the inverter side inductor, and the inverter side inductor current amplitude increases linearly.

[0044] In working mode 6, as shown in FIG2( f), the third power switch tube Q3 is turned on, the first power switch tube Q1, the second power switch tube Q2, the fourth power switch tube Q4, the fifth power switch tube Q5, the sixth power switch tube Q6, the seventh power switch tube Q7 and the eighth power switch tube Q8 are turned off, and the output voltage V g The polarity is negative, the output level of the inverter bridge arm is 0, and the voltage on the inverter side inductor is -V g However, the first power switch tube Q1 is turned off, and the current is clamped by the body diode of the first power switch tube Q1 and has no path. The inverter side inductor and the parasitic capacitance of the power switch tube Q1 resonate, but the amplitude is very low and can be ignored here. The inverter side inductor current is 0.

[0045] In working mode 7, as shown in FIG2(g), the first power switch tube Q1 and the third power switch tube Q3 are turned on, the second power switch tube Q2, the fourth power switch tube Q4, the fifth power switch tube Q5, the sixth power switch tube Q6, the seventh power switch tube Q7 and the eighth power switch tube Q8 are turned off, and the output voltage V g The polarity is negative, the output level of the inverter bridge arm is 0, and the voltage on the inverter side inductor is -V g The inverter side inductor current flows through the inverter side inductor, the first power switch tube Q1, and the third power switch tube Q3, and the amplitude decreases linearly.

[0046] In working mode 8, as shown in FIG2(h), the third power switch tube Q3 and the eighth power switch tube Q8 are turned on, the first power switch tube Q1, the second power switch tube Q2, the fourth power switch tube Q4, the fifth power switch tube Q5, the sixth power switch tube Q6 and the seventh power switch tube Q7 are turned off, and the output voltage V g The output level of the inverter bridge arm is -V dc / 4, the inductor withstand voltage on the inverter side is -V dc / 4-V g, the inverter side inductor current flows through the inverter side inductor, the second power diode D2, the eighth power switch tube Q8, the first energy storage capacitor C1, and the third power switch tube Q3, V g Greater than -V dc / 4, the inductor current amplitude on the inverter side increases linearly, V g Less than -V dc / 4, the amplitude of the inverter side inductor current decreases linearly.

[0047] In working mode 9, as shown in FIG2(i), the third power switch tube Q3 and the sixth power switch tube Q6 are turned on, the first power switch tube Q1, the second power switch tube Q2, the fourth power switch tube Q4, the fifth power switch tube Q5, the seventh power switch tube Q7 and the eighth power switch tube Q8 are turned off, and the output voltage V g The output level of the inverter bridge arm is -V dc / 2, the voltage on the inverter side inductor is -V dc / 2-V g , the inverter side inductor current flows through the inverter side inductor, the sixth power switch tube Q6, the body diode of the fifth power switch tube Q5, the second energy storage capacitor, the first energy storage capacitor, and the third power switch tube Q3, V g Greater than -V dc / 2, the inductor current amplitude on the inverter side increases linearly, V g Less than -V dc / 2, the amplitude of the inverter side inductor current decreases linearly.

[0048] In working mode 10, as shown in FIG2(j), the second power switch tube Q2 and the third power switch tube Q3 are turned on, the first power switch tube Q1, the fourth power switch tube Q4, the fifth power switch tube Q5, the sixth power switch tube Q6, the seventh power switch tube Q7 and the eighth power switch tube Q8 are turned off, and the output voltage V g The output level of the inverter bridge arm is -V dc , the voltage on the inverter side inductor is -V dc -V g The inverter side inductor current flows through the inverter side inductor, the second power switch tube Q2, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the second energy storage capacitor C2, the first energy storage capacitor C1, and the third power switch tube Q3, and the amplitude increases linearly.

[0049] A control method for a seven-level inverter circuit, used for controlling the above-mentioned seven-level inverter circuit, comprises:

[0050] S101, sample output voltage V g and output current I g , and the output current I g The reference current I refThe error signal is obtained by comparison.

[0051] Here the reference voltage I ref is a preset target current value used to compare with the actual output current I g The comparison is performed to generate an error signal. By adjusting the working mode of the seven-level inverter circuit, the actual output current is made as close to the reference current as possible, thereby achieving the purpose of stable output.

[0052] Error signal = I ref -I g Reflects the difference between the actual output and the target output.

[0053] S102, input the error signal to the PID regulator, and calculate the desired inverter bridge arm output charge Q through the PID algorithm b .

[0054] The error signal e is input into the PID regulator, and after proportional, fractional and differential operations, the desired inverter bridge arm output charge Q is calculated. b The function of the PID regulator is to adjust the response of the system so that the output current I g As close as possible to the reference current I ref .

[0055] S103, outputting the charge Q according to the desired inverter bridge arm b , inverter side inductor L and current output voltage V g , select the working mode.

[0056] The selection of the operating mode is based on the polarity and amplitude of the output voltage, which is determined by comparing the output voltage with different classification values ​​of the input DC voltage.

[0057] S104. Calculate the duty cycle of each power switch tube according to the selected working mode.

[0058] The duty cycle determines the proportion of the conduction time of each switch tube in a working cycle, thereby controlling the amount of output charge.

[0059] S105, the duty cycle of each power switch tube controls the output charge of the inverter bridge arm, and outputs the desired voltage and current through the filter capacitor.

[0060] like Figure 5 The flowchart of the control method of the seven-level inverter circuit is shown below. The control method of the seven-level inverter circuit is further described below. First, the output voltage V g The polarity of the output voltage V g When the polarity is positive, the fourth power switch tube Q4 is turned on and the third power switch tube Q3 is turned off; the output voltage V gWhen the voltage is negative, the third power switch Q3 is turned on and the fourth power switch Q4 is turned off; the output voltage V g The working mode and output voltage V of the seven-level inverter circuit when the polarity is positive g The working mode of the seven-level inverter circuit is symmetrical when the polarity is negative, so the output voltage V g Take the positive polarity as an example. Figure 3 As shown in the figure, it is a flow chart for judging the working mode of the seven-level inverter circuit of the present invention. g The input DC power supply voltage is half V dc / 2 comparison, V g <V dc / 2, then the output voltage V g With the input DC supply voltage one quarter V dc / 4 comparison, V g <V dc / 4, determine the expected inverter bridge arm output charge Q b The polarity of the inverter bridge arm is expected to output a charge Q b When it is negative polarity, the seven-level inverter circuit works in working mode 1;

[0061] V g <V dc / 4 and the expected inverter bridge arm output charge Q b When the polarity is positive, the judgment in Example 1 shown in Table 1 is carried out. s Indicates the switching frequency of the high-frequency level selection bridge arm. When Case 1 is established, the seven-level inverter circuit works in working mode 2, that is, the inverter bridge arm outputs V dc / 4, 0, the seven-level inverter circuit works in DCM, and Case 1 is not established. The seven-level inverter circuit works in working mode 3, that is, the inverter bridge arm outputs V dc 、V dc / 4, 0 three levels, the seven-level inverter circuit works in TPCM state;

[0062] V g <V dc / 2 and V g ≥ at V dc / 4, the judgment of Case 2 shown in Table 1 is carried out. Case 2 is established. The seven-level inverter circuit works in working mode 4, that is, the inverter bridge arm outputs V dc / 2, V dc / 4 two levels, the seven-level inverter circuit works in DCM, Case 2 is not established, and the judgment of Case 3 shown in Table 1 is performed. Case 3 is established, and the seven-level inverter circuit works in working mode 5, that is, the inverter bridge arm outputs V dc / 2, V dc / 4, 0, the seven-level inverter circuit works in TPCM. When both Case 2 and Case 3 are not true, the seven-level inverter circuit works in working mode 6, that is, the inverter bridge arm outputs V dc 、V dc / 2, 0 three levels, the seven-level inverter circuit works in TPCM state;

[0063] V g ≥V dc / 2, the judgment case 4 shown in Table 1 is performed. When the judgment case 4 is established, the seven-level inverter circuit works in working mode 7, that is, the inverter bridge arm outputs Vdc, V dc / 2, the seven-level inverter circuit works in DCM. When Case 4 is not true, the seven-level inverter circuit works in working mode 8, that is, the inverter bridge arm outputs V dc 、V dc / 2, 0 three levels, the seven-level inverter circuit works in TPCM state.

[0064] The working mode selection method is as follows Figure 3 shown.

[0065] Table 1

[0066]

[0067] The following is the output voltage V g When the polarity is positive, that is, half the output voltage cycle, the eight working modes of the seven-level inverter circuit are described in detail. In each working mode, the seven-level inverter circuit is in several different working modes.

[0068] Working mode 1: In this working mode, the output voltage V g Positive polarity and V g <V dc / 4, the expected inverter bridge arm output charge Q b It is negative polarity. When there is a phase difference between the output voltage and the output current, it appears near the output voltage zero crossing point. The inverter bridge arm outputs V dc The seven-level inverter circuit operates in DCM with two levels of 0 and 0. The waveform of the inverter-side inductor current in one working cycle is shown in FIG4( a ).

[0069] Interval 1 [t0 - t1]: At t0, the second power switch tube Q2 is turned on, the seven-level inverter circuit is in working mode 2, the output voltage of the inverter bridge arm is 0, and the voltage on the inverter side inductor L is -V g The inverter side inductor current flows through the inverter side inductor L, the second power switch tube Q2, and the fourth power switch tube Q4. The inverter side inductor current is negative and its amplitude increases linearly.

[0070] Interval 2 [t1 - t2]: At t1, the second power switch tube Q2 is turned off, the first power switch tube Q1 is turned on, the seven-level inverter circuit is in working mode 5, and the inverter bridge arm output voltage is V dc , the voltage on the inverter side inductor L is V dc -V g The inverter side inductor current flows through the inverter side inductor L, the first power switch tube Q1, the first energy storage capacitor C1, the second energy storage capacitor C2, the third energy storage capacitor C3, the fourth energy storage capacitor C4, and the fourth power switch tube Q4. The inverter side inductor current is negative and the amplitude decreases linearly. At time t3, the inverter side inductor current linearly decreases to 0, and the first power switch tube Q1 is turned off.

[0071] Interval 3 [t2 - t3]: At t2, the first power switch Q1 is turned off, the seven-level inverter circuit is in working mode 1, the output voltage of the inverter bridge arm is 0, and the voltage on the inverter side inductor L is -V g However, the second power switch tube Q2 is turned off, and the current is clamped by the body diode of the second power switch tube Q2 and has no path. The inverter side inductor L and the parasitic capacitance of the second power switch tube Q2 resonate, but the amplitude is extremely low and can be ignored here. The inverter side inductor current is 0.

[0072] The duty cycles of the second power switch tube Q2 and the first power switch tube Q1 are calculated according to the duty cycle calculation formula group 1 shown in Table 2, and the timing is sequentially non-overlapping. In the duty cycle calculation formula group, d0 represents the duty cycle of the second power switch tube Q2, d1 represents the duty cycle of the seventh power switch tube Q7, d2 represents the duty cycle of the fifth power switch tube Q5, and d4 represents the duty cycle of the first power switch tube Q1.

[0073] Working mode 2: At this time, the output voltage V g Positive polarity and V g <V dc / 4, the expected inverter bridge arm output charge Q b The polarity is positive and Case 1 in Table 1 is established. The inverter bridge arm outputs V dc The seven-level inverter circuit operates in DCM with two levels of / 4 and 0. The waveform of the inverter side inductor current in one working cycle is shown in Figure 4(b).

[0074] Interval 1 [t0 - t1]: At t0, the seventh power switch tube Q7 is turned on, the seven-level inverter circuit is in working mode 3, and the output voltage of the inverter bridge arm is V dc / 4, the voltage on the inverter side inductor L is V dc / 4-V gThe inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the seventh power switch tube Q7, the first power diode D1, and the inverter side inductor L. The inverter side inductor current is positive and its amplitude increases linearly.

[0075] Interval 2 [t1 - t2]: At t1, the seventh power switch tube Q7 is turned off, the second power switch tube Q2 is turned on, the seven-level inverter circuit is in working mode 2, the output voltage of the inverter bridge arm is 0, and the voltage on the inverter side inductor L is -V g The inverter side inductor current flows through the fourth power switch tube Q4, the second power switch tube Q2, and the inverter side inductor L. The inverter side inductor current is positive and its amplitude decreases linearly. At time t3, the inverter side inductor current decreases linearly to 0, and the second power switch tube Q2 is turned off.

[0076] Interval 3 [t2 - t3]: At t2, the second power switch Q2 is turned off, the seven-level inverter circuit is in working mode 1, the inverter bridge arm output voltage is 0, and the inverter side inductor L withstands a voltage of -V g However, the second power switch tube Q2 is turned off, and the current is clamped by the body diode of the second power switch tube and has no path. The inverter side inductor L and the parasitic capacitance of the second power switch tube Q2 resonate, but the amplitude is very low and can be ignored here. The inverter side inductor current is 0.

[0077] The duty cycles of the seventh power switch tube Q7 and the second power switch tube Q2 are calculated according to the duty cycle calculation formula group 2 shown in Table 2, and the timing sequences are sequential and non-overlapping.

[0078] Working mode 3: At this time, the output voltage V g Positive polarity and V g <V dc / 4, the expected inverter bridge arm output charge Q b The polarity is positive and Case 1 in Table 1 does not hold true. The inverter bridge arm outputs V dc 、V dc The seven-level inverter circuit operates in TPCM mode. The inverter side inductor current waveform in one working cycle is shown in Figure 4(c).

[0079] Interval 1 [t0 - t1]: At t0, the first power switch Q1 is turned on, the seven-level inverter circuit is in working mode 5, and the inverter bridge arm output voltage is V dc , the voltage on the inverter side inductor L is V dc -V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the second energy storage capacitor C2, the first energy storage capacitor C1, the first power switch tube Q1, and the inverter side inductor L. The inverter side inductor current is positive and its amplitude increases linearly with a large slope.

[0080] Interval 2 [t1 - t2]: At t1, the first power switch tube Q1 is turned off, the seventh power switch tube Q7 is turned on, the seven-level inverter circuit is in working mode 3, and the output voltage of the inverter bridge arm is V dc / 4. The voltage on the inverter side inductor L is V dc / 4-V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the seventh power switch tube Q7, the first power diode D1, and the inverter side inductor L. The inverter side inductor current is positive and the amplitude continues to increase linearly with a small slope.

[0081] Interval 3 [t2 - t3]: At t2, the seventh power switch tube Q7 is turned off, the second power switch tube Q2 is turned on, the seven-level inverter circuit is in working mode 2, the output voltage of the inverter bridge arm is 0, and the voltage on the inverter side inductor L is -V g The inverter side inductor current flows through the fourth power switch tube Q4, the second power switch tube Q2, and the inverter side inductor. The inverter side inductor current is positive and its amplitude decreases linearly. At time t3, the inverter side inductor current decreases linearly to 0, and the second power switch tube Q2 is turned off.

[0082] The duty cycles of the first power switch tube Q1 , the seventh power switch tube Q7 , and the second power switch tube Q2 are calculated according to the duty cycle calculation formula group 3 shown in Table 2, and the timing sequences are sequentially non-overlapping.

[0083] Working mode 4: At this time, the output voltage V g Positive polarity and V dc / 2>V g >V dc / 4, the expected inverter bridge arm output charge Q b The polarity is positive and Case 2 in Table 1 is established. The inverter bridge arm outputs V dc / 2 and V dc / 4 two levels, the seven-level inverter circuit works in DCM, and the inverter side inductor current waveform in one working cycle is shown in Figure 4(d).

[0084] Interval 1 [t0 - t1]: At t0, the fifth power switch tube Q5 is turned on, the seven-level inverter circuit is in working mode 4, and the output voltage of the inverter bridge arm is V dc / 2, the voltage on the inverter side inductor L is V dc / 2-V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the fifth power switch tube Q5, the body diode of the sixth power switch tube Q6, and the inverter side inductor L. The inverter side inductor current is positive and its amplitude increases linearly.

[0085] Interval 2 [t1 - t2]: At t1, the fifth power switch tube Q5 is turned off, the seventh power switch tube Q7 is turned on, the seven-level inverter circuit is in working mode 3, and the output voltage of the inverter bridge arm is V dc / 4, the voltage on the inverter side inductor L is V dc / 4-V g The inverter side inductor current passes through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the seventh power switch tube Q7, the first power diode D1, and the inverter side inductor current L. The inverter side inductor current is positive and the amplitude decreases linearly. At time t2, the inverter side inductor current decreases linearly to 0, and the seventh power switch tube Q7 is turned off.

[0086] Interval 3 [t2 - t3]: The seven-level inverter circuit is in working mode 1, the inverter bridge arm output voltage is 0, and the inverter side inductor withstand voltage is -V g However, the second power switch tube Q2 is turned off, and the current is clamped by the body diode of the second power switch tube Q2 and has no path. The inverter side inductor and the parasitic capacitance of the second power switch tube Q2 resonate, but the amplitude is very low and can be ignored here. The inverter side inductor current is 0.

[0087] The duty cycles of the fifth power switch tube Q5 and the seventh power switch tube Q7 are calculated according to the duty cycle calculation formula group 4 shown in Table 2, and the timing sequences are sequentially appeared without overlap.

[0088] Working mode 5: At this time, the output voltage V g Positive polarity and V dc / 2>V g >V dc / 4, the expected inverter bridge arm output charge Q b The polarity is positive and the judgment case 2 in Table 1 is not established, the judgment case 3 is established, and the inverter bridge arm outputs V dc / 2, V dc The seven-level inverter circuit operates in TPCM mode. The waveform of the inverter-side inductor current in one working cycle is shown in FIG4( e ).

[0089] Interval 1 [t0 - t1]: At t0, the fifth power switch tube Q5 is turned on, the seven-level inverter circuit is in working mode 4, and the output voltage of the inverter bridge arm is V dc / 2, the voltage on the inverter side inductor L is V dc / 2-V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the fifth power switch tube Q5, the body diode of the sixth power switch tube Q6, and the inverter side inductor L. The inverter side inductor current is positive and its amplitude increases linearly.

[0090] Interval 2 [t1 - t2]: At t1, the fifth power switch tube Q5 is turned off, the seventh power switch tube Q7 is turned on, the seven-level inverter circuit is in working mode 3, and the output voltage of the inverter bridge arm is V dc / 4, the voltage on the inverter side inductor L is V dc / 4-V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the seventh power switch tube Q7, the first power diode D1, and the inverter side inductor L. The inverter side inductor current is positive and its amplitude decreases linearly with a small slope.

[0091] Interval 3 [t2 - t3]: At t2, the seventh power switch tube Q7 is turned off, the second power switch tube Q2 is turned on, the seven-level inverter circuit is in working mode 2, the output voltage of the inverter bridge arm is 0, and the voltage on the inverter side inductor L is -V g The inverter side inductor current flows through the fourth power switch tube Q4, the second power switch tube Q2, and the inverter side inductor L. The inverter side inductor current is positive and the amplitude continues to decrease linearly with a large slope. At time t3, the inverter side inductor current linearly decreases to 0, and the second power switch tube Q2 is turned off.

[0092] The duty cycles of the fifth power switch tube Q5, the seventh power switch tube Q7, and the second power switch tube Q2 are calculated according to the duty cycle calculation formula group 5 shown in Table 2, and the timing sequences are sequentially non-overlapping.

[0093] Working mode 6: At this time, the output voltage V g Positive polarity and V dc / 2>V g >V dc / 4, the expected inverter bridge arm output charge Q b The polarity is positive and both Case 2 and Case 3 in Table 1 are not true. The inverter bridge arm outputs V dc 、V dc The seven-level inverter circuit operates in TPCM mode. The inverter side inductor current waveform in one working cycle is shown in Figure 4(f).

[0094] Interval 1 [t0 - t1]: At t0, the first power switch Q1 is turned on, the seven-level inverter circuit is in working mode 5, and the inverter bridge arm output voltage is V dc , the voltage on the inverter side inductor L is V dc -V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the second energy storage capacitor C2, the first energy storage capacitor C1, the first power switch tube Q1, and the inverter side inductor L. The inverter side inductor current is positive and its amplitude increases linearly with a large slope.

[0095] Interval 2 [t1 - t2]: At t1, the first power switch tube Q1 is turned off, the fifth power switch tube Q5 is turned on, the seven-level inverter circuit is in working mode 4, and the output voltage of the inverter bridge arm is V dc / 2, the voltage on the inverter side inductor L is V dc / 2-V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the fifth power switch tube Q5, the body diode of the sixth power switch tube Q6, and the inverter side inductor L. The inverter side inductor current is positive and the amplitude continues to increase linearly with a small slope.

[0096] Interval 3 [t2 - t3]: At t2, the fifth power switch tube Q5 is turned off, the second power switch tube Q2 is turned on, the seven-level inverter circuit is in working mode 2, the output voltage of the inverter bridge arm is 0, and the voltage on the inverter side inductor L is -V g The inverter side inductor current flows through the fourth power switch tube Q4, the second power switch tube Q2, and the inverter side inductor L. The inverter side inductor current is positive and its amplitude decreases linearly. At time t3, the inverter side inductor current linearly decreases to 0, and the second power switch tube Q2 is turned off.

[0097] The duty cycles of the first power switch tube Q1 , the fifth power switch tube Q5 , and the second power switch tube Q2 are calculated according to the duty cycle calculation formula group 6 shown in Table 2, and the timing sequences are sequentially non-overlapping.

[0098] Working mode 7: At this time, the output voltage V g Positive polarity and V g >V dc / 2, the expected inverter bridge arm output charge Q b The polarity is positive and Case 4 in Table 1 is established. The inverter bridge arm outputs V dc and V dc / 2 two levels, the seven-level inverter circuit works in DCM, and the waveform of the inverter side inductor current in one working cycle is shown in Figure 4(g).

[0099] Interval 1 [t0 - t1]: At t0, the first power switch Q1 is turned on, the seven-level inverter circuit is in working mode 5, and the inverter bridge arm output voltage is V dc , the voltage on the inverter side inductor L is V dc -V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the second energy storage capacitor C2, the first energy storage capacitor C1, the first power switch tube Q1, and the inverter side inductor L. The inverter side inductor current is positive and its amplitude increases linearly.

[0100] Interval 2 [t1 - t2]: At t1, the first power switch tube Q1 is turned off, the fifth power switch tube Q5 is turned on, the seven-level inverter circuit is in working mode 4, and the output voltage of the inverter bridge arm is V dc / 2, the voltage on the inverter side inductor L is V dc / 2-V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the fifth power switch tube Q5, the body diode of the sixth power switch tube Q6, and the inverter side inductor L. The inverter side inductor current is positive and the amplitude decreases linearly. At time t3, the inverter side inductor current linearly decreases to 0, and the fifth power switch tube Q5 is turned off.

[0101] Interval 3 [t2 - t3]: At t2, the fifth power switch Q5 is turned off, the seven-level inverter circuit is in working mode 1, the inverter bridge arm output voltage is 0, and the inverter side inductor L withstands a voltage of -V g However, the second power switch tube Q2 is turned off, and the current is clamped by the body diode of the second power switch tube Q2 and has no path. The inverter side inductor and the parasitic capacitance of the second power switch tube Q2 resonate, but the amplitude is very low and can be ignored here. The inverter side inductor current is 0.

[0102] The duty cycles of the first power switch tube Q1 and the fifth power switch tube Q5 are calculated according to the duty cycle calculation formula group 7 shown in Table 2, and the timing sequences are sequentially non-overlapping.

[0103] Working mode 8: At this time, the output voltage V g Positive polarity and V g >V dc / 2, the expected inverter bridge arm output charge Q b The polarity is positive and Case 4 in Table 1 does not hold true. The inverter bridge arm outputs V dc 、V dc The seven-level inverter circuit operates in TPCM mode. The inverter side inductor current waveform in one working cycle is shown in Figure 4(h).

[0104] Interval 1 [t0 - t1]: At t0, the first power switch Q1 is turned on, the seven-level inverter circuit is in working mode 5, and the inverter bridge arm output voltage is V dc , the voltage on the inverter side inductor L is V dc -V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the second energy storage capacitor C2, the first energy storage capacitor C1, the first power switch tube Q1, and the inverter side inductor L. The inverter side inductor current is positive and its amplitude increases linearly.

[0105] Interval 2 [t1 - t2]: At t1, the first power switch tube Q1 is turned off, the fifth power switch tube Q5 is turned on, the seven-level inverter circuit is in working mode 4, and the output voltage of the inverter bridge arm is V dc / 2, the voltage on the inverter side inductor L is V dc / 2-V g The inverter side inductor current flows through the fourth power switch tube Q4, the fourth energy storage capacitor C4, the third energy storage capacitor C3, the fifth power switch tube Q5, the body diode of the sixth power switch tube Q6, and the inverter side inductor L. The inverter side inductor current is positive and the amplitude decreases linearly with a small slope.

[0106] Interval 3 [t2 - t3]: At t2, the fifth power switch tube Q5 is turned off, the second power switch tube Q2 is turned on, the seven-level inverter circuit is in working mode 2, the output voltage of the inverter bridge arm is 0, and the voltage on the inverter side inductor L is -V g The inverter side inductor current flows through the fourth power switch tube Q4, the second power switch tube Q2, and the inverter side inductor L. The inverter side inductor current is positive and the amplitude continues to decrease linearly with a large slope. At time t3, the inverter side inductor current linearly decreases to 0, and the second power switch tube Q2 is turned off.

[0107] The duty cycles of the first power switch tube Q1 , the fifth power switch tube Q5 , and the second power switch tube Q2 are calculated according to the duty cycle calculation formula group 8 shown in Table 2, and the timing sequences are sequentially non-overlapping.

[0108] Table 2

[0109]

[0110]

[0111] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A seven-level inverter circuit, characterized in that: include: Input DC power supply, used to provide DC voltage V dc ; The high-frequency level selection bridge arm has a positive input terminal connected to the positive pole of the input DC power supply, a negative input terminal connected to the negative pole of the input DC power supply, and an output terminal connected to the positive pole of the inverter side inductor, which is used to output 0, V dc / 4, V dc / 2, V dc Four voltage levels; The low-frequency polarity changing bridge arm, the positive input end is connected to the positive input end of the high-frequency level selection bridge arm, the negative input end is connected to the negative input end of the high-frequency level selection bridge arm, and the midpoint of the bridge arm is connected to the negative electrode of the filter capacitor. It is used for single power supply bipolar inversion. The low-frequency polarity changing bridge arm and the high-frequency level selection bridge arm constitute the inverter bridge arm, which is used to output 0, V dc / 4, V dc / 2, V dc , -V dc / 4, -V dc / 2, -V dc Seven voltage levels; The inverter side inductor L has a negative electrode connected to the positive electrode of the filter capacitor, and a positive electrode connected to the output end of the high frequency level selection bridge arm; The filter capacitor C0, with its positive electrode connected to the positive electrode of the load and its negative electrode connected to the negative electrode of the load, is used to filter out the harmonics of the high-frequency level selection bridge arm operating frequency and output the output voltage V of the desired frequency. g ; The high-frequency level selection bridge arm is composed of a first energy storage capacitor C1, a second energy storage capacitor C2, a third energy storage capacitor C3, a fourth energy storage capacitor C4, a first power switch tube Q1, a second power switch tube Q2, a fifth power switch tube Q5, a sixth power switch tube Q6, a seventh power switch tube Q7, an eighth power switch tube Q8, a first power diode D1 and a second power diode D2; The first energy storage capacitor C1, the second energy storage capacitor C2, the third energy storage capacitor C3 and the fourth energy storage capacitor C4 are sequentially connected in series and then connected in parallel on both sides of the input DC power supply, wherein the positive electrode of the first energy storage capacitor C1 is connected to the positive electrode of the input DC power supply, the negative electrode of the fourth energy storage capacitor C4 is connected to the negative electrode of the input DC power supply, and the voltages of the four energy storage capacitors are equal; The drain of the first power switch tube Q1 is connected to the positive electrode of the input DC power supply, and the source of the first power switch tube Q1 is connected to the anode of the second power diode D2, the drain of the sixth power switch tube Q6, the cathode of the first power diode D1, the drain of the second power switch tube Q2 and the positive electrode of the inverter side inductor; the source of the second power switch tube Q2 is connected to the negative electrode of the input DC power supply; the drain of the fifth power switch tube Q5 is connected to the positive electrode of the third energy storage capacitor C3, and the source of the fifth power switch tube Q5 is connected to the source of the sixth power switch tube Q6; the drain of the seventh power switch tube Q7 is connected to the positive electrode of the fourth energy storage capacitor C4, and the source of the seventh power switch tube Q7 is connected to the anode of the first power diode D1; the source of the eighth power switch tube Q8 is connected to the positive electrode of the second energy storage capacitor C2, and the drain of the eighth power switch tube Q8 is connected to the cathode of the second power diode D2; The low-frequency polarity conversion bridge arm is a power polarity conversion bridge composed of a third power switch tube Q3 and a fourth power switch tube Q4 connected in series. The drain of the third power switch tube Q3 is connected to the positive polarity input end of the high-frequency level selection bridge arm, the source of the third power switch tube Q3 is connected to the drain of the fourth power switch tube Q4, and the source of the fourth power switch tube Q4 is connected to the negative polarity input end of the high-frequency level selection bridge arm.

2. A control method for a seven-level inverter circuit, used to control a seven-level inverter circuit as claimed in claim 1, characterized in that: include: Sample output voltage V g and output current I g , and the output current I g The reference current I ref By comparison, an error signal is obtained; The error signal is input to the PID regulator, and the desired inverter bridge arm output charge Q is calculated through the PID algorithm. b ; According to the desired inverter bridge arm output charge Q b , inverter side inductor L and current output voltage V g , select the working mode; According to the selected working mode, calculate the duty cycle of each power switch tube; The duty cycle of each power switch tube controls the amount of charge output by the inverter bridge arm, and the desired voltage and current are output through the filter capacitor.

3. The control method of a seven-level inverter circuit according to claim 2, characterized in that: Output voltage V g It is divided into positive polarity and negative polarity. The seven-level inverter circuit under each polarity includes eight working modes, and the output voltage V g The working mode and output voltage V of the seven-level inverter circuit when the polarity is positive g When the polarity is negative, the working mode of the seven-level inverter circuit is symmetrical, and the output voltage V g When the polarity is positive, the fourth power switch tube Q4 is turned on and the third power switch tube Q3 is turned off; the output voltage V g When the polarity is negative, the third power switch Q3 is turned on and the fourth power switch Q4 is turned off.

4. The control method of a seven-level inverter circuit according to claim 3, characterized in that: According to the desired inverter bridge arm output charge Q b , inverter side inductor L and current output voltage V g , the working mode selection includes: When V g When the polarity is positive, the output voltage V g With the input DC power supply voltage V dc Compared with half of V g <V dc / 2, then the output voltage V g With the input DC power supply voltage V dc Compared with one quarter of V g <V dc / 4, determine the expected inverter bridge arm output charge Q b The polarity of the inverter bridge arm is expected to output a charge Q b When it is negative polarity, the seven-level inverter circuit works in working mode 1; V g <V dc / 4 and the expected inverter bridge arm output charge Q b When the polarity is positive, the judgment of case 1 is performed. When case 1 is established, the seven-level inverter circuit works in working mode 2. When case 1 is not established, the seven-level inverter circuit works in working mode 3. V g <V dc / 2 and V g ≥ at V dc / 4, conduct case 2 judgment, if case 2 is established, the seven-level inverter circuit works in working mode 4, if case 2 is not established, conduct case 3 judgment, if case 3 is established, the seven-level inverter circuit works in working mode 5, if both case 2 and case 3 are not established, the seven-level inverter circuit works in working mode 6; When Vg≥Vdc / 2, the judgment of Case 4 is performed. When Case 4 is established, the seven-level inverter circuit operates in working mode 7. When Case 4 is not established, the seven-level inverter circuit operates in working mode 8.

5. The control method of a seven-level inverter circuit according to claim 4, characterized in that: The output voltage V g When the polarity is positive, the eight working modes of the seven-level inverter circuit are: Working mode 1, inverter bridge arm output V dc and 0, the working state of the seven-level inverter circuit is DCM; Working mode 2, inverter bridge arm output V dc / 4 and 0, the seven-level inverter circuit works in DCM; Working mode 3, inverter bridge arm output V dc 、V dc / 4 and 0, the seven-level inverter circuit works in TPCM; Working mode 4, inverter bridge arm output V dc / 2 and V dc / 4 two levels, the seven-level inverter circuit works in DCM; Working mode 5, inverter bridge arm output V dc / 2, V dc / 4 and 0, the seven-level inverter circuit works in TPCM; Working mode 6, inverter bridge arm output V dc 、V dc / 2 and 0, the seven-level inverter circuit works in TPCM state; Working mode 7, inverter bridge arm output V dc and V dc / 2 two levels, the seven-level inverter circuit works in DCM; Working mode 8, inverter bridge arm output V dc 、V dc / 2 and 0, the working state of the seven-level inverter circuit is TPCM.

6. The control method of a seven-level inverter circuit according to claim 4, characterized in that: The case 1 is: ; Case 2 is: ; Case 3 is: ; Case 4 is: , where f s Indicates the switching frequency of the high-frequency level selection bridge arm.

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