Method, communication device, chip, and chip system for achieving codeword synchronization

Abstract

The present application provides a method for achieving codeword synchronization, a communication device, a chip, and a chip system, belonging to the field of communication technologies. The method includes: in response to a start signal, entering a synchronization position determination state, and in the synchronization position determination state, determining a synchronization position in a received data sequence, where the synchronization position is used to indicate the starting position of a codeword in the data sequence; in response to determining the synchronization position, entering a loss-of-lock detection state, and in the loss-of-lock detection state, verifying a plurality of codewords selected based on the synchronization position; and in response to a verification failure, re-entering the synchronization position determination state. By adopting the solution of the present application, continuous codeword synchronization can be achieved without the need to additionally insert alignment markers, and transmission resources can be saved.

Description

[0001] This application claims the priority of Chinese patent applications with application numbers 202210113601.8, titled "A Method for Implementing Self-Synchronization of Block Codes Based on State Machines", filed on January 30, 2022, and 202210520888.6, titled "A Method for Implementing Codeword Synchronization, Communication Device, Chip, and Chip System", filed on May 12, 2022. The entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technologies, and particularly to a method for implementing codeword synchronization, a communication device, a chip, and a chip system. Background Art

[0003] Currently, with the development of communication technologies, channel loss and noise have become key factors restricting data transmission rate and distance. The emergence of forward error correction (FEC) provides error correction protection for data in transmission, thereby improving the data transmission rate and transmission distance of the channel. FEC involves block codes, which include linear block codes and non-linear block codes. Linear block codes are widely used in the physical layer of the open system interconnection model (OSI) of Ethernet and the media access control (MAC) sublayer of the data link layer because their encoding and decoding are relatively simple to implement.

[0004] The error detection and error correction functions of linear block codes must be implemented based on a complete code word. Therefore, it is necessary to determine the code word boundary in the data sequence, that is, to find the start and end of a complete code word. This process is called code word synchronization or frame synchronization.

[0005] Currently, there are already synchronization schemes applicable to linear block codes in the industry. Taking the alignment marker (AM) synchronization scheme used in 200 / 400GE within the 802.3 standard as an example, in this scheme, a fixed AM sequence must be inserted at regular intervals of the codewords. The receiving end can identify this AM sequence to perform codeword synchronization. However, the existence of the AM sequence is equivalent to inserting additional data into the data stream transmitted at the sending end, increasing the redundant information. Summary of the Invention

[0006] This application provides a method for implementing codeword synchronization, a communication device, a chip, and a chip system, which can achieve codeword synchronization without inserting an AM, and can save transmission resources.

[0007] In a first aspect, this application provides a method for implementing codeword synchronization. The method includes: in response to a start signal, entering a synchronization position determination state; in this synchronization position determination state, determining a synchronization position in the received data sequence, where the synchronization position is used to indicate the starting position of the codewords in the data sequence; in response to determining the synchronization position, entering a loss-of-lock detection state; in this loss-of-lock detection state, verifying multiple codewords selected based on the synchronization position, and in response to a verification failure, re-entering the synchronization position determination state.

[0008] In the solution shown in this application, in response to a start signal, enter the synchronization position determination state, and in the synchronization position determination state, determine the synchronization position. After determining the synchronization position, enter the loss-of-lock detection state. In the loss-of-lock detection state, once it is determined that the synchronization position does not meet the verification conditions, the synchronization position is re-determined. In this way, this synchronization method is a self-synchronization method, which can achieve codeword synchronization without inserting an AM at the sending end, and can save transmission resources. Moreover, when it is detected that the synchronization position is inaccurate, the synchronization position can be re-determined. Therefore, it can also keep the codewords continuously synchronized. And a state machine is also used to achieve continuous codeword synchronization, which can more accurately achieve continuous codeword synchronization.

[0009] In a possible implementation manner, in this synchronization position determination state, determining a synchronization position in the received data sequence includes: in this synchronization position determination state, selecting N observation bits in the data sequence, and based on the positions where the N observation bits are located, determining the synchronization position, where N is an integer greater than or equal to 1.

[0010] In the solution shown in this application, the observation bits belong to the data sequence, and the positions where the observation bits are located are the positions in the data sequence that may be the synchronization position.

[0011] In a possible implementation manner, based on the positions where the N observation bits are located, determining the synchronization position includes: selecting the synchronization position from the positions where the N observation bits are located.

[0012] In the solution shown in this application, the synchronization position can be directly determined among the positions where N observation bits are located.

[0013] In a possible implementation, the synchronization position determination state includes a first counter reset sub-state and a first codeword verification sub-state; in this synchronization position determination state, when selecting N observation bits from the data sequence and selecting the synchronization position among the positions where the N observation bits are located, it includes: in the first counter reset sub-state, setting the initial value of the first codeword counter and selecting an observation bit from the data sequence; in response to selecting a first test block from the data sequence based on the current observation bit, entering the first codeword verification sub-state, where the length of the first test block is equal to the codeword length, and the start position of the first test block is separated from the position where the current observation bit is located by an integer number of the codeword lengths; in the first codeword verification sub-state, verifying the first test block; in response to the first test block meeting the verification condition, increasing the count value of the first codeword counter by X, where X is an integer greater than or equal to 1; in response to the count value of the first codeword counter being equal to the first threshold, determining the position where the current observation bit is located as the synchronization position.

[0014] In the solution shown in this application, among the test blocks selected using the current observation bit, when a cumulative total of the first threshold number of consecutive test blocks meet the verification condition, determine the position where the current observation bit is located as the synchronization position. In this way, since the number of states of the state machine is small, the synchronization position can be determined quickly.

[0015] In a possible implementation, in this synchronization position determination state, when selecting N observation bits from the data sequence and selecting the synchronization position among the positions where the N observation bits are located, it further includes: in response to the count value of the first codeword counter being less than the first threshold, re-entering the first codeword verification sub-state and performing the verification operation on the next first test block selected based on the current observation bit.

[0016] In a possible implementation, the synchronization position determination state further includes a first codeword valid sub-state; the step of increasing the count value of the first codeword counter by X in response to the first test block meeting the verification condition includes: in response to the first test block meeting the verification condition, entering the first codeword valid sub-state; in the first codeword valid sub-state, increasing the count value of the first codeword counter by X.

[0017] In a possible implementation, in the state where the synchronization position is determined, N observation bits are selected from the data sequence, and the synchronization position is selected from the positions where the N observation bits are located. It further includes: in response to the first test block not meeting the verification condition, performing a verification operation on the next observation bit selected from the data sequence.

[0018] In the solution shown in this application, after the first test block is selected based on the current observation bit, if the first test block does not meet the verification condition, it indicates that the position where the current observation bit is located is not the synchronization position, and it continues to determine whether the next observation bit is the synchronization position. In this way, the synchronization position can be quickly determined.

[0019] In a possible implementation, the synchronization position determination state further includes a first shift sub-state; the performing a verification operation on the next observation bit selected from the data sequence in response to the first test block not meeting the verification condition includes: in response to the first test block not meeting the verification condition, entering the first shift sub-state; in the first shift sub-state, shifting to the next observation bit; in response to shifting to the next observation bit, re-entering the first counter reset sub-state and performing a verification operation on the next observation bit.

[0020] In the solution shown in this application, when the first test block does not meet the verification condition, it enters the first shift sub-state, performs a shift process, shifts to the next observation bit, and re-enters the first counter reset sub-state.

[0021] In a possible implementation, the synchronization position determination state further includes a first synchronization lock initialization sub-state; before setting the initial value of the first codeword counter in the first counter reset sub-state, it further includes: in the first synchronization lock initialization sub-state, setting the value of the first synchronization lock variable to a first value.

[0022] In a possible implementation, the synchronization position determination state further includes a first synchronization lock success sub-state; the determining that the position where the current observation bit is located is the synchronization position in response to the count value of the first codeword counter being equal to a first threshold includes: in response to the count value of the first codeword counter being equal to the first threshold, entering the first synchronization lock success sub-state; in the first synchronization lock success sub-state, setting the value of the first synchronization lock variable to a second value, and the value of the first synchronization lock variable being the second value is used to indicate that the position where the current observation bit is located is the synchronization position.

[0023] In a possible implementation, the method further includes: in the initialization sub-state of the first synchronization lock, setting the value of the first codeword to-be-verified variable to a third value; the response to selecting a first test block from the data sequence based on the current observed bit and entering the first codeword verification sub-state includes: in response to selecting a first test block from the data sequence based on the current observed bit, setting the value of the first codeword to-be-verified variable to a fourth value; in response to the value of the first codeword to-be-verified variable being the fourth value and the value of the first synchronization lock variable being the first value, entering the first codeword verification sub-state.

[0024] In a possible implementation, the out-of-lock detection state includes a second codeword verification sub-state; in the out-of-lock detection state, verifying a plurality of codewords selected based on the synchronization position includes: in response to determining the synchronization position, re-entering the first counter reset sub-state; in response to selecting a first codeword based on the synchronization position, entering the second codeword verification sub-state; in the second codeword verification sub-state, verifying the first codeword.

[0025] In a possible implementation, in the out-of-lock detection state, verifying a plurality of codewords selected based on the synchronization position further includes: in the first counter reset sub-state, setting the initial values of the first codeword counter and the first invalid codeword counter; the response to verification failure and re-entering the synchronization position determination state includes: in response to the first codeword not meeting the verification condition, incrementing the count value of the first codeword counter by Y and incrementing the count value of the first invalid codeword counter by Z, where both Y and Z are integers greater than or equal to 1; in response to the count value of the first invalid codeword counter being equal to a third threshold when the count value of the first codeword counter is less than or equal to a second threshold, re-entering the synchronization position determination state, where the third threshold is less than the second threshold.

[0026] In the solution shown in this application, the synchronization position determination process and the out-of-lock detection process can share some states. Therefore, the process of achieving continuous synchronization of codewords can be simplified.

[0027] In a possible implementation, the synchronization position determination state includes a first shift sub-state; re-entering the synchronization position determination state includes: entering the first shift sub-state; in the first shift sub-state, shifting to the next observed bit; in response to shifting to the next observed bit, re-entering the first counter reset sub-state and performing a verification operation on the next observed bit.

[0028] In a possible implementation, determining the synchronization position based on the positions of the N observed bits includes: selecting alternative positions in the data sequence from among the positions of the N observed bits; and determining the synchronization position based on the alternative positions.

[0029] In the solution shown in this application, the position most likely to be the synchronization position, that is, the alternative position, can be first selected from among the positions of the N observed bits, and then the alternative position can be used to determine the synchronization position, so that the determined synchronization position is more accurate.

[0030] In a possible implementation, N is greater than 1, and the synchronization position determination state includes a second counter reset sub-state and a third codeword verification sub-state; in the synchronization position determination state, N observed bits are selected from the data sequence, and selecting alternative positions in the data sequence from among the positions of the N observed bits includes: in the second counter reset sub-state, setting the initial values of a second codeword counter and a first current valid codeword counter, and selecting one observed bit from the data sequence; in response to selecting a second test block from the data sequence based on the current observed bit, entering the third codeword verification sub-state, where the length of the second test block is equal to the codeword length, and the starting position of the second test block is separated from the position of the current observed bit by an integer number of the codeword lengths; in the third codeword verification sub-state, verifying the second test block, incrementing the count value of the second codeword counter by W, where W is an integer greater than or equal to 1, and in response to the second test block satisfying the verification condition, incrementing the count value of the first current valid codeword counter by P, where P is an integer greater than or equal to 1; in response to the count value of the second codeword counter being equal to a fourth threshold, incrementing the value of an observed bit number variable by 1, in response to the count value of the first current valid codeword counter being greater than the current value of a maximum valid codeword number variable, updating the value of an alternative synchronization position variable to the position of the current observed bit, and updating the current value of the maximum valid codeword number variable to the count value of the first current valid codeword counter; in response to the value of the observed bit number variable being equal to N, determining the value of the current alternative synchronization position variable as the alternative position.

[0031] In the solution shown in this application, N observed bits are continuously verified, and the observed bit with the most test blocks satisfying the verification condition among the N observed bits is selected, and the position of the observed bit is determined as the alternative position. In this way, since each observed bit is verified to select the alternative position, the determined alternative position can be made more accurate, that is, the determined alternative position is more likely to be the synchronization position.

[0032] In a possible implementation, the synchronization position determination state further includes an alternative position selection sub-state; in response to the count value of the second codeword counter being equal to a fourth threshold, incrementing the value of the observed bit number variable by 1, and in response to the count value of the first current valid codeword counter being greater than the current value of the maximum valid codeword number variable, updating the value of the alternative synchronization position variable to the position where the current observed bit is located, and updating the current value of the maximum valid codeword number variable to the count value of the first current valid codeword counter, includes: in response to the count value of the second codeword counter being equal to the fourth threshold, entering the alternative position selection sub-state; in the alternative position selection sub-state, in response to the count value of the second codeword counter being equal to the fourth threshold, incrementing the value of the observed bit number variable by 1, and in response to the count value of the first current valid codeword counter being greater than the current value of the maximum valid codeword number variable, updating the value of the alternative synchronization position variable to the position where the current observed bit is located, and updating the current value of the maximum valid codeword number variable to the count value of the first current valid codeword counter.

[0033] In a possible implementation, in the synchronization position determination state, selecting N observed bits from the data sequence, and among the positions where the N observed bits are located, selecting an alternative position in the data sequence, further includes: in response to the value of the observed bit number variable being less than N, performing a verification operation on the next observed bit selected from the data sequence.

[0034] In a possible implementation, the synchronization position determination state further includes a second shift sub-state; in response to the value of the observed bit number variable being less than N, performing a verification operation on the next observed bit selected from the data sequence, includes: in response to the value of the observed bit number variable being less than N, entering the second shift sub-state; in the second shift sub-state, shifting to the next observed bit; in response to shifting to the next observed bit, re-entering the second counter reset sub-state and performing a verification operation on the next observed bit.

[0035] In a possible implementation, the synchronization position determination state further includes an initialization sub-state for second synchronization lock; before setting the initial values of the second codeword counter and the first current valid codeword counter in the second counter reset sub-state, further includes: in the initialization sub-state for second synchronization lock, setting the value of the observed bit number variable to a fifth value, setting the value of the alternative synchronization position variable to a sixth value, and setting the value of the maximum valid codeword number variable to a seventh value.

[0036] In a possible implementation, the method further includes: in the initialization sub-state of the second synchronization lock, setting the value of the second codeword to-be-verified variable to a third value; the entering the third codeword verification sub-state in response to selecting a second test block from the data sequence based on the current observed bit includes: in response to selecting a second test block from the data sequence based on the current observed bit, setting the value of the second codeword to-be-verified variable to a fourth value; and entering the third codeword verification sub-state in response to the value of the second codeword to-be-verified variable being the fourth value.

[0037] In a possible implementation, in the synchronization position determination state, when selecting N observed bits from the data sequence and selecting an alternative position in the data sequence among the positions where the N observed bits are located, it further includes: in response to the count value of the second codeword counter being less than the fourth threshold, re-entering the third codeword verification sub-state to perform a verification operation on the next second test block selected based on the current observed bit.

[0038] In a possible implementation, the synchronization position determination state includes a third counter reset sub-state and a fourth codeword verification sub-state; in the synchronization position determination state, when selecting N observed bits from the data sequence and selecting an alternative position in the data sequence among the positions where the N observed bits are located, it includes: in the third counter reset sub-state, setting the initial values of the third codeword counter and the first valid codeword counter, and selecting an observed bit from the data sequence; in response to selecting a third test block from the data sequence based on the current observed bit, entering the fourth codeword verification sub-state, where the length of the third test block is equal to the codeword length, and the starting position of the third test block is separated from the position where the current observed bit is located by an integer number of the codeword lengths; in the fourth codeword verification sub-state, verifying the third test block; in response to the third test block meeting the verification conditions, increasing the count value of the third codeword counter by M and increasing the count value of the first valid codeword counter by Q, where both M and Q are integers greater than or equal to 1; in response to the count value of the first valid codeword counter being equal to the sixth threshold when the count value of the third codeword counter is less than or equal to the fifth threshold, determining the position where the current observed bit is located as the alternative position, where the fifth threshold is greater than or equal to the sixth threshold.

[0039] In the solution shown in this application, N observed bits are verified in sequence. When the cumulative number of test blocks that meet the verification conditions in the test blocks selected based on a certain observed bit reaches a certain number, the position where the observed bit is located is determined as the alternative position. By using this method, it is possible not to verify all the observed bits, so the alternative position can be determined quickly.

[0040] In a possible implementation, the synchronization position determination state further includes a second codeword valid sub-state; the step of increasing the count value of the third codeword counter by M and increasing the count value of the first valid codeword counter by Q in response to the third test block satisfying the verification condition includes: entering the second codeword valid sub-state in response to the third test block satisfying the verification condition; in the second codeword valid sub-state, increasing the count value of the third codeword counter by M and increasing the count value of the first valid codeword counter by Q.

[0041] In a possible implementation, the step of selecting N observed bits in the data sequence and selecting an alternative position in the data sequence from the positions where the N observed bits are located in the synchronization position determination state further includes: in the second codeword valid sub-state, in response to the count value of the third codeword counter being equal to the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold, performing a verification operation on the next observed bit selected from the data sequence.

[0042] In a possible implementation, the step of selecting N observed bits in the data sequence and selecting an alternative position in the data sequence from the positions where the N observed bits are located in the synchronization position determination state further includes: in the second codeword valid sub-state, in response to the count value of the third codeword counter being less than the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold, re-entering the fourth codeword verification sub-state and performing a verification operation on the next third test block selected based on the current observed bit.

[0043] In a possible implementation, the synchronization position determination state further includes a first codeword invalid sub-state; the step of selecting N observed bits in the data sequence and selecting an alternative position in the data sequence from the positions where the N observed bits are located in the synchronization position determination state further includes: entering the first codeword invalid sub-state in response to the third test block not satisfying the verification condition; in the first codeword invalid sub-state, increasing the count value of the third codeword counter by M; in response to the count value of the third codeword counter being equal to the fifth threshold, performing a verification operation on the next observed bit selected from the data sequence.

[0044] In a possible implementation, the step of selecting N observed bits in the data sequence and determining an alternative position in the data sequence based on the N observed bits in the synchronization position determination state further includes: in the first codeword invalid sub-state, in response to the count value of the third codeword counter being less than the fifth threshold, re-entering the fourth codeword verification sub-state and performing a verification operation on the next third test block selected based on the current observed bit.

[0045] In a possible implementation, the synchronization position determination state further includes a third shift sub-state; performing a verification operation on the next observed bit selected from the data sequence includes: entering the third shift sub-state; in the third shift sub-state, shifting to the next observed bit; in response to shifting to the next observed bit, re-entering the third counter reset sub-state and performing a verification operation on the next observed bit.

[0046] In a possible implementation, the synchronization position determination state further includes an initialization sub-state of the third synchronization lock; before setting the initial value of the third codeword counter and the initial value of the first valid codeword counter in the third counter reset sub-state, it further includes: in the initialization sub-state of the third synchronization lock, setting the value of the third codeword to-be-verified variable to a third value.

[0047] In a possible implementation, entering the fourth codeword verification sub-state in response to selecting a third test block from the data sequence based on the current observed bit includes: in response to selecting a third test block from the data sequence based on the current observed bit, setting the value of the third codeword to-be-verified variable to a fourth value; in response to the value of the third codeword to-be-verified variable being the fourth value, entering the fourth codeword verification sub-state.

[0048] In a possible implementation, determining the synchronization position based on the alternative position includes: verifying the alternative position, and after successful verification, determining the alternative position as the synchronization position.

[0049] In the solution shown in this application, after selecting the alternative position, the alternative position is verified, and after successful verification, the alternative position is determined as the synchronization position. Since the alternative position is also verified, the determined synchronization position can be made more accurate.

[0050] In a possible implementation, the synchronization position determination state further includes a fourth counter reset sub-state and a fifth codeword verification sub-state; verifying the alternative position and after successful verification, determining the alternative position as the synchronization position includes: in the fourth counter reset sub-state, setting the initial value of the fourth codeword counter, and selecting a fourth test block from the sequence based on the alternative position; in response to selecting a fourth test block from the data sequence based on the alternative position, entering the fifth codeword verification sub-state; in the fifth codeword verification sub-state, verifying the fourth test block; in response to the fourth test block meeting the verification condition, increasing the count value of the fourth codeword counter by R, where R is an integer greater than or equal to 1; in response to the count value of the fourth codeword counter being equal to the seventh threshold, determining the alternative position as the synchronization position.

[0051] In the solution shown in this application, when verifying the fourth test block selected based on the alternative position in sequence and the cumulative number of fourth test blocks that continuously meet the verification conditions reaches a certain number, it is determined that this alternative position is the synchronization position. By using this method, it is possible to determine whether the alternative position is the synchronization position.

[0052] In a possible implementation manner, the synchronization position determination state further includes a third codeword valid sub-state; the step of increasing the count value of the fourth codeword counter by R in response to the fourth test block meeting the verification conditions includes: entering the third codeword valid sub-state in response to the fourth test block meeting the verification conditions; and in the third codeword valid sub-state, increasing the count value of the fourth codeword counter by R.

[0053] In a possible implementation manner, after verifying the alternative position and determining that the alternative position is the synchronization position upon successful verification, it further includes: in response to the count value of the fourth codeword counter being less than the seventh threshold, re-entering the fifth codeword verification sub-state and performing the verification operation on the next fourth test block selected based on the alternative position.

[0054] In a possible implementation manner, after verifying the alternative position and determining that the alternative position is the synchronization position upon successful verification, it further includes: in response to the fourth test block not meeting the verification conditions, re-selecting the alternative position.

[0055] In the solution shown in this application, as long as one fourth test block does not meet the verification conditions, the alternative position is re-selected, which can make the selected alternative position more likely to be the synchronization position.

[0056] In a possible implementation manner, the synchronization position determination state further includes a first re-synchronization sub-state; the step of re-selecting the alternative position in response to the fourth test block not meeting the verification conditions includes: entering the first re-synchronization sub-state in response to the fourth test block not meeting the verification conditions; and in the first re-synchronization sub-state, setting the value of the first re-synchronization lock variable to a second value, and the value of the first re-synchronization lock variable being the second value is used to indicate re-selecting the alternative position in the data sequence.

[0057] In a possible implementation manner, the synchronization position determination state further includes a second synchronization lock success sub-state; the step of determining that the alternative position is the synchronization position in response to the count value of the fourth codeword counter being equal to the seventh threshold includes: entering the second synchronization lock success sub-state in response to the count value of the fourth codeword counter being equal to the seventh threshold; and in the second synchronization lock success sub-state, setting the value of the second synchronization lock variable to a second value, and the value of the second synchronization lock variable being the second value is used to indicate that the alternative position is the synchronization position.

[0058] In a possible implementation, determining the synchronization position based on the alternative position includes: determining the alternative position as the synchronization position.

[0059] In the solution shown in this application, directly determining the alternative position as the synchronization position can quickly determine the synchronization position.

[0060] In a possible implementation, in the out-of-lock detection state, verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, re-entering the synchronization position determination state includes: in the out-of-lock detection state, verifying the codewords in the codeword set selected based on the synchronization position, where the codeword set includes a target number of codewords; in response to the number of codewords that do not meet the verification conditions in the codeword set reaching an eighth threshold, re-entering the synchronization position determination state.

[0061] In the solution shown in this application, after the synchronization position is selected, continuously determining whether the synchronization position is correct can keep the codewords in synchronization. Moreover, since it is to determine whether the number of codewords that do not meet the verification conditions reaches a certain value, and the number of codewords that do not meet the verification conditions is relatively small, so determining whether the synchronization position is accurate according to the number of codewords that do not meet the verification conditions can more quickly determine whether the synchronization position is correct.

[0062] In a possible implementation, the out-of-lock detection state includes a fifth counter reset sub-state and a sixth codeword verification sub-state; in the out-of-lock detection state, verifying the codewords in the codeword set selected based on the synchronization position, where the codeword set includes a target number of codewords; in response to the number of codewords that do not meet the verification conditions in the codeword set reaching an eighth threshold, re-entering the synchronization position determination state includes: in the fifth counter reset sub-state, setting the initial values of a fifth codeword counter and a second invalid codeword counter; in response to selecting a second codeword from the data sequence based on the synchronization position, entering the sixth codeword verification sub-state; in the sixth codeword verification sub-state, verifying the second codeword; in response to the second codeword not meeting the verification conditions, incrementing the count value of the fifth codeword counter by 1 and incrementing the count value of the second invalid codeword counter by 1; in response to the count value of the second invalid codeword counter being equal to the eighth threshold when the count value of the fifth codeword counter is less than the target number, re-entering the synchronization position determination state.

[0063] In the solution shown in this application, after the synchronization position is selected, continuously determining whether the synchronization position is correct can keep the codewords in synchronization.

[0064] In a possible implementation, the out-of-lock detection state further includes a second codeword invalid sub-state; the step of incrementing the count value of the fifth codeword counter by 1 and incrementing the count value of the second invalid codeword counter by 1 in response to the second codeword not satisfying the verification condition includes: entering the second codeword invalid sub-state in response to the second codeword not satisfying the verification condition; and in the second codeword invalid sub-state, incrementing the count value of the fifth codeword counter by 1 and incrementing the count value of the second invalid codeword counter by 1.

[0065] In a possible implementation, in the out-of-lock detection state, verifying the codewords in the codeword set selected based on the synchronization position, where the codeword set includes a target number of codewords; and in response to the number of codewords in the codeword set that do not satisfy the verification condition reaching an eighth threshold, re-entering the synchronization position determination state, further includes: incrementing the count value of the fifth codeword counter in response to the second codeword satisfying the verification condition; and in response to the count value of the fifth codeword counter being equal to the target number, re-entering the fifth counter reset sub-state to perform the next verification of the synchronization position.

[0066] In a possible implementation, the out-of-lock detection state further includes a fourth codeword valid sub-state; the step of incrementing the count value of the fifth codeword counter by 1 in response to the second codeword satisfying the verification condition includes: entering the fourth codeword valid sub-state in response to the second codeword satisfying the verification condition; and in the fourth codeword valid sub-state, incrementing the count value of the fifth codeword counter by 1.

[0067] In a possible implementation, in the out-of-lock detection state, verifying the codewords in the codeword set selected based on the synchronization position, where the codeword set includes a target number of codewords; and in response to the number of codewords in the codeword set that do not satisfy the verification condition reaching an eighth threshold, re-entering the synchronization position determination state, further includes: in the third codeword valid sub-state, re-entering the sixth codeword verification sub-state to perform the verification operation on the next second codeword selected based on the synchronization position in response to the count value of the fifth codeword counter being less than the target number.

[0068] In a possible implementation, in the out-of-lock detection state, verifying the codewords in the codeword set selected based on the synchronization position, where the codeword set includes a target number of codewords; and in response to the number of codewords in the codeword set that do not satisfy the verification condition reaching an eighth threshold, re-entering the synchronization position determination state, further includes: in the second codeword invalid sub-state, re-entering the sixth codeword verification sub-state to perform the verification operation on the next second codeword selected based on the synchronization position in response to the count value of the fifth codeword counter being less than the target number and the count value of the second invalid codeword counter being less than the eighth threshold.

[0069] In a possible implementation, in the out-of-lock detection state, the codewords in the set of codewords selected based on the synchronization position are verified, and the set of codewords includes a target number of codewords; in response to the number of codewords that do not meet the verification conditions in the set of codewords reaching an eighth threshold, re-enter the synchronization position determination state, and further include: in the second codeword invalid sub-state, in response to the count value of the fifth codeword counter being equal to the target number, and the count value of the second invalid codeword counter being less than the eighth threshold, re-enter the fifth counter reset sub-state to perform the next verification on the synchronization position.

[0070] In a possible implementation, the verification condition is that the number of zero elements in the check sequence of the test block or codeword is greater than the synchronization threshold; or, the verification condition is that the number of non-zero elements in the check sequence of the test block or codeword is less than the non-synchronization threshold; or, the verification condition is that the test block or codeword is an error-correctable test block; or, the verification condition is that the re-check bit of the test block or codeword is the same as the original check bit.

[0071] In the solution shown in this application, there are multiple ways to verify the test block or codeword, making the verification of the test block and codeword more flexible.

[0072] In a possible implementation, the start signal includes a system reset or start signal, a data reception failure signal, or a re-synchronization signal.

[0073] In a possible implementation, the data sequence is a bit stream encoded by FEC. In this way, the method of codeword synchronization can be applied to the FEC-encoded bit stream.

[0074] In a second aspect, this application provides a device for implementing codeword synchronization, and the device includes:

[0075] A synchronization position determination module, configured to: in response to a start signal, enter a synchronization position determination state; in the synchronization position determination state, determine a synchronization position in the received data sequence, where the synchronization position is used to indicate the start position of a codeword in the data sequence;

[0076] An out-of-lock detection module, configured to: in response to determining the synchronization position, enter an out-of-lock detection state; in the out-of-lock detection state, verify a plurality of codewords selected based on the synchronization position, and in response to a verification failure, re-enter the synchronization position determination state.

[0077] In a third aspect, this application provides a communication device, and the communication device includes a processor and a memory; at least one computer instruction is stored in the memory; the computer instruction is loaded and executed by the processor to implement the method for implementing codeword synchronization in the first aspect or a possible implementation in the first aspect.

[0078] In a fourth aspect, the present application provides a chip for implementing the implementation codeword synchronization method in the first aspect or possible implementation manners in the first aspect.

[0079] In a fifth aspect, the present application provides a chip system including a cascaded first chip and a second chip; the first chip is used to implement the implementation codeword synchronization method in the first aspect or possible implementation manners in the first aspect; the second chip is used to perform codeword synchronization based on the AM method. Description of the Drawings

[0080] Figure 1 is a schematic diagram of the principle of the state machine provided by an exemplary embodiment of the present application;

[0081] Figure 2 is a schematic diagram of the codeword and the synchronization position provided by an exemplary embodiment of the present application;

[0082] Figure 3 is an application scenario diagram provided by an exemplary embodiment of the present application;

[0083] Figure 4 is an application scenario diagram provided by an exemplary embodiment of the present application;

[0084] Figure 5 is an application scenario diagram provided by an exemplary embodiment of the present application;

[0085] Figure 6 is an application scenario diagram provided by an exemplary embodiment of the present application;

[0086] Figure 7 is a logical schematic diagram of codeword synchronization provided by an exemplary embodiment of the present application;

[0087] Figure 8 is a flowchart of the method for implementing codeword synchronization based on a state machine provided by an exemplary embodiment of the present application;

[0088] Figure 9 is a state diagram for determining the synchronization position provided by an exemplary embodiment of the present application;

[0089] Figure 10 is a state diagram for determining the synchronization position and out-of-lock detection provided by an exemplary embodiment of the present application;

[0090] Figure 11 is a state diagram for determining the alternative position provided by an exemplary embodiment of the present application;

[0091] Figure 12 is a state diagram for determining the alternative position provided by an exemplary embodiment of the present application;

[0092] Figure 13 is a state diagram for determining the status of an alternative position provided by an exemplary embodiment of the present application;

[0093] Figure 14 is a state diagram for determining the verification of an alternative position provided by an exemplary embodiment of the present application;

[0094] Figure 15 is a state diagram for determining the verification of an alternative position provided by an exemplary embodiment of the present application;

[0095] Figure 16 is a state diagram for the out-of-lock detection process provided by an exemplary embodiment of the present application;

[0096] Figure 17 is a state diagram for the out-of-lock detection process provided by an exemplary embodiment of the present application;

[0097] Figure 18 is a state diagram for determining the status of an alternative position provided by an exemplary embodiment of the present application;

[0098] Figure 19 is a schematic structural diagram of a device for achieving codeword synchronization provided by an exemplary embodiment of the present application;

[0099] Figure 20 is a schematic structural diagram of a communication device provided by an exemplary embodiment of the present application;

[0100] Figure 21 is a schematic structural diagram of a communication device provided by an exemplary embodiment of the present application. Detailed implementation manners

[0101] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0102] The following explains some term concepts related to the embodiments of the present application.

[0103] 1. Codeword synchronization refers to the process of determining the start position and end position of a complete codeword in a data sequence. The data sequence can also be referred to as a data stream or a bit stream, and codeword synchronization can also be referred to as frame synchronization.

[0104] 2. A state machine, also known as a finite state machine (FSM), is a mathematical model obtained by refining and abstracting the operations required to implement a specific function. The state machine decomposes all the operations (operations) required for function implementation into finite and interrelated states. Each state includes one or more sub-operations. The transitions between states are triggered by changes in input signals or specific parameters, and the specific parameters are stored in registers and are considered register variables. At any given moment, the state machine can only be in one state.

[0105] When implemented in hardware, the state machine includes combinational logic circuits and registers. The combinational logic circuits are used to perform operations, and the registers are used to store register variables.

[0106] There are various ways to represent a state machine. Among them, the state diagram (state diagram or state transition diagram) is more commonly used due to its intuitiveness. In the state diagram, each state is represented by a rectangle and is divided into upper and lower parts by a horizontal line inside it. The upper part is the state name, and the lower part is the operations that need to be executed within this state. The transitions between states are represented by one-way arrows, and the text on the arrow describes the conditions (conditions) that need to be met for this transition, which is called the transition condition. Figure 1 An example of a single state and its entry and exit conditions is provided. When the state machine enters a state, it first executes the operations within the state, and then checks whether the transition conditions are met. If the transition conditions are met, it enters the corresponding next state.

[0107] In Figure 1 the states are represented by rectangles. This is just an example. The states can also be represented by other shapes such as circles, and the state transitions can also be represented by other arrows or forms. The embodiments of the present application do not make any limitations.

[0108] The background of the present application is described below.

[0109] Due to signal loss and noise, errors occur when signals are transmitted in a channel, affecting the reliability of the communication system. When a signal is in the form of a data sequence composed of multiple bits (bit), the transmission error is specifically manifested as a change in the values of some bits in the data sequence, that is, error bits appear. FEC is a technology for controlling transmission errors in a communication system. In FEC technology, redundant information is sent together with the original data sequence for error recovery during transmission, reducing the bit error rate. FEC can be divided into block codes and convolutional codes according to different processing methods for the data sequence. For block codes, they can be further divided into linear block codes and non-linear block codes. Taking the systematic code in linear block codes as an example, the sending end divides the original data sequence into groups, with each group having a length of k bits. In each group, according to a specific coding rule, n - k bits of redundant information are added. This redundant information is called parity, and finally a codeword with a length of n bits is obtained. Both n and k are integers. In this way, in a codeword with a length of n bits, the first k bits are the original data, also called information bits, and the last n - k bits are parity bits. A complete codeword consists of information bits and parity bits. After the codeword is sent from the sending end and transmitted through the channel to reach the receiving end, if the number of error bits in the codeword is within the error correction range, the receiving end can check and correct the error bits through the decoding process, and restore the received codeword to the original data sent by the sending end, thereby reducing the interference brought by the channel and improving the reliability of the communication system. The error detection and error correction functions of linear block codewords must be based on complete codewords. Therefore, before decoding the data sequence received by the receiving end, it is necessary to determine the boundary of the codeword in the data sequence, that is, find the starting position and ending position of a complete codeword. This process is called codeword synchronization or frame synchronization. If the codeword synchronization is incorrect, that is, the correct starting position cannot be determined, the subsequent decoding process cannot achieve the expected error detection or error correction effect, and may even increase the bit error rate, resulting in the deterioration of the performance of the communication system. It can be seen that codeword synchronization is crucial.

[0110] Taking the systematic code as an example, Figure 2 provides the synchronization position of the codeword. As Figure 2 shown, the length of the entire codeword is n bits, where the first k bits are the original data and the last n - k bits are parity bits. The synchronization position in the data sequence is the starting position of the codeword, that is, the position of the first bit in the codeword. In the data sequence, the number of synchronization positions is multiple, and multiple synchronization positions are correlated, that is, the interval between adjacent synchronization positions is fixed, and this interval is equal to the length of the codeword, simply referred to as the codeword length.

[0111] In the embodiments of the present application, although the system code is used as an example for illustration in the following text, the present application is not limited to the system code and can also be applied to non-system codes. The present application can be applied to all communication systems using linear block codes. Linear block codes include, but are not limited to, Reed-Solomon code (RS code), Bose–Chaudhuri–Hocquenghem code (BCH code), Low-Density Parity-Check code (LDPC code), Hamming code, Golay code, and Reed–Muller code, etc.

[0112] The following describes the hardware devices and application scenarios of the embodiments of the present application.

[0113] The embodiments of the present application can be applied to communication devices using FEC, such as routers, switches, and servers, etc.

[0114] The following gives three application scenarios implemented in combination with the Ethernet standard physical layer. Exemplarily, in the two-stage concatenated FEC scenario, the Reed-Solomon code (RS) in the Ethernet standard is used as the outer FEC (FEC1) of the concatenation. Since the AM scheme has been used for the codeword synchronization of the RS-FEC at the receiving end in the Ethernet standard, the codeword synchronization scheme in the embodiments of the present application can be applied to the inner FEC (FEC2) of the two-stage concatenated FEC. The inner FEC can also be referred to as the first FEC, and the outer FEC can also be referred to as the second FEC.

[0115] Application Scenario 1: The two-stage concatenated FECs are in different chips respectively. The chip where FEC1 is located can follow the transmitter and receiver structures defined by the existing standard, and the AM scheme is used for codeword synchronization during decoding. See Figure 3, at the sending end and the receiving end, FEC1 is often integrated into an application specific integrated circuit (ASIC), and the AM scheme is used for codeword synchronization during decoding. FEC2 is often integrated into components such as clock and data recovery (CDR), retimer, or optical digital signal processor (oDSP), and the scheme of this embodiment of the present application is used for codeword synchronization during decoding. Application scenario 1 is mostly for long-distance or high-rate transmission scenarios, and it is necessary to use FEC2 at the relay node to enhance the error correction ability. Here, when the relay node is an oDSP, the link can transmit optical signals.

[0116] Application scenario 2: The two-stage concatenated FEC is within the same chip at both the sending end and the receiving end. Refer to Figure 4 , at the sending end and the receiving end, FEC1 is integrated into the ASIC, and the AM scheme is used for codeword synchronization during decoding. FEC2 is integrated into the ASIC, and the codeword synchronization scheme of this embodiment of the present application is used for codeword synchronization during decoding. In application scenario 2, physical units of FEC2 are additionally added on the sending-end chip and the receiving-end chip.

[0117] Application scenario 3: The two-stage concatenated FEC is within the same chip at one end of the sending end and the receiving end, and within different chips at the other end. The AM scheme is used for codeword synchronization during decoding in FEC1, and the codeword synchronization scheme of this embodiment of the present application is used for codeword synchronization during decoding in FEC2. In this application scenario 3, physical units of FEC2 are added at the end where the two-stage concatenated FEC is within the same chip. At the other end, the sending-end structure or receiving-end structure defined by the Ethernet standard is adopted for FEC1, and FEC2 is integrated into components such as CDR, retimer, or oDSP. Refer to Figure 5 , at the sending end, FEC1 and FEC2 are integrated into the ASIC. At the receiving end, FEC1 is integrated into the ASIC, and FEC2 are all integrated into CDR, retimer, or oDSP. Refer to Figure 6 , at the sending end, FEC1 is integrated into the ASIC, and FEC2 are all integrated into CDR, retimer, or oDSP. At the receiving end, FEC1 and FEC2 are integrated into the ASIC.

[0118] It should be noted that these three application scenarios are described by taking the two-stage concatenated FEC as an example. The codeword synchronization scheme in this embodiment of the present application can also be applied to the scenario of multi-stage concatenated FEC, and it can be applied not only to the inner-layer FEC technology, but also to each layer of FEC technology. This embodiment of the present application does not make any limitations.

[0119] In addition, the embodiments of the present application can also be applied to the scenario of non-cascaded FEC, that is, both the sending end and the receiving end perform FEC once, and the codeword synchronization scheme in the embodiments of the present application can also be applied to this single FEC.

[0120] The following describes the method flow for implementing codeword synchronization based on a state machine in the embodiments of the present application.

[0121] In the embodiments of the present application, the complete synchronization process includes two stages, namely, the synchronization locking stage and the out-of-lock detection stage, thereby forming a closed loop to keep the receiving side of the communication system in the synchronization locking state as much as possible. See Figure 7 . Exemplarily, in the synchronization locking stage, the synchronization position is determined. In the out-of-lock detection stage, it is continuously determined whether the synchronization position is still accurate. When the synchronization position is incorrect, the synchronization position is re-determined.

[0122] In the embodiments of the present application, each state is represented by a rectangle and is divided into upper and lower parts by a horizontal line inside it. The upper part is the state name, and the lower part is the operations to be performed within this state. The representation of the state is only an example, and the embodiments of the present application do not limit this. In the text description, the name of a single state is represented within {}, and the name of a register variable is represented within []. In the state diagram, "+" is logical OR, "*" is logical AND, "!" is logical NOT, "<=" assigns the variable on the right to the variable on the left, and "++" increments the value of the register variable saved in the register by 1. UCT is an unconditional transition.

[0123] Figure 8 The method flow diagram of the embodiments of the present application is provided. This method is applied to a communication device in a communication network, specifically a receiving end device for receiving data. This communication device can be various devices that perform FEC, including but not limited to routers, switches, and servers, etc. The steps of this method include step 801 to step 804.

[0124] Step 801, in response to detecting a start signal, enter the synchronization position determination state.

[0125] In this embodiment, when determining the synchronization position, after detecting the [start signal], trigger the unconditional transition to enter the {synchronization position determination state}.

[0126] Exemplarily, the [start signal] includes a system reset signal, a system start signal, a data reception failure or resynchronization signal. The system reset signal is used to indicate the reconfiguration of the part for decoding in the receiving end, the system start signal is used to indicate the start of the part for decoding in the receiving end. For example, when a data sequence is received, the system start signal will be detected. The data reception failure is used to indicate the decoding failure in the receiving end, and the resynchronization signal is used to indicate the re - determination of the synchronization position.

[0127] Here, the system reset signal, the system start signal, the system reception signal or the resynchronization signal are all register variables, which are respectively represented as [system reset signal], [system start signal], [system reception signal] and [resynchronization signal].

[0128] Step 802: In the state where the synchronization position is determined, the state machine determines the synchronization position in the data sequence, and the synchronization position is used to indicate the starting position of the codeword in the data sequence.

[0129] Among them, the data sequence is received from the sending end. The data sequence includes multiple bits, and each bit is binary data. The data sequence can also be called a bit sequence. The data sequence uses a linear block code. After being transmitted through the channel, there may be error codes, and error detection and error correction operations need to be performed.

[0130] In this embodiment, in the {synchronization position determination state}, the state machine determines the synchronization position in the data sequence, and the synchronization position is the starting position of the codeword in the data sequence.

[0131] Step 803: In response to determining the synchronization position, the state machine enters the out - of - lock detection state.

[0132] Among them, the out - of - lock detection state is a state of the state machine, which is represented as {out - of - lock detection state}.

[0133] Step 804: In the out - of - lock detection state, the state machine verifies multiple codewords selected based on the synchronization position, and in response to the verification failure, updates the synchronization position.

[0134] Adopting the solution of this application, there is no need to insert additional overhead bits in the data sequence sent by the sending end, and the codeword synchronization of the data sequence can be achieved at the receiving end, and the synchronization reliability is relatively high. Moreover, after the synchronization position is determined, a out - of - lock detection mechanism is also used to judge whether the synchronization position is still accurate, further improving the synchronization reliability.

[0135] Regarding step 802, the process of determining the synchronization position is specifically as follows:

[0136] In the {synchronous position determination state}, N observation bits are selected from the data sequence. Based on the positions where the observation bits are located, the synchronous position is determined, where N is an integer greater than or equal to 1. Among them, the positions where the observation bits are located may be the synchronous position. There are various ways to select the observation bits, and three possible implementation methods are provided below.

[0137] In one implementation, N observation bits are selected from the data sequence. When N is greater than 1, the intervals between adjacent observation bits among the multiple observation bits are the same.

[0138] In another implementation, during the codeword synchronization process, the concept of a test block is introduced. The test block belongs to the data sequence, and the test block includes multiple bits. The length of the test block is the same as the length of the codeword. It can be considered that each test block simulates a codeword. When N is greater than 1, the N observation bits can be located within the same test block, and the positions of each of the N observation bits within the same test block move backward in sequence. For example, the number of the N observation bits is equal to the length of the test block, that is, the positions of the N observation bits traverse all the bit positions within a single test block. Since the positions of all the bits within a single test block are traversed, it can be considered that the positions of all the bits within a single codeword are traversed, so the determined synchronous position can be more accurate. However, as the number of observation bits increases, the resources consumed during the codeword synchronization process will also increase. Another example is that when the number of the N observation bits is less than the test block length, one observation bit can be selected every M bits within the test block, where M is an integer greater than or equal to 1 and less than n, and n is the number of bits included in the codeword.

[0139] In another implementation, the positions of each of the N observation bits within each test block move backward in sequence. For example, one bit is selected as an observation bit every L*n + M bits, where L is the number of test blocks separated, L is an integer greater than or equal to 1, and the length of the test block is n, that is, the test block includes n bits. By using this method to select the observation bits, the intervals between adjacent observation bits are relatively large, and the correlation between the observation bits is lower, which can reduce the influence of burst errors and further improve the accuracy of codeword synchronization. Here, the number of observation bits is less than or equal to n. When the number of observation bits is equal to n, since the positions of the first bit in each of the multiple test blocks are regarded as an equivalent position, and the position of the i-th bit is regarded as an equivalent position, when the number of observation bits is equal to n, the positions where the N observation bits are located can traverse all the equivalent positions. Then, traversing the N observation bits can traverse all the positions in the multiple test blocks, where i is greater than 1 and less than or equal to n.

[0140] Exemplarily, two possible implementation methods for determining the synchronous position based on the positions where the observation bits are located are provided below.

[0141] In one implementation, a synchronization position is selected among the positions where N observed bits are located.

[0142] In this implementation, the principle of selecting a synchronization position is as follows: observed bits are selected in sequence. Based on each selected observed bit, multiple test blocks are continuously selected. If for a certain observed bit, multiple test blocks all meet the verification condition, then the position where this observed bit is located is determined as the synchronization position. The positions of multiple test blocks in the data sequence can be continuous or discontinuous. For the convenience of description, in this implementation, the test blocks are referred to as first test blocks. The number of multiple test blocks can be set according to empirical values or according to the results of simulation analysis. In the embodiments of the present application, a test block meeting the verification condition means that the test block is an acceptable grouped codeword, and a test block not meeting the verification condition means that the test block is not an acceptable grouped codeword. Here, a test block being an acceptable grouped codeword is based on the current verification method considering the test block as an acceptable grouped codeword.

[0143] Specifically, Figure 9 a schematic diagram for implementing codeword synchronization is provided. As Figure 9 shown, {synchronization position determination state} includes {first counter reset sub-state} and {first codeword verification sub-state}. The {first counter reset sub-state} is the state for resetting the counter required in the codeword synchronization process, and the {first codeword verification sub-state} is the state for verifying the test block. Based on the positions where N observed bits are located, the processing method for selecting the synchronization position is as follows:

[0144] In the {first counter reset sub-state}, the initial value of [first codeword counter] is set, and this initial value can be 0 or other values. An observed bit is selected from the received data sequence, and a first test block is selected from the data sequence based on this observed bit. The starting position of the first test block is separated from the current observed bit by an integer number of codeword lengths. The method for selecting the observed bit refers to the previous description and will not be elaborated here.

[0145] In response to selecting a first test block, enter the {first codeword verification sub-state}. In the {first codeword verification sub-state}, the first test block is verified. In response to the first test block meeting the verification condition, the count value of [first codeword counter] is incremented by X, where X is a value greater than or equal to 1.

[0146] Judge the magnitude relationship between the count value of [first codeword counter] and the first threshold. In response to the count value of [first codeword counter] being equal to the first threshold, determine the position where the current observed bit is located as the synchronization position.

[0147] Among them, when X is equal to 1, the first threshold is the number of first test blocks selected based on the observed bits. When X is greater than 1, the first threshold is X times the number of first test blocks selected based on the observed bits.

[0148] Optionally, in response to the count value of [the first codeword counter] being less than the first threshold, the next first test block is selected based on the current observed bits, the next first test block is selected from the data sequence based on the current observed bits, and the next first test block is verified. Here, when selecting the next first test block based on the current observed bits, the first test blocks are sequentially selected from the front to the back in the data sequence, and the intervals between adjacent first test blocks can be equal or unequal, and the positions of adjacent first test blocks in the data sequence can be adjacent or non - adjacent.

[0149] Optionally, {synchronization position determination state} further includes {first codeword valid sub - state}. In response to the first test block satisfying the verification condition, enter the {first codeword valid sub - state}. In the {first codeword valid sub - state}, increase the count value of [the first codeword counter] by X.

[0150] Optionally, in response to the first test block satisfying the verification condition, set the value of [the first codeword valid variable] to the second value. In response to the value of [the first codeword valid variable] being the second value, enter the {first codeword valid sub - state}.

[0151] Optionally, in response to the first test block not satisfying the verification condition, select the next observed bit from the data sequence and perform the verification operation on the next observed bit. The verification method for each observed bit is the same. Here, the observed bits are sequentially selected, that is, the observed bits selected continuously twice are sequentially moved backward in the data sequence.

[0152] Optionally, {synchronization position determination state} further includes {first shift sub - state}, and {first shift sub - state} is the state for shifting the observed bits. In response to the first test block not satisfying the verification condition, enter the {first shift sub - state}. In the {first shift sub - state}, shift to the next observed bit in the data sequence, and the shift operation can be implemented by the shift (SLIP) function. In response to shifting to the next observed bit, enter the {first counter reset sub - state} and perform the verification operation on the next observed bit.

[0153] Optionally, after shifting to the next observed bit, set the value of [the first shift completion variable] to true or other values. In response to the value of [the first shift completion variable] being true or other values used to indicate shift completion, enter the {first counter reset sub - state}.

[0154] Each time in the {first counter reset sub-state}, set the value of [first shift completion variable] to false or other values.

[0155] Optionally, in response to the first test block not meeting the verification condition, set the value of [first codeword valid variable] to a first value. In response to the value of [first codeword valid variable] being the first value, enter the {first shift sub-state}.

[0156] Optionally, the {synchronization position determination state} further includes a {first synchronization lock initialization sub-state}, and the {first synchronization lock initialization sub-state} is the state where synchronization starts.

[0157] In response to detecting the [start signal], enter the {first synchronization lock initialization sub-state}. In the {first synchronization lock initialization sub-state}, set the value of [first synchronization lock variable] to a first value, and the first value can be false or 0, etc.

[0158] Optionally, in the {first synchronization lock initialization sub-state}, after setting the value of [first synchronization lock variable] to the first value, enter the {first counter reset sub-state} without a conversion condition.

[0159] Optionally, in the {first synchronization lock initialization sub-state}, set the value of [first codeword to be verified variable] to a third value, and the third value can be false or 0, etc. After selecting a first test block, set the value of [first codeword to be verified variable] to a fourth value, and the fourth value can be true or 1, etc. In response to the value of [first codeword to be verified variable] being the fourth value and the value of [first synchronization lock variable] being set to the first value, enter the {first codeword verification sub-state}. When entering the {first codeword verification sub-state}, set the [first codeword to be verified variable] to the third value.

[0160] Optionally, in the case where the {synchronization position determination state} further includes the {first synchronization lock initialization sub-state}, in response to the count value of [first codeword counter] being equal to a first threshold, set the value of [first synchronization lock variable] to a second value, and the second value can be true or 1, etc. The value of [first synchronization lock variable] being the second value indicates that the position of the current observed bit is the synchronization position.

[0161] Optionally, in the case where the {synchronization position determination state} further includes the {first synchronization lock initialization sub-state}, the {synchronization position determination state} further includes a {first synchronization lock success sub-state}, and the {first synchronization lock success sub-state} is the state where synchronization is completed.

[0162] In response to the count value of the [first codeword counter] being equal to the first threshold, enter the {success sub-state of the first synchronization lock}. In the {success sub-state of the first synchronization lock}, set the value of the [first synchronization lock variable] to a second value, which can be true, 1, etc. The value of the [first synchronization lock variable] being the second value indicates that the position where the current observed bit is located is the synchronization position.

[0163] Optionally, based on the eigenvalue of the first test block, it can be determined whether the first test block meets the verification condition. The eigenvalue of the first test block includes a syndrome, a parity bit, or correctability. When the corresponding eigenvalue is a syndrome, the verification function can be a computer syndrome (CAL_SYNDROME) function. When the corresponding eigenvalue is a parity bit, the verification function can be a compare parity (COMPARE_PARITY) function. When the corresponding eigenvalue is correctability, the verification function can be an error correction (ERROR_CORRECTION) function. The verification function shown in Figure 9 is the CAL_SYNDROME function.

[0164] For example, when the eigenvalue of the first test block is a syndrome, determine whether the number of zero elements in the syndrome is greater than the synchronization threshold. If it is greater than the synchronization threshold, determine that the first test block meets the verification condition and the first test block is an acceptable block codeword; otherwise, determine that the first test block does not meet the verification condition and the first test block is not an acceptable block codeword. Or, determine whether the number of non-zero elements in the syndrome is less than the non-synchronization threshold. If it is less than the non-synchronization threshold, determine that the first test block meets the verification condition and the first test block is an acceptable block codeword; otherwise, determine that the first test block does not meet the verification condition and the first test block is not an acceptable block codeword.

[0165] When the eigenvalue of the first test block is a parity bit, determine whether the parity bit is the same as the original parity bit. If the parity bit is the same as the original parity bit, it can be determined that the first test block meets the verification condition and the first test block is an acceptable block codeword; otherwise, determine that the first test block does not meet the verification condition and the first test block is not an acceptable block codeword.

[0166] When the eigenvalue of the first test block is correctability, determine whether the first test block can be corrected by a decoding algorithm. If it can be corrected by the decoding algorithm, determine that the first test block meets the verification condition and the first test block is an acceptable block codeword; otherwise, determine that the first test block does not meet the verification condition and the first test block is not an acceptable block codeword.

[0167] It should be noted that the above three possible verification methods can all verify the test block, and two or three of the above three possible verification methods can also be used to verify the test block. In addition, other methods can also be used for verification, which is not limited in the embodiments of the present application.

[0168] The principle of verifying that the test block meets the verification conditions and then determining that the position where the observed bit is located is the synchronization position:

[0169] For each linear block codeword, a parity-check matrix can be generated. This parity-check matrix describes the linear relationship between the data within the codeword of the linear block codeword, and this parity-check matrix can be applied to the decoding process. When the data sequence is a linear block codeword, there is also a parity-check matrix for this data sequence, which can be called the parity-check matrix of this data sequence. Specifically, the relationship between the data sequence and the parity-check matrix of the data sequence is shown in Equation (1).

[0170]

[0171] In Equation (1), C is a codeword in the data sequence, S is the parity-check sequence of this codeword, and H is the parity-check matrix of this data sequence. It can be seen from Equation (1) that the parity-check sequence of the codeword in the data sequence is obtained by multiplying the transpose matrix of the parity-check matrix of this data sequence, and the parity-check sequence is a zero vector.

[0172] When this data sequence is the data sequence received by the receiving end, the starting position of the codeword is determined in the data sequence. If the codeword is not selected from the data sequence at the correct starting position, the obtained codeword will no longer satisfy Equation (1). At this time, the parity-check sequence of the codeword in the data sequence can be expressed as Equation (2).

[0173] S R =R·H T (2)

[0174] In Equation (2), R is a codeword in the data sequence received by the receiving end, S R is the parity-check sequence of this codeword, and H is the parity-check matrix of the original data sequence sent by the sending end. The parity-check sequence of the codeword in the data sequence received by the receiving end is the product of this codeword and the transpose matrix of the parity-check matrix of the original data sequence sent by the sending end. It can be seen from Equation (1) and Equation (2) that when the codeword includes an error bit, S R is no longer an all-zero matrix. In this way, the parity-check sequence of the first test block in the data sequence received by the receiving end can be used to determine whether the first test block meets the verification conditions.

[0175] In Figure 9In the state diagram shown, the {initialization sub-state of the first synchronous lock} is denoted as FEC_LOCK_INIT_1, the {first counter reset sub-state} is denoted as RESET_CNT_1, the {first codeword verification sub-state} is denoted as CW_CHECK_1, the {first shift sub-state} is denoted as SLIP_1, and the {successful sub-state of the first synchronous lock} is denoted as FEC_LOCK_GOOD_1. The [first synchronous lock variable] is denoted as fec_cw_sync_1, the [first codeword to be verified variable] is denoted as test_cw_1, the count value of the [first codeword counter] is denoted as cw_cnt_1, setting the value of the [first codeword valid variable] to the second value is denoted as valid_cw_1, setting the value of the [first codeword valid variable] to the first value is denoted as!valid_cw_1, and the [first shift completion variable] is denoted as slip_done_1.

[0176] Another principle for selecting the synchronization position is as follows: Traverse N observed bits and determine the synchronization position among the positions where the N observed bits are located. For example, traverse N observed bits, continuously select the fourth threshold number of test blocks based on each observed bit, determine the number of test blocks that meet the verification conditions among the fourth threshold number of test blocks. The positions of the fourth threshold number of test blocks in the data sequence can be continuous or discontinuous. Determine the position where the observed bit with the largest number of test blocks that meet the verification conditions is located as the synchronization position, or determine the position where the observed bit with the smallest number of test blocks that do not meet the verification conditions is located as the synchronization position. Here, the fourth threshold is the value when W equals 1 in the following text. The fourth threshold can be set according to empirical values or according to the results of simulation analysis.

[0177] Specifically, refer to the description in the following text for the state diagram of determining the synchronization position, which is equivalent to Figure 11 the output signal is the second conversion signal, and the second conversion signal is used to trigger entry into the {loss-of-lock detection state}. Figure 11

[0178] Yet another principle for selecting the synchronization position is as follows: Starting from the first observed bit, sequentially verify whether each observed bit meets the synchronization condition. The synchronization condition can be that among the fifth threshold number of test blocks continuously selected based on the observed bit, at least the sixth threshold number of test blocks meet the verification conditions. The positions of the fifth threshold number of test blocks in the data sequence can be continuous or discontinuous, and the positions of the sixth threshold number of test blocks in the data sequence can be continuous or discontinuous. If an observed bit meets the synchronization condition, determine the position where the observed bit is located as the synchronization position. In this way, it is possible to end the verification of the observed bits in advance and save the resources for determining the synchronization position.

[0179] ​Here, the fifth threshold value is the value when M equals 1 in the following text, and the sixth threshold value is the value when Q equals 1 in the following text. The fifth threshold value and the sixth threshold value can be set according to empirical values or according to the results of simulation analysis.

[0180] Specifically, the state diagram for determining the synchronization position is shown in the following text Figure 12 which is equivalent to Figure 12 The output signal is the second conversion signal, and the second conversion signal is used to trigger the entry into the {out-of-lock detection state}.

[0181] Exemplarily, after determining the synchronization position, enter the {out-of-lock detection state}, Figure 10 A state diagram for implementing the codeword synchronization process by a state machine is provided. In Figure 10 the shown state diagram, the synchronization position determination process and the out-of-lock detection process share the {first counter reset sub-state} and the {first shift sub-state}.

[0182] Specifically, refer to Figure 10 The {out-of-lock detection state} includes the {second codeword verification sub-state}, and the {second codeword verification sub-state} is the state for performing codeword verification. In response to determining the synchronization position, enter the {first counter reset sub-state}, or when the value of [the first synchronization lock variable] is the second value, enter the {first counter reset sub-state} without a conversion condition. In the {first counter reset sub-state}, set the initial values of [the first codeword counter] and [the first invalid codeword counter], and both initial values can be 0. Select a codeword from the data sequence based on the synchronization position. Here, for the convenience of description, the codeword selected based on the synchronization position is called the first codeword.

[0183] In response to selecting a first codeword, enter the {second codeword verification sub-state}. In the {second codeword verification sub-state}, verify the first codeword.

[0184] In response to the first codeword not satisfying the verification condition, increase the count value of the [first codeword counter] by Y, and increase the count value of the [first invalid codeword counter] by Z, where both Y and Z are integers greater than or equal to 1. When the count value of the [first codeword counter] is less than or equal to the second threshold, in response to the count value of the [first invalid codeword counter] being equal to the third threshold, it indicates that the number of invalid codewords has reached the number of updated synchronization positions, and re-enter the {synchronization position determination state} to perform the operation of updating the synchronization position. Among them, when Y is equal to 1, the second threshold is the number of first codewords selected based on the synchronization position. When Y is greater than 1, the second threshold is Y times the number of first codewords selected based on the synchronization position. When Z is equal to 1, the third threshold is the number of first codewords that do not satisfy the verification condition. When Z is greater than 1, the third threshold is Z times the number of first codewords that do not satisfy the verification condition. The second threshold and the third threshold can be set according to empirical values or according to the results of simulation analysis.

[0185] Optionally, it is possible to determine whether the first codeword satisfies the verification condition based on the eigenvalue of the first codeword. The principle is shown in Equations (1) and (2).

[0186] Optionally, the {out-of-lock detection state} further includes a {codeword invalid sub-state}, which is the state entered when the first codeword does not satisfy the verification condition. In response to the first codeword not satisfying the verification condition, enter the {codeword invalid sub-state}. In the {codeword invalid sub-state}, increase the count value of the [first codeword counter] by Y, and increase the count value of the [first invalid codeword counter] by Z.

[0187] Optionally, in response to the count value of the [first codeword counter] being less than the second threshold and the count value of the [first invalid codeword counter] being less than the third threshold, re-enter the {second codeword verification sub-state}. Select the next first codeword based on this synchronization position and verify this next first codeword. Here, the count value of the [first invalid codeword counter] being less than the third threshold indicates that the number of invalid codewords is still relatively small, and the next first codeword can be verified.

[0188] Optionally, in response to the count value of the [first codeword counter] being equal to the second threshold and the count value of the [first invalid codeword counter] being less than the third threshold, re-enter the {first counter reset sub-state} to continue the next verification of the synchronization position. Here, the number of invalid codewords among the second threshold number of first codewords is relatively small, indicating that the synchronization position is still accurate at present and the verification can continue.

[0189] Optionally, in response to the first codeword not satisfying the verification condition, set the value of the [codeword valid variable] to the first value. In response to the value of the [codeword valid variable] being the first value, enter the {codeword invalid sub-state}.

[0190] Optionally, in response to the first codeword satisfying the verification condition, increment the count value of [the first codeword counter] by Y. In response to the count value of [the first codeword counter] being equal to the second threshold, re-enter {the first counter reset sub-state}, indicating that the synchronization position is accurate, and continue to perform the next verification on the synchronization position.

[0191] In response to the count value of [the first codeword counter] being less than the second threshold, re-enter {the second codeword verification sub-state}. Select the next first codeword based on this synchronization position and verify this next first codeword.

[0192] Optionally, the {loss of lock detection state} further includes a {codeword valid sub-state}, which is the state entered when the first codeword satisfies the verification condition. In response to the first codeword satisfying the verification condition, enter the {codeword valid sub-state}.

[0193] Optionally, in response to the first codeword satisfying the verification condition, set the value of [the codeword valid variable] to the second value. In response to the value of [the codeword valid variable] being the second value, enter the {codeword valid sub-state}.

[0194] Optionally, in the case where the {synchronization position determination state} further includes a {first shift sub-state}, the process of re-entering the {synchronization position determination state} is as follows: In response to the count value of [the first invalid codeword counter] being equal to the third threshold, enter the {first shift sub-state}. In the {first shift sub-state}, shift to the next observed bit in the data sequence. In response to shifting to this next observed bit, enter the {first counter reset sub-state} and perform the operation of verifying the next observed bit.

[0195] Optionally, after shifting to the next observed bit, set the value of [the first shift completion variable] to the second value. In response to the value of [the first shift completion variable] being the second value, re-enter the {first counter reset sub-state}. In the {first counter reset sub-state}, set the value of [the first shift completion variable] to the first value and perform the operation of verifying the next observed bit.

[0196] Optionally, after selecting a first codeword, set the value of [the first codeword to be verified variable] to the fourth value. In response to the value of [the first codeword to be verified variable] being the fourth value and the value of [the first synchronization lock variable] being the second value, enter the {second codeword verification sub-state}. After entering the {second codeword verification sub-state}, set [the first codeword to be verified variable] to the third value.

[0197] In Figure 10In the state diagram shown, the {first synchronization lock initialization sub-state} is denoted as FEC_LOCK_INIT_1, the {first counter reset sub-state} is denoted as RESET_CNT_1, the {second codeword verification sub-state} is denoted as CW_CHECK_2, the {codeword valid sub-state} is denoted as VALID_CW_0, the {first shift sub-state} is denoted as SLIP_1, the {first synchronization lock success sub-state} is denoted as FEC_LOCK_GOOD_1, and the {codeword invalid sub-state} is denoted as INVALID_CW_0. [The first synchronization lock variable] is denoted as fec_cw_sync_1, [the first codeword to be verified variable] is denoted as test_cw_1, the count value of [the first codeword counter] is denoted as cw_cnt_1, setting the value of [the codeword valid variable] to the second value is denoted as valid_cw_0, setting the value of [the codeword valid variable] to the first value is denoted as!valid_cw_0, the count value of [the first invalid codeword counter] is denoted as invalid_cw_cnt_1, and [the first shift completion variable] is denoted as slip_done_1.

[0198] In Figure 10 In the state diagram shown, the first test block selected based on the observed bits belongs to the first subsequence, the first codeword selected based on the synchronization position belongs to the second subsequence, both the first subsequence and the second subsequence belong to the data sequence, and the second subsequence is located after the first subsequence.

[0199] In another implementation, in the {synchronization position determination state}, N observed bits are selected from the data sequence, where N is greater than or equal to 1. Among the positions where the N observed bits are located, alternative positions are selected. The synchronization position is determined based on the alternative positions.

[0200] Among them, the alternative position is the position most likely to be the synchronization position. The alternative position can be determined as the synchronization position. Or, multiple test blocks selected based on the alternative position are verified, and after the verification passes, the alternative position is determined as the synchronization position.

[0201] Exemplarily, there are multiple ways to determine the alternative position. Three possible implementation methods are given below. Refer to Method 1 to Method 3.

[0202] In Method 1, traverse N observed bits and determine candidate positions among the positions where the N observed bits are located. For example, traverse the N observed bits, continuously select the fourth-threshold test blocks based on each observed bit, determine the number of test blocks that meet the verification condition in the fourth-threshold test blocks. The positions of the fourth-threshold test blocks in the data sequence can be continuous or discontinuous. Determine the position where the observed bit with the largest number of test blocks that meet the verification condition is located as the candidate position, or determine the position where the observed bit with the smallest number of test blocks that do not meet the verification condition is located as the candidate position. In this way, since the N observed bits are traversed, it is possible to make the determined candidate position most likely to be the synchronization position. In this implementation, the value of N can be the number of bits included in a single codeword.

[0203] Specifically, refer to Figure 11 the state diagram shown in {The synchronization position determination state} includes {The second counter reset sub-state}, {The third codeword verification sub-state}, and {The candidate position selection sub-state}. {The second counter reset sub-state} is the state for resetting the counter, {The third codeword verification sub-state} is the state for verifying the test block, and {The candidate position selection sub-state} is the state for selecting the candidate position.

[0204] In {The second counter reset sub-state}, set the initial values of [the second codeword counter] and [the first current valid codeword counter], select an observed bit from the received data sequence, and based on the current observed bit, select a test block from the data sequence. For the convenience of description, the selected test block is called the second test block. The length of the second test block is equal to the length of the codeword, and one second test block simulates one codeword.

[0205] In response to the selection of the second test block, enter {The third codeword verification sub-state}.

[0206] In {The third codeword verification sub-state}, verify the second test block. The verification method refers to the verification method of the first test block in the previous text and will not be elaborated here. In {The third codeword verification sub-state}, increase the count value of [the second codeword counter] by W. In response to the second test block meeting the verification condition, increase the count value of [the first current valid codeword counter] by P. Both W and P are integers greater than or equal to 1.

[0207] In response to the count value of the [second codeword counter] being equal to the fourth threshold, enter the {alternative position selection sub-state}. Here, when the count value of the [second codeword counter] is equal to the fourth threshold and W = 1, it indicates that the fourth threshold number of second test blocks corresponding to the current observed bit have been verified, and it can be determined whether the position where the current observed bit is located is an alternative position. When W > 1, it indicates that multiple second test blocks corresponding to the current observed bit have been verified, and it can be determined whether the position where the current observed bit is located is an alternative position.

[0208] In the {alternative position selection sub-state}, increment the value of the [observed bit number variable] by 1.

[0209] In the {alternative position selection sub-state}, in response to the count value of the [first current valid codeword counter] being greater than the current value of the [maximum valid codeword number variable], update the value of the [alternative synchronization position variable] to the position where the current observed bit is located, and update the value of the [maximum valid codeword number variable] to the count value of the [first current valid codeword counter]. When the count value of the [first current valid codeword counter] is less than the current value of the [maximum valid codeword number variable], do not update the [alternative synchronization position variable]. When the count value of the [first current valid codeword counter] is equal to the current value of the [maximum valid codeword number variable], the [alternative synchronization position variable] can be updated or not updated.

[0210] In response to the value of the [observed bit number variable] being less than N, perform a verification operation on the next observed bit in the data sequence after the current observed bit. Here, when the value of the [observed bit number variable] is less than N, it indicates that not all N observed bits have been verified, and the next observed bit should be selected and verified.

[0211] In response to the value of the [observed bit number variable] being equal to N, determine the value of the [alternative synchronization position variable] as the alternative position. Optionally, after determining the alternative position, a first conversion signal can be output. The first conversion signal can be the position where the alternative position is located or a signal triggering the entry into the next state.

[0212] In response to the second test block not meeting the verification condition, judge the magnitude relationship between the count value of the [second codeword counter] and the fourth threshold. In response to the count value of the [second codeword counter] being less than the fourth threshold, select the next second test block based on the current observed bit and verify the next second test block. In response to the count value of the [second codeword counter] being equal to the fourth threshold, enter the {alternative position selection sub-state}.

[0213] Optionally, the {synchronization position determination state} further includes a {second synchronization lock initialization sub-state}.

[0214] Before entering the {second counter reset sub-state}, in response to detecting the [start signal], enter the {second synchronization lock initialization sub-state}. In the {second synchronization lock initialization sub-state}, set the value of the [number of observed bits variable] to the fifth value, which can be 0, set the value of the [alternate synchronization position variable] to the sixth value, which can be 0, and set the value of the [maximum number of valid codewords variable] to the seventh value, which can be 0.

[0215] Optionally, after setting these variables, enter the {second counter reset sub-state} without a transition condition.

[0216] Optionally, in the {second synchronization lock initialization sub-state}, set the value of the [second synchronization lock variable] to the first value.

[0217] Optionally, in the {second synchronization lock initialization sub-state}, set the value of the [current position number variable] to 0, etc. In the {alternate position selection sub-state}, increment the value of the [current position number variable] by 1. In this way, by recording the current position variable, the position where the currently traversed observed bit is located can be obtained.

[0218] Optionally, in the {second synchronization lock initialization sub-state}, set the value of the [second codeword to be verified variable] to the third value.

[0219] Optionally, in response to selecting a second test block from the data sequence based on the current observed bit, set the value of the [second codeword to be verified variable] to the fourth value, which can be true or other values. In response to the value of the [second codeword to be verified variable] being the fourth value, enter the {third codeword verification sub-state}. In the {third codeword verification sub-state}, set the value of the [second codeword to be verified variable] to the third value to verify the second test block.

[0220] Optionally, in response to the count value of the [second codeword counter] being less than the fourth threshold and the value of the [second codeword to be verified variable] being the fourth value, re-enter the {third codeword verification sub-state}, select the next second test block based on the current observed bit, and verify the next second test block.

[0221] Optionally, the {synchronous position determination state} further includes a {second shift sub-state}, and the {second shift sub-state} is a state for shifting the observed bits. In response to the value of the [number of observed bits variable] being less than N, indicating that the N observed bits have not been traversed yet, enter the {second shift sub-state}. In the {second shift sub-state}, shift to the position of the next observed bit in the data sequence. In response to shifting to the next observed bit, enter the {second counter reset sub-state} and perform the verification operation on the next observed bit. In this way, all the observed bits can be traversed in this manner, and the most likely alternative positions can be selected from them, which can make the selected alternative positions more accurate.

[0222] Among them, after shifting to the next observed bit, set the value of the [second shift completion variable] to a second value, and the second value is true or other values. In response to the value of the [second shift completion variable] being the second value, enter the {second counter reset sub-state} and perform the operation of verifying the next observed bit. In the {second counter reset sub-state}, set the value of the [second shift completion variable] to a first value, and the first value is false or other values.

[0223] Here, the processing of performing the verification operation on each observed bit is the same. The method of selecting the observed bits can be referred to the description in the previous text and will not be elaborated here.

[0224] In Figure 11 In the state diagram shown, the {second synchronous lock initialization sub-state} is represented as FEC_LOCK_INIT_2, the {second counter reset sub-state} is represented as RESET_CNT_2, the {third codeword verification sub-state} is represented as CW_CHECK_3, the {alternative position selection sub-state} is represented as SELECT_SYNC_LOCK, and the {second shift sub-state} is represented as SLIP_2. The [second synchronous lock variable] is represented as fec_cw_sync_2, the [second codeword to be verified variable] is represented as test_cw_2, the count value of the [second codeword counter] is represented as cw_cnt_2, the [second shift completion variable] is represented as slip_done_2, the [number of observed bits variable] is represented as location_num, the [alternative synchronous position variable] is represented as sync_location, the [maximum number of valid codewords variable] is represented as max_valid_cw_cnt, the [current position number variable] is represented as current_location, and the count value of the [first current valid codeword counter] is represented as current_valid_cw_cnt. The codeword is valid is represented as vaild_cw, and "if" means if or when.

[0225] Method 2: Starting from the first observed bit, verify whether each observed bit meets the synchronization condition in sequence. The synchronization condition can be that among multiple test blocks consecutively selected based on the observed bits, at least a certain number of test blocks meet the verification condition. The positions of the multiple test blocks in the data sequence can be consecutive or non-consecutive, and the positions of the certain number of test blocks in the data sequence can be consecutive or non-consecutive. If an observed bit meets the synchronization condition, determine the position where the observed bit is located as an alternative position. In this way, it is possible to end the verification of the observed bits in advance and save the resources for determining the alternative positions.

[0226] Specifically, refer to Figure 12 the state diagram shown in Figure 12 . The {synchronization position determination state} includes the {third counter reset sub-state}, the {fourth codeword verification sub-state}, and the {second codeword valid sub-state}. The {third counter reset sub-state} is the state for resetting the counter, the {fourth codeword verification sub-state} is the state for verifying the test block, and the {second codeword valid sub-state} is the state entered when the test block meets the verification condition.

[0227] In the {third counter reset sub-state}, set the initial values of the [third codeword counter] and the [first valid codeword counter]. Select an observed bit from the data sequence. Based on the current observed bit, select a test block from the data sequence. For the convenience of description, the selected test block is called the third test block. The length of the third test block is equal to the codeword length, and the starting position of the third test block is separated from the position where the observed bit is located by an integer number of codeword lengths.

[0228] In response to selecting a third test block, enter the {fourth codeword verification sub-state}. In the {fourth codeword verification sub-state}, verify the third test block. The verification method refers to the method for verifying the first test block.

[0229] In response to the third test block meeting the verification condition, enter the {second codeword valid sub-state}. In the {second codeword valid sub-state}, increase the count value of the [third codeword counter] by M, and increase the count value of the [first valid codeword counter] by Q, where both M and Q are integers greater than or equal to 1.

[0230] When the count value of the [third codeword counter] is less than or equal to the fifth threshold, in response to the count value of the [first valid codeword counter] being equal to the sixth threshold, the position where the current observed bit is located is determined as the alternative position. Optionally, after determining the alternative position, a first conversion signal can be output. The first conversion signal can be the position where the alternative position is located, or a signal to trigger entering the next state. Among them, when M = 1, the fifth threshold is the number of the third test blocks selected based on the observed bits. When M > 1, the fifth threshold is M times the number of the third test blocks selected based on the observed bits. When Q = 1, the sixth threshold is the number of the third test blocks that meet the verification conditions. When Q > 1, the sixth threshold is Q times the number of the third test blocks that meet the verification conditions. The fifth threshold and the sixth threshold can be set according to empirical values or according to the results of simulation analysis.

[0231] Optionally, in the {second codeword valid sub-state}, in response to the count value of the [third codeword counter] being equal to the fifth threshold and the count value of the [first valid codeword counter] being less than the sixth threshold, it indicates that there are no sixth threshold third test blocks among the fifth threshold third test blocks that meet the verification conditions, and an operation of selecting the next observed bit from the data sequence for verification is performed.

[0232] In the {second codeword valid sub-state}, in response to the count value of the [third codeword counter] being less than the fifth threshold and the count value of the [first valid codeword counter] being less than the sixth threshold, it indicates that the fifth threshold third test blocks have not been fully verified yet. Re-enter the {fourth codeword verification sub-state} to verify the next third test block selected based on the current observed bit.

[0233] Optionally, when the third test block meets the verification conditions, the value of the [second codeword valid variable] is set to the second value. In response to the value of the [second codeword valid variable] being the second value, enter the {second codeword valid sub-state}.

[0234] Optionally, the {synchronization position determination state} further includes the {first codeword invalid sub-state}, which is the state entered when the test block does not meet the verification conditions. In response to the third test block not meeting the verification conditions, enter the {first codeword invalid sub-state}. In the {first codeword invalid sub-state}, the count value of the [third codeword counter] is incremented by M.

[0235] In response to the count value of the [third codeword counter] being equal to the fifth threshold, an operation of selecting the next observed bit from the data sequence for verification is performed. In response to the count value of the [third codeword counter] being less than the fifth threshold, it indicates that the fifth threshold third test blocks have not been fully verified yet. Re-enter the {fourth codeword verification sub-state} to verify the next third test block selected based on the current observed bit.

[0236] Optionally, when the third test block fails to meet the verification condition, set the value of [second codeword valid variable] to the first value. In response to the value of [second codeword valid variable] being set to the first value, enter the {first codeword invalid sub-state}.

[0237] Optionally, the {synchronization position determination state} further includes a {third shift sub-state}, and the {third shift sub-state} is the state of shifting to the next observed bit. In the {first codeword invalid sub-state}, in response to the count value of [third codeword counter] being equal to the fifth threshold, enter the {third shift sub-state}. Alternatively, in the {second codeword valid sub-state}, in response to the count value of [third codeword counter] being equal to the fifth threshold and the count value of [first valid codeword counter] being less than the sixth threshold, enter the {third shift sub-state}. In the {third shift sub-state}, shift to the next observed bit. In response to shifting to the next observed bit, re-enter the {third counter reset sub-state} and perform the operation of verifying the next observed bit.

[0238] Wherein, after shifting to the next observed bit, set the value of [third shift completion variable] to the second value, and the second value is true or other values. In response to the value of [third shift completion variable] being the second value, enter the {third counter reset sub-state} and perform the operation of verifying the next observed bit. In the {third counter reset sub-state}, set the value of [third shift completion variable] to the first value, and the first value is false or other values.

[0239] Optionally, the {synchronization position determination state} further includes a {third synchronization lock initialization sub-state}, and the {third synchronization lock initialization sub-state} is the initialization state. Before entering the {third counter reset sub-state}, in response to detecting the start signal, enter the {third synchronization lock initialization sub-state}.

[0240] In the {third synchronization lock initialization sub-state}, set the value of [third synchronization lock variable] to the first value, and set the value of [third codeword to be verified variable] to the third value, and the third value is false or other values. After these processes are completed, enter the {third counter reset sub-state} without conversion conditions. After selecting a third test block based on the current observed bit, set the value of [third codeword to be verified variable] to the fourth value, and the fourth value is true or other values.

[0241] In the {third counter reset sub-state}, in response to the value of [third codeword to be verified variable] being the fourth value, enter the {fourth codeword verification sub-state}.

[0242] In the {second codeword valid sub-state}, in response to the value of [the third codeword to be verified variable] being the fourth value, and the count value of [the third codeword counter] being less than the fifth threshold, and the count value of [the first valid codeword counter] being less than the sixth threshold, re-enter the {fourth codeword verification sub-state} to verify the next third test block selected based on the current observed bit.

[0243] In the {first codeword invalid sub-state}, in response to the value of [the third codeword to be verified variable] being the fourth value, and the count value of [the third codeword counter] being less than the fifth threshold, re-enter the {fourth codeword verification sub-state} to verify the next third test block selected based on the current observed bit.

[0244] In Figure 12 In the shown process, the processing of performing the verification operation for each observed bit is the same. The method of selecting the observed bit is as described in the previous text and will not be elaborated here.

[0245] Method 3: Starting from the first observed bit, verify whether each observed bit satisfies the synchronization condition in sequence. The synchronization condition can be that multiple test blocks continuously selected based on the observed bit satisfy the verification condition, and the positions of these multiple test blocks in the data sequence can be continuous or discontinuous. If an observed bit satisfies the synchronization condition, determine the position where the observed bit is located as the alternative position. In this way, it is possible to end the verification of the observed bit in advance and save the resources for determining the alternative position. This implementation is a special case of Method 2.

[0246] Specifically, referring to Figure 13 the shown state diagram, the {synchronization position determination state} includes the {third counter reset sub-state}, the {fourth codeword verification sub-state}, and the {second codeword valid sub-state}.

[0247] In the {third counter reset sub-state}, set the initial value of the third codeword counter. Select an observed bit in the data sequence, and based on the current observed bit, select a test block from the data sequence. For the convenience of description, the selected test block is called the third test block.

[0248] In response to selecting a third test block, enter the {fourth codeword verification sub-state}. In the {fourth codeword verification sub-state}, verify the third test block. For example, verify the third test block based on the eigenvalue of the third test block.

[0249] In response to the third test block satisfying the verification condition, enter the {second codeword valid sub-state}. In the {second codeword valid sub-state}, increase the count value of [the third codeword counter] by M.

[0250] In response to the count value of the [third codeword counter] being equal to the fifth threshold, determine the position where the current observed bit is located as an alternative position. Optionally, after determining the alternative position, a first conversion signal can be output. The first conversion signal can be the position where the alternative position is located, or a signal to trigger the entry into the next state.

[0251] In response to the count value of the [third codeword counter] being less than the fifth threshold, verify the next third test block selected based on the current observed bit.

[0252] In response to the third test block not meeting the verification condition, enter the {third shift sub-state}. In the {third shift sub-state}, shift to the next observed bit. In response to shifting to the next observed bit, enter the {third counter reset sub-state} and perform the operation of verifying the next observed bit.

[0253] Optionally, when the third test block meets the verification condition, set the value of the [second codeword valid variable] to the second value. In response to the value of the [second codeword valid variable] being the second value, enter the {second codeword valid sub-state}. For the specific shift description, refer to the description for Figure 12 in.

[0254] Optionally, the {synchronization position determination state} further includes the {initialization sub-state of the third synchronization lock}. The description is referred to the previous description and will not be elaborated here.

[0255] In Figure 12 and Figure 13 In the state diagrams shown, the {third counter reset sub-state} is represented as RESET_CNT_3, the {fourth codeword verification sub-state} is represented as CW_CHECK_4, the {third shift sub-state} is represented as SLIP_3, the {initialization sub-state of the third synchronization lock} is represented as FEC_LOCK_INIT_3, the {first codeword invalid sub-state} is represented as INVALID_CW_1, and the {second codeword valid sub-state} is represented as VALID_CW_2. The [third synchronization lock variable] is represented as fec_cw_sync_3, the [third codeword to be verified variable] is represented as test_cw_3, the count value of the [third codeword counter] is represented as cw_cnt_3, the [third shift completion variable] is represented as slip_done_3, the count value of the [first valid codeword counter] is represented as valid_cw_cnt_1, setting the value of the [second codeword valid variable] to the second value is represented as valid_cw_2, and setting the value of the [second codeword valid variable] to the first value is represented as!valid_cw_2.

[0256] Exemplarily, after selecting the alternative position, determine the synchronization position based on the alternative position.

[0257] In the first implementation of determining the synchronization position based on the alternative position, the alternative position is determined as the synchronization position. Specifically, the {synchronization position determination state} further includes the {successful sub-state of the third synchronization lock}. When determining the alternative position based on the above-mentioned first method, in response to the value of the [observation bit number variable] being equal to N, enter the {successful sub-state of the third synchronization lock}. When determining the alternative position based on the above-mentioned second method, in response to the count value of the [second valid codeword counter] being equal to the sixth threshold, enter the {successful sub-state of the third synchronization lock}. When determining the alternative position based on the above-mentioned third method, in response to the count value of the [third codeword counter] being equal to the fifth threshold, enter the {successful sub-state of the third synchronization lock}. In the {successful sub-state of the third synchronization lock}, set the value of the [synchronization lock variable] to the second value. In this first implementation of determining the synchronization position based on the alternative position, directly determining the alternative position as the synchronization position can save the resources for determining the synchronization position.

[0258] In the second implementation of determining the synchronization position based on the alternative position, the alternative position is verified, and after successful verification, the alternative position is determined as the synchronization position.

[0259] Specifically, in one implementation, refer to Figure 14 the state diagram shown. Continuously select multiple test blocks based on the alternative position. For the convenience of description, the test blocks selected in this implementation are called the fourth test blocks. If all of these multiple test blocks meet the verification conditions, determine the alternative position as the synchronization position. The positions of these multiple test blocks in the data sequence can be continuous or discontinuous.

[0260] The {synchronization position determination state} further includes the {fourth counter reset sub-state} and the {fifth codeword verification sub-state}. The {fourth counter reset sub-state} is the state for resetting the counter, and the {fifth codeword verification sub-state} is the state for verifying the test blocks.

[0261] In the {fourth counter reset sub-state}, set the initial value of the [fourth codeword counter]. For the alternative position, the [fourth codeword counter] is used to record the number of test blocks selected based on this alternative position. Select the fourth test block from the data sequence based on the alternative position. In response to selecting a fourth test block, enter the {fifth codeword verification sub-state}.

[0262] In the {fifth codeword verification sub-state}, verify the fourth test block. The verification method refers to the method for verifying the first test block in the previous text and will not be elaborated here.

[0263] In response to the fourth test block meeting the verification conditions, increase the count value of the [fourth codeword counter] by R, where R is an integer greater than or equal to 1. In response to the count value of the [fourth codeword counter] being equal to the seventh threshold, determine this alternative position as the synchronization position.

[0264] Among them, when R is equal to 1, the seventh threshold is the number of the fourth test blocks selected based on the alternative positions. When R is greater than 1, the seventh threshold is R times the number of the fourth test blocks selected based on the alternative positions. The seventh threshold can be set according to empirical values or according to the results of simulation analysis.

[0265] Optionally, the synchronization position determination state further includes {the third codeword valid sub-state}, and {the third codeword valid sub-state} is the state when the test block meets the verification condition. In response to the fourth test block meeting the verification condition, enter {the third codeword valid sub-state}. In {the third codeword valid sub-state}, increase the count value of [the fourth codeword counter] by R. In response to the count value of [the fourth codeword counter] being equal to the seventh threshold, determine that this alternative position is the synchronization position. In response to the count value of [the fourth codeword counter] being less than the seventh threshold, re-enter {the fifth codeword verification sub-state} to verify the next fourth test block selected based on the alternative position.

[0266] Optionally, in response to the fourth test block not meeting the verification condition, perform the operation of re-selecting the alternative position.

[0267] Optionally, in response to the fourth test block meeting the verification condition, set the value of [the third codeword valid variable] to the second value, and the second value is true or other values. In response to the value of [the third codeword valid variable] being the second value, enter {the third codeword valid sub-state}.

[0268] In response to the fourth test not meeting the verification condition, set the value of [the third codeword valid variable] to the first value, and the first value is false or other values. In response to the value of [the third codeword valid variable] being the first value, perform the operation of re-selecting the alternative position.

[0269] Optionally, {the synchronization position determination state} further includes {the first restart sub-state}. In response to the value of [the third codeword valid variable] being the first value, enter {the first restart sub-state}. In {the first restart sub-state}, set the value of [the resynchronization lock variable] to the second value. In response to the value of [the resynchronization lock variable] being the second value, determine that a start signal is detected, and perform the operation of re-selecting the alternative position.

[0270] Optionally, the {synchronization position determination state} further includes a {successful sub-state of the third synchronization lock}, and the {successful sub-state of the third synchronization lock} is the state where the synchronization position is determined. In response to the count value of the [fourth codeword counter] being equal to the seventh threshold, enter the {successful sub-state of the third synchronization lock}. In the {successful sub-state of the third synchronization lock}, set the value of the [third synchronization lock variable] to the second value. In response to the value of the [third synchronization lock variable] being the second value, the value of the [third synchronization lock variable] being the second value is used to indicate that the alternative position is the synchronization position, and the second conversion signal can be output without a conversion condition. The second conversion signal is used to trigger the entry into the {out-of-lock detection state}, and the second conversion signal can be the synchronization position or other trigger signals.

[0271] Optionally, after selecting a fourth test block based on the synchronization position, set the value of the [fourth codeword to be verified variable] to the second value. In response to the value of the [fourth codeword to be verified variable] being the second value, enter the {fifth codeword verification sub-state}. Alternatively, in response to the value of the [fourth codeword to be verified variable] being the second value and the count value of the [fourth codeword counter] being less than the seventh threshold, enter the {fifth codeword verification sub-state}. In the {fifth codeword verification sub-state}, set the value of the [fourth codeword to be verified variable] to the first value.

[0272] In this way, since after determining the alternative position, it continues to confirm whether the alternative position is the synchronization position, the accuracy of the synchronization position is further improved.

[0273] In Figure 14 In the state diagram shown, the {successful sub-state of the third synchronization lock} is represented as FEC_LOCK_GOOD_3, the {fourth counter reset sub-state} is represented as RESET_CNT_4, the {fifth codeword verification sub-state} is represented as CW_CHECK_5, the {third codeword valid sub-state} is represented as VALID_CW_3, and the {first restart sub-state} is represented as RESTART_1. The [third synchronization lock variable] is represented as fec_cw_sync_3, the [fourth codeword to be verified variable] is represented as test_cw_4, the count value of the [fourth codeword counter] is represented as cw_cnt_4, the [resynchronization lock variable] is represented as restart_fec_lock, the value of the [third codeword valid variable] being the first value is represented as!valid_cw_3, and the value of the [third codeword valid variable] being the second value is represented as valid_cw_3.

[0274] In another implementation, multiple test blocks are successively selected based on the alternative positions. For the convenience of description, in this implementation, the selected test blocks are referred to as the fifth test blocks. A certain number of test blocks among the multiple test blocks meet the verification conditions, and the alternative position is determined as the synchronization position. The positions of the multiple test blocks in the data sequence can be continuous or discontinuous, and the positions of the certain number of test blocks in the data sequence can be continuous or discontinuous.

[0275] Specifically, refer to Figure 15 the state diagram shown in {the synchronization position determination state} also includes {the sixth counter reset sub-state}, {the seventh codeword verification sub-state}, and {the fifth codeword valid sub-state}. The {sixth counter reset sub-state} is the state for resetting the counter, the {seventh codeword verification sub-state} is the state for verifying the test blocks, and the {fifth codeword valid sub-state} is the state when the test blocks meet the verification conditions.

[0276] In the {sixth counter reset sub-state}, set the initial values of [the sixth codeword counter] and [the fourth valid codeword counter]. For the alternative position, [the sixth codeword counter] is used to record the number of test blocks selected based on this alternative position, and [the fourth valid codeword counter] is used to record the number of test blocks that meet the verification conditions. Select a fifth test block from the data sequence based on the alternative position. In response to selecting a fifth test block, enter the {seventh codeword verification sub-state}.

[0277] Optionally, in the {sixth counter reset sub-state}, the value of [the fourth shift completion variable] can also be set to the first value to indicate that no shift is required currently.

[0278] In the {seventh codeword verification sub-state}, verify the fifth test block. The verification method refers to the method for verifying the first test block in the previous text and will not be elaborated here.

[0279] In response to the fifth test block satisfying the verification condition, enter the {fifth codeword valid sub-state}. In the {fifth codeword valid sub-state}, increment the count value of [the sixth codeword counter] by E, where E is an integer greater than or equal to 1, and increment the count value of [the fourth valid codeword counter] by F, where F is an integer greater than or equal to 1. When the count value of [the sixth codeword counter] is less than or equal to the ninth threshold, in response to the count value of [the fourth valid codeword counter] being equal to the tenth threshold, determine this alternative position as the synchronization position. In response to the count value of [the sixth codeword counter] being equal to the ninth threshold and the count value of [the fourth valid codeword counter] being less than the tenth threshold, perform the operation of reselecting the alternative position. In response to the count value of [the sixth codeword counter] being less than the ninth threshold and the count value of [the fourth valid codeword counter] being less than the tenth threshold, re-enter the {seventh codeword verification sub-state} to continue verifying the next fifth test block selected based on the alternative position. Among them, when E is equal to 1, the ninth threshold is the number of fifth test blocks selected based on the alternative position. When E is greater than 1, the ninth threshold is E times the number of fifth test blocks selected based on the alternative position. When F is equal to 1, the tenth threshold is the number of fifth test blocks that satisfy the verification condition. When F is greater than 1, the tenth threshold is F times the number of fifth test blocks that satisfy the verification condition. The ninth threshold and the tenth threshold can be set according to empirical values or according to the results of simulation analysis.

[0280] Optionally, the {synchronization position determination state} further includes a {third codeword invalid sub-state}, which is the state entered when the test block does not satisfy the verification condition. In response to the fifth test block not satisfying the verification condition, enter the {third codeword invalid sub-state}. In the {third codeword invalid sub-state}, increment the count value of [the sixth codeword counter] by E. In response to the count value of [the sixth codeword counter] being equal to the ninth threshold, perform the operation of re-determining the alternative position. In response to the count value of [the sixth codeword counter] being less than the ninth threshold, re-enter the {seventh codeword verification sub-state} to continue verifying the next fifth test block selected based on the alternative position.

[0281] Optionally, in response to the fifth test block satisfying the verification condition, set the value of [the fourth codeword valid variable] to the second value. In response to the value of [the fourth codeword valid variable] being the second value, enter the {fifth codeword valid sub-state}.

[0282] In response to the fifth test block not satisfying the verification condition, set the value of [the fourth codeword valid variable] to the first value. In response to the value of [the fourth codeword valid variable] being the first value, enter the {third codeword invalid sub-state}.

[0283] Optionally, the {synchronization position determination state} further includes a {second restart sub-state}, and the {second restart sub-state} is a state for outputting a signal for re-determining an alternative position. In the {third codeword invalid sub-state}, in response to the count value of the [sixth codeword counter] being equal to the ninth threshold, enter the {second restart sub-state}. Alternatively, in the {fifth codeword valid sub-state}, in response to the count value of the [sixth codeword counter] being equal to the ninth threshold and the count value of the [fourth valid codeword counter] being less than the tenth threshold, enter the {second restart sub-state}. In the {second restart sub-state}, set the value of the [resynchronization lock variable] to a second value. In response to the value of the [resynchronization lock variable] being set to the second value, it is determined that a start signal is detected, and an operation of re-selecting an alternative position is performed.

[0284] Optionally, the {synchronization position determination state} further includes a {fourth synchronization lock success sub-state}, and the {fourth synchronization lock success sub-state} is a state where synchronization is completed. In response to the count value of the [fourth valid codeword counter] being equal to the tenth threshold, enter the {fourth synchronization lock success sub-state}. In the {fourth synchronization lock success sub-state}, set the value of the [fourth synchronization lock variable] to a second value. The value of the [fourth synchronization lock variable] being the second value is used to indicate that the alternative position is the synchronization position, and a second conversion signal can be output without conversion conditions. This second conversion signal is used to trigger entry into the {loss of lock detection state}.

[0285] Optionally, in response to selecting a fifth test block based on an alternative position, set the value of the [fifth codeword to be verified variable] to a second value. In response to the value of the [fifth codeword to be verified variable] being the second value, enter the {seventh codeword verification sub-state}. Alternatively, in response to the value of the [fifth codeword to be verified variable] being the second value and the count value of the [sixth codeword counter] being less than the ninth threshold, re-enter the {seventh codeword verification sub-state}. Alternatively, in response to the value of the [fifth codeword to be verified variable] being the second value, the count value of the [sixth codeword counter] being less than the ninth threshold, and the count value of the [fourth valid codeword counter] being less than the tenth threshold, re-enter the {seventh codeword verification sub-state}. In the {seventh codeword verification sub-state}, set the value of the [fifth codeword to be verified variable] to a first value.

[0286] In Figure 15In the state diagram shown, the {Sixth Counter Reset Sub-state} is denoted as RESET_CNT_6, the {Seventh Codeword Verification Sub-state} is denoted as CW_CHECK_7, the {Fourth Synchronization Lock Success Sub-state} is denoted as FEC_LOCK_GOOD_4, the {Fifth Codeword Valid Sub-state} is denoted as VALID_CW_5, the {Third Codeword Invalid Sub-state} is denoted as INVALID_CW_3, and the {Second Restart Sub-state} is denoted as RESTART_2. The [Fourth Synchronization Lock Variable] is denoted as fec_cw_sync_4, the [Fifth Codeword to be Verified Variable] is denoted as test_cw_5, the count value of the [Sixth Codeword Counter] is denoted as cw_cnt_6, the count value of the [Fourth Valid Codeword Counter] is denoted as valid_cw_cnt_4, the [Resynchronization Lock Variable] is denoted as restart_fec_lock, the value of the [Fourth Codeword Valid Variable] corresponding to the first value is!valid_cw_4, and the value of the [Fourth Codeword Valid Variable] corresponding to the second value is valid_cw_4.

[0287] In Figure 9 and Figures 11 to 13 the state diagram shown, the test block selected based on the observed bits belongs to the first subsequence. In Figure 14 and Figure 15 the state diagram shown, the test block selected based on the alternative position belongs to the third subsequence. Both the first subsequence and the third subsequence belong to the received sequence, and the third subsequence is located after the first subsequence. Additionally, there may be partial overlap between the first subsequence and the third subsequence.

[0288] In another implementation, the ninth threshold number of fifth test blocks can be continuously selected based on the alternative position, and the ninth threshold number of fifth test blocks can be traversed. If there is a tenth threshold number of fifth test blocks in the ninth threshold number of fifth test blocks that meet the verification conditions, the alternative position is determined as the synchronization position.

[0289] Exemplarily, in step 804, enter the {Lock Loss Detection State} to perform lock loss detection. There are multiple ways to perform lock loss detection, and three feasible ways are provided below.

[0290] Method 1: In the {lock loss detection state}, verify multiple codewords selected based on the synchronization position. In response to the number of codewords that do not meet the verification conditions among the multiple codewords reaching a certain value, re-enter the {synchronization position determination state}. For example, continuously select a target number of codewords based on the synchronization position. If there are an eighth threshold number of codewords among the target number of codewords that do not meet the verification conditions, determine that the synchronization position is incorrect and update the synchronization position; otherwise, determine that the synchronization position is correct. When the synchronization position is correct, the number of codewords that do not meet the verification conditions is relatively small. Therefore, by determining whether the number of codewords that do not meet the verification conditions reaches the eighth threshold, it is possible to more quickly determine whether the synchronization position is incorrect. Here, the target number of codewords can be continuous or discontinuous in the data sequence.

[0291] Specifically, refer to Figure 16 the state diagram shown. The {lock loss detection state} includes the {fifth counter reset sub-state} and the {sixth codeword verification sub-state}. The {fifth counter reset sub-state} is the state for resetting the counter, and the {sixth codeword verification sub-state} is the state for verifying the codewords.

[0292] After determining the synchronization position, enter the {fifth counter reset sub-state}. In the {fifth counter reset sub-state}, set the initial values of the [fifth codeword counter] and the [second invalid codeword counter]. Here, the two initial values can be 0.

[0293] Select a codeword from the data sequence based on the synchronization position. For the sake of convenience, the codeword selected based on the synchronization position is referred to as the second codeword. Optionally, select a codeword from the fourth subsequence of the data sequence based on the synchronization position. The fourth subsequence is different from the first subsequence and the third subsequence mentioned above, and the fourth subsequence is located after the third subsequence.

[0294] In response to the selection of the second codeword, enter the {sixth codeword verification sub-state}. In the {sixth codeword verification sub-state}, verify the second codeword. The method of verifying the second codeword is the same as that of verifying the first codeword, which will not be elaborated here.

[0295] In response to the second codeword not meeting the verification conditions, increment the count value of the [fifth codeword counter] by 1 and increment the count value of the [second invalid codeword counter] by 1. In response to the count value of the [fifth codeword counter] being equal to the target value and the count value of the [second invalid codeword counter] being less than the eighth threshold, perform the operation of verifying the synchronization position next time. Here, the count value of the [fifth codeword counter] being equal to the target value and the count value of the [second invalid codeword counter] being less than the eighth threshold indicates that there are relatively few codewords that do not meet the verification conditions among the target number of codewords, and the synchronization position is correct.

[0296] In response to the count value of the [second invalid codeword counter] being equal to the eighth threshold, an operation of re-determining the synchronization position of the data sequence is performed. Here, when the count value of the [second invalid codeword counter] is equal to the eighth threshold, it indicates that the number of codewords that do not meet the verification conditions is relatively large and the synchronization position is inaccurate.

[0297] Optionally, the {out-of-lock detection state} further includes a {second codeword invalid sub-state}, which is the state entered when the codeword does not meet the verification conditions. In response to the second codeword not meeting the verification conditions, enter the {second codeword invalid sub-state}. In the {second codeword invalid sub-state}, increment the count value of the [fifth codeword counter] by 1 and increment the count value of the [second invalid codeword counter] by 1.

[0298] Optionally, in the {second codeword invalid sub-state}, in response to the count value of the [fifth codeword counter] being less than the target value and the count value of the [first invalid codeword counter] being less than the eighth threshold, re-enter the {sixth codeword verification sub-state} and perform the operation of verifying the next second codeword selected based on the synchronization position.

[0299] Optionally, the {out-of-lock detection state} further includes a {fourth codeword valid sub-state}, which is the state entered when the codeword meets the verification conditions. In response to the second codeword meeting the verification conditions, enter the {fourth codeword valid sub-state}. In the {fourth codeword valid sub-state}, increment the count value of the [fifth codeword counter] by 1. In response to the count value of the [fifth codeword counter] being equal to the target value, perform the operation of verifying the synchronization position for the next time. In response to the count value of the [fifth codeword counter] being less than the target value, perform the operation of verifying the next second codeword selected based on the synchronization position.

[0300] Optionally, in response to the second codeword meeting the verification conditions, set the value of the [fifth codeword valid variable] to the second value. In response to the value of the [fifth codeword valid variable] being the second value, enter the {fourth codeword valid sub-state}.

[0301] In response to the second codeword not meeting the verification conditions, set the value of the [fifth codeword valid variable] to the first value. In response to the value of the [fifth codeword valid variable] being the first value, enter the {second codeword invalid sub-state}.

[0302] Optionally, after selecting a second codeword based on the synchronization position, set the value of [Sixth codeword to be verified variable] to a second value, and enter the {Sixth codeword verification sub-state} in response to the value of [Sixth codeword to be verified variable] being the second value. Alternatively, in the {Fourth codeword valid sub-state}, in response to the value of [Sixth codeword to be verified variable] being the second value and the count value of [Fifth codeword counter] being less than the target value, re-enter the {Sixth codeword verification sub-state}. Alternatively, in the {Second codeword invalid sub-state}, in response to the value of [Sixth codeword to be verified variable] being the second value, the count value of [Fifth codeword counter] being less than the target value, and the count value of [Second invalid codeword counter] being less than the eighth threshold, re-enter the {Sixth codeword verification sub-state}. In the {Sixth codeword verification sub-state}, set the value of [Sixth codeword to be verified variable] to a first value.

[0303] Optionally, in response to the value of [Second synchronization lock parameter] being the second value, enter the {Fifth counter reset sub-state}. Alternatively, in response to the value of [Third synchronization lock parameter] being the second value, enter the {Fifth counter reset sub-state}. In response to the value of [Fourth synchronization lock parameter] being the second value, enter the {Fifth counter reset sub-state}. Alternatively, in response to the second conversion signal, enter the {Fifth counter reset sub-state}, where the second conversion signal is a signal output when it is determined that the position determination is complete.

[0304] Optionally, in response to the count value of [Second invalid codeword counter] being equal to the eighth threshold, output a third conversion signal, where the third conversion signal is used to indicate an operation to re-determine the synchronization position of the data sequence.

[0305] Optionally, the out-of-lock detection state further includes a {Third restart sub-state}, which is a state for outputting a signal to re-determine the synchronization position. In response to the count value of [First invalid codeword counter] being equal to the eighth threshold, enter the {Third restart sub-state}. In the {Third restart sub-state}, set the value of [Re-synchronization lock variable] to a second value. A value of the [Re-synchronization lock variable] being the second value indicates re-determining the synchronization position.

[0306] In Figure 16In the state diagram shown, the {Fifth Counter Reset Sub-State} is denoted as RESET_CNT_5, the {Sixth Codeword Verification Sub-State} is denoted as CW_CHECK_6, the {Fourth Codeword Valid Sub-State} is denoted as VALID_CW_4, and the {Second Codeword Invalid Sub-State} is denoted as INVALID_CW_2. The [Sixth Codeword to be Verified Variable] is denoted as test_cw_6, the count value of the [Fifth Codeword Counter] is denoted as cw_cnt_5, the count value of the [Second Invalid Codeword Counter] is denoted as invalid_cw_cnt_2, the [Resynchronization Lock Variable] is denoted as restart_fec_lock, the value of the [Fifth Codeword Valid Variable] corresponding to the first value is!valid_cw_5, and the value of the [Fifth Codeword Valid Variable] corresponding to the second value is valid_cw_5.

[0307] Method 2: Continuously select a target number of codewords based on the synchronization position, traverse the target number of codewords. If there are eleven thresholds of codewords among the target number of codewords that meet the verification conditions, it is determined that the synchronization position is correct; otherwise, it is determined that the synchronization position is incorrect. The eleven thresholds are greater than the eight thresholds.

[0308] Specifically, refer to Figure 17 the state diagram shown. The {Lock Loss Detection State} includes the {Seventh Counter Reset Sub-State} and the {Eighth Codeword Verification Sub-State}. The {Seventh Counter Reset Sub-State} is the state for resetting the counter, and the {Eighth Codeword Verification Sub-State} is the state for verifying the codeword.

[0309] After determining the synchronization position, enter the {Seventh Counter Reset Sub-State}. In the {Seventh Counter Reset Sub-State}, set the initial values of the [Seventh Codeword Counter] and the [Fifth Valid Codeword Counter]. Here, the two initial values can be 0.

[0310] Select a codeword from the data sequence based on the synchronization position. For the convenience of description, the codeword selected based on the synchronization position is called the second codeword. Optionally, select a codeword from the fourth subsequence of the data sequence based on the synchronization position. The fourth subsequence is different from the first subsequence and the third subsequence mentioned above, and the fourth subsequence is located after the third subsequence.

[0311] In response to the selection of the second codeword, enter the {Eighth Codeword Verification Sub-State}. In the {Eighth Codeword Verification Sub-State}, verify the second codeword, increment the count value of the [Seventh Codeword Counter] by 1. The method for verifying the second codeword is the same as the method for verifying the first test block, which will not be elaborated here.

[0312] In the {Eighth Codeword Verification Sub-State}, in response to the second codeword meeting the verification conditions, increment the count value of the [Fifth Valid Codeword Counter] by 1.

[0313] In response to the count value of the [seventh codeword counter] being less than the target value, verify the next second codeword selected based on the synchronization position.

[0314] In response to the count value of the [seventh codeword counter] being equal to the target value and the count value of the [fifth valid codeword counter] being greater than or equal to the eleventh threshold, continue to perform the next verification on the synchronization position.

[0315] In response to the count value of the [seventh codeword counter] being equal to the target value and the count value of the [fifth valid codeword counter] being less than the eleventh threshold, output a third conversion signal, where the third conversion signal is used to indicate an operation of re-determining the synchronization position in the data sequence. Alternatively, the out-of-lock detection state further includes a {fourth restart sub-state}. In response to the count value of the [seventh codeword counter] being equal to the target value and the count value of the [fifth valid codeword counter] being less than the eleventh threshold, re-enter the {fourth restart sub-state}. In the {fourth restart sub-state}, set the value of the [resynchronization lock variable] to a second value. The value of the [resynchronization lock variable] being the second value indicates re-determining the synchronization device.

[0316] Optionally, in response to selecting a second codeword based on the synchronization position, set the value of the [seventh codeword to be verified variable] to a second value (such as true). In response to the value of the [seventh codeword to be verified variable] being the second value, enter the {eighth codeword verification sub-state}. Alternatively, in response to the value of the [seventh codeword to be verified variable] being the second value and the count value of the [seventh codeword counter] being less than the target value, re-enter the {eighth codeword verification sub-state}. In the {eighth codeword verification sub-state}, set the value of the [seventh codeword to be verified variable] to a first value (such as false).

[0317] In Figure 17 In the state diagram shown, the {seventh counter reset sub-state} is denoted as RESET_CNT_7, and the {eighth codeword verification sub-state} is denoted as CW_CHECK_8. The [seventh codeword to be verified variable] is denoted as test_cw_7, the count value of the [seventh codeword counter] is denoted as cw_cnt_7, the count value of the [fifth valid codeword counter] is denoted as valid_cw_cnt_5, the second codeword satisfying the verification condition is denoted as valid_cw, and "if" means if or when.

[0318] Method 3: Verify the codewords selected based on the synchronization position one by one, determine the number of codewords that cumulatively satisfy the verification condition until up to the target number of codewords. During this process, when the number of codewords that satisfy the verification condition reaches the eleventh threshold, it is determined that the synchronization position is correct.

[0319] It should be noted that the above synchronization position determination process and the out-of-lock detection process can be combined arbitrarily. In addition, the above synchronization position determination and out-of-lock detection can be implemented using the same state machine. Alternatively, they can be implemented by two sub-state machines, namely sub-state machine 1 and sub-state machine 2. Sub-state machine 1 is used to implement the process of determining the synchronization position, and sub-state machine 2 is used to implement the out-of-lock detection process. Alternatively, they can be implemented by three sub-state machines, namely sub-state machine 3, sub-state machine 4, and sub-state machine 5. Sub-state machine 3 is used to implement the process of determining the alternative position, sub-state machine 4 is used to implement the process of determining the synchronization position based on the alternative position, and sub-state machine 5 is used to implement the out-of-lock detection process.

[0320] For example, Figure 18 A state diagram for implementing the synchronization position determination process by a single state machine is provided. Figure 18 For the description of the shown state diagram, refer to Figure 13 and Figure 14 the description in the shown state diagram. Compared with Figure 13 and Figure 14 it adds a {third synchronization lock success sub-state}, denoted as (FEC_LOCK_GOOD_3), and replaces the {first restart sub-state} with a {third shift sub-state}.

[0321] It should be noted that in the state diagram of the embodiments of the present application, the values added to the register variables are all exemplified by 1.

[0322] Next, the structure of the apparatus for implementing codeword synchronization is described.

[0323] Figure 19 is the structural diagram of the apparatus for implementing codeword synchronization provided by the embodiments of the present application. This apparatus can be implemented as part or all of the apparatus through the combination of hardware. The apparatus provided by the embodiments of the present application can implement the Figure 8 processes described above. The apparatus includes a synchronization position determination module 1910 and an out-of-lock detection module 1920, where:

[0324] The synchronization position determination module 1910 is used for:

[0325] Responding to the start signal and entering the synchronization position determination state;

[0326] In the synchronization position determination state, determining the synchronization position in the received data sequence, where the synchronization position is used to indicate the starting position of the codeword in the data sequence, and can specifically be used to implement the synchronization position determination functions of steps 801 and 802 and execute the implicit steps included in steps 801 and 802;

[0327] The out-of-lock detection module 1920 is configured to: enter the out-of-lock detection state in response to determining the synchronization position;

[0328] In the out-of-lock detection state, verify a plurality of codewords selected based on the synchronization position, and re-enter the synchronization position determination state in response to a verification failure. Specifically, it can be used to implement the out-of-lock detection functions of steps 803 and 804 and execute the implicit steps included in steps 803 and 804.

[0329] In a possible implementation, the synchronization position determination module 1910 is configured to:

[0330] In the synchronization position determination state, select N observed bits in the data sequence, and determine the synchronization position based on the positions of the N observed bits, where N is an integer greater than or equal to 1.

[0331] In a possible implementation, the synchronization position determination module 1910 is configured to: select the synchronization position from the positions of the N observed bits.

[0332] In a possible implementation, the synchronization position determination state includes a first counter reset sub-state and a first codeword verification sub-state;

[0333] The synchronization position determination module 1910 is configured to:

[0334] In the first counter reset sub-state, set the initial value of the first codeword counter and select an observed bit in the data sequence;

[0335] In response to selecting a first test block from the data sequence based on the current observed bit, enter the first codeword verification sub-state. The length of the first test block is equal to the codeword length, and the starting position of the first test block is separated from the position of the current observed bit by an integer number of the codeword lengths;

[0336] In the first codeword verification sub-state, verify the first test block;

[0337] In response to the first test block satisfying the verification condition, increase the count value of the first codeword counter by X, where X is an integer greater than or equal to 1;

[0338] In response to the count value of the first codeword counter being equal to the first threshold, determine the position of the current observed bit as the synchronization position.

[0339] In a possible implementation, the synchronization position determination module 1910 is further configured to:

[0340] In response to the count value of the first codeword counter being less than the first threshold, re-enter the first codeword verification sub-state and perform the verification operation on the next first test block selected based on the current observed bit.

[0341] In a possible implementation, the synchronization position determination state further includes a first codeword valid sub-state;

[0342] The synchronization position determination module 1910 is further configured to: in response to the first test block satisfying the verification condition, enter the first codeword valid sub-state;

[0343] In the first codeword valid sub-state, increase the count value of the first codeword counter by X.

[0344] In a possible implementation, the synchronization position determination module 1910 is further configured to:

[0345] In response to the first test block not satisfying the verification condition, perform the verification operation on the next observed bit selected from the data sequence.

[0346] In a possible implementation, the synchronization position determination state further includes a first shift sub-state;

[0347] The synchronization position determination module 1910 is further configured to: in response to the first test block not satisfying the verification condition, enter the first shift sub-state;

[0348] In the first shift sub-state, shift to the next observed bit;

[0349] In response to shifting to the next observed bit, re-enter the first counter reset sub-state and perform the verification operation on the next observed bit.

[0350] In a possible implementation, the synchronization position determination state further includes a first synchronization lock initialization sub-state;

[0351] The synchronization position determination module 1910 is further configured to: in the first synchronization lock initialization sub-state, before setting the initial value of the first codeword counter in the first counter reset sub-state, set the value of the first synchronization lock variable to a first value.

[0352] In a possible implementation, the synchronization position determination state further includes a first synchronization lock success sub-state;

[0353] The synchronization position determination module 1910 is further configured to:

[0354] In response to the count value of the first codeword counter being equal to the first threshold, enter the successful sub-state of the first synchronization lock-in;

[0355] In the successful sub-state of the first synchronization lock-in, set the value of the first synchronization lock-in variable to a second value, and the value of the first synchronization lock-in variable being the second value is used to indicate that the position of the current observed bit is the synchronization position.

[0356] In a possible implementation, the synchronization position determination module 1910 is further configured to:

[0357] In the initialization sub-state of the first synchronization lock-in, set the value of the first codeword to be verified variable to a third value;

[0358] In response to selecting a first test block from the data sequence based on the current observed bit, set the value of the first codeword to be verified variable to a fourth value;

[0359] In response to the value of the first codeword to be verified variable being the fourth value and the value of the first synchronization lock-in variable being the first value, enter the first codeword verification sub-state.

[0360] In a possible implementation, the out-of-lock detection state includes a second codeword verification sub-state;

[0361] The out-of-lock detection module 1920 is configured to:

[0362] In response to determining the synchronization position, re-enter the first counter reset sub-state;

[0363] In response to selecting a first codeword based on the synchronization position, enter the second codeword verification sub-state;

[0364] In the second codeword verification sub-state, verify the first codeword.

[0365] In a possible implementation, the out-of-lock detection module 1920 is further configured to:

[0366] In the first counter reset sub-state, set the initial value of the first codeword counter and the initial value of the first invalid codeword counter;

[0367] The out-of-lock detection module 1920 is configured to:

[0368] In response to the first codeword not satisfying the verification condition, increase the count value of the first codeword counter by Y and increase the count value of the first invalid codeword counter by Z, where both Y and Z are integers greater than or equal to 1;

[0369] In response to the count value of the first codeword counter being less than or equal to a second threshold and the count value of the first invalid codeword counter being equal to a third threshold, re-enter the synchronization position determination state, where the third threshold is less than the second threshold.

[0370] In a possible implementation, the synchronization position determination state includes a first shift sub-state;

[0371] The out-of-lock detection module 1920 is configured to:

[0372] Enter the first shift sub-state;

[0373] In the first shift sub-state, shift to the next observed bit;

[0374] In response to shifting to the next observed bit, re-enter the first counter reset sub-state and perform a verification operation on the next observed bit.

[0375] In a possible implementation, the synchronization position determination module 1910 is configured to:

[0376] Among the positions where the N observed bits are located, select alternative positions in the data sequence;

[0377] Based on the alternative positions, determine the synchronization position.

[0378] In a possible implementation, N is greater than 1, and the synchronization position determination state includes a second counter reset sub-state and a third codeword verification sub-state;

[0379] The synchronization position determination module 1910 is configured to:

[0380] In the second counter reset sub-state, set the initial values of the second codeword counter and the first current valid codeword counter, and select an observed bit from the data sequence;

[0381] In response to selecting a second test block from the data sequence based on the current observed bit, enter the third codeword verification sub-state, where the length of the second test block is equal to the codeword length, and the starting position of the second test block and the position of the current observed bit are separated by an integer number of the codeword lengths;

[0382] In the third codeword verification sub-state, verify the second test block, increment the count value of the second codeword counter by W, where W is an integer greater than or equal to 1, and in response to the second test block satisfying the verification condition, increment the count value of the first current valid codeword counter by P, where P is an integer greater than or equal to 1;

[0383] In response to the count value of the second codeword counter being equal to the fourth threshold, increment the value of the observed bit number variable by 1. In response to the count value of the first current valid codeword counter being greater than the current value of the maximum valid codeword number variable, update the value of the alternative synchronization position variable to the position where the current observed bit is located, and update the current value of the maximum valid codeword number variable to the count value of the first current valid codeword counter;

[0384] In response to the value of the observed bit number variable being equal to N, determine the value of the current alternative synchronization position variable as the alternative position.

[0385] In a possible implementation, the synchronization position determination state further includes an alternative position selection sub-state;

[0386] The synchronization position determination module 1910 is configured to:

[0387] In response to the count value of the second codeword counter being equal to the fourth threshold, enter the alternative position selection sub-state;

[0388] In the alternative position selection sub-state, in response to the count value of the second codeword counter being equal to the fourth threshold, increment the value of the observed bit number variable by 1. In response to the count value of the first current valid codeword counter being greater than the current value of the maximum valid codeword number variable, update the value of the alternative synchronization position variable to the position where the current observed bit is located, and update the current value of the maximum valid codeword number variable to the count value of the first current valid codeword counter.

[0389] In a possible implementation, the synchronization position determination module 1910 is further configured to: In response to the value of the observed bit number variable being less than N, perform a verification operation on the next observed bit selected from the data sequence.

[0390] In a possible implementation, the synchronization position determination state further includes a second shift sub-state;

[0391] The synchronization position determination module 1910 is configured to:

[0392] In response to the value of the observed bit number variable being less than N, enter the second shift sub-state;

[0393] In the second shift sub-state, shift to the next observed bit;

[0394] In response to shifting to the next observed bit, re-enter the second counter reset sub-state and perform a verification operation on the next observed bit.

[0395] In a possible implementation, the synchronization position determination state further includes an initialization sub-state of second synchronization locking;

[0396] The synchronization position determination module 1910 is further configured to:

[0397] In the initialization sub-state of the second synchronization locking, set the value of the observed bit number variable to a fifth value, set the value of the alternative synchronization position variable to a sixth value, and set the value of the maximum valid codeword number variable to a seventh value.

[0398] In a possible implementation, the synchronization position determination module 1910 is further configured to:

[0399] In the initialization sub-state of the second synchronization locking, set the value of the second codeword to be verified variable to a third value;

[0400] The synchronization position determination module 1910 is configured to:

[0401] In response to selecting a second test block from the data sequence based on the current observed bit, set the value of the second codeword to be verified variable to a fourth value;

[0402] In response to the value of the second codeword to be verified variable being the fourth value, enter the third codeword verification sub-state.

[0403] In a possible implementation, the synchronization position determination module 1910 is further configured to:

[0404] In response to the count value of the second codeword counter being less than the fourth threshold, re-enter the third codeword verification sub-state and perform a verification operation on the next second test block selected based on the current observed bit.

[0405] In a possible implementation, the synchronization position determination state includes a third counter reset sub-state and a fourth codeword verification sub-state;

[0406] The synchronization position determination module 1910 is configured to:

[0407] In the third counter reset sub-state, set the initial values of the third codeword counter and the first valid codeword counter, and select an observed bit in the data sequence;

[0408] In response to selecting a third test block from the data sequence based on the current observed bit, enter the fourth codeword verification sub-state, where the length of the third test block is equal to the codeword length, and the starting position of the third test block is separated from the position of the current observed bit by an integer number of the codeword lengths;

[0409] In the fourth codeword verification sub-state, verify the third test block;

[0410] In response to the third test block meeting the verification condition, increase the count value of the third codeword counter by M and increase the count value of the first valid codeword counter by Q, where both M and Q are integers greater than or equal to 1;

[0411] In response to the count value of the first valid codeword counter being equal to the sixth threshold when the count value of the third codeword counter is less than or equal to the fifth threshold, determine the position of the current observed bit as the alternative position, where the fifth threshold is greater than or equal to the sixth threshold.

[0412] In a possible implementation, the synchronization position determination state further includes a second codeword valid sub-state;

[0413] The synchronization position determination module 1910 is configured to:

[0414] In response to the third test block meeting the verification condition, enter the second codeword valid sub-state;

[0415] In the second codeword valid sub-state, increase the count value of the third codeword counter by M and increase the count value of the first valid codeword counter by Q.

[0416] In a possible implementation, the synchronization position determination module 1910 is further configured to:

[0417] In the second codeword valid sub-state, in response to the count value of the third codeword counter being equal to the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold, perform a verification operation on the next observed bit selected from the data sequence.

[0418] In a possible implementation, the synchronization position determination module 1910 is further configured to:

[0419] In the second codeword valid sub-state, in response to the count value of the third codeword counter being less than the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold, re-enter the fourth codeword verification sub-state and perform a verification operation on the next third test block selected based on the current observed bit.

[0420] In a possible implementation, the synchronization position determination state further includes a first codeword invalid sub-state;

[0421] The synchronization position determination module 1910 is further configured to:

[0422] In response to the third test block not satisfying the verification condition, enter the first codeword invalid sub-state;

[0423] In the first codeword invalid sub-state, increase the count value of the third codeword counter by M;

[0424] In response to the count value of the third codeword counter being equal to the fifth threshold, perform a verification operation on the next observed bit selected from the data sequence.

[0425] In a possible implementation, the synchronization position determination module 1910 is further configured to: in the first codeword invalid sub-state, in response to the count value of the third codeword counter being less than the fifth threshold, re-enter the fourth codeword verification sub-state and perform a verification operation on the next third test block selected based on the current observed bit.

[0426] In a possible implementation, the synchronization position determination state further includes a third shift sub-state;

[0427] The synchronization position determination module 1910 is configured to:

[0428] Enter the third shift sub-state;

[0429] In the third shift sub-state, shift to the next observed bit;

[0430] In response to shifting to the next observed bit, re-enter the third counter reset sub-state and perform a verification operation on the next observed bit.

[0431] In a possible implementation, the synchronization position determination state further includes an initialization sub-state for the third synchronization lock;

[0432] The synchronization position determination module 1910 is further configured to:

[0433] In the initialization sub-state for the third synchronization lock, set the value of the third codeword to be verified variable to the third value.

[0434] In a possible implementation, the synchronization position determination module 1910 is configured to:

[0435] In response to selecting a third test block from the data sequence based on the current observed bit, set the value of the third codeword to be verified variable to the fourth value;

[0436] In response to the value of the third codeword to be verified variable being the fourth value, enter the fourth codeword verification sub-state.

[0437] In a possible implementation, the synchronization position determination module 1910 is configured to:

[0438] Verify the alternative position, and after successful verification, determine the alternative position as the synchronization position.

[0439] In a possible implementation, the synchronization position determination state further includes a fourth counter reset sub-state and a fifth codeword verification sub-state;

[0440] The synchronization position determination module 1910 is configured to:

[0441] In the fourth counter reset sub-state, set the initial value of the fourth codeword counter, and select a fourth test block from the data sequence based on the alternative position;

[0442] In response to selecting a fourth test block from the data sequence based on the alternative position, enter the fifth codeword verification sub-state;

[0443] In the fifth codeword verification sub-state, verify the fourth test block;

[0444] In response to the fourth test block meeting the verification conditions, increase the count value of the fourth codeword counter by R, where R is an integer greater than or equal to 1;

[0445] In response to the count value of the fourth codeword counter being equal to the seventh threshold, determine the alternative position as the synchronization position.

[0446] In a possible implementation, the synchronization position determination state further includes a third codeword valid sub-state;

[0447] The synchronization position determination module 1910 is configured to:

[0448] In response to the fourth test block meeting the verification conditions, enter the third codeword valid sub-state;

[0449] In the third codeword valid sub-state, increase the count value of the fourth codeword counter by R.

[0450] In a possible implementation, the synchronization position determination module 1910 is further configured to:

[0451] In response to the count value of the fourth codeword counter being less than the seventh threshold, re-enter the fifth codeword verification sub-state and perform the verification operation on the next fourth test block selected based on the alternative position.

[0452] In a possible implementation, the synchronization position determination module 1910 is further configured to:

[0453] In response to the fourth test block not meeting the verification conditions, re-select the alternative position.

[0454] In a possible implementation, the synchronization position determination state further includes a first resynchronization sub-state;

[0455] The synchronization position determination module 1910 is further configured to:

[0456] In response to the fourth test block not satisfying the verification condition, enter the first resynchronization sub-state;

[0457] In the first resynchronization sub-state, set the value of the first resynchronization lock variable to a second value, and the value of the first resynchronization lock variable being the second value is used to indicate that an alternative position is to be selected again in the data sequence.

[0458] In a possible implementation, the synchronization position determination state further includes a second synchronization lock success sub-state;

[0459] The synchronization position determination module 1910 is configured to:

[0460] In response to the count value of the fourth codeword counter being equal to a seventh threshold, enter the second synchronization lock success sub-state;

[0461] In the second synchronization lock success sub-state, set the value of the second synchronization lock variable to a second value, and the value of the second synchronization lock variable being the second value is used to indicate that the alternative position is the synchronization position.

[0462] In a possible implementation, the synchronization position determination module 1910 is configured to:

[0463] Determine that the alternative position is the synchronization position.

[0464] In a possible implementation, the out-of-lock detection module 1920 is configured to:

[0465] In the out-of-lock detection state, verify the codewords in the codeword set selected based on the synchronization position, where the codeword set includes a target number of codewords; in response to the number of codewords not satisfying the verification condition in the codeword set reaching an eighth threshold, re-enter the synchronization position determination state.

[0466] In a possible implementation, the out-of-lock detection state includes a fifth counter reset sub-state and a sixth codeword verification sub-state;

[0467] The out-of-lock detection module 1920 is configured to:

[0468] In the fifth counter reset sub-state, set the initial values of the fifth codeword counter and the second invalid codeword counter;

[0469] In response to selecting a second codeword from the data sequence based on the synchronization position, enter the sixth codeword verification sub-state;

[0470] In the sixth codeword verification sub-state, verify the second codeword;

[0471] In response to the second codeword not meeting the verification condition, increment the count value of the fifth codeword counter by 1 and increment the count value of the second invalid codeword counter by 1;

[0472] In response to the count value of the second invalid codeword counter being equal to the eighth threshold when the count value of the fifth codeword counter is less than the target value, re-enter the synchronization position determination state.

[0473] In a possible implementation, the out-of-lock detection state further includes a second codeword invalid sub-state;

[0474] The out-of-lock detection module 1920 is configured to:

[0475] In response to the second codeword not meeting the verification condition, enter the second codeword invalid sub-state;

[0476] In the second codeword invalid sub-state, increment the count value of the fifth codeword counter by 1 and increment the count value of the second invalid codeword counter by 1.

[0477] In a possible implementation, the out-of-lock detection module 1920 is further configured to:

[0478] In response to the second codeword meeting the verification condition, increment the count value of the fifth codeword counter by 1;

[0479] In response to the count value of the fifth codeword counter being equal to the target value, re-enter the fifth counter reset sub-state to perform the next verification of the synchronization position.

[0480] In a possible implementation, the out-of-lock detection state further includes a fourth codeword valid sub-state;

[0481] The out-of-lock detection module 1920 is further configured to:

[0482] In response to the second codeword meeting the verification condition, enter the fourth codeword valid sub-state;

[0483] In the fourth codeword valid sub-state, increment the count value of the fifth codeword counter by 1.

[0484] In a possible implementation, the out-of-lock detection module 1920 is further configured to:

[0485] In the fourth codeword valid sub-state, in response to the count value of the fifth codeword counter being less than the target value, re-enter the sixth codeword verification sub-state, and perform a verification operation on the next second codeword selected based on the synchronization position.

[0486] In a possible implementation, the out-of-lock detection module 1920 is further configured to:

[0487] In the second codeword invalid sub-state, in response to the count value of the fifth codeword counter being less than the target value and the count value of the second invalid codeword counter being less than the eighth threshold, re-enter the sixth codeword verification sub-state, and perform a verification operation on the next second codeword selected based on the synchronization position.

[0488] In a possible implementation, the out-of-lock detection module 1920 is further configured to:

[0489] In the second codeword invalid sub-state, in response to the count value of the fifth codeword counter being equal to the target value and the count value of the second invalid codeword counter being less than the eighth threshold, re-enter the fifth counter reset sub-state to perform the next verification on the synchronization position.

[0490] In a possible implementation, the verification condition is that the number of zero elements of the check sequence of the test block or codeword is greater than the synchronization threshold; or,

[0491] the verification condition is that the number of non-zero elements of the check sequence of the test block or codeword is less than the non-synchronization threshold; or,

[0492] the verification condition is that the test block or codeword is an error-correctable test block; or,

[0493] the verification condition is that the re-check bit of the test block or codeword is the same as the original check bit.

[0494] In a possible implementation, the start signal includes a system reset signal, a system start signal, a data reception failure signal, or a re-synchronization signal.

[0495] In a possible implementation, the data sequence is a bit stream encoded by FEC.

[0496] The structure of the communication device is described below.

[0497] Figure 20 A schematic structural diagram of a communication device involved in an embodiment of the present application. Refer to Figure 20, the communication device 2000 may optionally be implemented by a general bus architecture. The communication device 2000 includes at least one processor 2001, a communication bus 2002, a memory 2003, and at least one network interface 2004. Figure 20 The communication device with the structure shown may be a router or a switch mentioned above.

[0498] The processor 2001 is, for example, a general-purpose central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of this application. For example, the processor 2001 includes an ASIC, a programmable logic device (PLD), or a combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0499] The communication bus 2002 is used to transfer information between the above components. The communication bus 2002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 20 only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0500] The memory 2003 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, such as a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, such as an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 2003 is, for example, independent and connected to the processor 2001 through the communication bus 2002. The memory 2003 can also be integrated with the processor 2001.

[0501] The network interface 2004 uses any device such as a transceiver for communicating with other devices or communication networks. The network interface 2004 includes a wired network interface and may also include a wireless network interface. Among them, the wired network interface can be, for example, an Ethernet interface. The Ethernet interface can be an optical interface, an electrical interface or a combination thereof. The wireless network interface can be a wireless local area networks (WLAN) interface, a network interface of a cellular network or a combination thereof, etc.

[0502] In a specific implementation, as an example, the processor 2001 may include one or more CPUs.

[0503] In a specific implementation, as an example, the communication device 2000 may include multiple processors. Each of these processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processors here can refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0504] Figure 21 Another structural schematic diagram of the communication device involved in the embodiments of the present application. When the communication device is a forwarding device in a network, such as a router or a switch, the communication device can refer to Figure 21Schematic diagram of the device structure shown. Device 2100 includes a main control board and one or more interface boards, and the main control board is communicatively connected to the interface boards. The main control board is also referred to as the main processing unit (MPU) or the route processor card. The main control board is responsible for the control and management of each component in device 2100, including routing calculation, device management, and maintenance functions. The interface board is also referred to as the line processing unit (LPU) or the line card, and is used for forwarding data.

[0505] In some embodiments, device 2100 may also include a switching fabric board, which is communicatively connected to the main control board and the interface boards. The switching fabric board is used for forwarding data between the interface boards, and the switching fabric board may also be referred to as the switchfabric unit (SFU). The interface board includes a central processing unit, a memory, a forwarding chip, and a physical interface card (PIC). The central processing unit is communicatively connected to the memory, the network processor, and the physical interface card respectively. The memory is used for storing the forwarding table. The forwarding chip is used for forwarding the received data frames based on the forwarding table stored in the memory. If the destination address of the data frame is the address of device 2100, the data frame is sent to the CPU for processing; if the destination address of the data frame is not the address of device 2100, the next hop and the outgoing interface corresponding to the destination address are found from the forwarding table according to the destination address, and the data frame is forwarded to the outgoing interface corresponding to the destination address. The forwarding chip may be a network processor (NP). The PIC is also referred to as a daughter card, which can be installed on the interface board and is responsible for converting optical and electrical signals into data frames, performing a legality check on the data frames, and then forwarding them to the forwarding chip for processing.

[0506] In some embodiments, the central processing unit may also perform the functions of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that there is no need for a forwarding chip in the interface board. The communication connections between the main control board, the interface board, and the switching fabric board can be implemented through a bus. In some embodiments, the forwarding chip may be implemented by an ASIC or an FPGA.

[0507] Logically, device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board and a central processing unit. The forwarding plane includes various components that perform forwarding, such as a memory, PIC, and NP. The control plane performs functions such as acting as a router, generating a forwarding table, processing signaling and protocol packets, configuring and maintaining the state of PE1, etc. The control plane sends the generated forwarding table to the forwarding plane. In the forwarding plane, the NP looks up and forwards the packets received by the PIC of device 2100 based on the forwarding table sent by the control plane. The forwarding table sent by the control plane can be stored in the memory. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same device.

[0508] In a specific embodiment, the interface board is used to receive a data sequence, and the data sequence includes a plurality of bits.

[0509] The main control board is used to determine the synchronization position in the data sequence. The synchronization position is used to indicate the starting position of the codeword in the data sequence, and to perform out-of-lock detection. For the detailed processing process, please refer to the description above Figure 8 and will not be elaborated here.

[0510] In a possible implementation, an interprocess communication (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate through the IPC channel.

[0511] In the embodiments of the present application, a chip is further provided, and the chip is used to implement the method for codeword synchronization in the foregoing text.

[0512] In the embodiments of the present application, a chip system is further provided. The chip system includes a cascaded first chip and second chip. The first chip is used to implement the method for codeword synchronization in the foregoing text, and the second chip is used to perform codeword synchronization based on the AM method. That is, the inner-layer FEC uses the method for codeword synchronization in the present application, and the outer-layer FEC uses the method for codeword synchronization based on the AM method.

[0513] In several embodiments provided in the present application, it should be understood that the disclosed system architectures, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there can be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling or communication connection to each other can be an indirect coupling or communication connection through some interfaces, devices, or modules, and can also be an electrical, mechanical, or other form of connection.

[0514] In this application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions. It should be understood that there is no logical or temporal dependency between "first" and "second", nor are the quantity and execution order limited. It should also be understood that although the following description uses terms such as first and second to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, the first test block may be referred to as the second test block, and similarly, the second test block may be referred to as the first test block. Both the first test block and the second test block can be test blocks, and in some cases, they can be separate and different test blocks.

[0515] In this application, the meaning of the term "at least one" refers to one or more, and the meaning of the term "a plurality of" refers to two or more.

[0516] The above description is only an exemplary embodiment of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art in the technical field disclosed in this application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should be covered within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

1. A method for achieving codeword synchronization, characterized in that The method includes: Entering a synchronization position determination state in response to a start signal; Selecting an alternative position in the received data sequence in the synchronization position determination state; The synchronization position determination state includes a seventh codeword verification sub-state; After entering the seventh codeword verification sub-state, increasing the count value of the sixth codeword counter by E; After entering the seventh codeword verification sub-state, in response to a test block satisfying the verification condition, increasing the count value of the fourth valid codeword counter by F, where both E and F are integers greater than or equal to 1, and the test block is selected based on the alternative position; In response to the count value of the sixth codeword counter being less than or equal to a ninth threshold and the count value of the fourth valid codeword counter being equal to a tenth threshold, determining the alternative position as the synchronization position in the received data sequence, where the synchronization position is used to indicate the starting position of the codewords in the data sequence.

2. The method according to claim 1, characterized in that The method further includes: Judging whether the test block satisfies the verification condition based on the eigenvalue of the test block.

3. The method according to claim 2, characterized in that, The eigenvalue includes a check sequence.

4. The method according to claim 2 or 3, characterized in that, Judging whether the test block satisfies the verification condition based on the eigenvalue of the test block includes: Judging that the test block satisfies the verification condition based on the check sequence of the test block being a zero vector.

5. The method according to any one of claims 1 to 3, characterized in that, The method further includes: In response to the count value of the sixth codeword counter being less than the ninth threshold and the count value of the fourth valid codeword counter being less than the tenth threshold, re-entering the seventh codeword verification sub-state and performing a verification operation on the next test block selected based on the alternative position.

6. The method according to any one of claims 1-3, characterized in that, The method further includes: In response to the count value of the sixth codeword counter being equal to the ninth threshold and the count value of the fourth valid codeword counter being less than the tenth threshold, performing an operation of re-selecting an alternative position.

7. The method according to any one of claims 1 to 3, characterized in that, The synchronization position determination state further includes a sixth counter reset sub-state, and the method further includes: After entering the sixth counter reset sub-state, setting the initial values of the sixth codeword counter and the fourth valid codeword counter.

8. The method according to any one of claims 1 to 3, characterized in that, The selecting of the alternative position in the data sequence in the synchronization position determination state includes: In the synchronization position determination state, selecting N observed bits in the data sequence, and selecting the alternative position in the data sequence from the positions where the N observed bits are located, where N is an integer greater than or equal to 1.

9. The method according to claim 8, wherein The synchronization position determination state further includes a fourth codeword verification sub-state; The selecting of the alternative position in the data sequence in the synchronization position determination state includes: After entering the fourth codeword verification sub-state, increasing the count value of the third codeword counter by M; After entering the fourth codeword verification sub-state, in response to a test block satisfying the verification condition, increasing the count value of the first valid codeword counter by Q, where both M and Q are integers greater than or equal to 1, and the test block is selected based on the current observed bit; In response to the count value of the third codeword counter being less than or equal to a fifth threshold and the count value of the first valid codeword counter being equal to a sixth threshold, determine that the position where the current observed bit is located is the alternative position.

10. The method according to claim 9, wherein: In the state of determining the synchronization position, selecting an alternative position in the data sequence further includes: In response to the count value of the third codeword counter being less than the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold, re-enter the fourth codeword verification sub-state and perform a verification operation on the next test block selected based on the current observed bit.

11. The method according to claim 9 or 10, wherein: In the state of determining the synchronization position, selecting an alternative position in the data sequence further includes: In response to the count value of the third codeword counter being equal to the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold, perform a verification operation on the next observed bit selected from the data sequence.

12. The method according to claim 11, wherein The state of determining the synchronization position further includes a third counter reset sub-state, and the method further includes: After entering the third counter reset sub-state, set the initial values of the third codeword counter and the first valid codeword counter.

13. The method according to claim 12, characterized in that The state of determining the synchronization position further includes a third shift sub-state; Performing the verification operation on the next observed bit selected from the data sequence includes: Enter the third shift sub-state; After entering the third shift sub-state, shift to the next observed bit; In response to shifting to the next observed bit, re-enter the third counter reset sub-state and perform a verification operation on the next observed bit.

14. The method according to claim 9, wherein The test block selected based on the current observed bit belongs to a first subsequence in the data sequence, and the test block selected based on the alternative position belongs to a second subsequence in the data sequence, and the second subsequence is located after the first subsequence.

15. The method according to any one of claims 1 to 3, characterized in that, The method further includes: In response to determining the synchronization position, enter the out-of-lock detection state; In the out-of-lock detection state, verify a plurality of codewords selected based on the synchronization position, and in response to a verification failure, re-enter the synchronization position determination state.

16. The method according to claim 15, characterized in that, The out-of-lock detection state includes a sixth codeword verification sub-state; In the out-of-lock detection state, verifying a plurality of codewords selected based on the synchronization position and re-entering the synchronization position determination state in response to a verification failure includes: After entering the sixth codeword verification sub-state, increment the count value of the fifth codeword counter by 1; After entering the sixth codeword verification sub-state, in response to the codeword not satisfying the verification condition, increment the count value of the second invalid codeword counter by 1, where the codeword is selected based on the synchronization position; In response to the count value of the fifth codeword counter being less than or equal to a target value and the count value of the second invalid codeword counter being equal to an eighth threshold, re-enter the synchronization position determination state.

17. The method according to claim 16, wherein In the lock loss detection state, verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, re-entering the synchronization position determination state, further includes: In response to the count value of the fifth codeword counter being less than the target value and the count value of the second invalid codeword counter being less than the eighth threshold, re-entering the sixth codeword verification sub-state and performing a verification operation on the next codeword selected based on the synchronization position.

18. The method according to claim 16, wherein The lock loss detection state further includes a fifth counter reset sub-state, and the method further includes: After entering the fifth counter reset sub-state, setting the initial values of the fifth codeword counter and the second invalid codeword counter.

19. The method according to claim 18, characterized in that, In the lock loss detection state, verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, re-entering the synchronization position determination state, further includes: In response to the count value of the fifth codeword counter being equal to the target value and the count value of the second invalid codeword counter being less than the eighth threshold, re-entering the fifth counter reset sub-state to perform the next verification of the synchronization position.

20. The method according to any one of claims 1 to 3, characterized in that, The start signal includes a system reset signal, a system start signal, a data reception failure signal, or a resynchronization signal.

21. The method according to any one of claims 1 to 3, characterized in that, The data sequence is a bit stream encoded by forward error correction (FEC).

22. A communication device, characterized in that, The communication device is configured to implement the method according to any one of claims 1 to 21.

23. A chip, characterized in that, The chip is configured to implement the method according to any one of claims 1 to 21.

24. A chip system, characterized in that, The chip system includes a cascaded first chip and a second chip; The first chip is configured to implement the method according to any one of claims 1 to 21; The second chip is configured to perform codeword synchronization based on the alignment mark (AM) method.

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