On-chip termination signal generating circuit and storage system

Abstract

Embodiments of the present disclosure provide an on-chip termination signal generating circuit and a storage system. The circuit includes a trigger signal generating circuit and a control signal generating circuit. The trigger signal generating circuit is configured to receive a command / address signal received by the memory, and if the command / address signal has a target state, generate a trigger clock signal in response to a first clock; if the command / address signal does not have the target state, do not generate the trigger clock signal. The control signal generating circuit is configured to receive an operation command and output a control signal in response to the trigger clock signal. The ODT circuit receives the control signal to adjust the operating state.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to an on-chip termination signal generating circuit and a storage system. Background Art

[0002] Memory systems are typically provided as internal semiconductor integrated circuits within computers or other electronic systems. There are many different types of memory systems, including, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low-power double data rate memory (LPDDR), phase change memory (PCM), and flash memory.

[0003] Storage systems typically include a transmitter and a receiver, which transmit signals over a communication bus. This bus can be an address bus, a data bus, or a control signal bus. To reduce signal reflections between the transmitter and receiver and improve signal integrity, an on-die termination (ODT) circuit is introduced. The ODT circuit reduces signal reflections and improves signal integrity by providing a termination resistor that matches the impedance of the communication bus. Summary of the Invention

[0004] The embodiments of the present disclosure provide an on-chip termination signal generating circuit and a storage system, which are at least beneficial to reducing power consumption.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides an on-chip termination signal generating circuit, which is applied to a storage system, wherein the storage system includes a memory having an ODT circuit, including: a trigger signal generating circuit, configured to receive a command / address signal received by the memory, and if the command / address signal has a target state, generate a trigger clock signal in response to a first clock, and if the command / address signal does not have the target state, do not generate the trigger clock signal; a control signal generating circuit, configured to receive an operation command and output a control signal in response to the trigger clock signal, and the ODT circuit receives the control signal to adjust the working state.

[0006] In some embodiments, the trigger signal generating circuit includes: a selection signal generator, configured to receive the command / address signal and generate a selection signal in response to a second clock; wherein, if the command / address signal has the target state, the selection signal is valid; if the command / address signal does not have the target state, the selection signal is invalid; a trigger signal generator, configured to receive the selection signal and a third clock, and output the third clock as the trigger clock signal during the period when the selection signal is valid; wherein, the second clock and the third clock are both generated based on the first clock.

[0007] In some embodiments, the selection signal generator includes: a sampling circuit, configured to receive the command / address signal, and sample whether the command / address signal is in the target state in response to the second clock, and output a sampling signal from a first node; wherein, if the command / address signal is in the target state, the sampling signal has a valid level period, and the valid level period of the sampling signal is a first duration; an extension circuit, connected to the first node, configured to receive the sampling signal, output the selection signal, the duration of the valid level period of the selection signal is a second duration, and the second duration is M times the first duration.

[0008] In some embodiments, the sampling circuit includes: an input circuit configured to receive the command / address signal and output an identification signal; wherein, if the command / address signal is in the target state, the identification signal has a preset state; a sampler configured to sample the identification signal in response to the second clock and output the sampling signal via the first node; wherein, if the identification signal has the preset state, the sampling signal has a valid level period.

[0009] In some embodiments, the command / address signal includes a CA0 signal, a CA1 signal, and a CA2 signal; the input circuit is further configured to: receive the CA0 signal and output a first identification code; receive the CA1 signal and output a second identification code; receive the CA2 signal and output a third identification code; wherein the first identification code, the second identification code, and the third identification code constitute the identification signal.

[0010] In some embodiments, the command / address signal includes multiple sub-commands, each of the sub-commands is one of the CA0 signal, the CA1 signal or the CA2 signal; the input circuit is also configured to generate multiple selection signals in response to the address flip signal and the mirror signal, and select a sub-command based on each selection signal to generate a corresponding identification code, and the identification codes corresponding to all sub-commands constitute the identification signal.

[0011] In some embodiments, the identification signal includes multiple identification codes; the sampler includes: multiple sub-samplers, each of the multiple sub-samplers is configured to sample each corresponding identification code in response to the second clock to output a corresponding sub-sampled signal; a first logic circuit is configured to receive the sub-sampled signal output by each sub-sampler and perform a logical operation on all the sub-sampled signals to output the sampling signal via the first node.

[0012] In some embodiments, each of the sub-samplers includes: a first DFF trigger, whose input terminal receives the corresponding identification code, whose clock terminal receives the second clock, and whose output terminal outputs the sub-sampling signal; the first logic circuit includes: a first NOR gate, whose each input terminal receives a sub-sampling signal, and whose output terminal is connected to the first node.

[0013] In some embodiments, the first logic circuit further includes: a first NAND gate, one input end of which is connected to the output end of the first NOR gate, and the other input end of which receives a complementary chip select signal, the complementary chip select signal and the chip select signal are in anti-phase relationship with each other; wherein, the signal of the first node and the signal output from the output end of the first NAND gate are in anti-phase relationship with each other.

[0014] In some embodiments, the second clock includes an odd-frequency clock and an even-frequency clock, both of which are clocks obtained by dividing the first clock by n, the even-frequency clock is complementary to the odd-frequency clock, and n is a positive integer; the sampling circuit includes two samplers, both of which are connected to the same first node; one sampler samples the identification signal in response to the odd-frequency clock to output a first sampling signal, and the other sampler samples the identification signal in response to the even-frequency clock to output a second sampling signal; the sampling circuit also includes: a second logic circuit, configured to perform an OR operation on the first sampling signal and the second sampling signal to output the sampling signal.

[0015] In some embodiments, the second logic circuit includes: a second NOR gate, each input terminal of which is connected to receive the first sampling signal and the second sampling signal respectively, and an output terminal of which is connected to the first node.

[0016] In some embodiments, the extension circuit is further configured to receive a reset signal, where the reset signal is a signal obtained by extending the sampling signal by a target extension amount. When the reset signal enters a valid level period, the selection signal enters an invalid level period.

[0017] In some embodiments, the extension circuit includes: an SR latch, an S input terminal receiving the sampling signal, an R input terminal receiving the reset signal, and a Q output terminal outputting the selection signal.

[0018] In some embodiments, the strobe signal generator is further configured to receive a chip select signal, and if the command / address signal has the target state and the chip select signal is invalid, the strobe signal is invalid.

[0019] In some embodiments, the control signal generating circuit includes: at least one second DFF trigger, an input terminal of which receives the operation command, a clock terminal of which receives the trigger clock signal, and an output terminal of which outputs the control signal.

[0020] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a storage system, including: a memory, the memory having an ODT circuit; an on-chip termination signal generating circuit provided in any of the above embodiments, the ODT circuit adjusting the working state in response to the control signal.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0022] In the technical solution of the on-chip termination signal generating circuit provided by the embodiment of the present disclosure, if the command / address signal has a target state, the trigger signal generating circuit generates a trigger clock signal in response to the first clock, and if the command / address signal does not have a target state, the trigger clock signal is not generated. In this way, the power consumption caused by still generating the trigger clock signal during the period when the command / address signal does not have a target state can be avoided. The control signal generating circuit receives the operation command and outputs the control signal in response to the trigger clock signal. The ODT circuit receives the control signal to adjust the working state. During the period when there is no trigger clock signal, there is no need to output the control signal. From the above analysis, it can be seen that the embodiment of the present disclosure can reduce the power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A signal transmission circuit;

[0025] Figure 2 for Figure 1 Timing diagram of each signal in;

[0026] Figure 3 A block diagram of an on-chip termination signal generating circuit provided in an embodiment of the present disclosure;

[0027] Figure 4 for Figure 3 Timing diagram of each signal in;

[0028] Figure 5 Another block diagram of an on-chip termination signal generating circuit provided by an embodiment of the present disclosure;

[0029] Figure 6 for Figure 5 Timing diagram of each signal in;

[0030] Figure 7 for Figure 5 A block diagram of a strobe signal generator;

[0031] Figure 8 for Figure 7 Timing diagram of each signal in;

[0032] Figure 9 is another block diagram of a strobe signal generator;

[0033] Figure 10 and Figure 11 Schematic diagrams of two different circuit structures of the sampling circuit;

[0034] Figure 12 and Figure 13 Schematic diagrams of two different circuit structures of the sampling circuit;

[0035] Figure 14 Schematic diagram of another circuit structure of the sampling circuit;

[0036] Figure 15 and Figure 16 Schematic diagrams of two other circuit structures of the sampling circuit;

[0037] Figure 17 is another block diagram of a strobe signal generator;

[0038] Figure 18 for Figure 17 Timing diagram of each signal in;

[0039] Figure 19 A circuit structure diagram for extending the circuit;

[0040] Figure 20 is another block diagram of a strobe signal generator;

[0041] Figure 21 A circuit diagram of an on-chip termination signal generating circuit. DETAILED DESCRIPTION

[0042] Figure 1 A signal transmission circuit. Figure 2 for Figure 1 Timing diagram of each signal in. Figure 1 The signal transmission circuit includes: a first buffer circuit 11 that receives an external clock from a first pad PAD1, and the first buffer circuit 11 outputs an internal clock CLK; a second buffer circuit 12 that receives an operation command from a second pad PAD2, and the operation command is sampled and output by a first DFF trigger DFF1 and a second DFF trigger DFF2 in sequence, and is provided to a data terminal of a third DFF trigger DFF3, wherein the operation command received by the data terminal of the third DFF trigger DFF3 is identified as CMD; wherein the internal clock CLK is output to a clock terminal of the second DFF trigger DFF2 after passing through a first delay circuit G1 and a second delay circuit G2.

[0043] The signal transmission circuit also includes a third buffer circuit 13 that receives a chip select signal from the third pad PAD3. The chip select signal passes through a sixth delay circuit G6 to generate a chip select delay signal CS_gating. The chip select delay signal CS_gating and the internal clock CLK are output by the third delay circuit G3 and then provided to a fourth delay circuit G4. The fourth delay circuit G4 outputs a quadrature clock CLK_Q. The output of the third delay circuit G3 is also connected to one input of a fifth delay circuit G5. The other input of the fifth delay circuit G5 receives the chip select delay signal CS_gating. The fifth delay circuit G5 outputs another quadrature clock CLK_I. The quadrature clock CLK_I is provided to the clock terminal of the third DFF flip-flop DFF3, and the quadrature clock CLK_Q is provided to the clock terminal of the fourth DFF flip-flop DFF4.

[0044] In which, when the data end of the third DFF trigger DFF3 and the data end of the fourth DFF trigger DFF4 receive the operation command CMD, the output end of the third DFF trigger DFF3 outputs the ODT control signal under the triggering of the orthogonal clock CLK_I, and the output end of the fourth DFF4 outputs the ODT control signal under the triggering of the orthogonal clock CLK_Q.

[0045] Combined with reference Figure 1 and Figure 2The delay of the operation command CMD relative to the internal clock CLK is g1+g2, where g1 is the delay of the first delay circuit G1 and g2 is the delay of the second delay circuit G2. The chip select delay signal CS_gating is delayed by g6 relative to the internal clock CLK, where g6 is the delay of the sixth delay circuit G6. The quadrature clock CLK_I is delayed by g5+g6 relative to the internal clock CLK, where g5 is the delay of the fifth delay circuit G5.

[0046] If there is no operation command CMD corresponding to the ODT operation, that is, the ODT operation is not required, accordingly, the clock terminals of the third DFF flip-flop DFF3 and the fourth DFF flip-flop DFF4 do not need to receive the pulse period signal, that is, at this time, the orthogonal clocks CLK_I and CLK_Q can be kept as low level signals. Figure 1 and Figure 2 It can be seen that even without an operation command CMD corresponding to an ODT operation, taking the chip select signal as an example, which is active low, the quadrature clock CLK_I is affected by the chip select delay signal CS_gating and remains a pulse periodic signal. The quadrature clock CLK_I switches between high and low levels, which will result in unnecessary power consumption. Similarly, even without an operation command CMD corresponding to an ODT operation, the quadrature clock CLK_Q is also a pulse periodic signal, which also results in unnecessary power consumption.

[0047] The embodiment of the present disclosure provides an on-chip termination signal generating circuit, which generates a trigger clock signal only when the command / address signal has a target state, and does not generate a trigger clock signal when the command / address signal does not have the target state. The trigger clock signal is used to sample the operation command to output a control signal for adjusting the working state of the ODT circuit. Since the command / address signal has a target state, it indicates that an ODT operation needs to be performed, that is, the working state of the ODT circuit needs to be adjusted, and the trigger clock signal is needed at this time. The command / address signal does not have a target state, that is, the working state of the ODT circuit does not need to be adjusted, and there is no need to generate a trigger clock signal at this time. Therefore, the embodiment of the present disclosure can avoid the power consumption generated by generating a trigger clock signal when the working state of the ODT circuit does not need to be adjusted, thereby helping to reduce the power consumption of the circuit.

[0048] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0049] Figure 3A block diagram of an on-chip termination signal generating circuit provided by an embodiment of the present disclosure. Figure 3 The on-chip termination signal generation circuit provided by the embodiments of the present disclosure can be applied to a memory system including a memory device having an ODT circuit. The on-chip termination signal generation circuit can include a trigger signal generation circuit 101 and a control signal generation circuit 102.

[0050] The trigger signal generating circuit 101 is configured to receive a command / address signal CA received by the memory, and generate a trigger clock signal CLKT in response to the first clock CLK1 if the command / address signal CA has a target state; if the command / address signal CA does not have a target state, no trigger clock signal CLKT is generated.

[0051] The command / address signal CA having a target state indicates that the ODT circuit needs to operate. In other words, the on-chip termination signal generation circuit needs to generate a control signal for adjusting the operating state of the ODT circuit. The trigger clock signal CLKT is a periodically changing pulse signal that switches between a high-level signal and a low-level signal.

[0052] The control signal generating circuit 102 is configured to receive an operation command CMD and output a control signal CN in response to a trigger clock signal CLKT. The ODT circuit receives the control signal to adjust an operating state.

[0053] The operation command CMD may be a command for performing an ODT operation, including a read command READ, a write command WRITE, or a mode register write command (MWR, Mode Register Write).

[0054] Figure 4 for Figure 3 The timing diagram of each signal in FIG, wherein the period when CA is marked as Valid corresponds to the command / address signal CA having the target state, that is, having an operation command corresponding to the ODT operation. The period when CA is marked as Invalid corresponds to the command / address signal CA not having the target state, that is, not having an operation command corresponding to the ODT operation. During the period when the command / address signal CA has the target state, the trigger clock signal CLKT is generated; during the period when the command / address signal CA does not have the target state, the trigger clock signal CLKT is not generated. It can be understood that not generating the trigger clock signal CLKT means that the trigger clock signal CLKT remains a low-level signal, that is, it is not a periodically changing pulse signal.

[0055] From the above analysis, it can be seen that in the embodiment of the present disclosure, no periodic pulse signal is generated during a period when the ODT operation is not required, thereby reducing circuit power consumption.

[0056] The on-chip termination signal generating circuit provided by the embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0057] Figure 5 Another block diagram of an on-chip termination signal generating circuit provided by an embodiment of the present disclosure, Figure 6 for Figure 5 Timing diagram of each signal in. Figure 5 and Figure 6 The trigger signal generating circuit 101 may include a strobe signal generator 111 and a trigger signal generator 121 .

[0058] The strobe signal generator 111 may be configured to receive the command / address signal CA and generate the strobe signal CLK_enable in response to the second clock CLK2. The strobe signal CLK_enable is enabled if the command / address signal CA is in the target state, and disabled if the command / address signal CA is not in the target state.

[0059] The second clock CLK2 can be generated based on the first clock CLK1. In some examples, the first clock CLK1 can be directly used as the second clock CLK2. In some examples, the second clock CLK2 can be a clock signal obtained by dividing the first clock CLK1. The frequency of the second clock CLK2 is lower than the frequency of the first clock CLK1. In this way, the selection signal generator 111 can operate in response to the second clock CLK2 having a relatively lower frequency.

[0060] It can be understood that the strobe signal CLK_enable is valid means that the strobe signal CLK_enable has a valid level period. Figure 5 For example, the effective level period refers to the high level period. The effective duration of the strobe signal CLK_enable can be ntCK, where 1tCK is one clock cycle of the first clock CLK1, and n is a positive integer greater than 2. In addition, the effective duration of the strobe signal CLK_enable is greater than or equal to mT1, where T1 is one clock cycle of the second clock CLK2, and m is a positive integer greater than or equal to 2.

[0061] It should be noted that, in other examples, if the selection signal CLK_enable is active at a low level, then the selection signal CLK_enable being active means that the selection signal CLK_enable has an active level period, and the active level period refers to a low level period.

[0062] The trigger signal generator 121 may be configured to receive the enable signal CLK_enable and the third clock CLK3 , and output the third clock CLK3 as the trigger clock signal CLKT when the enable signal CLK_enable is valid.

[0063] The third clock CLK3 can be generated based on the first clock CLK1. In some examples, the first clock CLK1 can be directly used as the third clock CLK3. In some examples, the third clock CLK3 can be a clock signal obtained by dividing the first clock CLK1. The frequency of the third clock CLK3 is lower than the frequency of the first clock CLK1. In this way, the frequency of the trigger clock signal CLKT can be relatively low, thereby reducing the difficulty of the control signal generation circuit 102 generating and outputting the control signal CN in response to the trigger clock signal CLKT.

[0064] It is understood that the trigger clock signal CLKT may be a signal obtained by performing a logical AND operation on the strobe signal CLK_enable and the third clock CLK3. The third clock CLK3 is a periodically changing pulse signal. The third clock CLK3 is output as the trigger clock signal CLKT only when the strobe signal CLK_enable is valid. The third clock CLK3 is not output when the strobe signal CLK_enable is invalid, and accordingly, the trigger clock signal CLKT is not output.

[0065] Figure 7 for Figure 5 A block diagram of a strobe signal generator, Figure 8 for Figure 7 Timing diagram of each signal in. Figure 7 and Figure 8 The strobe signal generator 111 may include a sampling circuit 201 and an extension circuit 202 .

[0066] The sampling circuit 201 is configured to receive a command / address signal CA and, in response to a second clock CLK2, sample whether the command / address signal CA is in a target state, and output a sampling signal Samp from a first node net1. If the command / address signal CA is in the target state, the sampling signal Samp has an active level period, and the active level period of the sampling signal Samp is a first duration t1.

[0067] Because the target state corresponds to the need for an ODT operation, the sampling circuit 201 accordingly functions to determine whether the ODT operation is required by sampling whether the command / address signal CA is in the target state, and outputting a sampling signal Samp indicating whether the ODT operation is required. The presence of an active level period in the sampling signal Samp indicates the need for an ODT operation. In some examples, the presence of an active level period in the sampling signal Samp refers to a period in which the sampling signal Samp is high.

[0068] It can also be understood that if the command / address signal CA is in the target state, the sampling circuit 201 samples the command / address signal CA in the target state, so that the sampling signal Samp has an active level period corresponding to the target state. If the command / address signal CA is not in the target state, the sampling circuit 201 samples the command / address signal CA not in the target state, so that the sampling signal Samp is in an inactive level period, which can be a low level period.

[0069] Extension circuit 202 is connected to first node net1. Extension circuit 202 is configured to receive sampling signal Samp and output enable signal CLK_enable. The duration of the active level period of enable signal CLK_enable is a second duration t2, which is M times the first duration t1. In other words, extension circuit 202 receives sampling signal Samp and extends the active level period of sampling signal Samp to generate enable signal CLK_enable, ensuring that the duration of the active level period of enable signal CLK_enable meets requirements.

[0070] The effective start time of the enable signal CLK_enable may be aligned with the effective start time of the sampling signal Samp. In consideration of signal delay, the effective start time of the enable signal CLK_enable may also be slightly delayed from the effective start time of the sampling signal Samp.

[0071] Figure 9 Another block diagram of the strobe signal generator. Figure 9 , the sampling circuit 201 may include an input circuit 301 and a sampler 302 .

[0072] The input circuit 301 may be configured to receive a command / address signal CA and output an identification signal ID; wherein if the command / address signal CA is in a target state, the identification signal ID is in a preset state. In other words, if the command / address signal CA is not in the target state, the identification signal ID is not in the preset state.

[0073] In some examples, the identification signal ID having a preset state may mean that the identification signal having the preset state is a low-level signal, or in other words, the identification signal having the preset state is a logic "0." Furthermore, the identification signal ID may include multiple identification codes, and the identification signal ID having a preset state may mean that each of the multiple identification codes is a low-level signal.

[0074] It is understandable that, in other examples, the identification signal has a preset state, which may also mean that the identification signal with the preset state is a high-level signal, or in other words, the identification signal with the preset state is logic "1".

[0075] The sampler 302 may be configured to sample the identification signal ID in response to the second clock CLK2 and output a sampling signal Samp via the first node net1 ; wherein, if the identification signal ID has a preset state, the sampling signal Samp has an active level period.

[0076] The command / address signal CA includes the CA0 signal, the CA1 signal, and the CA2 signal. Analysis shows that when the command / address signal CA is in the target state, the CA0 signal is high (i.e., 1), the CA1 signal is low (i.e., 0), and the CA2 signal is high (i.e., 1). Based on the CA0, CA1, and CA2 signals, the input circuit 301 can generate an identification signal ID indicating whether an ODT operation is in progress.

[0077] Please refer to Table 1 for details. Table 1 is a truth table of the CA0 signal, CA1 signal and CA2 signal in the command / address signal corresponding to different states (Function). Among them, the corresponding relationship in Table 1 is specified in the current industry-wide JDEC standard.

[0078]

[0079] In Table 1, L represents 0 or a low level, H represents 1 or a high level, and V, C2, C3, and C4 are signals other than H and L. It is not difficult to find that when the chip select signal CS is low, that is, the chip select signal is valid, the CA0 signal, CA1 signal, and CA2 signal are 1, 0, and 1, respectively.

[0080] The input circuit 301 is further configured to receive the CA0 signal and output a first identification code, receive the CA1 signal and output a second identification code, receive the CA2 signal and output a third identification code, wherein the first identification code, the second identification code and the third identification code together constitute an identification signal.

[0081] Figure 10 and Figure 11 Schematic diagrams of two different circuit structures of sampling circuits.

[0082] refer to Figure 10 In some examples, the first identification code CA0_B is the inverted signal of the CA0 signal, the second identification code CA1 is the CA1 signal, and the third identification code CA2_B is the inverted signal of the CA2 signal. During periods when the CA0, CA1, and CA2 signals are high, low, and high, respectively (i.e., the command / address signal CA is in the target state), the identification signals have a preset state, i.e., the first identification code CA0_B, the second identification code CA1, and the third identification code CA2_B are all low, i.e., all are logic "0."

[0083] Continue to refer Figure 10 Accordingly, the input circuit 301 may include: an odd number of first inverters Inv_1, the first inverter Inv_1 at the head stage receives the CA0 signal, and the first inverter Inv_1 at the tail stage outputs the first identification code CA0_B; an odd number of second inverters Inv_2, the second inverter Inv_2 at the head stage receives the CA2 signal, and the second inverter Inv_2 at the tail stage outputs the third identification code CA2_B.

[0084] Figure 10 Only one first inverter and one second inverter are shown. In practice, the number of first inverters and second inverters may be greater than one. In addition, the input circuit 301 may also include an even number of third inverters, with the first third inverter receiving the CA1 signal and the last third inverter outputting the second identification code CA1.

[0085] It can be understood that in order to shorten the time interval between the sampling moments when the first identification code, the second identification code and the third identification code are respectively sampled by the sampler 302, the difference in the number of the first inverter, the second inverter and the third inverter should be as small as possible, such as the difference in number can be controlled at 1.

[0086] refer to Figure 11 In some examples, the first identification code CA0 is the CA0 signal, the second identification code CA1_B is the inverted signal of CA1, and the third identification code CA2 is the CA2 signal. During periods when the CA0 signal, the CA1 signal, and the CA2 signal are high-level signals, low-level signals, and high-level signals, respectively (i.e., the command / address signal CA is in the target state), the identification signals have a preset state, i.e., the first identification code CA0, the second identification code CA1_B, and the third identification code CA2 are all high-level signals, i.e., all are logic "1."

[0087] Continue to refer Figure 11Accordingly, the input circuit 301 may include an odd number of fourth inverters Inv_4 , the first-stage fourth inverter Inv_4 receives the CA1 signal, and the last-stage fourth inverter Inv_4 outputs the second identification code CA1_B.

[0088] Figure 11 Only one fourth inverter is shown; in practice, the number of fourth inverters may be greater than one. Furthermore, the input circuit 301 may include an even number of fifth inverters, with the first fifth inverter receiving the CA0 signal and the last fifth inverter outputting the first identification code CA0. The input circuit 301 may also include an even number of sixth inverters, with the first sixth inverter receiving the CA2 signal and the last sixth inverter outputting the third identification code CA2.

[0089] It can be understood that in order to shorten the time interval between the sampling moments when the first identification code, the second identification code and the third identification code are respectively sampled by the sampler 302, the difference in the number of the third inverter, the fourth inverter and the fifth inverter should be as small as possible, such as the difference in number can be controlled at 1.

[0090] Continue to refer Figure 10 and Figure 11 The identification signal includes multiple identification codes, namely a first identification code, a second identification code, and a third identification code. The sampler 302 may include multiple sub-samplers. Each sub-sampler 31 of the multiple sub-samplers is configured to sample each corresponding identification code in response to the second clock CLK2 to output a corresponding sub-sampled signal (not shown); the first logic circuit 32 is configured to receive the sub-sampled signal output by each sub-sampler 31 and perform a logical operation on all the sub-sampled signals to output a sampling signal (not shown) via the first node net1.

[0091] Each sub-sampler 31 may be a first DFF trigger D1 , an input terminal of which receives a corresponding identification code, a clock terminal of which receives a second clock CLK2 , and an output terminal of which outputs a sub-sampling signal.

[0092] refer to Figure 10The first logic circuit 32 may include a first NOR gate NOR_1, each input of which receives a sub-sampled signal, and an output connected to the first node net1. In other words, the sampling signal Samp is a signal obtained by sampling all identification codes and then performing a NOR operation. Only when the identification signal is in a preset state, that is, all identification codes are logic "0," does the sampling signal Samp have a logic "1" state, or a period of active level. When the identification signal is not in the preset state, and at least one of the identification codes is logic "1," the sampling signal Samp, according to the NOR operation logic, always has a logic "0" state, or a period of active level.

[0093] refer to Figure 11 The first logic circuit 32 may include an AND gate, each input of which receives a sub-sampled signal, and an output connected to the first node net1. In other words, the sampling signal Samp is a signal obtained by sampling all identification codes and then performing an AND operation. Only when the identification signal is in a preset state, that is, all identification codes are logical "1," does the sampling signal Samp have a logical "1" state, i.e., a period of active level. If the identification signal is not in the preset state, i.e., at least one of all identification codes is logical "0," then according to the AND operation logic, the sampling signal Samp is always logical "0," i.e., the sampling signal Samp has no active level period.

[0094] Continue to refer Figure 10 and Figure 11 The command / address signal CA can be output by the first buffer circuit 33, and the first buffer circuit 33 is connected to the command pad CAPAD. The command pad CAPAD receives the command / address signal CA and transmits it to the first buffer circuit 33. The second clock signal CLK2 can be output by the second buffer circuit 34, and the second buffer circuit 34 is connected to the clock pad CLKPAD. The clock pad CLKPAD receives the external clock and transmits it to the second buffer circuit 34.

[0095] Figure 12 and Figure 13 Schematic diagrams of two different circuit structures of sampling circuits. Figure 12 For Figure 10 Improvements based on Figure 13 For Figure 11 Improvements on the basis.

[0096] refer to Figure 12The first logic circuit 32 may further include a first NAND gate. One input of the first NAND gate is connected to the output of the first NOR gate NOR_1, and the other input receives a complementary chip select signal CS_B. The complementary chip select signal CS_B is in anti-phase relation to the chip select signal. The sampling signal at the first node of net1 is in anti-phase relation to the signal output from the output of the first NAND gate.

[0097] refer to Figure 13 The first logic circuit 32 may further include a first NAND gate, one input of which is connected to the output of the AND gate, and the other input of which receives a complementary chip select signal CS_B. The complementary chip select signal CS_B is in anti-phase relation to the chip select signal. The sampling signal at the first node of net1 is in anti-phase relation to the signal output from the output of the first NAND gate.

[0098] refer to Figure 12 and Figure 13 A zeroth inverter Inv_0 is further provided between the output end of the first NAND gate NAND and the first node net1.

[0099] In other words, sampling circuit 201 is also controlled by the complementary chip select signal CS_B. The chip select signal is active low, meaning that when the chip select signal is active, the complementary chip select signal CS_B is high. In this case, the first NAND gate NAND acts as an inverter. When the chip select signal is inactive, the complementary chip select signal CS_B is low, meaning that the complementary chip select signal CS_B is 0. At this point, the signal output from the output of the first NAND gate NAND is high, and the signal output from the corresponding first node net1 is low. In other words, when the chip select signal is inactive, the sampling signal output from the first node net1 remains low, regardless of whether the command / address signal CA is in the target state. This helps further reduce circuit power consumption.

[0100] It should be noted that, in order to avoid repetition, the following figures are all Figure 10 and Figure 12 provided on a Figure 11 and Figure 13 The specific circuit structure of the illustrated first logic circuit is also applicable to the embodiments and drawings provided subsequently.

[0101] Figure 14 is another circuit structure diagram of the sampling circuit. In some examples, reference Figure 14The on-chip termination signal generating circuit can also be applied to a DIMM (Dual-Inline-Memory-Modules) storage system. The command / address signal includes multiple sub-commands, and each of the multiple sub-commands is a CA0 signal, a CA1 signal, a CA2 signal, and a CA3 signal. Accordingly, the input circuit 301 can also be configured to generate multiple selection signals in response to the address flip signal CAI and the mirror signal MIR, and select a sub-command based on each selection signal to generate a corresponding identification code.

[0102] The DIMM storage system may include two RANKs, each RANK may include at least two memory chips, and each memory chip in the same RANK is connected to the same chip select signal line, and the memory controller can control all memory chips in the same RANK. In other words, the two memory chips in the same RANK share the command / address signal, and the two memory chips are usually face-to-face stacked packages. In order to ensure the accurate correspondence between each memory chip in the same RANK and the command / address signal to be received, the address flip signal CAI and the mirror signal MIR are introduced to ensure that the correct identification code can be generated for different memory chips in the same RANK based on the received command / address signal CA. For example, in a state where address flip and mirroring are not generated, the first identification code is generated based on the CA0 signal, the second identification code is generated based on the CA1 signal, and the third identification code is generated based on the CA2 signal. In a state where address flip and mirroring are generated, the first identification code is generated based on the CA1 signal, the second identification code is generated based on the CA0 signal, and the third identification code is generated based on the CA3 signal.

[0103] refer to Figure 14 The input circuit may further include: three multiplexers, each multiplexer 401 is controlled by a plurality of selection signals, and the plurality of selection signals are sequentially identified as SEL <0> , SEL <1> , SEL <2> and SEL <3> , and receives two sub-signals, responds to multiple selection signals, and outputs a corresponding sub-command for generating a corresponding identification code.

[0104] Each multiplexer 401 includes: a first sub-NAND gate 41, whose two input terminals receive a sub-command and a selection signal respectively; a first sub-inverter 51, whose input terminal receives a sub-command, and the sub-command received by the first sub-inverter 51 is the same as the sub-command received by the first sub-NAND gate 41; a second sub-NAND gate 42, whose one input terminal receives another selection signal and the other input terminal is connected to the output terminal of the first sub-inverter 51; a third sub-NAND gate 43, whose two input terminals are connected to the output terminal of the first sub-NAND gate 41 and the output terminal of the second sub-NAND gate 42 respectively; a fourth sub-NAND gate 44, whose two input terminals are connected to the output terminal of the first sub-NAND gate 41 and the output terminal of the second sub-NAND gate 42 respectively; receive another sub-command and another selection signal; the second sub-inverter 52 receives a sub-command at its input, and the sub-command received by the second sub-inverter 52 is the same as the sub-command received by the fourth sub-NAND gate 44; the fifth sub-NAND gate 45 receives another selection signal at one input, and the other input is connected to the output of the second sub-inverter 52; the sixth sub-NAND gate 46 has two inputs connected to the output of the fourth sub-NAND gate 44 and the output of the fifth sub-NAND gate 45, respectively; the first sub-NOR gate 47 has two inputs connected to the output of the third sub-NAND gate 43 and the output of the sixth sub-NAND gate 46, respectively.

[0105] Figure 14 The address inversion signal CAI, the mirror signal MIR and the selection signal SEL are also shown. <0> , select signal SEL <1> , select signal SEL <2> and the selection signal SEL <3> The circuit structure relationship between them is shown, wherein the address inversion signal CAI is sequentially output through the third sub-inverter 53 to output the address inversion inverted signal CAIB, and then through the fourth sub-inverter 54 to output the address inversion inverted signal CAIT. The mirror signal MIR is output through the fifth sub-inverter 55 to output the mirror inverted signal MIRB, and then through the sixth sub-inverter 56 to output the mirror inverted signal MIRT.

[0106] The input terminal of the second sub-NOR gate 57 receives the address inversion in-phase signal CAIT and the mirror in-phase signal MIRT, and the output terminal outputs the selection signal SEL. <0> The input terminal of the third sub-NOR gate 58 receives the address flip signal CAIT and the mirror inverted signal MIRB, and the output terminal outputs the selection signal SEL <1> The fourth sub-OR gate 59 receives the input terminal of the address flip inverted signal CAIB and the mirror image in-phase signal MIRT, and the output terminal outputs the selection signal SEL <2> The fifth sub-NOR gate 60 receives the input end of the mirror inverted signal MIRB and the address flip inverted signal CAIB, and the output end outputs the selection signal SEL <3> .

[0107] Table 2 is Figure 14 Truth table of each signal in .

[0108] Table 2

[0109] Serial number CAI MIR CELL <0> CELL <1> CELL <2> CELL <3> 1 0 0 1 0 0 0 2 0 1 0 1 0 0 3 1 0 0 0 1 0 4 1 1 0 0 0 1

[0110] Combined with reference table 2 and Figure 14 In the case of sequence number 1, the selection signal SEL <0> is 1, Figure 14 In the order from top to bottom, the three multiplexers 401 output the CA0 signal, the CA1 signal and the CA2 signal in sequence. In the case of sequence number 2, the selection signal SEL <1> =1, the three multiplexers 401 output the CA1 signal, the CA0 signal, and the CA3 signal in sequence. In the case of sequence number 3, the selection signal SEL <2> =1, the three multiplexers 401 output the CA0 signal, the CA1 signal, and the CA2 signal in sequence. In the case of sequence number 4, the selection signal SEL <3> is 1, the three multiplexers 401 sequentially output the CA1 signal, the CA0 signal, and the CA3 signal.

[0111] It should be noted that, in order to avoid repetition, the address inversion signal CAI and the mirror signal MIR are not shown in the subsequent figures, but the aforementioned address inversion signal CAI and the mirror signal MIR are also applicable to the subsequent embodiments and figures.

[0112] Figure 15 and Figure 16 The following are two other circuit structure diagrams of the sampling circuit. Figure 15 and Figure 16 The second clock may include an odd-frequency clock CLK_ODD and an even-frequency clock CLK_EVEN. Both the odd-frequency clock CLK_ODD and the even-frequency clock CLK_EVEN are clocks obtained by dividing the first clock CLK1 by n. The even-frequency clock CLK_EVEN is complementary to the odd-frequency clock CLK_ODD, where n is a positive integer. The first clock CLK1 may be an external clock, i.e., a clock signal received by the clock pad CLK PAD.

[0113] The first clock CLK1 may be outputted by the second buffer circuit 34 and then transmitted to the first frequency dividing circuit 35 and the second frequency dividing circuit 36 ​​. The first frequency dividing circuit 35 outputs the even-frequency clock CLK_EVEN, and the second frequency dividing circuit 36 ​​outputs the odd-frequency clock CLK_ODD.

[0114] Continue to refer Figure 15 and Figure 16 , sampling circuit 201 (reference Figure 9 ) may include two samplers 302, both connected to the same first node net1. One of the samplers 302 samples the identification signal in response to the odd-frequency clock CLK_ODD to output a first sampled signal. The other sampler 302 samples the identification signal in response to the even-frequency clock CLK_EVEN to output a second sampled signal.

[0115] Since the frequencies of the odd-frequency clock CLK_ODD and the even-frequency clock CLK_EVEN are both lower than the frequency of the first clock CLK1, compared with the solution of sampling in response to the first clock CLK1, the sampling rate of the sampler 301 in response to the odd-frequency clock CLK_ODD or the even-frequency clock CLK_EVEN is slower, which is more conducive to sampling.

[0116] The sampling circuit 201 further includes a second logic circuit 303. The second logic circuit 303 is configured to perform a NOR operation on the first sampling signal and the second sampling signal to output a sampling signal.

[0117] The second logic circuit 303 may include a second NOR gate NOR_2 , wherein two input terminals of the second NOR gate NOR_2 receive the first sampling signal and the second sampling signal respectively, and an output terminal of the second NOR gate NOR_2 is connected to the first node net1 .

[0118] Figure 17 Another block diagram of the strobe signal generator is shown below. Figure 18 for Figure 17 Timing diagram of each signal in. Figure 17 and Figure 18 The extension circuit 202 can also be configured to receive a reset signal RST, where the reset signal RST is a signal obtained by extending the sampling signal Samp by a target extension amount T. When the reset signal RST enters a valid level period, the selection signal CLK_enable enters an invalid level period.

[0119] Accordingly, the extension circuit 202 may also include a reset signal generator. The reset signal generator is configured to receive the sampling signal Samp and extend the sampling signal Samp by a target delay amount T to output a reset signal RST.

[0120] Figure 19 This is a circuit diagram for extending the circuit. Figure 19 The extension circuit 202 includes: an SR latch, an S input terminal receiving a sampling signal Samp (reference Figure 17 ), that is, the S input terminal is connected to the first node net1, the R input terminal receives the reset signal RST, and the Q output terminal outputs the enable signal CLK_enable.

[0121] The SR latch includes a third NOR gate NOR_3 and a fourth NOR gate NOR_4. One input of the third NOR gate NOR_3 serves as the S input, the other input of the third NOR gate NOR_3 is connected to the output of the fourth NOR gate NOR_4, and the output of the third NOR gate NOR_3 is connected to one input of the fourth NOR gate NOR_4. The other input of the fourth NOR gate NOR_4 serves as the R input. The output of the third NOR gate NOR_3 serves as the Q output.

[0122] It should be noted that Figure 19 This is a specific circuit structure of the extension circuit. Other circuits that can generate the enable signal CLK_enable based on the sampling signal can also be applied to the embodiment of the present application. In addition, the extension circuit of the embodiment of the present application may not receive a reset signal.

[0123] Figure 20 This is another block diagram of a strobe signal generator. Figure 20 The strobe signal generator 111 may be configured to receive the chip select signal CS, and if the command / address signal CA has a target state and the chip select signal CS is invalid, the strobe signal CLK_enable is invalid.

[0124] In this way, the situation where the chip select signal is invalid but the enable signal CLK_enable is valid can be avoided, which is beneficial to further reduce power consumption.

[0125] Combined with reference Figure 7 as well as Figure 20 In some examples, the sampling circuit 201 can be controlled by the chip select signal CS. If the chip select signal CS is inactive, the sampling signal Samp provided via the first node net1 is inactive, i.e., the sampling signal Samp does not have an active level period. In other examples, the extension circuit 202 can be controlled by the chip select signal CS. If the chip select signal CS is inactive, the selection signal CLK_enable remains inactive even if the sampling signal Samp provided via the first node net1 has an active level period.

[0126] Figure 21 This is a circuit diagram of an on-chip termination signal generation circuit. Figure 5 、 Figure 6 as well as Figure 21 , the trigger clock signal CLKT may include quadrature clocks CLK_I and CLK_Q.

[0127] The trigger signal generator 121 may include a first delay circuit G11, a second delay circuit G21, and a third delay circuit G51, connected in sequence. The first delay circuit G11 receives the third clock CLK3, and the second delay circuit G21 receives the clock output by the first delay circuit G11 and outputs a delayed clock. The trigger signal generator 121 may also include a fourth delay circuit G31 and a fifth delay circuit G41, connected in sequence. The fourth delay circuit G31 receives the third clock CLK3. The fourth delay circuit G31 performs an AND operation on the third clock CLK3 and the enable signal CLK_enable, and transmits the resulting clock to the fifth delay circuit G41. The fifth delay circuit G41 outputs a quadrature clock CLK_Q, and transmits the resulting clock to the third delay circuit G51. The third delay circuit G51 performs an AND operation on the received clock and the enable signal CLK_enable to output another quadrature clock CLK_I.

[0128] It is understandable that the fifth delay circuit G41 may also be configured to perform an AND operation on the received clock and the enable signal CLK_enable to output another quadrature clock CLK_Q.

[0129] The on-chip termination signal generating circuit may also include a first sub-flip-flop DFF11 and a second sub-flip-flop DFF21. The first sub-flip-flop DFF11 has an input terminal receiving an operation command, a Q output terminal connected to an input terminal of the second sub-flip-flop DFF21, and a Q output terminal of the second sub-flip-flop DFF21 outputting the operation command CMD.

[0130] Continue to refer Figure 21 The control signal generating circuit 102 may include: at least one second DFF trigger DFF31, an input terminal receiving an operation command CMD, a clock terminal receiving a trigger clock signal, and an output terminal outputting a control signal CN.

[0131] like Figure 21 As shown, the trigger clock signal includes quadrature clocks CLK_I and CLK_Q, and the control signal generating circuit 102 may include two second DFF flip-flops DFF31, wherein a clock end of one second DFF flip-flop DFF31 receives the quadrature clock CLK_I, and a clock end of the other second DFF flip-flop DFF31 receives the quadrature clock CLK_Q.

[0132] When ODT operation is required, the trigger clock signal is a periodic pulse signal—that is, both the quadrature clocks CLK_I and CLK_Q are periodic pulse signals. This allows the second DFF flip-flop DFF31 to sample the operation command CMD and output the control signal CN, which is used to control the ODT circuit's operating state. When ODT operation is not required, the trigger clock signal remains low—that is, both the quadrature clocks CLK_I and CLK_Q are low. This helps avoid the increased power consumption that would otherwise occur if the trigger clock signal were still a periodic pulse signal in this state.

[0133] In other examples, the trigger clock signal may also be a single clock signal, and accordingly, the control signal generating circuit may include a second DFF trigger.

[0134] The on-chip termination control signal generating circuit provided by the embodiment of the present disclosure is different from the solution in the related art of generating a trigger clock signal based on a chip select signal. The embodiment of the present disclosure generates a trigger clock signal based on a command / address signal, thereby avoiding the problem of additional power consumption caused by generating a trigger clock signal when the chip select signal is valid but no ODT operation is actually required.

[0135] An embodiment of the present disclosure also provides a storage system, including the on-chip termination control signal generating circuit provided by the above embodiment. The storage system will be described in detail below. It should be noted that the description of the above embodiment is also applicable to the embodiment of the storage system. To avoid repetition, the contents mentioned in the above embodiment will not be described in detail below.

[0136] The storage system includes a memory having an ODT circuit; the on-chip termination control signal generating circuit provided in the above embodiment, and the ODT circuit adjusts its working state in response to the control signal.

[0137] The memory system may be a random access memory system (RAM), a read-only memory system (ROM), a dynamic random access memory system (DRAM), a synchronous dynamic random access memory system (SDRAM), a resistive random access memory system (RRAM), a double data rate memory system (DDR), a low power double data rate memory system (LPDDR), a phase change memory system (PCM), or a flash memory system.

[0138] The storage system may further include a controller, and the controller and the memory are connected via a communication bus, which may include a command / address bus for transmitting command / address signals, a data bus for transmitting data signals, and a control bus for transmitting control signals.

[0139] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. An on-chip termination signal generating circuit, applied to a storage system, wherein the storage system includes a memory having an ODT circuit, characterized in that: include: a trigger signal generating circuit configured to receive a command / address signal received by the memory, generate a trigger clock signal in response to a first clock if the command / address signal has a target state, and not generate the trigger clock signal if the command / address signal does not have the target state; a control signal generating circuit configured to receive an operation command and output a control signal in response to the trigger clock signal, wherein the ODT circuit receives the control signal to adjust an operating state; The trigger signal generating circuit comprises: a strobe signal generator configured to receive the command / address signal and generate a strobe signal in response to a second clock; wherein the strobe signal is valid if the command / address signal has the target state; and invalid if the command / address signal does not have the target state; a trigger signal generator configured to receive the strobe signal and a third clock, and output the third clock as the trigger clock signal during a valid period of the strobe signal; The second clock and the third clock are both generated based on the first clock.

2. The on-chip termination signal generating circuit according to claim 1, wherein: The strobe signal generator comprises: a sampling circuit configured to receive the command / address signal and, in response to the second clock, sample whether the command / address signal is in the target state, and output a sampling signal through a first node; wherein, if the command / address signal is in the target state, the sampling signal has an effective level period, and the effective level period of the sampling signal is a first duration; The extension circuit is connected to the first node and is configured to receive the sampling signal and output the selection signal, wherein the effective level period of the selection signal has a second duration, and the second duration is M times the first duration.

3. The on-chip termination signal generating circuit according to claim 2, wherein: The sampling circuit comprises: an input circuit configured to receive the command / address signal and output an identification signal; wherein if the command / address signal is in the target state, the identification signal has a preset state; The sampler is configured to sample the identification signal in response to the second clock and output the sampling signal via the first node; wherein if the identification signal has a preset state, the sampling signal has a valid level period.

4. The on-chip termination signal generating circuit according to claim 3, wherein: The command / address signal includes a CA0 signal, a CA1 signal, and a CA2 signal; and the input circuit is further configured to: receiving the CA0 signal and outputting a first identification code; receiving the CA1 signal and outputting a second identification code; receiving the CA2 signal and outputting a third identification code; The first identification code, the second identification code and the third identification code constitute the identification signal.

5. The on-chip termination signal generating circuit according to claim 4, wherein: The command / address signal includes multiple sub-commands, each of which is one of the CA0 signal, the CA1 signal or the CA2 signal; the input circuit is also configured to generate multiple selection signals in response to the address flip signal and the mirror signal, and select a sub-command based on each selection signal to generate a corresponding identification code, and the identification codes corresponding to all sub-commands constitute the identification signal.

6. The on-chip termination signal generating circuit according to claim 3, wherein: The identification signal includes a plurality of identification codes; the sampler includes: a plurality of sub-samplers, each of the plurality of sub-samplers being configured to sample each corresponding identification code in response to the second clock to output a corresponding sub-sampled signal; The first logic circuit is configured to receive the sub-sampled signal output by each sub-sampler and perform a logic operation on all the sub-sampled signals to output the sampling signal via the first node.

7. The on-chip termination signal generating circuit according to claim 6, wherein: Each of the subsamplers comprises: a first DFF trigger, wherein an input terminal receives the corresponding identification code, a clock terminal receives the second clock, and an output terminal outputs the sub-sampling signal; The first logic circuit includes: The first NOR gate has each input terminal receiving the sub-sampling signal and an output terminal connected to the first node.

8. The on-chip termination signal generating circuit according to claim 7, wherein: The first logic circuit further includes: a first NAND gate, one input end of which is connected to the output end of the first NOR gate, and the other input end of which receives a complementary chip select signal, wherein the complementary chip select signal and the chip select signal are in anti-phase relation to each other; The signal of the first node and the signal outputted from the output terminal of the first NAND gate are in anti-phase relationship with each other.

9. The on-chip termination signal generating circuit according to any one of claims 3 to 8, characterized in that: The second clock includes an odd-frequency clock and an even-frequency clock, wherein both the odd-frequency clock and the even-frequency clock are clocks obtained by dividing the first clock by n, the even-frequency clock is complementary to the odd-frequency clock, and n is a positive integer; The sampling circuit includes two samplers, and both of the samplers are connected to the same first node; One of the samplers samples the identification signal in response to the odd-frequency clock to output a first sampling signal, and the other sampler samples the identification signal in response to the even-frequency clock to output a second sampling signal; The sampling circuit further includes: The second logic circuit is configured to perform a NOR operation on the first sampling signal and the second sampling signal to output the sampling signal.

10. The on-chip termination signal generating circuit according to claim 9, wherein: The second logic circuit includes: The second NOR gate has each input terminal connected to receive the first sampling signal and the second sampling signal respectively, and an output terminal connected to the first node.

11. The on-chip termination signal generating circuit according to claim 2, wherein: The extension circuit is further configured to: A reset signal is received, where the reset signal is a signal obtained by extending the sampling signal by a target extension amount. The reset signal enters a valid level period, and the selection signal enters an invalid level period.

12. The on-chip termination signal generating circuit according to claim 11, wherein: The extension circuit comprises: SR latch, the S input terminal receives the sampling signal, the R input terminal receives the reset signal, and the Q output terminal outputs the selection signal.

13. The on-chip termination signal generating circuit according to claim 1, wherein: The strobe signal generator is further configured to receive a chip select signal, and if the command / address signal has the target state and the chip select signal is invalid, the strobe signal is invalid.

14. The on-chip termination signal generating circuit according to claim 1, wherein: The control signal generating circuit comprises: At least one second DFF trigger has an input terminal receiving the operation command, a clock terminal receiving the trigger clock signal, and an output terminal outputting the control signal.

15. A storage system, characterized in that: include: A memory having an ODT circuit; The on-chip termination signal generating circuit according to any one of claims 1 to 14, wherein the ODT circuit adjusts its operating state in response to the control signal.

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